1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * QCOM QPIC common APIs header file 4 * 5 * Copyright (c) 2023 Qualcomm Inc. 6 * Authors: Md sadre Alam <quic_mdalam@quicinc.com> 7 * 8 */ 9 #ifndef __MTD_NAND_QPIC_COMMON_H__ 10 #define __MTD_NAND_QPIC_COMMON_H__ 11 12 /* NANDc reg offsets */ 13 #define NAND_FLASH_CMD 0x00 14 #define NAND_ADDR0 0x04 15 #define NAND_ADDR1 0x08 16 #define NAND_FLASH_CHIP_SELECT 0x0c 17 #define NAND_EXEC_CMD 0x10 18 #define NAND_FLASH_STATUS 0x14 19 #define NAND_BUFFER_STATUS 0x18 20 #define NAND_DEV0_CFG0 0x20 21 #define NAND_DEV0_CFG1 0x24 22 #define NAND_DEV0_ECC_CFG 0x28 23 #define NAND_AUTO_STATUS_EN 0x2c 24 #define NAND_DEV1_CFG0 0x30 25 #define NAND_DEV1_CFG1 0x34 26 #define NAND_READ_ID 0x40 27 #define NAND_READ_STATUS 0x44 28 #define NAND_DEV_CMD0 0xa0 29 #define NAND_DEV_CMD1 0xa4 30 #define NAND_DEV_CMD2 0xa8 31 #define NAND_DEV_CMD_VLD 0xac 32 #define SFLASHC_BURST_CFG 0xe0 33 #define NAND_ERASED_CW_DETECT_CFG 0xe8 34 #define NAND_ERASED_CW_DETECT_STATUS 0xec 35 #define NAND_EBI2_ECC_BUF_CFG 0xf0 36 #define FLASH_BUF_ACC 0x100 37 38 #define NAND_CTRL 0xf00 39 #define NAND_VERSION 0xf08 40 #define NAND_READ_LOCATION_0 0xf20 41 #define NAND_READ_LOCATION_1 0xf24 42 #define NAND_READ_LOCATION_2 0xf28 43 #define NAND_READ_LOCATION_3 0xf2c 44 #define NAND_READ_LOCATION_LAST_CW_0 0xf40 45 #define NAND_READ_LOCATION_LAST_CW_1 0xf44 46 #define NAND_READ_LOCATION_LAST_CW_2 0xf48 47 #define NAND_READ_LOCATION_LAST_CW_3 0xf4c 48 49 /* dummy register offsets, used by qcom_write_reg_dma */ 50 #define NAND_DEV_CMD1_RESTORE 0xdead 51 #define NAND_DEV_CMD_VLD_RESTORE 0xbeef 52 53 /* NAND_FLASH_CMD bits */ 54 #define PAGE_ACC BIT(4) 55 #define LAST_PAGE BIT(5) 56 57 /* NAND_FLASH_CHIP_SELECT bits */ 58 #define NAND_DEV_SEL 0 59 #define DM_EN BIT(2) 60 61 /* NAND_FLASH_STATUS bits */ 62 #define FS_OP_ERR BIT(4) 63 #define FS_READY_BSY_N BIT(5) 64 #define FS_MPU_ERR BIT(8) 65 #define FS_DEVICE_STS_ERR BIT(16) 66 #define FS_DEVICE_WP BIT(23) 67 68 /* NAND_BUFFER_STATUS bits */ 69 #define BS_UNCORRECTABLE_BIT BIT(8) 70 #define BS_CORRECTABLE_ERR_MSK 0x1f 71 72 /* NAND_DEVn_CFG0 bits */ 73 #define DISABLE_STATUS_AFTER_WRITE BIT(4) 74 #define CW_PER_PAGE 6 75 #define CW_PER_PAGE_MASK GENMASK(8, 6) 76 #define UD_SIZE_BYTES 9 77 #define UD_SIZE_BYTES_MASK GENMASK(18, 9) 78 #define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19) 79 #define SPARE_SIZE_BYTES 23 80 #define SPARE_SIZE_BYTES_MASK GENMASK(26, 23) 81 #define NUM_ADDR_CYCLES 27 82 #define NUM_ADDR_CYCLES_MASK GENMASK(29, 27) 83 #define STATUS_BFR_READ BIT(30) 84 #define SET_RD_MODE_AFTER_STATUS BIT(31) 85 86 /* NAND_DEVn_CFG0 bits */ 87 #define DEV0_CFG1_ECC_DISABLE BIT(0) 88 #define WIDE_FLASH BIT(1) 89 #define NAND_RECOVERY_CYCLES 2 90 #define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2) 91 #define CS_ACTIVE_BSY BIT(5) 92 #define BAD_BLOCK_BYTE_NUM 6 93 #define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6) 94 #define BAD_BLOCK_IN_SPARE_AREA BIT(16) 95 #define WR_RD_BSY_GAP 17 96 #define WR_RD_BSY_GAP_MASK GENMASK(22, 17) 97 #define ENABLE_BCH_ECC BIT(27) 98 99 /* NAND_DEV0_ECC_CFG bits */ 100 #define ECC_CFG_ECC_DISABLE BIT(0) 101 #define ECC_SW_RESET BIT(1) 102 #define ECC_MODE 4 103 #define ECC_MODE_MASK GENMASK(5, 4) 104 #define ECC_PARITY_SIZE_BYTES_BCH 8 105 #define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8) 106 #define ECC_NUM_DATA_BYTES 16 107 #define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16) 108 #define ECC_FORCE_CLK_OPEN BIT(30) 109 110 /* NAND_DEV_CMD1 bits */ 111 #define READ_ADDR_MASK GENMASK(7, 0) 112 113 /* NAND_DEV_CMD_VLD bits */ 114 #define READ_START_VLD BIT(0) 115 #define READ_STOP_VLD BIT(1) 116 #define WRITE_START_VLD BIT(2) 117 #define ERASE_START_VLD BIT(3) 118 #define SEQ_READ_START_VLD BIT(4) 119 120 /* NAND_EBI2_ECC_BUF_CFG bits */ 121 #define NUM_STEPS 0 122 #define NUM_STEPS_MASK GENMASK(9, 0) 123 124 /* NAND_ERASED_CW_DETECT_CFG bits */ 125 #define ERASED_CW_ECC_MASK 1 126 #define AUTO_DETECT_RES 0 127 #define MASK_ECC BIT(ERASED_CW_ECC_MASK) 128 #define RESET_ERASED_DET BIT(AUTO_DETECT_RES) 129 #define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) 130 #define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) 131 #define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) 132 133 /* NAND_ERASED_CW_DETECT_STATUS bits */ 134 #define PAGE_ALL_ERASED BIT(7) 135 #define CODEWORD_ALL_ERASED BIT(6) 136 #define PAGE_ERASED BIT(5) 137 #define CODEWORD_ERASED BIT(4) 138 #define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) 139 #define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) 140 141 /* NAND_READ_LOCATION_n bits */ 142 #define READ_LOCATION_OFFSET 0 143 #define READ_LOCATION_OFFSET_MASK GENMASK(9, 0) 144 #define READ_LOCATION_SIZE 16 145 #define READ_LOCATION_SIZE_MASK GENMASK(25, 16) 146 #define READ_LOCATION_LAST 31 147 #define READ_LOCATION_LAST_MASK BIT(31) 148 149 /* Version Mask */ 150 #define NAND_VERSION_MAJOR_MASK 0xf0000000 151 #define NAND_VERSION_MAJOR_SHIFT 28 152 #define NAND_VERSION_MINOR_MASK 0x0fff0000 153 #define NAND_VERSION_MINOR_SHIFT 16 154 155 /* NAND OP_CMDs */ 156 #define OP_PAGE_READ 0x2 157 #define OP_PAGE_READ_WITH_ECC 0x3 158 #define OP_PAGE_READ_WITH_ECC_SPARE 0x4 159 #define OP_PAGE_READ_ONFI_READ 0x5 160 #define OP_PROGRAM_PAGE 0x6 161 #define OP_PAGE_PROGRAM_WITH_ECC 0x7 162 #define OP_PROGRAM_PAGE_SPARE 0x9 163 #define OP_BLOCK_ERASE 0xa 164 #define OP_CHECK_STATUS 0xc 165 #define OP_FETCH_ID 0xb 166 #define OP_RESET_DEVICE 0xd 167 168 /* Default Value for NAND_DEV_CMD_VLD */ 169 #define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \ 170 ERASE_START_VLD | SEQ_READ_START_VLD) 171 172 /* NAND_CTRL bits */ 173 #define BAM_MODE_EN BIT(0) 174 175 /* 176 * the NAND controller performs reads/writes with ECC in 516 byte chunks. 177 * the driver calls the chunks 'step' or 'codeword' interchangeably 178 */ 179 #define NANDC_STEP_SIZE 512 180 181 /* 182 * the largest page size we support is 8K, this will have 16 steps/codewords 183 * of 512 bytes each 184 */ 185 #define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) 186 187 /* we read at most 3 registers per codeword scan */ 188 #define MAX_REG_RD (3 * MAX_NUM_STEPS) 189 190 /* ECC modes supported by the controller */ 191 #define ECC_NONE BIT(0) 192 #define ECC_RS_4BIT BIT(1) 193 #define ECC_BCH_4BIT BIT(2) 194 #define ECC_BCH_8BIT BIT(3) 195 196 /* 197 * Returns the actual register address for all NAND_DEV_ registers 198 * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD) 199 */ 200 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) 201 202 /* Returns the NAND register physical address */ 203 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset)) 204 205 /* Returns the dma address for reg read buffer */ 206 #define reg_buf_dma_addr(chip, vaddr) \ 207 ((chip)->reg_read_dma + \ 208 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf)) 209 210 #define QPIC_PER_CW_CMD_ELEMENTS 32 211 #define QPIC_PER_CW_CMD_SGL 32 212 #define QPIC_PER_CW_DATA_SGL 8 213 214 #define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000) 215 216 /* 217 * Flags used in DMA descriptor preparation helper functions 218 * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_write_data_dma) 219 */ 220 /* Don't set the EOT in current tx BAM sgl */ 221 #define NAND_BAM_NO_EOT BIT(0) 222 /* Set the NWD flag in current BAM sgl */ 223 #define NAND_BAM_NWD BIT(1) 224 /* Finish writing in the current BAM sgl and start writing in another BAM sgl */ 225 #define NAND_BAM_NEXT_SGL BIT(2) 226 /* 227 * Erased codeword status is being used two times in single transfer so this 228 * flag will determine the current value of erased codeword status register 229 */ 230 #define NAND_ERASED_CW_SET BIT(4) 231 232 #define MAX_ADDRESS_CYCLE 5 233 234 /* 235 * This data type corresponds to the BAM transaction which will be used for all 236 * NAND transfers. 237 * @bam_ce - the array of BAM command elements 238 * @cmd_sgl - sgl for NAND BAM command pipe 239 * @data_sgl - sgl for NAND BAM consumer/producer pipe 240 * @last_data_desc - last DMA desc in data channel (tx/rx). 241 * @last_cmd_desc - last DMA desc in command channel. 242 * @txn_done - completion for NAND transfer. 243 * @bam_ce_pos - the index in bam_ce which is available for next sgl 244 * @bam_ce_start - the index in bam_ce which marks the start position ce 245 * for current sgl. It will be used for size calculation 246 * for current sgl 247 * @cmd_sgl_pos - current index in command sgl. 248 * @cmd_sgl_start - start index in command sgl. 249 * @tx_sgl_pos - current index in data sgl for tx. 250 * @tx_sgl_start - start index in data sgl for tx. 251 * @rx_sgl_pos - current index in data sgl for rx. 252 * @rx_sgl_start - start index in data sgl for rx. 253 */ 254 struct bam_transaction { 255 struct bam_cmd_element *bam_ce; 256 struct scatterlist *cmd_sgl; 257 struct scatterlist *data_sgl; 258 struct dma_async_tx_descriptor *last_data_desc; 259 struct dma_async_tx_descriptor *last_cmd_desc; 260 struct completion txn_done; 261 struct_group(bam_positions, 262 u32 bam_ce_pos; 263 u32 bam_ce_start; 264 u32 cmd_sgl_pos; 265 u32 cmd_sgl_start; 266 u32 tx_sgl_pos; 267 u32 tx_sgl_start; 268 u32 rx_sgl_pos; 269 u32 rx_sgl_start; 270 271 ); 272 }; 273 274 /* 275 * This data type corresponds to the nand dma descriptor 276 * @dma_desc - low level DMA engine descriptor 277 * @list - list for desc_info 278 * 279 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by 280 * ADM 281 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM 282 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM 283 * @dir - DMA transfer direction 284 */ 285 struct desc_info { 286 struct dma_async_tx_descriptor *dma_desc; 287 struct list_head node; 288 289 union { 290 struct scatterlist adm_sgl; 291 struct { 292 struct scatterlist *bam_sgl; 293 int sgl_cnt; 294 }; 295 }; 296 enum dma_data_direction dir; 297 }; 298 299 /* 300 * holds the current register values that we want to write. acts as a contiguous 301 * chunk of memory which we use to write the controller registers through DMA. 302 */ 303 struct nandc_regs { 304 __le32 cmd; 305 __le32 addr0; 306 __le32 addr1; 307 __le32 chip_sel; 308 __le32 exec; 309 310 __le32 cfg0; 311 __le32 cfg1; 312 __le32 ecc_bch_cfg; 313 314 __le32 clrflashstatus; 315 __le32 clrreadstatus; 316 317 __le32 cmd1; 318 __le32 vld; 319 320 __le32 orig_cmd1; 321 __le32 orig_vld; 322 323 __le32 ecc_buf_cfg; 324 __le32 read_location0; 325 __le32 read_location1; 326 __le32 read_location2; 327 __le32 read_location3; 328 __le32 read_location_last0; 329 __le32 read_location_last1; 330 __le32 read_location_last2; 331 __le32 read_location_last3; 332 __le32 spi_cfg; 333 __le32 num_addr_cycle; 334 __le32 busy_wait_cnt; 335 __le32 flash_feature; 336 337 __le32 erased_cw_detect_cfg_clr; 338 __le32 erased_cw_detect_cfg_set; 339 }; 340 341 /* 342 * NAND controller data struct 343 * 344 * @dev: parent device 345 * 346 * @base: MMIO base 347 * 348 * @core_clk: controller clock 349 * @aon_clk: another controller clock 350 * @iomacro_clk: io macro clock 351 * 352 * @regs: a contiguous chunk of memory for DMA register 353 * writes. contains the register values to be 354 * written to controller 355 * 356 * @props: properties of current NAND controller, 357 * initialized via DT match data 358 * 359 * @controller: base controller structure 360 * @qspi: qpic spi structure 361 * @host_list: list containing all the chips attached to the 362 * controller 363 * 364 * @chan: dma channel 365 * @cmd_crci: ADM DMA CRCI for command flow control 366 * @data_crci: ADM DMA CRCI for data flow control 367 * 368 * @desc_list: DMA descriptor list (list of desc_infos) 369 * 370 * @data_buffer: our local DMA buffer for page read/writes, 371 * used when we can't use the buffer provided 372 * by upper layers directly 373 * @reg_read_buf: local buffer for reading back registers via DMA 374 * 375 * @base_phys: physical base address of controller registers 376 * @base_dma: dma base address of controller registers 377 * @reg_read_dma: contains dma address for register read buffer 378 * 379 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf 380 * functions 381 * @max_cwperpage: maximum QPIC codewords required. calculated 382 * from all connected NAND devices pagesize 383 * 384 * @reg_read_pos: marker for data read in reg_read_buf 385 * 386 * @cmd1/vld: some fixed controller register values 387 * 388 * @exec_opwrite: flag to select correct number of code word 389 * while reading status 390 */ 391 struct qcom_nand_controller { 392 struct device *dev; 393 394 void __iomem *base; 395 396 struct clk *core_clk; 397 struct clk *aon_clk; 398 399 struct nandc_regs *regs; 400 struct bam_transaction *bam_txn; 401 402 const struct qcom_nandc_props *props; 403 404 struct nand_controller *controller; 405 struct qpic_spi_nand *qspi; 406 struct list_head host_list; 407 408 union { 409 /* will be used only by QPIC for BAM DMA */ 410 struct { 411 struct dma_chan *tx_chan; 412 struct dma_chan *rx_chan; 413 struct dma_chan *cmd_chan; 414 }; 415 416 /* will be used only by EBI2 for ADM DMA */ 417 struct { 418 struct dma_chan *chan; 419 unsigned int cmd_crci; 420 unsigned int data_crci; 421 }; 422 }; 423 424 struct list_head desc_list; 425 426 u8 *data_buffer; 427 __le32 *reg_read_buf; 428 429 phys_addr_t base_phys; 430 dma_addr_t base_dma; 431 dma_addr_t reg_read_dma; 432 433 int buf_size; 434 int buf_count; 435 int buf_start; 436 unsigned int max_cwperpage; 437 438 int reg_read_pos; 439 440 u32 cmd1, vld; 441 bool exec_opwrite; 442 }; 443 444 /* 445 * This data type corresponds to the NAND controller properties which varies 446 * among different NAND controllers. 447 * @ecc_modes - ecc mode for NAND 448 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset 449 * @supports_bam - whether NAND controller is using BAM 450 * @nandc_part_of_qpic - whether NAND controller is part of qpic IP 451 * @qpic_version2 - flag to indicate QPIC IP version 2 452 * @use_codeword_fixup - whether NAND has different layout for boot partitions 453 */ 454 struct qcom_nandc_props { 455 u32 ecc_modes; 456 u32 dev_cmd_reg_start; 457 bool supports_bam; 458 bool nandc_part_of_qpic; 459 bool qpic_version2; 460 bool use_codeword_fixup; 461 }; 462 463 void qcom_free_bam_transaction(struct qcom_nand_controller *nandc); 464 struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc); 465 void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc); 466 void qcom_qpic_bam_dma_done(void *data); 467 void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu); 468 int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc, 469 struct dma_chan *chan, unsigned long flags); 470 int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, 471 int reg_off, const void *vaddr, int size, unsigned int flags); 472 int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, 473 const void *vaddr, int size, unsigned int flags); 474 int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off, 475 const void *vaddr, int size, bool flow_control); 476 int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs, 477 unsigned int flags); 478 int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, int first, 479 int num_regs, unsigned int flags); 480 int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, 481 int size, unsigned int flags); 482 int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr, 483 int size, unsigned int flags); 484 int qcom_submit_descs(struct qcom_nand_controller *nandc); 485 void qcom_clear_read_regs(struct qcom_nand_controller *nandc); 486 void qcom_nandc_unalloc(struct qcom_nand_controller *nandc); 487 int qcom_nandc_alloc(struct qcom_nand_controller *nandc); 488 #endif 489 490