1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Functions to access TPS65215/TPS65219 Power Management Integrated Chips 4 * 5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ 6 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef MFD_TPS65219_H 10 #define MFD_TPS65219_H 11 12 #include <linux/bitops.h> 13 #include <linux/notifier.h> 14 #include <linux/regmap.h> 15 #include <linux/regulator/driver.h> 16 17 /* Chip id list*/ 18 enum pmic_id { 19 TPS65214, 20 TPS65215, 21 TPS65219, 22 }; 23 24 /* I2C ID for TPS65219 part */ 25 #define TPS65219_I2C_ID 0x24 26 27 /* All register addresses */ 28 #define TPS65219_REG_TI_DEV_ID 0x00 29 #define TPS65219_REG_NVM_ID 0x01 30 #define TPS65219_REG_ENABLE_CTRL 0x02 31 #define TPS65219_REG_BUCKS_CONFIG 0x03 32 #define TPS65214_REG_LOCK 0x03 33 #define TPS65219_REG_LDO4_VOUT 0x04 34 #define TPS65214_REG_LDO1_VOUT_STBY 0x04 35 #define TPS65219_REG_LDO3_VOUT 0x05 36 #define TPS65215_REG_LDO2_VOUT 0x05 37 #define TPS65214_REG_LDO1_VOUT 0x05 38 #define TPS65219_REG_LDO2_VOUT 0x06 39 #define TPS65214_REG_LDO2_VOUT 0x06 40 #define TPS65219_REG_LDO1_VOUT 0x07 41 #define TPS65214_REG_LDO2_VOUT_STBY 0x07 42 #define TPS65219_REG_BUCK3_VOUT 0x8 43 #define TPS65219_REG_BUCK2_VOUT 0x9 44 #define TPS65219_REG_BUCK1_VOUT 0xA 45 #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB 46 #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC 47 #define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC 48 #define TPS65214_REG_LDO1_SEQUENCE_SLOT 0xC 49 #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD 50 #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE 51 #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF 52 #define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 53 #define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 54 #define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 55 #define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 56 #define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 57 #define TPS65214_REG_GPIO_GPI_SEQUENCE_SLOT 0x14 58 #define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 59 #define TPS65214_REG_GPO_SEQUENCE_SLOT 0x15 60 #define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 61 #define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 62 /* _SLOT_DURATION_3 doesn't apply to TPS65215*/ 63 #define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 64 #define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 65 #define TPS65214_REG_BUCK3_VOUT_STBY 0x19 66 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A 67 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B 68 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C 69 #define TPS65214_REG_BUCK2_VOUT_STBY 0x1C 70 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D 71 #define TPS65214_REG_BUCK1_VOUT_STBY 0x1D 72 #define TPS65219_REG_GENERAL_CONFIG 0x1E 73 #define TPS65219_REG_MFP_1_CONFIG 0x1F 74 #define TPS65219_REG_MFP_2_CONFIG 0x20 75 #define TPS65219_REG_STBY_1_CONFIG 0x21 76 #define TPS65219_REG_STBY_2_CONFIG 0x22 77 #define TPS65219_REG_OC_DEGL_CONFIG 0x23 78 /* 'sub irq' MASK registers */ 79 #define TPS65219_REG_INT_MASK_UV 0x24 80 #define TPS65219_REG_MASK_CONFIG 0x25 81 82 #define TPS65219_REG_I2C_ADDRESS_REG 0x26 83 #define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 84 #define TPS65219_REG_MANUFACTURING_VER 0x28 85 #define TPS65219_REG_MFP_CTRL 0x29 86 #define TPS65219_REG_DISCHARGE_CONFIG 0x2A 87 /* main irq registers */ 88 #define TPS65219_REG_INT_SOURCE 0x2B 89 90 /* TPS65219 'sub irq' registers */ 91 #define TPS65219_REG_INT_LDO_3_4 0x2C 92 #define TPS65219_REG_INT_LDO_1_2 0x2D 93 94 /* TPS65215 specific 'sub irq' registers */ 95 #define TPS65215_REG_INT_LDO_2 0x2C 96 #define TPS65215_REG_INT_LDO_1 0x2D 97 98 /* TPS65214 specific 'sub irq' register */ 99 #define TPS65214_REG_INT_LDO_1_2 0x2D 100 101 /* Common TPS65215 & TPS65219 'sub irq' registers */ 102 #define TPS65219_REG_INT_BUCK_3 0x2E 103 #define TPS65219_REG_INT_BUCK_1_2 0x2F 104 #define TPS65219_REG_INT_SYSTEM 0x30 105 #define TPS65219_REG_INT_RV 0x31 106 #define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 107 #define TPS65219_REG_INT_PB 0x33 108 109 #define TPS65219_REG_INT_LDO_3_4_POS 0 110 #define TPS65219_REG_INT_LDO_1_2_POS 1 111 #define TPS65219_REG_INT_BUCK_3_POS 2 112 #define TPS65219_REG_INT_BUCK_1_2_POS 3 113 #define TPS65219_REG_INT_SYS_POS 4 114 #define TPS65219_REG_INT_RV_POS 5 115 #define TPS65219_REG_INT_TO_RV_POS 6 116 #define TPS65219_REG_INT_PB_POS 7 117 118 #define TPS65215_REG_INT_LDO_2_POS 0 119 #define TPS65215_REG_INT_LDO_1_POS 1 120 121 #define TPS65214_REG_INT_LDO_1_2_POS 0 122 #define TPS65214_REG_INT_BUCK_3_POS 1 123 #define TPS65214_REG_INT_BUCK_1_2_POS 2 124 #define TPS65214_REG_INT_SYS_POS 3 125 #define TPS65214_REG_INT_RV_POS 4 126 #define TPS65214_REG_INT_TO_RV_POS 5 127 #define TPS65214_REG_INT_PB_POS 6 128 129 #define TPS65219_REG_USER_NVM_CMD 0x34 130 #define TPS65219_REG_POWER_UP_STATUS 0x35 131 #define TPS65219_REG_SPARE_2 0x36 132 #define TPS65219_REG_SPARE_3 0x37 133 #define TPS65219_REG_FACTORY_CONFIG_2 0x41 134 135 /* Register field definitions */ 136 #define TPS65219_DEVID_REV_MASK GENMASK(7, 0) 137 #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) 138 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) 139 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7) 140 #define LDO_BYP_SHIFT 6 141 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) 142 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) 143 /* Regulators enable control */ 144 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) 145 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) 146 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) 147 #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) 148 #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) 149 #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) 150 #define TPS65215_ENABLE_LDO2_EN_MASK BIT(5) 151 #define TPS65214_ENABLE_LDO1_EN_MASK BIT(5) 152 #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) 153 /* power ON-OFF sequence slot */ 154 #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) 155 #define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) 156 /* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */ 157 #define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0) 158 #define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1) 159 #define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2) 160 #define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3) 161 #define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4) 162 #define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5) 163 #define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6) 164 /* STBY_2 config */ 165 #define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0) 166 #define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1) 167 #define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2) 168 /* MFP Control */ 169 #define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0) 170 #define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1) 171 #define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2) 172 #define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3) 173 #define TPS65219_MFP_GPIO_STATUS_MASK BIT(4) 174 /* MFP_1 Config */ 175 #define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0) 176 #define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1) 177 #define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2) 178 /* MFP_2 Config */ 179 #define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0) 180 #define TPS65219_MFP_2_MODE_RESET_MASK BIT(2) 181 #define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3) 182 #define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4) 183 #define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6) 184 #define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7) 185 #define TPS65219_MFP_2_EN 0 186 #define TPS65219_MFP_2_PB BIT(4) 187 #define TPS65219_MFP_2_VSENSE BIT(5) 188 /* MASK_UV Config */ 189 #define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0) 190 #define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1) 191 #define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2) 192 #define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3) 193 #define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4) 194 #define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5) 195 #define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6) 196 #define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7) 197 /* MASK Config */ 198 // SENSOR_N_WARM_MASK already defined in Thermal 199 #define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4) 200 #define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) 201 #define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) 202 /* UnderVoltage - Short to GND - OverCurrent*/ 203 /* LDO3-4: only for TPS65219*/ 204 #define TPS65219_INT_LDO3_SCG_MASK BIT(0) 205 #define TPS65219_INT_LDO3_OC_MASK BIT(1) 206 #define TPS65219_INT_LDO3_UV_MASK BIT(2) 207 #define TPS65219_INT_LDO4_SCG_MASK BIT(3) 208 #define TPS65219_INT_LDO4_OC_MASK BIT(4) 209 #define TPS65219_INT_LDO4_UV_MASK BIT(5) 210 /* LDO1-2: TPS65214 & TPS65219 */ 211 #define TPS65219_INT_LDO1_SCG_MASK BIT(0) 212 #define TPS65219_INT_LDO1_OC_MASK BIT(1) 213 #define TPS65219_INT_LDO1_UV_MASK BIT(2) 214 #define TPS65219_INT_LDO2_SCG_MASK BIT(3) 215 #define TPS65219_INT_LDO2_OC_MASK BIT(4) 216 #define TPS65219_INT_LDO2_UV_MASK BIT(5) 217 /* TPS65215 LDO1-2*/ 218 #define TPS65215_INT_LDO1_SCG_MASK BIT(0) 219 #define TPS65215_INT_LDO1_OC_MASK BIT(1) 220 #define TPS65215_INT_LDO1_UV_MASK BIT(2) 221 #define TPS65215_INT_LDO2_SCG_MASK BIT(0) 222 #define TPS65215_INT_LDO2_OC_MASK BIT(1) 223 #define TPS65215_INT_LDO2_UV_MASK BIT(2) 224 /* BUCK3 */ 225 #define TPS65219_INT_BUCK3_SCG_MASK BIT(0) 226 #define TPS65219_INT_BUCK3_OC_MASK BIT(1) 227 #define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2) 228 #define TPS65219_INT_BUCK3_UV_MASK BIT(3) 229 /* BUCK1-2 */ 230 #define TPS65219_INT_BUCK1_SCG_MASK BIT(0) 231 #define TPS65219_INT_BUCK1_OC_MASK BIT(1) 232 #define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2) 233 #define TPS65219_INT_BUCK1_UV_MASK BIT(3) 234 #define TPS65219_INT_BUCK2_SCG_MASK BIT(4) 235 #define TPS65219_INT_BUCK2_OC_MASK BIT(5) 236 #define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) 237 #define TPS65219_INT_BUCK2_UV_MASK BIT(7) 238 /* Thermal Sensor: TPS65219/TPS65215 */ 239 #define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) 240 #define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) 241 /* Thermal Sensor: TPS65219/TPS65215/TPS65214 */ 242 #define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) 243 #define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) 244 #define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) 245 #define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) 246 #define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) 247 #define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) 248 /* Residual Voltage */ 249 #define TPS65219_INT_BUCK1_RV_MASK BIT(0) 250 #define TPS65219_INT_BUCK2_RV_MASK BIT(1) 251 #define TPS65219_INT_BUCK3_RV_MASK BIT(2) 252 #define TPS65219_INT_LDO1_RV_MASK BIT(3) 253 #define TPS65219_INT_LDO2_RV_MASK BIT(4) 254 #define TPS65219_INT_LDO3_RV_MASK BIT(5) 255 #define TPS65215_INT_LDO2_RV_MASK BIT(5) 256 #define TPS65214_INT_LDO2_RV_MASK BIT(5) 257 #define TPS65219_INT_LDO4_RV_MASK BIT(6) 258 /* Residual Voltage ShutDown */ 259 #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) 260 #define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1) 261 #define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2) 262 #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) 263 #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) 264 #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) 265 #define TPS65215_INT_LDO2_RV_SD_MASK BIT(5) 266 #define TPS65214_INT_LDO1_RV_SD_MASK BIT(5) 267 #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) 268 #define TPS65219_INT_TIMEOUT_MASK BIT(7) 269 /* Power Button */ 270 #define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0) 271 #define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1) 272 #define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) 273 274 #define TPS65219_PB_POS 7 275 #define TPS65219_TO_RV_POS 6 276 #define TPS65219_RV_POS 5 277 #define TPS65219_SYS_POS 4 278 #define TPS65219_BUCK_1_2_POS 3 279 #define TPS65219_BUCK_3_POS 2 280 #define TPS65219_LDO_1_2_POS 1 281 #define TPS65219_LDO_3_4_POS 0 282 283 /* IRQs */ 284 enum { 285 /* LDO3-4 register IRQs */ 286 TPS65219_INT_LDO3_SCG, 287 TPS65219_INT_LDO3_OC, 288 TPS65219_INT_LDO3_UV, 289 TPS65219_INT_LDO4_SCG, 290 TPS65219_INT_LDO4_OC, 291 TPS65219_INT_LDO4_UV, 292 /* TPS65215 LDO1*/ 293 TPS65215_INT_LDO1_SCG, 294 TPS65215_INT_LDO1_OC, 295 TPS65215_INT_LDO1_UV, 296 /* TPS65215 LDO2*/ 297 TPS65215_INT_LDO2_SCG, 298 TPS65215_INT_LDO2_OC, 299 TPS65215_INT_LDO2_UV, 300 /* LDO1-2: TPS65219/TPS65214 */ 301 TPS65219_INT_LDO1_SCG, 302 TPS65219_INT_LDO1_OC, 303 TPS65219_INT_LDO1_UV, 304 TPS65219_INT_LDO2_SCG, 305 TPS65219_INT_LDO2_OC, 306 TPS65219_INT_LDO2_UV, 307 /* BUCK3 */ 308 TPS65219_INT_BUCK3_SCG, 309 TPS65219_INT_BUCK3_OC, 310 TPS65219_INT_BUCK3_NEG_OC, 311 TPS65219_INT_BUCK3_UV, 312 /* BUCK1-2 */ 313 TPS65219_INT_BUCK1_SCG, 314 TPS65219_INT_BUCK1_OC, 315 TPS65219_INT_BUCK1_NEG_OC, 316 TPS65219_INT_BUCK1_UV, 317 TPS65219_INT_BUCK2_SCG, 318 TPS65219_INT_BUCK2_OC, 319 TPS65219_INT_BUCK2_NEG_OC, 320 TPS65219_INT_BUCK2_UV, 321 /* Thermal Sensor */ 322 TPS65219_INT_SENSOR_3_WARM, 323 TPS65219_INT_SENSOR_2_WARM, 324 TPS65219_INT_SENSOR_1_WARM, 325 TPS65219_INT_SENSOR_0_WARM, 326 TPS65219_INT_SENSOR_3_HOT, 327 TPS65219_INT_SENSOR_2_HOT, 328 TPS65219_INT_SENSOR_1_HOT, 329 TPS65219_INT_SENSOR_0_HOT, 330 /* Residual Voltage */ 331 TPS65219_INT_BUCK1_RV, 332 TPS65219_INT_BUCK2_RV, 333 TPS65219_INT_BUCK3_RV, 334 TPS65219_INT_LDO1_RV, 335 TPS65219_INT_LDO2_RV, 336 TPS65215_INT_LDO2_RV, 337 TPS65214_INT_LDO2_RV, 338 TPS65219_INT_LDO3_RV, 339 TPS65219_INT_LDO4_RV, 340 /* Residual Voltage ShutDown */ 341 TPS65219_INT_BUCK1_RV_SD, 342 TPS65219_INT_BUCK2_RV_SD, 343 TPS65219_INT_BUCK3_RV_SD, 344 TPS65219_INT_LDO1_RV_SD, 345 TPS65214_INT_LDO1_RV_SD, 346 TPS65215_INT_LDO2_RV_SD, 347 TPS65219_INT_LDO2_RV_SD, 348 TPS65219_INT_LDO3_RV_SD, 349 TPS65219_INT_LDO4_RV_SD, 350 TPS65219_INT_TIMEOUT, 351 /* Power Button */ 352 TPS65219_INT_PB_FALLING_EDGE_DETECT, 353 TPS65219_INT_PB_RISING_EDGE_DETECT, 354 }; 355 356 enum tps65214_regulator_id { 357 /* 358 * DCDC's same as TPS65219 359 * LDO1 maps to TPS65219's LDO3 360 * LDO2 is the same as TPS65219 361 * 362 */ 363 TPS65214_LDO_1 = 3, 364 TPS65214_LDO_2 = 4, 365 }; 366 367 enum tps65215_regulator_id { 368 /* DCDC's same as TPS65219 */ 369 /* LDO1 is the same as TPS65219 */ 370 TPS65215_LDO_2 = 4, 371 }; 372 373 enum tps65219_regulator_id { 374 /* DCDC's */ 375 TPS65219_BUCK_1, 376 TPS65219_BUCK_2, 377 TPS65219_BUCK_3, 378 /* LDOs */ 379 TPS65219_LDO_1, 380 TPS65219_LDO_2, 381 TPS65219_LDO_3, 382 TPS65219_LDO_4, 383 }; 384 385 /* Number of step-down converters available */ 386 #define TPS6521X_NUM_BUCKS 3 387 /* Number of LDO voltage regulators available */ 388 #define TPS65219_NUM_LDO 4 389 #define TPS65215_NUM_LDO 2 390 #define TPS65214_NUM_LDO 2 391 /* Number of total regulators available */ 392 #define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO) 393 #define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO) 394 #define TPS65214_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65214_NUM_LDO) 395 396 /* Define the TPS65214 IRQ numbers */ 397 enum tps65214_irqs { 398 /* INT source registers */ 399 TPS65214_TO_RV_SD_SET_IRQ, 400 TPS65214_RV_SET_IRQ, 401 TPS65214_SYS_SET_IRQ, 402 TPS65214_BUCK_1_2_SET_IRQ, 403 TPS65214_BUCK_3_SET_IRQ, 404 TPS65214_LDO_1_2_SET_IRQ, 405 TPS65214_PB_SET_IRQ = 7, 406 }; 407 408 /* Define the TPS65215 IRQ numbers */ 409 enum tps65215_irqs { 410 /* INT source registers */ 411 TPS65215_TO_RV_SD_SET_IRQ, 412 TPS65215_RV_SET_IRQ, 413 TPS65215_SYS_SET_IRQ, 414 TPS65215_BUCK_1_2_SET_IRQ, 415 TPS65215_BUCK_3_SET_IRQ, 416 TPS65215_LDO_1_SET_IRQ, 417 TPS65215_LDO_2_SET_IRQ, 418 TPS65215_PB_SET_IRQ, 419 }; 420 421 /* Define the TPS65219 IRQ numbers */ 422 enum tps65219_irqs { 423 /* INT source registers */ 424 TPS65219_TO_RV_SD_SET_IRQ, 425 TPS65219_RV_SET_IRQ, 426 TPS65219_SYS_SET_IRQ, 427 TPS65219_BUCK_1_2_SET_IRQ, 428 TPS65219_BUCK_3_SET_IRQ, 429 TPS65219_LDO_1_2_SET_IRQ, 430 TPS65219_LDO_3_4_SET_IRQ, 431 TPS65219_PB_SET_IRQ, 432 }; 433 434 /** 435 * struct tps65219 - tps65219 sub-driver chip access routines 436 * 437 * Device data may be used to access the TPS65219 chip 438 * 439 * @dev: MFD device 440 * @regmap: Regmap for accessing the device registers 441 * @chip_id: Chip ID 442 * @irq_data: Regmap irq data used for the irq chip 443 * @nb: notifier block for the restart handler 444 */ 445 struct tps65219 { 446 struct device *dev; 447 struct regmap *regmap; 448 449 unsigned int chip_id; 450 struct regmap_irq_chip_data *irq_data; 451 struct notifier_block nb; 452 }; 453 454 #endif /* MFD_TPS65219_H */ 455