1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018 Nuvoton Technology corporation.
3 // Copyright (c) 2018 IBM Corp.
4
5 #include <linux/bitops.h>
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 #include <linux/watchdog.h>
15
16 #define NPCM_WTCR 0x1C
17
18 #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
19 #define NPCM_WTE BIT(7) /* Enable */
20 #define NPCM_WTIE BIT(6) /* Enable irq */
21 #define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
22 #define NPCM_WTIF BIT(3) /* Interrupt flag*/
23 #define NPCM_WTRF BIT(2) /* Reset flag */
24 #define NPCM_WTRE BIT(1) /* Reset enable */
25 #define NPCM_WTR BIT(0) /* Reset counter */
26
27 /*
28 * Watchdog timeouts
29 *
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
38 * 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830
39 * 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10
40 * 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20
41 * 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30
42 */
43
44 struct npcm_wdt {
45 struct watchdog_device wdd;
46 void __iomem *reg;
47 struct clk *clk;
48 };
49
to_npcm_wdt(struct watchdog_device * wdd)50 static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)
51 {
52 return container_of(wdd, struct npcm_wdt, wdd);
53 }
54
npcm_wdt_ping(struct watchdog_device * wdd)55 static int npcm_wdt_ping(struct watchdog_device *wdd)
56 {
57 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
58 u32 val;
59
60 val = readl(wdt->reg);
61 writel(val | NPCM_WTR, wdt->reg);
62
63 return 0;
64 }
65
npcm_wdt_start(struct watchdog_device * wdd)66 static int npcm_wdt_start(struct watchdog_device *wdd)
67 {
68 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
69 u32 val;
70
71 clk_prepare_enable(wdt->clk);
72
73 if (wdd->timeout < 2)
74 val = 0x800;
75 else if (wdd->timeout < 3)
76 val = 0x420;
77 else if (wdd->timeout < 6)
78 val = 0x810;
79 else if (wdd->timeout < 11)
80 val = 0x430;
81 else if (wdd->timeout < 22)
82 val = 0x820;
83 else if (wdd->timeout < 44)
84 val = 0xC00;
85 else if (wdd->timeout < 87)
86 val = 0x830;
87 else if (wdd->timeout < 173)
88 val = 0xC10;
89 else if (wdd->timeout < 688)
90 val = 0xC20;
91 else
92 val = 0xC30;
93
94 val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
95
96 writel(val, wdt->reg);
97
98 return 0;
99 }
100
npcm_wdt_stop(struct watchdog_device * wdd)101 static int npcm_wdt_stop(struct watchdog_device *wdd)
102 {
103 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
104
105 writel(0, wdt->reg);
106
107 clk_disable_unprepare(wdt->clk);
108
109 return 0;
110 }
111
npcm_wdt_set_timeout(struct watchdog_device * wdd,unsigned int timeout)112 static int npcm_wdt_set_timeout(struct watchdog_device *wdd,
113 unsigned int timeout)
114 {
115 if (timeout < 2)
116 wdd->timeout = 1;
117 else if (timeout < 3)
118 wdd->timeout = 2;
119 else if (timeout < 6)
120 wdd->timeout = 5;
121 else if (timeout < 11)
122 wdd->timeout = 10;
123 else if (timeout < 22)
124 wdd->timeout = 21;
125 else if (timeout < 44)
126 wdd->timeout = 43;
127 else if (timeout < 87)
128 wdd->timeout = 86;
129 else if (timeout < 173)
130 wdd->timeout = 172;
131 else if (timeout < 688)
132 wdd->timeout = 687;
133 else
134 wdd->timeout = 2750;
135
136 if (watchdog_active(wdd))
137 npcm_wdt_start(wdd);
138
139 return 0;
140 }
141
npcm_wdt_interrupt(int irq,void * data)142 static irqreturn_t npcm_wdt_interrupt(int irq, void *data)
143 {
144 struct npcm_wdt *wdt = data;
145
146 watchdog_notify_pretimeout(&wdt->wdd);
147
148 return IRQ_HANDLED;
149 }
150
npcm_wdt_restart(struct watchdog_device * wdd,unsigned long action,void * data)151 static int npcm_wdt_restart(struct watchdog_device *wdd,
152 unsigned long action, void *data)
153 {
154 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
155
156 /* For reset, we start the WDT clock and leave it running. */
157 clk_prepare_enable(wdt->clk);
158
159 writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
160 udelay(1000);
161
162 return 0;
163 }
164
npcm_is_running(struct watchdog_device * wdd)165 static bool npcm_is_running(struct watchdog_device *wdd)
166 {
167 struct npcm_wdt *wdt = to_npcm_wdt(wdd);
168
169 return readl(wdt->reg) & NPCM_WTE;
170 }
171
172 static const struct watchdog_info npcm_wdt_info = {
173 .identity = KBUILD_MODNAME,
174 .options = WDIOF_SETTIMEOUT
175 | WDIOF_KEEPALIVEPING
176 | WDIOF_MAGICCLOSE,
177 };
178
179 static const struct watchdog_ops npcm_wdt_ops = {
180 .owner = THIS_MODULE,
181 .start = npcm_wdt_start,
182 .stop = npcm_wdt_stop,
183 .ping = npcm_wdt_ping,
184 .set_timeout = npcm_wdt_set_timeout,
185 .restart = npcm_wdt_restart,
186 };
187
npcm_wdt_probe(struct platform_device * pdev)188 static int npcm_wdt_probe(struct platform_device *pdev)
189 {
190 struct device *dev = &pdev->dev;
191 struct npcm_wdt *wdt;
192 int irq;
193 int ret;
194
195 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
196 if (!wdt)
197 return -ENOMEM;
198
199 wdt->reg = devm_platform_ioremap_resource(pdev, 0);
200 if (IS_ERR(wdt->reg))
201 return PTR_ERR(wdt->reg);
202
203 wdt->clk = devm_clk_get_optional(&pdev->dev, NULL);
204 if (IS_ERR(wdt->clk))
205 return PTR_ERR(wdt->clk);
206
207 irq = platform_get_irq(pdev, 0);
208 if (irq < 0)
209 return irq;
210
211 wdt->wdd.info = &npcm_wdt_info;
212 wdt->wdd.ops = &npcm_wdt_ops;
213 wdt->wdd.min_timeout = 1;
214 wdt->wdd.max_timeout = 2750;
215 wdt->wdd.parent = dev;
216
217 wdt->wdd.timeout = 86;
218 watchdog_init_timeout(&wdt->wdd, 0, dev);
219
220 /* Ensure timeout is able to be represented by the hardware */
221 npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
222
223 if (npcm_is_running(&wdt->wdd)) {
224 /* Restart with the default or device-tree specified timeout */
225 npcm_wdt_start(&wdt->wdd);
226 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
227 }
228
229 ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, "watchdog",
230 wdt);
231 if (ret)
232 return ret;
233
234 ret = devm_watchdog_register_device(dev, &wdt->wdd);
235 if (ret)
236 return ret;
237
238 dev_info(dev, "NPCM watchdog driver enabled\n");
239
240 return 0;
241 }
242
243 #ifdef CONFIG_OF
244 static const struct of_device_id npcm_wdt_match[] = {
245 {.compatible = "nuvoton,wpcm450-wdt"},
246 {.compatible = "nuvoton,npcm750-wdt"},
247 {},
248 };
249 MODULE_DEVICE_TABLE(of, npcm_wdt_match);
250 #endif
251
252 static struct platform_driver npcm_wdt_driver = {
253 .probe = npcm_wdt_probe,
254 .driver = {
255 .name = "npcm-wdt",
256 .of_match_table = of_match_ptr(npcm_wdt_match),
257 },
258 };
259 module_platform_driver(npcm_wdt_driver);
260
261 MODULE_AUTHOR("Joel Stanley");
262 MODULE_DESCRIPTION("Watchdog driver for NPCM");
263 MODULE_LICENSE("GPL v2");
264