1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * xHCI host controller driver
4  *
5  * Copyright (C) 2008 Intel Corp.
6  *
7  * Author: Sarah Sharp
8  * Some code borrowed from the Linux EHCI driver.
9  */
10 
11 /*
12  * Ring initialization rules:
13  * 1. Each segment is initialized to zero, except for link TRBs.
14  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
15  *    Consumer Cycle State (CCS), depending on ring function.
16  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
17  *
18  * Ring behavior rules:
19  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
20  *    least one free TRB in the ring.  This is useful if you want to turn that
21  *    into a link TRB and expand the ring.
22  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23  *    link TRB, then load the pointer with the address in the link TRB.  If the
24  *    link TRB had its toggle bit set, you may need to update the ring cycle
25  *    state (see cycle bit rules).  You may have to do this multiple times
26  *    until you reach a non-link TRB.
27  * 3. A ring is full if enqueue++ (for the definition of increment above)
28  *    equals the dequeue pointer.
29  *
30  * Cycle bit rules:
31  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32  *    in a link TRB, it must toggle the ring cycle state.
33  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34  *    in a link TRB, it must toggle the ring cycle state.
35  *
36  * Producer rules:
37  * 1. Check if ring is full before you enqueue.
38  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39  *    Update enqueue pointer between each write (which may update the ring
40  *    cycle state).
41  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
42  *    and endpoint rings.  If HC is the producer for the event ring,
43  *    and it generates an interrupt according to interrupt modulation rules.
44  *
45  * Consumer rules:
46  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
47  *    the TRB is owned by the consumer.
48  * 2. Update dequeue pointer (which may update the ring cycle state) and
49  *    continue processing TRBs until you reach a TRB which is not owned by you.
50  * 3. Notify the producer.  SW is the consumer for the event ring, and it
51  *   updates event ring dequeue pointer.  HC is the consumer for the command and
52  *   endpoint rings; it generates events on the event ring for these.
53  */
54 
55 #include <linux/jiffies.h>
56 #include <linux/scatterlist.h>
57 #include <linux/slab.h>
58 #include <linux/string_choices.h>
59 #include <linux/dma-mapping.h>
60 #include "xhci.h"
61 #include "xhci-trace.h"
62 
63 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
64 			 u32 field1, u32 field2,
65 			 u32 field3, u32 field4, bool command_must_succeed);
66 
67 /*
68  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
69  * address of the TRB.
70  */
xhci_trb_virt_to_dma(struct xhci_segment * seg,union xhci_trb * trb)71 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
72 		union xhci_trb *trb)
73 {
74 	unsigned long segment_offset;
75 
76 	if (!seg || !trb || trb < seg->trbs)
77 		return 0;
78 	/* offset in TRBs */
79 	segment_offset = trb - seg->trbs;
80 	if (segment_offset >= TRBS_PER_SEGMENT)
81 		return 0;
82 	return seg->dma + (segment_offset * sizeof(*trb));
83 }
84 
trb_is_noop(union xhci_trb * trb)85 static bool trb_is_noop(union xhci_trb *trb)
86 {
87 	return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
88 }
89 
trb_is_link(union xhci_trb * trb)90 static bool trb_is_link(union xhci_trb *trb)
91 {
92 	return TRB_TYPE_LINK_LE32(trb->link.control);
93 }
94 
last_trb_on_seg(struct xhci_segment * seg,union xhci_trb * trb)95 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
96 {
97 	return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
98 }
99 
last_trb_on_ring(struct xhci_ring * ring,struct xhci_segment * seg,union xhci_trb * trb)100 static bool last_trb_on_ring(struct xhci_ring *ring,
101 			struct xhci_segment *seg, union xhci_trb *trb)
102 {
103 	return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
104 }
105 
link_trb_toggles_cycle(union xhci_trb * trb)106 static bool link_trb_toggles_cycle(union xhci_trb *trb)
107 {
108 	return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
109 }
110 
last_td_in_urb(struct xhci_td * td)111 static bool last_td_in_urb(struct xhci_td *td)
112 {
113 	struct urb_priv *urb_priv = td->urb->hcpriv;
114 
115 	return urb_priv->num_tds_done == urb_priv->num_tds;
116 }
117 
unhandled_event_trb(struct xhci_ring * ring)118 static bool unhandled_event_trb(struct xhci_ring *ring)
119 {
120 	return ((le32_to_cpu(ring->dequeue->event_cmd.flags) & TRB_CYCLE) ==
121 		ring->cycle_state);
122 }
123 
inc_td_cnt(struct urb * urb)124 static void inc_td_cnt(struct urb *urb)
125 {
126 	struct urb_priv *urb_priv = urb->hcpriv;
127 
128 	urb_priv->num_tds_done++;
129 }
130 
trb_to_noop(union xhci_trb * trb,u32 noop_type)131 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
132 {
133 	if (trb_is_link(trb)) {
134 		/* unchain chained link TRBs */
135 		trb->link.control &= cpu_to_le32(~TRB_CHAIN);
136 	} else {
137 		trb->generic.field[0] = 0;
138 		trb->generic.field[1] = 0;
139 		trb->generic.field[2] = 0;
140 		/* Preserve only the cycle bit of this TRB */
141 		trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
142 		trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
143 	}
144 }
145 
146 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
147  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
148  * effect the ring dequeue or enqueue pointers.
149  */
next_trb(struct xhci_segment ** seg,union xhci_trb ** trb)150 static void next_trb(struct xhci_segment **seg,
151 			union xhci_trb **trb)
152 {
153 	if (trb_is_link(*trb) || last_trb_on_seg(*seg, *trb)) {
154 		*seg = (*seg)->next;
155 		*trb = ((*seg)->trbs);
156 	} else {
157 		(*trb)++;
158 	}
159 }
160 
161 /*
162  * See Cycle bit rules. SW is the consumer for the event ring only.
163  */
inc_deq(struct xhci_hcd * xhci,struct xhci_ring * ring)164 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
165 {
166 	unsigned int link_trb_count = 0;
167 
168 	/* event ring doesn't have link trbs, check for last trb */
169 	if (ring->type == TYPE_EVENT) {
170 		if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
171 			ring->dequeue++;
172 			return;
173 		}
174 		if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
175 			ring->cycle_state ^= 1;
176 		ring->deq_seg = ring->deq_seg->next;
177 		ring->dequeue = ring->deq_seg->trbs;
178 
179 		trace_xhci_inc_deq(ring);
180 
181 		return;
182 	}
183 
184 	/* All other rings have link trbs */
185 	if (!trb_is_link(ring->dequeue)) {
186 		if (last_trb_on_seg(ring->deq_seg, ring->dequeue))
187 			xhci_warn(xhci, "Missing link TRB at end of segment\n");
188 		else
189 			ring->dequeue++;
190 	}
191 
192 	while (trb_is_link(ring->dequeue)) {
193 		ring->deq_seg = ring->deq_seg->next;
194 		ring->dequeue = ring->deq_seg->trbs;
195 
196 		trace_xhci_inc_deq(ring);
197 
198 		if (link_trb_count++ > ring->num_segs) {
199 			xhci_warn(xhci, "Ring is an endless link TRB loop\n");
200 			break;
201 		}
202 	}
203 	return;
204 }
205 
206 /*
207  * If enqueue points at a link TRB, follow links until an ordinary TRB is reached.
208  * Toggle the cycle bit of passed link TRBs and optionally chain them.
209  */
inc_enq_past_link(struct xhci_hcd * xhci,struct xhci_ring * ring,u32 chain)210 static void inc_enq_past_link(struct xhci_hcd *xhci, struct xhci_ring *ring, u32 chain)
211 {
212 	unsigned int link_trb_count = 0;
213 
214 	while (trb_is_link(ring->enqueue)) {
215 
216 		/*
217 		 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
218 		 * set, but other sections talk about dealing with the chain bit set. This was
219 		 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
220 		 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
221 		 *
222 		 * On 0.95 and some 0.96 HCs the chain bit is set once at segment initalization
223 		 * and never changed here. On all others, modify it as requested by the caller.
224 		 */
225 		if (!xhci_link_chain_quirk(xhci, ring->type)) {
226 			ring->enqueue->link.control &= cpu_to_le32(~TRB_CHAIN);
227 			ring->enqueue->link.control |= cpu_to_le32(chain);
228 		}
229 
230 		/* Give this link TRB to the hardware */
231 		wmb();
232 		ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
233 
234 		/* Toggle the cycle bit after the last ring segment. */
235 		if (link_trb_toggles_cycle(ring->enqueue))
236 			ring->cycle_state ^= 1;
237 
238 		ring->enq_seg = ring->enq_seg->next;
239 		ring->enqueue = ring->enq_seg->trbs;
240 
241 		trace_xhci_inc_enq(ring);
242 
243 		if (link_trb_count++ > ring->num_segs) {
244 			xhci_warn(xhci, "Link TRB loop at enqueue\n");
245 			break;
246 		}
247 	}
248 }
249 
250 /*
251  * See Cycle bit rules. SW is the consumer for the event ring only.
252  *
253  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
254  * chain bit is set), then set the chain bit in all the following link TRBs.
255  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
256  * have their chain bit cleared (so that each Link TRB is a separate TD).
257  *
258  * @more_trbs_coming:	Will you enqueue more TRBs before calling
259  *			prepare_transfer()?
260  */
inc_enq(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming)261 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
262 			bool more_trbs_coming)
263 {
264 	u32 chain;
265 
266 	chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
267 
268 	if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
269 		xhci_err(xhci, "Tried to move enqueue past ring segment\n");
270 		return;
271 	}
272 
273 	ring->enqueue++;
274 
275 	/*
276 	 * If we are in the middle of a TD or the caller plans to enqueue more
277 	 * TDs as one transfer (eg. control), traverse any link TRBs right now.
278 	 * Otherwise, enqueue can stay on a link until the next prepare_ring().
279 	 * This avoids enqueue entering deq_seg and simplifies ring expansion.
280 	 */
281 	if (trb_is_link(ring->enqueue) && (chain || more_trbs_coming))
282 		inc_enq_past_link(xhci, ring, chain);
283 }
284 
285 /*
286  * If the suspect DMA address is a TRB in this TD, this function returns that
287  * TRB's segment. Otherwise it returns 0.
288  */
trb_in_td(struct xhci_td * td,dma_addr_t suspect_dma)289 static struct xhci_segment *trb_in_td(struct xhci_td *td, dma_addr_t suspect_dma)
290 {
291 	dma_addr_t start_dma;
292 	dma_addr_t end_seg_dma;
293 	dma_addr_t end_trb_dma;
294 	struct xhci_segment *cur_seg;
295 
296 	start_dma = xhci_trb_virt_to_dma(td->start_seg, td->start_trb);
297 	cur_seg = td->start_seg;
298 
299 	do {
300 		if (start_dma == 0)
301 			return NULL;
302 		/* We may get an event for a Link TRB in the middle of a TD */
303 		end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
304 				&cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
305 		/* If the end TRB isn't in this segment, this is set to 0 */
306 		end_trb_dma = xhci_trb_virt_to_dma(cur_seg, td->end_trb);
307 
308 		if (end_trb_dma > 0) {
309 			/* The end TRB is in this segment, so suspect should be here */
310 			if (start_dma <= end_trb_dma) {
311 				if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
312 					return cur_seg;
313 			} else {
314 				/* Case for one segment with
315 				 * a TD wrapped around to the top
316 				 */
317 				if ((suspect_dma >= start_dma &&
318 							suspect_dma <= end_seg_dma) ||
319 						(suspect_dma >= cur_seg->dma &&
320 						 suspect_dma <= end_trb_dma))
321 					return cur_seg;
322 			}
323 			return NULL;
324 		}
325 		/* Might still be somewhere in this segment */
326 		if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
327 			return cur_seg;
328 
329 		cur_seg = cur_seg->next;
330 		start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
331 	} while (cur_seg != td->start_seg);
332 
333 	return NULL;
334 }
335 
336 /*
337  * Return number of free normal TRBs from enqueue to dequeue pointer on ring.
338  * Not counting an assumed link TRB at end of each TRBS_PER_SEGMENT sized segment.
339  * Only for transfer and command rings where driver is the producer, not for
340  * event rings.
341  */
xhci_num_trbs_free(struct xhci_ring * ring)342 static unsigned int xhci_num_trbs_free(struct xhci_ring *ring)
343 {
344 	struct xhci_segment *enq_seg = ring->enq_seg;
345 	union xhci_trb *enq = ring->enqueue;
346 	union xhci_trb *last_on_seg;
347 	unsigned int free = 0;
348 	int i = 0;
349 
350 	/* Ring might be empty even if enq != deq if enq is left on a link trb */
351 	if (trb_is_link(enq)) {
352 		enq_seg = enq_seg->next;
353 		enq = enq_seg->trbs;
354 	}
355 
356 	/* Empty ring, common case, don't walk the segments */
357 	if (enq == ring->dequeue)
358 		return ring->num_segs * (TRBS_PER_SEGMENT - 1);
359 
360 	do {
361 		if (ring->deq_seg == enq_seg && ring->dequeue >= enq)
362 			return free + (ring->dequeue - enq);
363 		last_on_seg = &enq_seg->trbs[TRBS_PER_SEGMENT - 1];
364 		free += last_on_seg - enq;
365 		enq_seg = enq_seg->next;
366 		enq = enq_seg->trbs;
367 	} while (i++ < ring->num_segs);
368 
369 	return free;
370 }
371 
372 /*
373  * Check to see if there's room to enqueue num_trbs on the ring and make sure
374  * enqueue pointer will not advance into dequeue segment. See rules above.
375  * return number of new segments needed to ensure this.
376  */
377 
xhci_ring_expansion_needed(struct xhci_hcd * xhci,struct xhci_ring * ring,unsigned int num_trbs)378 static unsigned int xhci_ring_expansion_needed(struct xhci_hcd *xhci, struct xhci_ring *ring,
379 					       unsigned int num_trbs)
380 {
381 	struct xhci_segment *seg;
382 	int trbs_past_seg;
383 	int enq_used;
384 	int new_segs;
385 
386 	enq_used = ring->enqueue - ring->enq_seg->trbs;
387 
388 	/* how many trbs will be queued past the enqueue segment? */
389 	trbs_past_seg = enq_used + num_trbs - (TRBS_PER_SEGMENT - 1);
390 
391 	/*
392 	 * Consider expanding the ring already if num_trbs fills the current
393 	 * segment (i.e. trbs_past_seg == 0), not only when num_trbs goes into
394 	 * the next segment. Avoids confusing full ring with special empty ring
395 	 * case below
396 	 */
397 	if (trbs_past_seg < 0)
398 		return 0;
399 
400 	/* Empty ring special case, enqueue stuck on link trb while dequeue advanced */
401 	if (trb_is_link(ring->enqueue) && ring->enq_seg->next->trbs == ring->dequeue)
402 		return 0;
403 
404 	new_segs = 1 + (trbs_past_seg / (TRBS_PER_SEGMENT - 1));
405 	seg = ring->enq_seg;
406 
407 	while (new_segs > 0) {
408 		seg = seg->next;
409 		if (seg == ring->deq_seg) {
410 			xhci_dbg(xhci, "Adding %d trbs requires expanding ring by %d segments\n",
411 				 num_trbs, new_segs);
412 			return new_segs;
413 		}
414 		new_segs--;
415 	}
416 
417 	return 0;
418 }
419 
420 /* Ring the host controller doorbell after placing a command on the ring */
xhci_ring_cmd_db(struct xhci_hcd * xhci)421 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
422 {
423 	if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
424 		return;
425 
426 	xhci_dbg(xhci, "// Ding dong!\n");
427 
428 	trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
429 
430 	writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
431 	/* Flush PCI posted writes */
432 	readl(&xhci->dba->doorbell[0]);
433 }
434 
xhci_mod_cmd_timer(struct xhci_hcd * xhci)435 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci)
436 {
437 	return mod_delayed_work(system_wq, &xhci->cmd_timer,
438 			msecs_to_jiffies(xhci->current_cmd->timeout_ms));
439 }
440 
xhci_next_queued_cmd(struct xhci_hcd * xhci)441 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
442 {
443 	return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
444 					cmd_list);
445 }
446 
447 /*
448  * Turn all commands on command ring with status set to "aborted" to no-op trbs.
449  * If there are other commands waiting then restart the ring and kick the timer.
450  * This must be called with command ring stopped and xhci->lock held.
451  */
xhci_handle_stopped_cmd_ring(struct xhci_hcd * xhci,struct xhci_command * cur_cmd)452 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
453 					 struct xhci_command *cur_cmd)
454 {
455 	struct xhci_command *i_cmd;
456 
457 	/* Turn all aborted commands in list to no-ops, then restart */
458 	list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
459 
460 		if (i_cmd->status != COMP_COMMAND_ABORTED)
461 			continue;
462 
463 		i_cmd->status = COMP_COMMAND_RING_STOPPED;
464 
465 		xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
466 			 i_cmd->command_trb);
467 
468 		trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
469 
470 		/*
471 		 * caller waiting for completion is called when command
472 		 *  completion event is received for these no-op commands
473 		 */
474 	}
475 
476 	xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
477 
478 	/* ring command ring doorbell to restart the command ring */
479 	if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
480 	    !(xhci->xhc_state & XHCI_STATE_DYING)) {
481 		xhci->current_cmd = cur_cmd;
482 		if (cur_cmd)
483 			xhci_mod_cmd_timer(xhci);
484 		xhci_ring_cmd_db(xhci);
485 	}
486 }
487 
488 /* Must be called with xhci->lock held, releases and acquires lock back */
xhci_abort_cmd_ring(struct xhci_hcd * xhci,unsigned long flags)489 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
490 {
491 	struct xhci_segment *new_seg	= xhci->cmd_ring->deq_seg;
492 	union xhci_trb *new_deq		= xhci->cmd_ring->dequeue;
493 	u64 crcr;
494 	int ret;
495 
496 	xhci_dbg(xhci, "Abort command ring\n");
497 
498 	reinit_completion(&xhci->cmd_ring_stop_completion);
499 
500 	/*
501 	 * The control bits like command stop, abort are located in lower
502 	 * dword of the command ring control register.
503 	 * Some controllers require all 64 bits to be written to abort the ring.
504 	 * Make sure the upper dword is valid, pointing to the next command,
505 	 * avoiding corrupting the command ring pointer in case the command ring
506 	 * is stopped by the time the upper dword is written.
507 	 */
508 	next_trb(&new_seg, &new_deq);
509 	if (trb_is_link(new_deq))
510 		next_trb(&new_seg, &new_deq);
511 
512 	crcr = xhci_trb_virt_to_dma(new_seg, new_deq);
513 	xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
514 
515 	/* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
516 	 * completion of the Command Abort operation. If CRR is not negated in 5
517 	 * seconds then driver handles it as if host died (-ENODEV).
518 	 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
519 	 * and try to recover a -ETIMEDOUT with a host controller reset.
520 	 */
521 	ret = xhci_handshake_check_state(xhci, &xhci->op_regs->cmd_ring,
522 			CMD_RING_RUNNING, 0, 5 * 1000 * 1000,
523 			XHCI_STATE_REMOVING);
524 	if (ret < 0) {
525 		xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
526 		xhci_halt(xhci);
527 		xhci_hc_died(xhci);
528 		return ret;
529 	}
530 	/*
531 	 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
532 	 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
533 	 * but the completion event in never sent. Wait 2 secs (arbitrary
534 	 * number) to handle those cases after negation of CMD_RING_RUNNING.
535 	 */
536 	spin_unlock_irqrestore(&xhci->lock, flags);
537 	ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
538 					  msecs_to_jiffies(2000));
539 	spin_lock_irqsave(&xhci->lock, flags);
540 	if (!ret) {
541 		xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
542 		xhci_cleanup_command_queue(xhci);
543 	} else {
544 		xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
545 	}
546 	return 0;
547 }
548 
xhci_ring_ep_doorbell(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)549 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
550 		unsigned int slot_id,
551 		unsigned int ep_index,
552 		unsigned int stream_id)
553 {
554 	__le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
555 	struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
556 	unsigned int ep_state = ep->ep_state;
557 
558 	/* Don't ring the doorbell for this endpoint if there are pending
559 	 * cancellations because we don't want to interrupt processing.
560 	 * We don't want to restart any stream rings if there's a set dequeue
561 	 * pointer command pending because the device can choose to start any
562 	 * stream once the endpoint is on the HW schedule.
563 	 */
564 	if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
565 	    (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
566 		return;
567 
568 	trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
569 
570 	writel(DB_VALUE(ep_index, stream_id), db_addr);
571 	/* flush the write */
572 	readl(db_addr);
573 }
574 
575 /* Ring the doorbell for any rings with pending URBs */
ring_doorbell_for_active_rings(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)576 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
577 		unsigned int slot_id,
578 		unsigned int ep_index)
579 {
580 	unsigned int stream_id;
581 	struct xhci_virt_ep *ep;
582 
583 	ep = &xhci->devs[slot_id]->eps[ep_index];
584 
585 	/* A ring has pending URBs if its TD list is not empty */
586 	if (!(ep->ep_state & EP_HAS_STREAMS)) {
587 		if (ep->ring && !(list_empty(&ep->ring->td_list)))
588 			xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
589 		return;
590 	}
591 
592 	for (stream_id = 1; stream_id < ep->stream_info->num_streams;
593 			stream_id++) {
594 		struct xhci_stream_info *stream_info = ep->stream_info;
595 		if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
596 			xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
597 						stream_id);
598 	}
599 }
600 
xhci_ring_doorbell_for_active_rings(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)601 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
602 		unsigned int slot_id,
603 		unsigned int ep_index)
604 {
605 	ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
606 }
607 
xhci_get_virt_ep(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)608 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
609 					     unsigned int slot_id,
610 					     unsigned int ep_index)
611 {
612 	if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
613 		xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
614 		return NULL;
615 	}
616 	if (ep_index >= EP_CTX_PER_DEV) {
617 		xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
618 		return NULL;
619 	}
620 	if (!xhci->devs[slot_id]) {
621 		xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
622 		return NULL;
623 	}
624 
625 	return &xhci->devs[slot_id]->eps[ep_index];
626 }
627 
xhci_virt_ep_to_ring(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,unsigned int stream_id)628 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
629 					      struct xhci_virt_ep *ep,
630 					      unsigned int stream_id)
631 {
632 	/* common case, no streams */
633 	if (!(ep->ep_state & EP_HAS_STREAMS))
634 		return ep->ring;
635 
636 	if (!ep->stream_info)
637 		return NULL;
638 
639 	if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
640 		xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
641 			  stream_id, ep->vdev->slot_id, ep->ep_index);
642 		return NULL;
643 	}
644 
645 	return ep->stream_info->stream_rings[stream_id];
646 }
647 
648 /* Get the right ring for the given slot_id, ep_index and stream_id.
649  * If the endpoint supports streams, boundary check the URB's stream ID.
650  * If the endpoint doesn't support streams, return the singular endpoint ring.
651  */
xhci_triad_to_transfer_ring(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)652 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
653 		unsigned int slot_id, unsigned int ep_index,
654 		unsigned int stream_id)
655 {
656 	struct xhci_virt_ep *ep;
657 
658 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
659 	if (!ep)
660 		return NULL;
661 
662 	return xhci_virt_ep_to_ring(xhci, ep, stream_id);
663 }
664 
665 
666 /*
667  * Get the hw dequeue pointer xHC stopped on, either directly from the
668  * endpoint context, or if streams are in use from the stream context.
669  * The returned hw_dequeue contains the lowest four bits with cycle state
670  * and possbile stream context type.
671  */
xhci_get_hw_deq(struct xhci_hcd * xhci,struct xhci_virt_device * vdev,unsigned int ep_index,unsigned int stream_id)672 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
673 			   unsigned int ep_index, unsigned int stream_id)
674 {
675 	struct xhci_ep_ctx *ep_ctx;
676 	struct xhci_stream_ctx *st_ctx;
677 	struct xhci_virt_ep *ep;
678 
679 	ep = &vdev->eps[ep_index];
680 
681 	if (ep->ep_state & EP_HAS_STREAMS) {
682 		st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
683 		return le64_to_cpu(st_ctx->stream_ring);
684 	}
685 	ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
686 	return le64_to_cpu(ep_ctx->deq);
687 }
688 
xhci_move_dequeue_past_td(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_td * td)689 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
690 				unsigned int slot_id, unsigned int ep_index,
691 				unsigned int stream_id, struct xhci_td *td)
692 {
693 	struct xhci_virt_device *dev = xhci->devs[slot_id];
694 	struct xhci_virt_ep *ep = &dev->eps[ep_index];
695 	struct xhci_ring *ep_ring;
696 	struct xhci_command *cmd;
697 	struct xhci_segment *new_seg;
698 	union xhci_trb *new_deq;
699 	int new_cycle;
700 	dma_addr_t addr;
701 	u64 hw_dequeue;
702 	bool hw_dequeue_found = false;
703 	bool td_last_trb_found = false;
704 	u32 trb_sct = 0;
705 	int ret;
706 
707 	ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
708 			ep_index, stream_id);
709 	if (!ep_ring) {
710 		xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
711 			  stream_id);
712 		return -ENODEV;
713 	}
714 
715 	hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
716 	new_seg = ep_ring->deq_seg;
717 	new_deq = ep_ring->dequeue;
718 	new_cycle = le32_to_cpu(td->end_trb->generic.field[3]) & TRB_CYCLE;
719 
720 	/*
721 	 * Walk the ring until both the next TRB and hw_dequeue are found (don't
722 	 * move hw_dequeue back if it went forward due to a HW bug). Cycle state
723 	 * is loaded from a known good TRB, track later toggles to maintain it.
724 	 */
725 	do {
726 		if (!hw_dequeue_found && xhci_trb_virt_to_dma(new_seg, new_deq)
727 		    == (dma_addr_t)(hw_dequeue & ~0xf)) {
728 			hw_dequeue_found = true;
729 			if (td_last_trb_found)
730 				break;
731 		}
732 		if (new_deq == td->end_trb)
733 			td_last_trb_found = true;
734 
735 		if (td_last_trb_found && trb_is_link(new_deq) &&
736 		    link_trb_toggles_cycle(new_deq))
737 			new_cycle ^= 0x1;
738 
739 		next_trb(&new_seg, &new_deq);
740 
741 		/* Search wrapped around, bail out */
742 		if (new_deq == ep->ring->dequeue) {
743 			xhci_err(xhci, "Error: Failed finding new dequeue state\n");
744 			return -EINVAL;
745 		}
746 
747 	} while (!hw_dequeue_found || !td_last_trb_found);
748 
749 	/* Don't update the ring cycle state for the producer (us). */
750 	addr = xhci_trb_virt_to_dma(new_seg, new_deq);
751 	if (addr == 0) {
752 		xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
753 		xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
754 		return -EINVAL;
755 	}
756 
757 	if ((ep->ep_state & SET_DEQ_PENDING)) {
758 		xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
759 			  &addr);
760 		return -EBUSY;
761 	}
762 
763 	/* This function gets called from contexts where it cannot sleep */
764 	cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
765 	if (!cmd) {
766 		xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
767 		return -ENOMEM;
768 	}
769 
770 	if (stream_id)
771 		trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
772 	ret = queue_command(xhci, cmd,
773 		lower_32_bits(addr) | trb_sct | new_cycle,
774 		upper_32_bits(addr),
775 		STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
776 		EP_INDEX_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
777 	if (ret < 0) {
778 		xhci_free_command(xhci, cmd);
779 		return ret;
780 	}
781 	ep->queued_deq_seg = new_seg;
782 	ep->queued_deq_ptr = new_deq;
783 
784 	xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
785 		       "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
786 
787 	/* Stop the TD queueing code from ringing the doorbell until
788 	 * this command completes.  The HC won't set the dequeue pointer
789 	 * if the ring is running, and ringing the doorbell starts the
790 	 * ring running.
791 	 */
792 	ep->ep_state |= SET_DEQ_PENDING;
793 	xhci_ring_cmd_db(xhci);
794 	return 0;
795 }
796 
797 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
798  * (The last TRB actually points to the ring enqueue pointer, which is not part
799  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
800  */
td_to_noop(struct xhci_td * td,bool flip_cycle)801 static void td_to_noop(struct xhci_td *td, bool flip_cycle)
802 {
803 	struct xhci_segment *seg	= td->start_seg;
804 	union xhci_trb *trb		= td->start_trb;
805 
806 	while (1) {
807 		trb_to_noop(trb, TRB_TR_NOOP);
808 
809 		/* flip cycle if asked to */
810 		if (flip_cycle && trb != td->start_trb && trb != td->end_trb)
811 			trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
812 
813 		if (trb == td->end_trb)
814 			break;
815 
816 		next_trb(&seg, &trb);
817 	}
818 }
819 
xhci_giveback_urb_in_irq(struct xhci_hcd * xhci,struct xhci_td * cur_td,int status)820 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
821 				     struct xhci_td *cur_td, int status)
822 {
823 	struct urb	*urb		= cur_td->urb;
824 	struct urb_priv	*urb_priv	= urb->hcpriv;
825 	struct usb_hcd	*hcd		= bus_to_hcd(urb->dev->bus);
826 
827 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
828 		xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
829 		if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs	== 0) {
830 			if (xhci->quirks & XHCI_AMD_PLL_FIX)
831 				usb_amd_quirk_pll_enable();
832 		}
833 	}
834 	xhci_urb_free_priv(urb_priv);
835 	usb_hcd_unlink_urb_from_ep(hcd, urb);
836 	trace_xhci_urb_giveback(urb);
837 	usb_hcd_giveback_urb(hcd, urb, status);
838 }
839 
xhci_unmap_td_bounce_buffer(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_td * td)840 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
841 		struct xhci_ring *ring, struct xhci_td *td)
842 {
843 	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
844 	struct xhci_segment *seg = td->bounce_seg;
845 	struct urb *urb = td->urb;
846 	size_t len;
847 
848 	if (!ring || !seg || !urb)
849 		return;
850 
851 	if (usb_urb_dir_out(urb)) {
852 		dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
853 				 DMA_TO_DEVICE);
854 		return;
855 	}
856 
857 	dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
858 			 DMA_FROM_DEVICE);
859 	/* for in transfers we need to copy the data from bounce to sg */
860 	if (urb->num_sgs) {
861 		len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
862 					   seg->bounce_len, seg->bounce_offs);
863 		if (len != seg->bounce_len)
864 			xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
865 				  len, seg->bounce_len);
866 	} else {
867 		memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
868 		       seg->bounce_len);
869 	}
870 	seg->bounce_len = 0;
871 	seg->bounce_offs = 0;
872 }
873 
xhci_td_cleanup(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_ring * ep_ring,int status)874 static void xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
875 			    struct xhci_ring *ep_ring, int status)
876 {
877 	struct urb *urb = NULL;
878 
879 	/* Clean up the endpoint's TD list */
880 	urb = td->urb;
881 
882 	/* if a bounce buffer was used to align this td then unmap it */
883 	xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
884 
885 	/* Do one last check of the actual transfer length.
886 	 * If the host controller said we transferred more data than the buffer
887 	 * length, urb->actual_length will be a very big number (since it's
888 	 * unsigned).  Play it safe and say we didn't transfer anything.
889 	 */
890 	if (urb->actual_length > urb->transfer_buffer_length) {
891 		xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
892 			  urb->transfer_buffer_length, urb->actual_length);
893 		urb->actual_length = 0;
894 		status = 0;
895 	}
896 	/* TD might be removed from td_list if we are giving back a cancelled URB */
897 	if (!list_empty(&td->td_list))
898 		list_del_init(&td->td_list);
899 	/* Giving back a cancelled URB, or if a slated TD completed anyway */
900 	if (!list_empty(&td->cancelled_td_list))
901 		list_del_init(&td->cancelled_td_list);
902 
903 	inc_td_cnt(urb);
904 	/* Giveback the urb when all the tds are completed */
905 	if (last_td_in_urb(td)) {
906 		if ((urb->actual_length != urb->transfer_buffer_length &&
907 		     (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
908 		    (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
909 			xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
910 				 urb, urb->actual_length,
911 				 urb->transfer_buffer_length, status);
912 
913 		/* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
914 		if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
915 			status = 0;
916 		xhci_giveback_urb_in_irq(xhci, td, status);
917 	}
918 }
919 
920 /* Give back previous TD and move on to the next TD. */
xhci_dequeue_td(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_ring * ring,u32 status)921 static void xhci_dequeue_td(struct xhci_hcd *xhci, struct xhci_td *td, struct xhci_ring *ring,
922 			    u32 status)
923 {
924 	ring->dequeue = td->end_trb;
925 	ring->deq_seg = td->end_seg;
926 	inc_deq(xhci, ring);
927 
928 	xhci_td_cleanup(xhci, td, ring, status);
929 }
930 
931 /* Complete the cancelled URBs we unlinked from td_list. */
xhci_giveback_invalidated_tds(struct xhci_virt_ep * ep)932 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
933 {
934 	struct xhci_ring *ring;
935 	struct xhci_td *td, *tmp_td;
936 
937 	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
938 				 cancelled_td_list) {
939 
940 		ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
941 
942 		if (td->cancel_status == TD_CLEARED) {
943 			xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
944 				 __func__, td->urb);
945 			xhci_td_cleanup(ep->xhci, td, ring, td->status);
946 		} else {
947 			xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
948 				 __func__, td->urb, td->cancel_status);
949 		}
950 		if (ep->xhci->xhc_state & XHCI_STATE_DYING)
951 			return;
952 	}
953 }
954 
xhci_reset_halted_ep(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,enum xhci_ep_reset_type reset_type)955 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
956 				unsigned int ep_index, enum xhci_ep_reset_type reset_type)
957 {
958 	struct xhci_command *command;
959 	int ret = 0;
960 
961 	command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
962 	if (!command) {
963 		ret = -ENOMEM;
964 		goto done;
965 	}
966 
967 	xhci_dbg(xhci, "%s-reset ep %u, slot %u\n",
968 		 (reset_type == EP_HARD_RESET) ? "Hard" : "Soft",
969 		 ep_index, slot_id);
970 
971 	ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
972 done:
973 	if (ret)
974 		xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
975 			 slot_id, ep_index, ret);
976 	return ret;
977 }
978 
xhci_handle_halted_endpoint(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_td * td,enum xhci_ep_reset_type reset_type)979 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
980 				struct xhci_virt_ep *ep,
981 				struct xhci_td *td,
982 				enum xhci_ep_reset_type reset_type)
983 {
984 	unsigned int slot_id = ep->vdev->slot_id;
985 	int err;
986 
987 	/*
988 	 * Avoid resetting endpoint if link is inactive. Can cause host hang.
989 	 * Device will be reset soon to recover the link so don't do anything
990 	 */
991 	if (ep->vdev->flags & VDEV_PORT_ERROR)
992 		return -ENODEV;
993 
994 	/* add td to cancelled list and let reset ep handler take care of it */
995 	if (reset_type == EP_HARD_RESET) {
996 		ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
997 		if (td && list_empty(&td->cancelled_td_list)) {
998 			list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
999 			td->cancel_status = TD_HALTED;
1000 		}
1001 	}
1002 
1003 	if (ep->ep_state & EP_HALTED) {
1004 		xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n",
1005 			 ep->ep_index);
1006 		return 0;
1007 	}
1008 
1009 	err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
1010 	if (err)
1011 		return err;
1012 
1013 	ep->ep_state |= EP_HALTED;
1014 
1015 	xhci_ring_cmd_db(xhci);
1016 
1017 	return 0;
1018 }
1019 
1020 /*
1021  * Fix up the ep ring first, so HW stops executing cancelled TDs.
1022  * We have the xHCI lock, so nothing can modify this list until we drop it.
1023  * We're also in the event handler, so we can't get re-interrupted if another
1024  * Stop Endpoint command completes.
1025  *
1026  * only call this when ring is not in a running state
1027  */
1028 
xhci_invalidate_cancelled_tds(struct xhci_virt_ep * ep)1029 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
1030 {
1031 	struct xhci_hcd		*xhci;
1032 	struct xhci_td		*td = NULL;
1033 	struct xhci_td		*tmp_td = NULL;
1034 	struct xhci_td		*cached_td = NULL;
1035 	struct xhci_ring	*ring;
1036 	u64			hw_deq;
1037 	unsigned int		slot_id = ep->vdev->slot_id;
1038 	int			err;
1039 
1040 	/*
1041 	 * This is not going to work if the hardware is changing its dequeue
1042 	 * pointers as we look at them. Completion handler will call us later.
1043 	 */
1044 	if (ep->ep_state & SET_DEQ_PENDING)
1045 		return 0;
1046 
1047 	xhci = ep->xhci;
1048 
1049 	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1050 		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1051 			       "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p",
1052 			       (unsigned long long)xhci_trb_virt_to_dma(
1053 				       td->start_seg, td->start_trb),
1054 			       td->urb->stream_id, td->urb);
1055 		list_del_init(&td->td_list);
1056 		ring = xhci_urb_to_transfer_ring(xhci, td->urb);
1057 		if (!ring) {
1058 			xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
1059 				  td->urb, td->urb->stream_id);
1060 			continue;
1061 		}
1062 		/*
1063 		 * If a ring stopped on the TD we need to cancel then we have to
1064 		 * move the xHC endpoint ring dequeue pointer past this TD.
1065 		 * Rings halted due to STALL may show hw_deq is past the stalled
1066 		 * TD, but still require a set TR Deq command to flush xHC cache.
1067 		 */
1068 		hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
1069 					 td->urb->stream_id);
1070 		hw_deq &= ~0xf;
1071 
1072 		if (td->cancel_status == TD_HALTED || trb_in_td(td, hw_deq)) {
1073 			switch (td->cancel_status) {
1074 			case TD_CLEARED: /* TD is already no-op */
1075 			case TD_CLEARING_CACHE: /* set TR deq command already queued */
1076 				break;
1077 			case TD_DIRTY: /* TD is cached, clear it */
1078 			case TD_HALTED:
1079 			case TD_CLEARING_CACHE_DEFERRED:
1080 				if (cached_td) {
1081 					if (cached_td->urb->stream_id != td->urb->stream_id) {
1082 						/* Multiple streams case, defer move dq */
1083 						xhci_dbg(xhci,
1084 							 "Move dq deferred: stream %u URB %p\n",
1085 							 td->urb->stream_id, td->urb);
1086 						td->cancel_status = TD_CLEARING_CACHE_DEFERRED;
1087 						break;
1088 					}
1089 
1090 					/* Should never happen, but clear the TD if it does */
1091 					xhci_warn(xhci,
1092 						  "Found multiple active URBs %p and %p in stream %u?\n",
1093 						  td->urb, cached_td->urb,
1094 						  td->urb->stream_id);
1095 					td_to_noop(cached_td, false);
1096 					cached_td->cancel_status = TD_CLEARED;
1097 				}
1098 				td_to_noop(td, false);
1099 				td->cancel_status = TD_CLEARING_CACHE;
1100 				cached_td = td;
1101 				break;
1102 			}
1103 		} else {
1104 			td_to_noop(td, false);
1105 			td->cancel_status = TD_CLEARED;
1106 		}
1107 	}
1108 
1109 	/* If there's no need to move the dequeue pointer then we're done */
1110 	if (!cached_td)
1111 		return 0;
1112 
1113 	err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
1114 					cached_td->urb->stream_id,
1115 					cached_td);
1116 	if (err) {
1117 		/* Failed to move past cached td, just set cached TDs to no-op */
1118 		list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
1119 			/*
1120 			 * Deferred TDs need to have the deq pointer set after the above command
1121 			 * completes, so if that failed we just give up on all of them (and
1122 			 * complain loudly since this could cause issues due to caching).
1123 			 */
1124 			if (td->cancel_status != TD_CLEARING_CACHE &&
1125 			    td->cancel_status != TD_CLEARING_CACHE_DEFERRED)
1126 				continue;
1127 			xhci_warn(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n",
1128 				  td->urb);
1129 			td_to_noop(td, false);
1130 			td->cancel_status = TD_CLEARED;
1131 		}
1132 	}
1133 	return 0;
1134 }
1135 
1136 /*
1137  * Erase queued TDs from transfer ring(s) and give back those the xHC didn't
1138  * stop on. If necessary, queue commands to move the xHC off cancelled TDs it
1139  * stopped on. Those will be given back later when the commands complete.
1140  *
1141  * Call under xhci->lock on a stopped endpoint.
1142  */
xhci_process_cancelled_tds(struct xhci_virt_ep * ep)1143 void xhci_process_cancelled_tds(struct xhci_virt_ep *ep)
1144 {
1145 	xhci_invalidate_cancelled_tds(ep);
1146 	xhci_giveback_invalidated_tds(ep);
1147 }
1148 
1149 /*
1150  * Returns the TD the endpoint ring halted on.
1151  * Only call for non-running rings without streams.
1152  */
find_halted_td(struct xhci_virt_ep * ep)1153 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
1154 {
1155 	struct xhci_td	*td;
1156 	u64		hw_deq;
1157 
1158 	if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
1159 		hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
1160 		hw_deq &= ~0xf;
1161 		td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
1162 		if (trb_in_td(td, hw_deq))
1163 			return td;
1164 	}
1165 	return NULL;
1166 }
1167 
1168 /*
1169  * When we get a command completion for a Stop Endpoint Command, we need to
1170  * unlink any cancelled TDs from the ring.  There are two ways to do that:
1171  *
1172  *  1. If the HW was in the middle of processing the TD that needs to be
1173  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
1174  *     in the TD with a Set Dequeue Pointer Command.
1175  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1176  *     bit cleared) so that the HW will skip over them.
1177  */
xhci_handle_cmd_stop_ep(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 comp_code)1178 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1179 				    union xhci_trb *trb, u32 comp_code)
1180 {
1181 	unsigned int ep_index;
1182 	struct xhci_virt_ep *ep;
1183 	struct xhci_ep_ctx *ep_ctx;
1184 	struct xhci_td *td = NULL;
1185 	enum xhci_ep_reset_type reset_type;
1186 	struct xhci_command *command;
1187 	int err;
1188 
1189 	if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1190 		if (!xhci->devs[slot_id])
1191 			xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1192 				  slot_id);
1193 		return;
1194 	}
1195 
1196 	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1197 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1198 	if (!ep)
1199 		return;
1200 
1201 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1202 
1203 	trace_xhci_handle_cmd_stop_ep(ep_ctx);
1204 
1205 	if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1206 	/*
1207 	 * If stop endpoint command raced with a halting endpoint we need to
1208 	 * reset the host side endpoint first.
1209 	 * If the TD we halted on isn't cancelled the TD should be given back
1210 	 * with a proper error code, and the ring dequeue moved past the TD.
1211 	 * If streams case we can't find hw_deq, or the TD we halted on so do a
1212 	 * soft reset.
1213 	 *
1214 	 * Proper error code is unknown here, it would be -EPIPE if device side
1215 	 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1216 	 * We use -EPROTO, if device is stalled it should return a stall error on
1217 	 * next transfer, which then will return -EPIPE, and device side stall is
1218 	 * noted and cleared by class driver.
1219 	 */
1220 		switch (GET_EP_CTX_STATE(ep_ctx)) {
1221 		case EP_STATE_HALTED:
1222 			xhci_dbg(xhci, "Stop ep completion raced with stall\n");
1223 			/*
1224 			 * If the halt happened before Stop Endpoint failed, its transfer event
1225 			 * should have already been handled and Reset Endpoint should be pending.
1226 			 */
1227 			if (ep->ep_state & EP_HALTED)
1228 				goto reset_done;
1229 
1230 			if (ep->ep_state & EP_HAS_STREAMS) {
1231 				reset_type = EP_SOFT_RESET;
1232 			} else {
1233 				reset_type = EP_HARD_RESET;
1234 				td = find_halted_td(ep);
1235 				if (td)
1236 					td->status = -EPROTO;
1237 			}
1238 			/* reset ep, reset handler cleans up cancelled tds */
1239 			err = xhci_handle_halted_endpoint(xhci, ep, td, reset_type);
1240 			xhci_dbg(xhci, "Stop ep completion resetting ep, status %d\n", err);
1241 			if (err)
1242 				break;
1243 reset_done:
1244 			/* Reset EP handler will clean up cancelled TDs */
1245 			ep->ep_state &= ~EP_STOP_CMD_PENDING;
1246 			return;
1247 		case EP_STATE_STOPPED:
1248 			/*
1249 			 * Per xHCI 4.6.9, Stop Endpoint command on a Stopped
1250 			 * EP is a Context State Error, and EP stays Stopped.
1251 			 *
1252 			 * But maybe it failed on Halted, and somebody ran Reset
1253 			 * Endpoint later. EP state is now Stopped and EP_HALTED
1254 			 * still set because Reset EP handler will run after us.
1255 			 */
1256 			if (ep->ep_state & EP_HALTED)
1257 				break;
1258 			/*
1259 			 * On some HCs EP state remains Stopped for some tens of
1260 			 * us to a few ms or more after a doorbell ring, and any
1261 			 * new Stop Endpoint fails without aborting the restart.
1262 			 * This handler may run quickly enough to still see this
1263 			 * Stopped state, but it will soon change to Running.
1264 			 *
1265 			 * Assume this bug on unexpected Stop Endpoint failures.
1266 			 * Keep retrying until the EP starts and stops again.
1267 			 */
1268 			fallthrough;
1269 		case EP_STATE_RUNNING:
1270 			/* Race, HW handled stop ep cmd before ep was running */
1271 			xhci_dbg(xhci, "Stop ep completion ctx error, ctx_state %d\n",
1272 					GET_EP_CTX_STATE(ep_ctx));
1273 			/*
1274 			 * Don't retry forever if we guessed wrong or a defective HC never starts
1275 			 * the EP or says 'Running' but fails the command. We must give back TDs.
1276 			 */
1277 			if (time_is_before_jiffies(ep->stop_time + msecs_to_jiffies(100)))
1278 				break;
1279 
1280 			command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1281 			if (!command) {
1282 				ep->ep_state &= ~EP_STOP_CMD_PENDING;
1283 				return;
1284 			}
1285 			xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1286 			xhci_ring_cmd_db(xhci);
1287 
1288 			return;
1289 		default:
1290 			break;
1291 		}
1292 	}
1293 
1294 	/* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1295 	xhci_invalidate_cancelled_tds(ep);
1296 	ep->ep_state &= ~EP_STOP_CMD_PENDING;
1297 
1298 	/* Otherwise ring the doorbell(s) to restart queued transfers */
1299 	xhci_giveback_invalidated_tds(ep);
1300 	ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1301 }
1302 
xhci_kill_ring_urbs(struct xhci_hcd * xhci,struct xhci_ring * ring)1303 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1304 {
1305 	struct xhci_td *cur_td;
1306 	struct xhci_td *tmp;
1307 
1308 	list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1309 		list_del_init(&cur_td->td_list);
1310 
1311 		if (!list_empty(&cur_td->cancelled_td_list))
1312 			list_del_init(&cur_td->cancelled_td_list);
1313 
1314 		xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1315 
1316 		inc_td_cnt(cur_td->urb);
1317 		if (last_td_in_urb(cur_td))
1318 			xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1319 	}
1320 }
1321 
xhci_kill_endpoint_urbs(struct xhci_hcd * xhci,int slot_id,int ep_index)1322 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1323 		int slot_id, int ep_index)
1324 {
1325 	struct xhci_td *cur_td;
1326 	struct xhci_td *tmp;
1327 	struct xhci_virt_ep *ep;
1328 	struct xhci_ring *ring;
1329 
1330 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1331 	if (!ep)
1332 		return;
1333 
1334 	if ((ep->ep_state & EP_HAS_STREAMS) ||
1335 			(ep->ep_state & EP_GETTING_NO_STREAMS)) {
1336 		int stream_id;
1337 
1338 		for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1339 				stream_id++) {
1340 			ring = ep->stream_info->stream_rings[stream_id];
1341 			if (!ring)
1342 				continue;
1343 
1344 			xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1345 					"Killing URBs for slot ID %u, ep index %u, stream %u",
1346 					slot_id, ep_index, stream_id);
1347 			xhci_kill_ring_urbs(xhci, ring);
1348 		}
1349 	} else {
1350 		ring = ep->ring;
1351 		if (!ring)
1352 			return;
1353 		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1354 				"Killing URBs for slot ID %u, ep index %u",
1355 				slot_id, ep_index);
1356 		xhci_kill_ring_urbs(xhci, ring);
1357 	}
1358 
1359 	list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1360 			cancelled_td_list) {
1361 		list_del_init(&cur_td->cancelled_td_list);
1362 		inc_td_cnt(cur_td->urb);
1363 
1364 		if (last_td_in_urb(cur_td))
1365 			xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1366 	}
1367 }
1368 
1369 /*
1370  * host controller died, register read returns 0xffffffff
1371  * Complete pending commands, mark them ABORTED.
1372  * URBs need to be given back as usb core might be waiting with device locks
1373  * held for the URBs to finish during device disconnect, blocking host remove.
1374  *
1375  * Call with xhci->lock held.
1376  * lock is relased and re-acquired while giving back urb.
1377  */
xhci_hc_died(struct xhci_hcd * xhci)1378 void xhci_hc_died(struct xhci_hcd *xhci)
1379 {
1380 	int i, j;
1381 
1382 	if (xhci->xhc_state & XHCI_STATE_DYING)
1383 		return;
1384 
1385 	xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1386 	xhci->xhc_state |= XHCI_STATE_DYING;
1387 
1388 	xhci_cleanup_command_queue(xhci);
1389 
1390 	/* return any pending urbs, remove may be waiting for them */
1391 	for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1392 		if (!xhci->devs[i])
1393 			continue;
1394 		for (j = 0; j < 31; j++)
1395 			xhci_kill_endpoint_urbs(xhci, i, j);
1396 	}
1397 
1398 	/* inform usb core hc died if PCI remove isn't already handling it */
1399 	if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1400 		usb_hc_died(xhci_to_hcd(xhci));
1401 }
1402 
1403 /*
1404  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1405  * we need to clear the set deq pending flag in the endpoint ring state, so that
1406  * the TD queueing code can ring the doorbell again.  We also need to ring the
1407  * endpoint doorbell to restart the ring, but only if there aren't more
1408  * cancellations pending.
1409  */
xhci_handle_cmd_set_deq(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 cmd_comp_code)1410 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1411 		union xhci_trb *trb, u32 cmd_comp_code)
1412 {
1413 	unsigned int ep_index;
1414 	unsigned int stream_id;
1415 	struct xhci_ring *ep_ring;
1416 	struct xhci_virt_ep *ep;
1417 	struct xhci_ep_ctx *ep_ctx;
1418 	struct xhci_slot_ctx *slot_ctx;
1419 	struct xhci_stream_ctx *stream_ctx;
1420 	struct xhci_td *td, *tmp_td;
1421 
1422 	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1423 	stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1424 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1425 	if (!ep)
1426 		return;
1427 
1428 	ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1429 	if (!ep_ring) {
1430 		xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1431 				stream_id);
1432 		/* XXX: Harmless??? */
1433 		goto cleanup;
1434 	}
1435 
1436 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1437 	slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1438 	trace_xhci_handle_cmd_set_deq(slot_ctx);
1439 	trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1440 
1441 	if (ep->ep_state & EP_HAS_STREAMS) {
1442 		stream_ctx = &ep->stream_info->stream_ctx_array[stream_id];
1443 		trace_xhci_handle_cmd_set_deq_stream(ep->stream_info, stream_id);
1444 	}
1445 
1446 	if (cmd_comp_code != COMP_SUCCESS) {
1447 		unsigned int ep_state;
1448 		unsigned int slot_state;
1449 
1450 		switch (cmd_comp_code) {
1451 		case COMP_TRB_ERROR:
1452 			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1453 			break;
1454 		case COMP_CONTEXT_STATE_ERROR:
1455 			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1456 			ep_state = GET_EP_CTX_STATE(ep_ctx);
1457 			slot_state = le32_to_cpu(slot_ctx->dev_state);
1458 			slot_state = GET_SLOT_STATE(slot_state);
1459 			xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1460 					"Slot state = %u, EP state = %u",
1461 					slot_state, ep_state);
1462 			break;
1463 		case COMP_SLOT_NOT_ENABLED_ERROR:
1464 			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1465 					slot_id);
1466 			break;
1467 		default:
1468 			xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1469 					cmd_comp_code);
1470 			break;
1471 		}
1472 		/* OK what do we do now?  The endpoint state is hosed, and we
1473 		 * should never get to this point if the synchronization between
1474 		 * queueing, and endpoint state are correct.  This might happen
1475 		 * if the device gets disconnected after we've finished
1476 		 * cancelling URBs, which might not be an error...
1477 		 */
1478 	} else {
1479 		u64 deq;
1480 		/* 4.6.10 deq ptr is written to the stream ctx for streams */
1481 		if (ep->ep_state & EP_HAS_STREAMS) {
1482 			deq = le64_to_cpu(stream_ctx->stream_ring) & SCTX_DEQ_MASK;
1483 
1484 			/*
1485 			 * Cadence xHCI controllers store some endpoint state
1486 			 * information within Rsvd0 fields of Stream Endpoint
1487 			 * context. This field is not cleared during Set TR
1488 			 * Dequeue Pointer command which causes XDMA to skip
1489 			 * over transfer ring and leads to data loss on stream
1490 			 * pipe.
1491 			 * To fix this issue driver must clear Rsvd0 field.
1492 			 */
1493 			if (xhci->quirks & XHCI_CDNS_SCTX_QUIRK) {
1494 				stream_ctx->reserved[0] = 0;
1495 				stream_ctx->reserved[1] = 0;
1496 			}
1497 		} else {
1498 			deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1499 		}
1500 		xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1501 			"Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1502 		if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1503 					 ep->queued_deq_ptr) == deq) {
1504 			/* Update the ring's dequeue segment and dequeue pointer
1505 			 * to reflect the new position.
1506 			 */
1507 			ep_ring->deq_seg = ep->queued_deq_seg;
1508 			ep_ring->dequeue = ep->queued_deq_ptr;
1509 		} else {
1510 			xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1511 			xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1512 				  ep->queued_deq_seg, ep->queued_deq_ptr);
1513 		}
1514 	}
1515 	/* HW cached TDs cleared from cache, give them back */
1516 	list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1517 				 cancelled_td_list) {
1518 		ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1519 		if (td->cancel_status == TD_CLEARING_CACHE) {
1520 			td->cancel_status = TD_CLEARED;
1521 			xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n",
1522 				 __func__, td->urb);
1523 			xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1524 		} else {
1525 			xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n",
1526 				 __func__, td->urb, td->cancel_status);
1527 		}
1528 	}
1529 cleanup:
1530 	ep->ep_state &= ~SET_DEQ_PENDING;
1531 	ep->queued_deq_seg = NULL;
1532 	ep->queued_deq_ptr = NULL;
1533 
1534 	/* Check for deferred or newly cancelled TDs */
1535 	if (!list_empty(&ep->cancelled_td_list)) {
1536 		xhci_dbg(ep->xhci, "%s: Pending TDs to clear, continuing with invalidation\n",
1537 			 __func__);
1538 		xhci_invalidate_cancelled_tds(ep);
1539 		/* Try to restart the endpoint if all is done */
1540 		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1541 		/* Start giving back any TDs invalidated above */
1542 		xhci_giveback_invalidated_tds(ep);
1543 	} else {
1544 		/* Restart any rings with pending URBs */
1545 		xhci_dbg(ep->xhci, "%s: All TDs cleared, ring doorbell\n", __func__);
1546 		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1547 	}
1548 }
1549 
xhci_handle_cmd_reset_ep(struct xhci_hcd * xhci,int slot_id,union xhci_trb * trb,u32 cmd_comp_code)1550 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1551 		union xhci_trb *trb, u32 cmd_comp_code)
1552 {
1553 	struct xhci_virt_ep *ep;
1554 	struct xhci_ep_ctx *ep_ctx;
1555 	unsigned int ep_index;
1556 
1557 	ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1558 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1559 	if (!ep)
1560 		return;
1561 
1562 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1563 	trace_xhci_handle_cmd_reset_ep(ep_ctx);
1564 
1565 	/* This command will only fail if the endpoint wasn't halted,
1566 	 * but we don't care.
1567 	 */
1568 	xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1569 		"Ignoring reset ep completion code of %u", cmd_comp_code);
1570 
1571 	/* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1572 	xhci_invalidate_cancelled_tds(ep);
1573 
1574 	/* Clear our internal halted state */
1575 	ep->ep_state &= ~EP_HALTED;
1576 
1577 	xhci_giveback_invalidated_tds(ep);
1578 
1579 	/* if this was a soft reset, then restart */
1580 	if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1581 		ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1582 }
1583 
xhci_handle_cmd_enable_slot(int slot_id,struct xhci_command * command,u32 cmd_comp_code)1584 static void xhci_handle_cmd_enable_slot(int slot_id, struct xhci_command *command,
1585 					u32 cmd_comp_code)
1586 {
1587 	if (cmd_comp_code == COMP_SUCCESS)
1588 		command->slot_id = slot_id;
1589 	else
1590 		command->slot_id = 0;
1591 }
1592 
xhci_handle_cmd_disable_slot(struct xhci_hcd * xhci,int slot_id)1593 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1594 {
1595 	struct xhci_virt_device *virt_dev;
1596 	struct xhci_slot_ctx *slot_ctx;
1597 
1598 	virt_dev = xhci->devs[slot_id];
1599 	if (!virt_dev)
1600 		return;
1601 
1602 	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1603 	trace_xhci_handle_cmd_disable_slot(slot_ctx);
1604 
1605 	if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1606 		/* Delete default control endpoint resources */
1607 		xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1608 }
1609 
xhci_handle_cmd_config_ep(struct xhci_hcd * xhci,int slot_id)1610 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id)
1611 {
1612 	struct xhci_virt_device *virt_dev;
1613 	struct xhci_input_control_ctx *ctrl_ctx;
1614 	struct xhci_ep_ctx *ep_ctx;
1615 	unsigned int ep_index;
1616 	u32 add_flags;
1617 
1618 	/*
1619 	 * Configure endpoint commands can come from the USB core configuration
1620 	 * or alt setting changes, or when streams were being configured.
1621 	 */
1622 
1623 	virt_dev = xhci->devs[slot_id];
1624 	if (!virt_dev)
1625 		return;
1626 	ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1627 	if (!ctrl_ctx) {
1628 		xhci_warn(xhci, "Could not get input context, bad type.\n");
1629 		return;
1630 	}
1631 
1632 	add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1633 
1634 	/* Input ctx add_flags are the endpoint index plus one */
1635 	ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1636 
1637 	ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1638 	trace_xhci_handle_cmd_config_ep(ep_ctx);
1639 
1640 	return;
1641 }
1642 
xhci_handle_cmd_addr_dev(struct xhci_hcd * xhci,int slot_id)1643 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1644 {
1645 	struct xhci_virt_device *vdev;
1646 	struct xhci_slot_ctx *slot_ctx;
1647 
1648 	vdev = xhci->devs[slot_id];
1649 	if (!vdev)
1650 		return;
1651 	slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1652 	trace_xhci_handle_cmd_addr_dev(slot_ctx);
1653 }
1654 
xhci_handle_cmd_reset_dev(struct xhci_hcd * xhci,int slot_id)1655 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1656 {
1657 	struct xhci_virt_device *vdev;
1658 	struct xhci_slot_ctx *slot_ctx;
1659 
1660 	vdev = xhci->devs[slot_id];
1661 	if (!vdev) {
1662 		xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1663 			  slot_id);
1664 		return;
1665 	}
1666 	slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1667 	trace_xhci_handle_cmd_reset_dev(slot_ctx);
1668 
1669 	xhci_dbg(xhci, "Completed reset device command.\n");
1670 }
1671 
xhci_handle_cmd_nec_get_fw(struct xhci_hcd * xhci,struct xhci_event_cmd * event)1672 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1673 		struct xhci_event_cmd *event)
1674 {
1675 	if (!(xhci->quirks & XHCI_NEC_HOST)) {
1676 		xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1677 		return;
1678 	}
1679 	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1680 			"NEC firmware version %2x.%02x",
1681 			NEC_FW_MAJOR(le32_to_cpu(event->status)),
1682 			NEC_FW_MINOR(le32_to_cpu(event->status)));
1683 }
1684 
xhci_complete_del_and_free_cmd(struct xhci_command * cmd,u32 comp_code,u32 comp_param)1685 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 comp_code, u32 comp_param)
1686 {
1687 	list_del(&cmd->cmd_list);
1688 
1689 	if (cmd->completion) {
1690 		cmd->status = comp_code;
1691 		cmd->comp_param = comp_param;
1692 		complete(cmd->completion);
1693 	} else {
1694 		kfree(cmd);
1695 	}
1696 }
1697 
xhci_cleanup_command_queue(struct xhci_hcd * xhci)1698 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1699 {
1700 	struct xhci_command *cur_cmd, *tmp_cmd;
1701 	xhci->current_cmd = NULL;
1702 	list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1703 		xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED, 0);
1704 }
1705 
xhci_handle_command_timeout(struct work_struct * work)1706 void xhci_handle_command_timeout(struct work_struct *work)
1707 {
1708 	struct xhci_hcd	*xhci;
1709 	unsigned long	flags;
1710 	char		str[XHCI_MSG_MAX];
1711 	u64		hw_ring_state;
1712 	u32		cmd_field3;
1713 	u32		usbsts;
1714 
1715 	xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1716 
1717 	spin_lock_irqsave(&xhci->lock, flags);
1718 
1719 	/*
1720 	 * If timeout work is pending, or current_cmd is NULL, it means we
1721 	 * raced with command completion. Command is handled so just return.
1722 	 */
1723 	if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1724 		spin_unlock_irqrestore(&xhci->lock, flags);
1725 		return;
1726 	}
1727 
1728 	cmd_field3 = le32_to_cpu(xhci->current_cmd->command_trb->generic.field[3]);
1729 	usbsts = readl(&xhci->op_regs->status);
1730 	xhci_dbg(xhci, "Command timeout, USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1731 
1732 	/* Bail out and tear down xhci if a stop endpoint command failed */
1733 	if (TRB_FIELD_TO_TYPE(cmd_field3) == TRB_STOP_RING) {
1734 		struct xhci_virt_ep	*ep;
1735 
1736 		xhci_warn(xhci, "xHCI host not responding to stop endpoint command\n");
1737 
1738 		ep = xhci_get_virt_ep(xhci, TRB_TO_SLOT_ID(cmd_field3),
1739 				      TRB_TO_EP_INDEX(cmd_field3));
1740 		if (ep)
1741 			ep->ep_state &= ~EP_STOP_CMD_PENDING;
1742 
1743 		xhci_halt(xhci);
1744 		xhci_hc_died(xhci);
1745 		goto time_out_completed;
1746 	}
1747 
1748 	/* mark this command to be cancelled */
1749 	xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1750 
1751 	/* Make sure command ring is running before aborting it */
1752 	hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1753 	if (hw_ring_state == ~(u64)0) {
1754 		xhci_hc_died(xhci);
1755 		goto time_out_completed;
1756 	}
1757 
1758 	if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1759 	    (hw_ring_state & CMD_RING_RUNNING))  {
1760 		/* Prevent new doorbell, and start command abort */
1761 		xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1762 		xhci_dbg(xhci, "Command timeout\n");
1763 		xhci_abort_cmd_ring(xhci, flags);
1764 		goto time_out_completed;
1765 	}
1766 
1767 	/* host removed. Bail out */
1768 	if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1769 		xhci_dbg(xhci, "host removed, ring start fail?\n");
1770 		xhci_cleanup_command_queue(xhci);
1771 
1772 		goto time_out_completed;
1773 	}
1774 
1775 	/* command timeout on stopped ring, ring can't be aborted */
1776 	xhci_dbg(xhci, "Command timeout on stopped ring\n");
1777 	xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1778 
1779 time_out_completed:
1780 	spin_unlock_irqrestore(&xhci->lock, flags);
1781 	return;
1782 }
1783 
handle_cmd_completion(struct xhci_hcd * xhci,struct xhci_event_cmd * event)1784 static void handle_cmd_completion(struct xhci_hcd *xhci,
1785 		struct xhci_event_cmd *event)
1786 {
1787 	unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1788 	u32 status = le32_to_cpu(event->status);
1789 	u64 cmd_dma;
1790 	dma_addr_t cmd_dequeue_dma;
1791 	u32 cmd_comp_code;
1792 	union xhci_trb *cmd_trb;
1793 	struct xhci_command *cmd;
1794 	u32 cmd_type;
1795 
1796 	if (slot_id >= MAX_HC_SLOTS) {
1797 		xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1798 		return;
1799 	}
1800 
1801 	cmd_dma = le64_to_cpu(event->cmd_trb);
1802 	cmd_trb = xhci->cmd_ring->dequeue;
1803 
1804 	trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic, cmd_dma);
1805 
1806 	cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1807 
1808 	/* If CMD ring stopped we own the trbs between enqueue and dequeue */
1809 	if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1810 		complete_all(&xhci->cmd_ring_stop_completion);
1811 		return;
1812 	}
1813 
1814 	cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1815 			cmd_trb);
1816 	/*
1817 	 * Check whether the completion event is for our internal kept
1818 	 * command.
1819 	 */
1820 	if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1821 		xhci_warn(xhci,
1822 			  "ERROR mismatched command completion event\n");
1823 		return;
1824 	}
1825 
1826 	cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1827 
1828 	cancel_delayed_work(&xhci->cmd_timer);
1829 
1830 	if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1831 		xhci_err(xhci,
1832 			 "Command completion event does not match command\n");
1833 		return;
1834 	}
1835 
1836 	/*
1837 	 * Host aborted the command ring, check if the current command was
1838 	 * supposed to be aborted, otherwise continue normally.
1839 	 * The command ring is stopped now, but the xHC will issue a Command
1840 	 * Ring Stopped event which will cause us to restart it.
1841 	 */
1842 	if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1843 		xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1844 		if (cmd->status == COMP_COMMAND_ABORTED) {
1845 			if (xhci->current_cmd == cmd)
1846 				xhci->current_cmd = NULL;
1847 			goto event_handled;
1848 		}
1849 	}
1850 
1851 	cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1852 	switch (cmd_type) {
1853 	case TRB_ENABLE_SLOT:
1854 		xhci_handle_cmd_enable_slot(slot_id, cmd, cmd_comp_code);
1855 		break;
1856 	case TRB_DISABLE_SLOT:
1857 		xhci_handle_cmd_disable_slot(xhci, slot_id);
1858 		break;
1859 	case TRB_CONFIG_EP:
1860 		if (!cmd->completion)
1861 			xhci_handle_cmd_config_ep(xhci, slot_id);
1862 		break;
1863 	case TRB_EVAL_CONTEXT:
1864 		break;
1865 	case TRB_ADDR_DEV:
1866 		xhci_handle_cmd_addr_dev(xhci, slot_id);
1867 		break;
1868 	case TRB_STOP_RING:
1869 		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1870 				le32_to_cpu(cmd_trb->generic.field[3])));
1871 		if (!cmd->completion)
1872 			xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1873 						cmd_comp_code);
1874 		break;
1875 	case TRB_SET_DEQ:
1876 		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1877 				le32_to_cpu(cmd_trb->generic.field[3])));
1878 		xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1879 		break;
1880 	case TRB_CMD_NOOP:
1881 		/* Is this an aborted command turned to NO-OP? */
1882 		if (cmd->status == COMP_COMMAND_RING_STOPPED)
1883 			cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1884 		break;
1885 	case TRB_RESET_EP:
1886 		WARN_ON(slot_id != TRB_TO_SLOT_ID(
1887 				le32_to_cpu(cmd_trb->generic.field[3])));
1888 		xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1889 		break;
1890 	case TRB_RESET_DEV:
1891 		/* SLOT_ID field in reset device cmd completion event TRB is 0.
1892 		 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1893 		 */
1894 		slot_id = TRB_TO_SLOT_ID(
1895 				le32_to_cpu(cmd_trb->generic.field[3]));
1896 		xhci_handle_cmd_reset_dev(xhci, slot_id);
1897 		break;
1898 	case TRB_NEC_GET_FW:
1899 		xhci_handle_cmd_nec_get_fw(xhci, event);
1900 		break;
1901 	default:
1902 		/* Skip over unknown commands on the event ring */
1903 		xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1904 		break;
1905 	}
1906 
1907 	/* restart timer if this wasn't the last command */
1908 	if (!list_is_singular(&xhci->cmd_list)) {
1909 		xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1910 						struct xhci_command, cmd_list);
1911 		xhci_mod_cmd_timer(xhci);
1912 	} else if (xhci->current_cmd == cmd) {
1913 		xhci->current_cmd = NULL;
1914 	}
1915 
1916 event_handled:
1917 	xhci_complete_del_and_free_cmd(cmd, cmd_comp_code, COMP_PARAM(status));
1918 
1919 	inc_deq(xhci, xhci->cmd_ring);
1920 }
1921 
handle_vendor_event(struct xhci_hcd * xhci,union xhci_trb * event,u32 trb_type)1922 static void handle_vendor_event(struct xhci_hcd *xhci,
1923 				union xhci_trb *event, u32 trb_type)
1924 {
1925 	xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1926 	if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1927 		handle_cmd_completion(xhci, &event->event_cmd);
1928 }
1929 
handle_device_notification(struct xhci_hcd * xhci,union xhci_trb * event)1930 static void handle_device_notification(struct xhci_hcd *xhci,
1931 		union xhci_trb *event)
1932 {
1933 	u32 slot_id;
1934 	struct usb_device *udev;
1935 
1936 	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1937 	if (!xhci->devs[slot_id]) {
1938 		xhci_warn(xhci, "Device Notification event for "
1939 				"unused slot %u\n", slot_id);
1940 		return;
1941 	}
1942 
1943 	xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1944 			slot_id);
1945 	udev = xhci->devs[slot_id]->udev;
1946 	if (udev && udev->parent)
1947 		usb_wakeup_notification(udev->parent, udev->portnum);
1948 }
1949 
1950 /*
1951  * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1952  * Controller.
1953  * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1954  * If a connection to a USB 1 device is followed by another connection
1955  * to a USB 2 device.
1956  *
1957  * Reset the PHY after the USB device is disconnected if device speed
1958  * is less than HCD_USB3.
1959  * Retry the reset sequence max of 4 times checking the PLL lock status.
1960  *
1961  */
xhci_cavium_reset_phy_quirk(struct xhci_hcd * xhci)1962 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1963 {
1964 	struct usb_hcd *hcd = xhci_to_hcd(xhci);
1965 	u32 pll_lock_check;
1966 	u32 retry_count = 4;
1967 
1968 	do {
1969 		/* Assert PHY reset */
1970 		writel(0x6F, hcd->regs + 0x1048);
1971 		udelay(10);
1972 		/* De-assert the PHY reset */
1973 		writel(0x7F, hcd->regs + 0x1048);
1974 		udelay(200);
1975 		pll_lock_check = readl(hcd->regs + 0x1070);
1976 	} while (!(pll_lock_check & 0x1) && --retry_count);
1977 }
1978 
handle_port_status(struct xhci_hcd * xhci,union xhci_trb * event)1979 static void handle_port_status(struct xhci_hcd *xhci, union xhci_trb *event)
1980 {
1981 	struct usb_hcd *hcd;
1982 	u32 port_id;
1983 	u32 portsc, cmd_reg;
1984 	int max_ports;
1985 	unsigned int hcd_portnum;
1986 	struct xhci_bus_state *bus_state;
1987 	bool bogus_port_status = false;
1988 	struct xhci_port *port;
1989 
1990 	/* Port status change events always have a successful completion code */
1991 	if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1992 		xhci_warn(xhci,
1993 			  "WARN: xHC returned failed port status event\n");
1994 
1995 	port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1996 	max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1997 
1998 	if ((port_id <= 0) || (port_id > max_ports)) {
1999 		xhci_warn(xhci, "Port change event with invalid port ID %d\n",
2000 			  port_id);
2001 		return;
2002 	}
2003 
2004 	port = &xhci->hw_ports[port_id - 1];
2005 	if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
2006 		xhci_warn(xhci, "Port change event, no port for port ID %u\n",
2007 			  port_id);
2008 		bogus_port_status = true;
2009 		goto cleanup;
2010 	}
2011 
2012 	/* We might get interrupts after shared_hcd is removed */
2013 	if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
2014 		xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
2015 		bogus_port_status = true;
2016 		goto cleanup;
2017 	}
2018 
2019 	hcd = port->rhub->hcd;
2020 	bus_state = &port->rhub->bus_state;
2021 	hcd_portnum = port->hcd_portnum;
2022 	portsc = readl(port->addr);
2023 
2024 	xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
2025 		 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
2026 
2027 	trace_xhci_handle_port_status(port, portsc);
2028 
2029 	if (hcd->state == HC_STATE_SUSPENDED) {
2030 		xhci_dbg(xhci, "resume root hub\n");
2031 		usb_hcd_resume_root_hub(hcd);
2032 	}
2033 
2034 	if (hcd->speed >= HCD_USB3 &&
2035 	    (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
2036 		if (port->slot_id && xhci->devs[port->slot_id])
2037 			xhci->devs[port->slot_id]->flags |= VDEV_PORT_ERROR;
2038 	}
2039 
2040 	if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
2041 		xhci_dbg(xhci, "port resume event for port %d\n", port_id);
2042 
2043 		cmd_reg = readl(&xhci->op_regs->command);
2044 		if (!(cmd_reg & CMD_RUN)) {
2045 			xhci_warn(xhci, "xHC is not running.\n");
2046 			goto cleanup;
2047 		}
2048 
2049 		if (DEV_SUPERSPEED_ANY(portsc)) {
2050 			xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
2051 			/* Set a flag to say the port signaled remote wakeup,
2052 			 * so we can tell the difference between the end of
2053 			 * device and host initiated resume.
2054 			 */
2055 			bus_state->port_remote_wakeup |= 1 << hcd_portnum;
2056 			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2057 			usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2058 			xhci_set_link_state(xhci, port, XDEV_U0);
2059 			/* Need to wait until the next link state change
2060 			 * indicates the device is actually in U0.
2061 			 */
2062 			bogus_port_status = true;
2063 			goto cleanup;
2064 		} else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
2065 			xhci_dbg(xhci, "resume HS port %d\n", port_id);
2066 			port->resume_timestamp = jiffies +
2067 				msecs_to_jiffies(USB_RESUME_TIMEOUT);
2068 			set_bit(hcd_portnum, &bus_state->resuming_ports);
2069 			/* Do the rest in GetPortStatus after resume time delay.
2070 			 * Avoid polling roothub status before that so that a
2071 			 * usb device auto-resume latency around ~40ms.
2072 			 */
2073 			set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2074 			mod_timer(&hcd->rh_timer,
2075 				  port->resume_timestamp);
2076 			usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
2077 			bogus_port_status = true;
2078 		}
2079 	}
2080 
2081 	if ((portsc & PORT_PLC) &&
2082 	    DEV_SUPERSPEED_ANY(portsc) &&
2083 	    ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
2084 	     (portsc & PORT_PLS_MASK) == XDEV_U1 ||
2085 	     (portsc & PORT_PLS_MASK) == XDEV_U2)) {
2086 		xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
2087 		complete(&port->u3exit_done);
2088 		/* We've just brought the device into U0/1/2 through either the
2089 		 * Resume state after a device remote wakeup, or through the
2090 		 * U3Exit state after a host-initiated resume.  If it's a device
2091 		 * initiated remote wake, don't pass up the link state change,
2092 		 * so the roothub behavior is consistent with external
2093 		 * USB 3.0 hub behavior.
2094 		 */
2095 		if (port->slot_id && xhci->devs[port->slot_id])
2096 			xhci_ring_device(xhci, port->slot_id);
2097 		if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
2098 			xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2099 			usb_wakeup_notification(hcd->self.root_hub,
2100 					hcd_portnum + 1);
2101 			bogus_port_status = true;
2102 			goto cleanup;
2103 		}
2104 	}
2105 
2106 	/*
2107 	 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
2108 	 * RExit to a disconnect state).  If so, let the driver know it's
2109 	 * out of the RExit state.
2110 	 */
2111 	if (hcd->speed < HCD_USB3 && port->rexit_active) {
2112 		complete(&port->rexit_done);
2113 		port->rexit_active = false;
2114 		bogus_port_status = true;
2115 		goto cleanup;
2116 	}
2117 
2118 	if (hcd->speed < HCD_USB3) {
2119 		xhci_test_and_clear_bit(xhci, port, PORT_PLC);
2120 		if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
2121 		    (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
2122 			xhci_cavium_reset_phy_quirk(xhci);
2123 	}
2124 
2125 cleanup:
2126 
2127 	/* Don't make the USB core poll the roothub if we got a bad port status
2128 	 * change event.  Besides, at that point we can't tell which roothub
2129 	 * (USB 2.0 or USB 3.0) to kick.
2130 	 */
2131 	if (bogus_port_status)
2132 		return;
2133 
2134 	/*
2135 	 * xHCI port-status-change events occur when the "or" of all the
2136 	 * status-change bits in the portsc register changes from 0 to 1.
2137 	 * New status changes won't cause an event if any other change
2138 	 * bits are still set.  When an event occurs, switch over to
2139 	 * polling to avoid losing status changes.
2140 	 */
2141 	xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
2142 		 __func__, hcd->self.busnum);
2143 	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2144 	spin_unlock(&xhci->lock);
2145 	/* Pass this up to the core */
2146 	usb_hcd_poll_rh_status(hcd);
2147 	spin_lock(&xhci->lock);
2148 }
2149 
xhci_clear_hub_tt_buffer(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_virt_ep * ep)2150 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2151 		struct xhci_virt_ep *ep)
2152 {
2153 	/*
2154 	 * As part of low/full-speed endpoint-halt processing
2155 	 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2156 	 */
2157 	if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2158 	    (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2159 	    !(ep->ep_state & EP_CLEARING_TT)) {
2160 		ep->ep_state |= EP_CLEARING_TT;
2161 		td->urb->ep->hcpriv = td->urb->dev;
2162 		if (usb_hub_clear_tt_buffer(td->urb))
2163 			ep->ep_state &= ~EP_CLEARING_TT;
2164 	}
2165 }
2166 
2167 /*
2168  * Check if xhci internal endpoint state has gone to a "halt" state due to an
2169  * error or stall, including default control pipe protocol stall.
2170  * The internal halt needs to be cleared with a reset endpoint command.
2171  *
2172  * External device side is also halted in functional stall cases. Class driver
2173  * will clear the device halt with a CLEAR_FEATURE(ENDPOINT_HALT) request later.
2174  */
xhci_halted_host_endpoint(struct xhci_ep_ctx * ep_ctx,unsigned int comp_code)2175 static bool xhci_halted_host_endpoint(struct xhci_ep_ctx *ep_ctx, unsigned int comp_code)
2176 {
2177 	/* Stall halts both internal and device side endpoint */
2178 	if (comp_code == COMP_STALL_ERROR)
2179 		return true;
2180 
2181 	/* TRB completion codes that may require internal halt cleanup */
2182 	if (comp_code == COMP_USB_TRANSACTION_ERROR ||
2183 	    comp_code == COMP_BABBLE_DETECTED_ERROR ||
2184 	    comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2185 		/*
2186 		 * The 0.95 spec says a babbling control endpoint is not halted.
2187 		 * The 0.96 spec says it is. Some HW claims to be 0.95
2188 		 * compliant, but it halts the control endpoint anyway.
2189 		 * Check endpoint context if endpoint is halted.
2190 		 */
2191 		if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2192 			return true;
2193 
2194 	return false;
2195 }
2196 
xhci_is_vendor_info_code(struct xhci_hcd * xhci,unsigned int trb_comp_code)2197 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2198 {
2199 	if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2200 		/* Vendor defined "informational" completion code,
2201 		 * treat as not-an-error.
2202 		 */
2203 		xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2204 				trb_comp_code);
2205 		xhci_dbg(xhci, "Treating code as success.\n");
2206 		return 1;
2207 	}
2208 	return 0;
2209 }
2210 
finish_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,u32 trb_comp_code)2211 static void finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2212 		      struct xhci_ring *ep_ring, struct xhci_td *td,
2213 		      u32 trb_comp_code)
2214 {
2215 	struct xhci_ep_ctx *ep_ctx;
2216 
2217 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2218 
2219 	switch (trb_comp_code) {
2220 	case COMP_STOPPED_LENGTH_INVALID:
2221 	case COMP_STOPPED_SHORT_PACKET:
2222 	case COMP_STOPPED:
2223 		/*
2224 		 * The "Stop Endpoint" completion will take care of any
2225 		 * stopped TDs. A stopped TD may be restarted, so don't update
2226 		 * the ring dequeue pointer or take this TD off any lists yet.
2227 		 */
2228 		return;
2229 	case COMP_USB_TRANSACTION_ERROR:
2230 	case COMP_BABBLE_DETECTED_ERROR:
2231 	case COMP_SPLIT_TRANSACTION_ERROR:
2232 		/*
2233 		 * If endpoint context state is not halted we might be
2234 		 * racing with a reset endpoint command issued by a unsuccessful
2235 		 * stop endpoint completion (context error). In that case the
2236 		 * td should be on the cancelled list, and EP_HALTED flag set.
2237 		 *
2238 		 * Or then it's not halted due to the 0.95 spec stating that a
2239 		 * babbling control endpoint should not halt. The 0.96 spec
2240 		 * again says it should.  Some HW claims to be 0.95 compliant,
2241 		 * but it halts the control endpoint anyway.
2242 		 */
2243 		if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2244 			/*
2245 			 * If EP_HALTED is set and TD is on the cancelled list
2246 			 * the TD and dequeue pointer will be handled by reset
2247 			 * ep command completion
2248 			 */
2249 			if ((ep->ep_state & EP_HALTED) &&
2250 			    !list_empty(&td->cancelled_td_list)) {
2251 				xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2252 					 (unsigned long long)xhci_trb_virt_to_dma(
2253 						 td->start_seg, td->start_trb));
2254 				return;
2255 			}
2256 			/* endpoint not halted, don't reset it */
2257 			break;
2258 		}
2259 		/* Almost same procedure as for STALL_ERROR below */
2260 		xhci_clear_hub_tt_buffer(xhci, td, ep);
2261 		xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2262 		return;
2263 	case COMP_STALL_ERROR:
2264 		/*
2265 		 * xhci internal endpoint state will go to a "halt" state for
2266 		 * any stall, including default control pipe protocol stall.
2267 		 * To clear the host side halt we need to issue a reset endpoint
2268 		 * command, followed by a set dequeue command to move past the
2269 		 * TD.
2270 		 * Class drivers clear the device side halt from a functional
2271 		 * stall later. Hub TT buffer should only be cleared for FS/LS
2272 		 * devices behind HS hubs for functional stalls.
2273 		 */
2274 		if (ep->ep_index != 0)
2275 			xhci_clear_hub_tt_buffer(xhci, td, ep);
2276 
2277 		xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2278 
2279 		return; /* xhci_handle_halted_endpoint marked td cancelled */
2280 	default:
2281 		break;
2282 	}
2283 
2284 	xhci_dequeue_td(xhci, td, ep_ring, td->status);
2285 }
2286 
2287 /* sum trb lengths from the first trb up to stop_trb, _excluding_ stop_trb */
sum_trb_lengths(struct xhci_td * td,union xhci_trb * stop_trb)2288 static u32 sum_trb_lengths(struct xhci_td *td, union xhci_trb *stop_trb)
2289 {
2290 	u32 sum;
2291 	union xhci_trb *trb = td->start_trb;
2292 	struct xhci_segment *seg = td->start_seg;
2293 
2294 	for (sum = 0; trb != stop_trb; next_trb(&seg, &trb)) {
2295 		if (!trb_is_noop(trb) && !trb_is_link(trb))
2296 			sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2297 	}
2298 	return sum;
2299 }
2300 
2301 /*
2302  * Process control tds, update urb status and actual_length.
2303  */
process_ctrl_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2304 static void process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2305 			    struct xhci_ring *ep_ring,  struct xhci_td *td,
2306 			    union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2307 {
2308 	struct xhci_ep_ctx *ep_ctx;
2309 	u32 trb_comp_code;
2310 	u32 remaining, requested;
2311 	u32 trb_type;
2312 
2313 	trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2314 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2315 	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2316 	requested = td->urb->transfer_buffer_length;
2317 	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2318 
2319 	switch (trb_comp_code) {
2320 	case COMP_SUCCESS:
2321 		if (trb_type != TRB_STATUS) {
2322 			xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2323 				  (trb_type == TRB_DATA) ? "data" : "setup");
2324 			td->status = -ESHUTDOWN;
2325 			break;
2326 		}
2327 		td->status = 0;
2328 		break;
2329 	case COMP_SHORT_PACKET:
2330 		td->status = 0;
2331 		break;
2332 	case COMP_STOPPED_SHORT_PACKET:
2333 		if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2334 			td->urb->actual_length = remaining;
2335 		else
2336 			xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2337 		goto finish_td;
2338 	case COMP_STOPPED:
2339 		switch (trb_type) {
2340 		case TRB_SETUP:
2341 			td->urb->actual_length = 0;
2342 			goto finish_td;
2343 		case TRB_DATA:
2344 		case TRB_NORMAL:
2345 			td->urb->actual_length = requested - remaining;
2346 			goto finish_td;
2347 		case TRB_STATUS:
2348 			td->urb->actual_length = requested;
2349 			goto finish_td;
2350 		default:
2351 			xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2352 				  trb_type);
2353 			goto finish_td;
2354 		}
2355 	case COMP_STOPPED_LENGTH_INVALID:
2356 		goto finish_td;
2357 	default:
2358 		if (!xhci_halted_host_endpoint(ep_ctx, trb_comp_code))
2359 			break;
2360 		xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2361 			 trb_comp_code, ep->ep_index);
2362 		fallthrough;
2363 	case COMP_STALL_ERROR:
2364 		/* Did we transfer part of the data (middle) phase? */
2365 		if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2366 			td->urb->actual_length = requested - remaining;
2367 		else if (!td->urb_length_set)
2368 			td->urb->actual_length = 0;
2369 		goto finish_td;
2370 	}
2371 
2372 	/* stopped at setup stage, no data transferred */
2373 	if (trb_type == TRB_SETUP)
2374 		goto finish_td;
2375 
2376 	/*
2377 	 * if on data stage then update the actual_length of the URB and flag it
2378 	 * as set, so it won't be overwritten in the event for the last TRB.
2379 	 */
2380 	if (trb_type == TRB_DATA ||
2381 		trb_type == TRB_NORMAL) {
2382 		td->urb_length_set = true;
2383 		td->urb->actual_length = requested - remaining;
2384 		xhci_dbg(xhci, "Waiting for status stage event\n");
2385 		return;
2386 	}
2387 
2388 	/* at status stage */
2389 	if (!td->urb_length_set)
2390 		td->urb->actual_length = requested;
2391 
2392 finish_td:
2393 	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2394 }
2395 
2396 /*
2397  * Process isochronous tds, update urb packet status and actual_length.
2398  */
process_isoc_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2399 static void process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2400 			    struct xhci_ring *ep_ring, struct xhci_td *td,
2401 			    union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2402 {
2403 	struct urb_priv *urb_priv;
2404 	int idx;
2405 	struct usb_iso_packet_descriptor *frame;
2406 	u32 trb_comp_code;
2407 	bool sum_trbs_for_length = false;
2408 	u32 remaining, requested, ep_trb_len;
2409 	int short_framestatus;
2410 
2411 	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2412 	urb_priv = td->urb->hcpriv;
2413 	idx = urb_priv->num_tds_done;
2414 	frame = &td->urb->iso_frame_desc[idx];
2415 	requested = frame->length;
2416 	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2417 	ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2418 	short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2419 		-EREMOTEIO : 0;
2420 
2421 	/* handle completion code */
2422 	switch (trb_comp_code) {
2423 	case COMP_SUCCESS:
2424 		/* Don't overwrite status if TD had an error, see xHCI 4.9.1 */
2425 		if (td->error_mid_td)
2426 			break;
2427 		if (remaining) {
2428 			frame->status = short_framestatus;
2429 			sum_trbs_for_length = true;
2430 			break;
2431 		}
2432 		frame->status = 0;
2433 		break;
2434 	case COMP_SHORT_PACKET:
2435 		frame->status = short_framestatus;
2436 		sum_trbs_for_length = true;
2437 		break;
2438 	case COMP_BANDWIDTH_OVERRUN_ERROR:
2439 		frame->status = -ECOMM;
2440 		break;
2441 	case COMP_BABBLE_DETECTED_ERROR:
2442 		sum_trbs_for_length = true;
2443 		fallthrough;
2444 	case COMP_ISOCH_BUFFER_OVERRUN:
2445 		frame->status = -EOVERFLOW;
2446 		if (ep_trb != td->end_trb)
2447 			td->error_mid_td = true;
2448 		break;
2449 	case COMP_MISSED_SERVICE_ERROR:
2450 		frame->status = -EXDEV;
2451 		sum_trbs_for_length = true;
2452 		if (ep_trb != td->end_trb)
2453 			td->error_mid_td = true;
2454 		break;
2455 	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2456 	case COMP_STALL_ERROR:
2457 		frame->status = -EPROTO;
2458 		break;
2459 	case COMP_USB_TRANSACTION_ERROR:
2460 		frame->status = -EPROTO;
2461 		sum_trbs_for_length = true;
2462 		if (ep_trb != td->end_trb)
2463 			td->error_mid_td = true;
2464 		break;
2465 	case COMP_STOPPED:
2466 		sum_trbs_for_length = true;
2467 		break;
2468 	case COMP_STOPPED_SHORT_PACKET:
2469 		/* field normally containing residue now contains transferred */
2470 		frame->status = short_framestatus;
2471 		requested = remaining;
2472 		break;
2473 	case COMP_STOPPED_LENGTH_INVALID:
2474 		/* exclude stopped trb with invalid length from length sum */
2475 		sum_trbs_for_length = true;
2476 		ep_trb_len = 0;
2477 		remaining = 0;
2478 		break;
2479 	default:
2480 		sum_trbs_for_length = true;
2481 		frame->status = -1;
2482 		break;
2483 	}
2484 
2485 	if (td->urb_length_set)
2486 		goto finish_td;
2487 
2488 	if (sum_trbs_for_length)
2489 		frame->actual_length = sum_trb_lengths(td, ep_trb) +
2490 			ep_trb_len - remaining;
2491 	else
2492 		frame->actual_length = requested;
2493 
2494 	td->urb->actual_length += frame->actual_length;
2495 
2496 finish_td:
2497 	/* Don't give back TD yet if we encountered an error mid TD */
2498 	if (td->error_mid_td && ep_trb != td->end_trb) {
2499 		xhci_dbg(xhci, "Error mid isoc TD, wait for final completion event\n");
2500 		td->urb_length_set = true;
2501 		return;
2502 	}
2503 	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2504 }
2505 
skip_isoc_td(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_virt_ep * ep,int status)2506 static void skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2507 			 struct xhci_virt_ep *ep, int status)
2508 {
2509 	struct urb_priv *urb_priv;
2510 	struct usb_iso_packet_descriptor *frame;
2511 	int idx;
2512 
2513 	urb_priv = td->urb->hcpriv;
2514 	idx = urb_priv->num_tds_done;
2515 	frame = &td->urb->iso_frame_desc[idx];
2516 
2517 	/* The transfer is partly done. */
2518 	frame->status = -EXDEV;
2519 
2520 	/* calc actual length */
2521 	frame->actual_length = 0;
2522 
2523 	xhci_dequeue_td(xhci, td, ep->ring, status);
2524 }
2525 
2526 /*
2527  * Process bulk and interrupt tds, update urb status and actual_length.
2528  */
process_bulk_intr_td(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,struct xhci_ring * ep_ring,struct xhci_td * td,union xhci_trb * ep_trb,struct xhci_transfer_event * event)2529 static void process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2530 				 struct xhci_ring *ep_ring, struct xhci_td *td,
2531 				 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2532 {
2533 	struct xhci_slot_ctx *slot_ctx;
2534 	u32 trb_comp_code;
2535 	u32 remaining, requested, ep_trb_len;
2536 
2537 	slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2538 	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2539 	remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2540 	ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2541 	requested = td->urb->transfer_buffer_length;
2542 
2543 	switch (trb_comp_code) {
2544 	case COMP_SUCCESS:
2545 		ep->err_count = 0;
2546 		/* handle success with untransferred data as short packet */
2547 		if (ep_trb != td->end_trb || remaining) {
2548 			xhci_warn(xhci, "WARN Successful completion on short TX\n");
2549 			xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2550 				 td->urb->ep->desc.bEndpointAddress,
2551 				 requested, remaining);
2552 		}
2553 		td->status = 0;
2554 		break;
2555 	case COMP_SHORT_PACKET:
2556 		td->status = 0;
2557 		break;
2558 	case COMP_STOPPED_SHORT_PACKET:
2559 		td->urb->actual_length = remaining;
2560 		goto finish_td;
2561 	case COMP_STOPPED_LENGTH_INVALID:
2562 		/* stopped on ep trb with invalid length, exclude it */
2563 		td->urb->actual_length = sum_trb_lengths(td, ep_trb);
2564 		goto finish_td;
2565 	case COMP_USB_TRANSACTION_ERROR:
2566 		if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2567 		    (ep->err_count++ > MAX_SOFT_RETRY) ||
2568 		    le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2569 			break;
2570 
2571 		td->status = 0;
2572 
2573 		xhci_handle_halted_endpoint(xhci, ep, td, EP_SOFT_RESET);
2574 		return;
2575 	default:
2576 		/* do nothing */
2577 		break;
2578 	}
2579 
2580 	if (ep_trb == td->end_trb)
2581 		td->urb->actual_length = requested - remaining;
2582 	else
2583 		td->urb->actual_length =
2584 			sum_trb_lengths(td, ep_trb) +
2585 			ep_trb_len - remaining;
2586 finish_td:
2587 	if (remaining > requested) {
2588 		xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2589 			  remaining);
2590 		td->urb->actual_length = 0;
2591 	}
2592 
2593 	finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2594 }
2595 
2596 /* Transfer events which don't point to a transfer TRB, see xhci 4.17.4 */
handle_transferless_tx_event(struct xhci_hcd * xhci,struct xhci_virt_ep * ep,u32 trb_comp_code)2597 static int handle_transferless_tx_event(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2598 					u32 trb_comp_code)
2599 {
2600 	switch (trb_comp_code) {
2601 	case COMP_STALL_ERROR:
2602 	case COMP_USB_TRANSACTION_ERROR:
2603 	case COMP_INVALID_STREAM_TYPE_ERROR:
2604 	case COMP_INVALID_STREAM_ID_ERROR:
2605 		xhci_dbg(xhci, "Stream transaction error ep %u no id\n", ep->ep_index);
2606 		if (ep->err_count++ > MAX_SOFT_RETRY)
2607 			xhci_handle_halted_endpoint(xhci, ep, NULL, EP_HARD_RESET);
2608 		else
2609 			xhci_handle_halted_endpoint(xhci, ep, NULL, EP_SOFT_RESET);
2610 		break;
2611 	case COMP_RING_UNDERRUN:
2612 	case COMP_RING_OVERRUN:
2613 	case COMP_STOPPED_LENGTH_INVALID:
2614 		break;
2615 	default:
2616 		xhci_err(xhci, "Transfer event %u for unknown stream ring slot %u ep %u\n",
2617 			 trb_comp_code, ep->vdev->slot_id, ep->ep_index);
2618 		return -ENODEV;
2619 	}
2620 	return 0;
2621 }
2622 
xhci_spurious_success_tx_event(struct xhci_hcd * xhci,struct xhci_ring * ring)2623 static bool xhci_spurious_success_tx_event(struct xhci_hcd *xhci,
2624 					   struct xhci_ring *ring)
2625 {
2626 	switch (ring->old_trb_comp_code) {
2627 	case COMP_SHORT_PACKET:
2628 		return xhci->quirks & XHCI_SPURIOUS_SUCCESS;
2629 	case COMP_USB_TRANSACTION_ERROR:
2630 	case COMP_BABBLE_DETECTED_ERROR:
2631 	case COMP_ISOCH_BUFFER_OVERRUN:
2632 		return xhci->quirks & XHCI_ETRON_HOST &&
2633 			ring->type == TYPE_ISOC;
2634 	default:
2635 		return false;
2636 	}
2637 }
2638 
2639 /*
2640  * If this function returns an error condition, it means it got a Transfer
2641  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2642  * At this point, the host controller is probably hosed and should be reset.
2643  */
handle_tx_event(struct xhci_hcd * xhci,struct xhci_interrupter * ir,struct xhci_transfer_event * event)2644 static int handle_tx_event(struct xhci_hcd *xhci,
2645 			   struct xhci_interrupter *ir,
2646 			   struct xhci_transfer_event *event)
2647 {
2648 	struct xhci_virt_ep *ep;
2649 	struct xhci_ring *ep_ring;
2650 	unsigned int slot_id;
2651 	int ep_index;
2652 	struct xhci_td *td = NULL;
2653 	dma_addr_t ep_trb_dma;
2654 	struct xhci_segment *ep_seg;
2655 	union xhci_trb *ep_trb;
2656 	int status = -EINPROGRESS;
2657 	struct xhci_ep_ctx *ep_ctx;
2658 	u32 trb_comp_code;
2659 	bool ring_xrun_event = false;
2660 
2661 	slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2662 	ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2663 	trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2664 	ep_trb_dma = le64_to_cpu(event->buffer);
2665 
2666 	ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2667 	if (!ep) {
2668 		xhci_err(xhci, "ERROR Invalid Transfer event\n");
2669 		goto err_out;
2670 	}
2671 
2672 	ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2673 	ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2674 
2675 	if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2676 		xhci_err(xhci,
2677 			 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2678 			  slot_id, ep_index);
2679 		goto err_out;
2680 	}
2681 
2682 	if (!ep_ring)
2683 		return handle_transferless_tx_event(xhci, ep, trb_comp_code);
2684 
2685 	/* Look for common error cases */
2686 	switch (trb_comp_code) {
2687 	/* Skip codes that require special handling depending on
2688 	 * transfer type
2689 	 */
2690 	case COMP_SUCCESS:
2691 		if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2692 			trb_comp_code = COMP_SHORT_PACKET;
2693 			xhci_dbg(xhci, "Successful completion on short TX for slot %u ep %u with last td comp code %d\n",
2694 				 slot_id, ep_index, ep_ring->old_trb_comp_code);
2695 		}
2696 		break;
2697 	case COMP_SHORT_PACKET:
2698 		break;
2699 	/* Completion codes for endpoint stopped state */
2700 	case COMP_STOPPED:
2701 		xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2702 			 slot_id, ep_index);
2703 		break;
2704 	case COMP_STOPPED_LENGTH_INVALID:
2705 		xhci_dbg(xhci,
2706 			 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2707 			 slot_id, ep_index);
2708 		break;
2709 	case COMP_STOPPED_SHORT_PACKET:
2710 		xhci_dbg(xhci,
2711 			 "Stopped with short packet transfer detected for slot %u ep %u\n",
2712 			 slot_id, ep_index);
2713 		break;
2714 	/* Completion codes for endpoint halted state */
2715 	case COMP_STALL_ERROR:
2716 		xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2717 			 ep_index);
2718 		status = -EPIPE;
2719 		break;
2720 	case COMP_SPLIT_TRANSACTION_ERROR:
2721 		xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2722 			 slot_id, ep_index);
2723 		status = -EPROTO;
2724 		break;
2725 	case COMP_USB_TRANSACTION_ERROR:
2726 		xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2727 			 slot_id, ep_index);
2728 		status = -EPROTO;
2729 		break;
2730 	case COMP_BABBLE_DETECTED_ERROR:
2731 		xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2732 			 slot_id, ep_index);
2733 		status = -EOVERFLOW;
2734 		break;
2735 	/* Completion codes for endpoint error state */
2736 	case COMP_TRB_ERROR:
2737 		xhci_warn(xhci,
2738 			  "WARN: TRB error for slot %u ep %u on endpoint\n",
2739 			  slot_id, ep_index);
2740 		status = -EILSEQ;
2741 		break;
2742 	/* completion codes not indicating endpoint state change */
2743 	case COMP_DATA_BUFFER_ERROR:
2744 		xhci_warn(xhci,
2745 			  "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2746 			  slot_id, ep_index);
2747 		status = -ENOSR;
2748 		break;
2749 	case COMP_BANDWIDTH_OVERRUN_ERROR:
2750 		xhci_warn(xhci,
2751 			  "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2752 			  slot_id, ep_index);
2753 		break;
2754 	case COMP_ISOCH_BUFFER_OVERRUN:
2755 		xhci_warn(xhci,
2756 			  "WARN: buffer overrun event for slot %u ep %u on endpoint",
2757 			  slot_id, ep_index);
2758 		break;
2759 	case COMP_RING_UNDERRUN:
2760 		/*
2761 		 * When the Isoch ring is empty, the xHC will generate
2762 		 * a Ring Overrun Event for IN Isoch endpoint or Ring
2763 		 * Underrun Event for OUT Isoch endpoint.
2764 		 */
2765 		xhci_dbg(xhci, "Underrun event on slot %u ep %u\n", slot_id, ep_index);
2766 		ring_xrun_event = true;
2767 		break;
2768 	case COMP_RING_OVERRUN:
2769 		xhci_dbg(xhci, "Overrun event on slot %u ep %u\n", slot_id, ep_index);
2770 		ring_xrun_event = true;
2771 		break;
2772 	case COMP_MISSED_SERVICE_ERROR:
2773 		/*
2774 		 * When encounter missed service error, one or more isoc tds
2775 		 * may be missed by xHC.
2776 		 * Set skip flag of the ep_ring; Complete the missed tds as
2777 		 * short transfer when process the ep_ring next time.
2778 		 */
2779 		ep->skip = true;
2780 		xhci_dbg(xhci,
2781 			 "Miss service interval error for slot %u ep %u, set skip flag%s\n",
2782 			 slot_id, ep_index, ep_trb_dma ? ", skip now" : "");
2783 		break;
2784 	case COMP_NO_PING_RESPONSE_ERROR:
2785 		ep->skip = true;
2786 		xhci_dbg(xhci,
2787 			 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2788 			 slot_id, ep_index);
2789 		return 0;
2790 
2791 	case COMP_INCOMPATIBLE_DEVICE_ERROR:
2792 		/* needs disable slot command to recover */
2793 		xhci_warn(xhci,
2794 			  "WARN: detect an incompatible device for slot %u ep %u",
2795 			  slot_id, ep_index);
2796 		status = -EPROTO;
2797 		break;
2798 	default:
2799 		if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2800 			status = 0;
2801 			break;
2802 		}
2803 		xhci_warn(xhci,
2804 			  "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2805 			  trb_comp_code, slot_id, ep_index);
2806 		if (ep->skip)
2807 			break;
2808 		return 0;
2809 	}
2810 
2811 	/*
2812 	 * xhci 4.10.2 states isoc endpoints should continue
2813 	 * processing the next TD if there was an error mid TD.
2814 	 * So host like NEC don't generate an event for the last
2815 	 * isoc TRB even if the IOC flag is set.
2816 	 * xhci 4.9.1 states that if there are errors in mult-TRB
2817 	 * TDs xHC should generate an error for that TRB, and if xHC
2818 	 * proceeds to the next TD it should genete an event for
2819 	 * any TRB with IOC flag on the way. Other host follow this.
2820 	 *
2821 	 * We wait for the final IOC event, but if we get an event
2822 	 * anywhere outside this TD, just give it back already.
2823 	 */
2824 	td = list_first_entry_or_null(&ep_ring->td_list, struct xhci_td, td_list);
2825 
2826 	if (td && td->error_mid_td && !trb_in_td(td, ep_trb_dma)) {
2827 		xhci_dbg(xhci, "Missing TD completion event after mid TD error\n");
2828 		xhci_dequeue_td(xhci, td, ep_ring, td->status);
2829 	}
2830 
2831 	/* If the TRB pointer is NULL, missed TDs will be skipped on the next event */
2832 	if (trb_comp_code == COMP_MISSED_SERVICE_ERROR && !ep_trb_dma)
2833 		return 0;
2834 
2835 	if (list_empty(&ep_ring->td_list)) {
2836 		/*
2837 		 * Don't print wanings if ring is empty due to a stopped endpoint generating an
2838 		 * extra completion event if the device was suspended. Or, a event for the last TRB
2839 		 * of a short TD we already got a short event for. The short TD is already removed
2840 		 * from the TD list.
2841 		 */
2842 		if (trb_comp_code != COMP_STOPPED &&
2843 		    trb_comp_code != COMP_STOPPED_LENGTH_INVALID &&
2844 		    !ring_xrun_event &&
2845 		    !xhci_spurious_success_tx_event(xhci, ep_ring)) {
2846 			xhci_warn(xhci, "Event TRB for slot %u ep %u with no TDs queued\n",
2847 				  slot_id, ep_index);
2848 		}
2849 
2850 		ep->skip = false;
2851 		goto check_endpoint_halted;
2852 	}
2853 
2854 	do {
2855 		td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2856 				      td_list);
2857 
2858 		/* Is this a TRB in the currently executing TD? */
2859 		ep_seg = trb_in_td(td, ep_trb_dma);
2860 
2861 		if (!ep_seg) {
2862 
2863 			if (ep->skip && usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2864 				/* this event is unlikely to match any TD, don't skip them all */
2865 				if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID)
2866 					return 0;
2867 
2868 				skip_isoc_td(xhci, td, ep, status);
2869 
2870 				if (!list_empty(&ep_ring->td_list)) {
2871 					if (ring_xrun_event) {
2872 						/*
2873 						 * If we are here, we are on xHCI 1.0 host with no
2874 						 * idea how many TDs were missed or where the xrun
2875 						 * occurred. New TDs may have been added after the
2876 						 * xrun, so skip only one TD to be safe.
2877 						 */
2878 						xhci_dbg(xhci, "Skipped one TD for slot %u ep %u",
2879 								slot_id, ep_index);
2880 						return 0;
2881 					}
2882 					continue;
2883 				}
2884 
2885 				xhci_dbg(xhci, "All TDs skipped for slot %u ep %u. Clear skip flag.\n",
2886 					 slot_id, ep_index);
2887 				ep->skip = false;
2888 				td = NULL;
2889 				goto check_endpoint_halted;
2890 			}
2891 
2892 			/* TD was queued after xrun, maybe xrun was on a link, don't panic yet */
2893 			if (ring_xrun_event)
2894 				return 0;
2895 
2896 			/*
2897 			 * Skip the Force Stopped Event. The 'ep_trb' of FSE is not in the current
2898 			 * TD pointed by 'ep_ring->dequeue' because that the hardware dequeue
2899 			 * pointer still at the previous TRB of the current TD. The previous TRB
2900 			 * maybe a Link TD or the last TRB of the previous TD. The command
2901 			 * completion handle will take care the rest.
2902 			 */
2903 			if (trb_comp_code == COMP_STOPPED ||
2904 			    trb_comp_code == COMP_STOPPED_LENGTH_INVALID) {
2905 				return 0;
2906 			}
2907 
2908 			/*
2909 			 * Some hosts give a spurious success event after a short
2910 			 * transfer or error on last TRB. Ignore it.
2911 			 */
2912 			if (xhci_spurious_success_tx_event(xhci, ep_ring)) {
2913 				xhci_dbg(xhci, "Spurious event dma %pad, comp_code %u after %u\n",
2914 					 &ep_trb_dma, trb_comp_code, ep_ring->old_trb_comp_code);
2915 				ep_ring->old_trb_comp_code = 0;
2916 				return 0;
2917 			}
2918 
2919 			/* HC is busted, give up! */
2920 			goto debug_finding_td;
2921 		}
2922 
2923 		if (ep->skip) {
2924 			xhci_dbg(xhci,
2925 				 "Found td. Clear skip flag for slot %u ep %u.\n",
2926 				 slot_id, ep_index);
2927 			ep->skip = false;
2928 		}
2929 
2930 	/*
2931 	 * If ep->skip is set, it means there are missed tds on the
2932 	 * endpoint ring need to take care of.
2933 	 * Process them as short transfer until reach the td pointed by
2934 	 * the event.
2935 	 */
2936 	} while (ep->skip);
2937 
2938 	ep_ring->old_trb_comp_code = trb_comp_code;
2939 
2940 	/* Get out if a TD was queued at enqueue after the xrun occurred */
2941 	if (ring_xrun_event)
2942 		return 0;
2943 
2944 	ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / sizeof(*ep_trb)];
2945 	trace_xhci_handle_transfer(ep_ring, (struct xhci_generic_trb *) ep_trb, ep_trb_dma);
2946 
2947 	/*
2948 	 * No-op TRB could trigger interrupts in a case where a URB was killed
2949 	 * and a STALL_ERROR happens right after the endpoint ring stopped.
2950 	 * Reset the halted endpoint. Otherwise, the endpoint remains stalled
2951 	 * indefinitely.
2952 	 */
2953 
2954 	if (trb_is_noop(ep_trb))
2955 		goto check_endpoint_halted;
2956 
2957 	td->status = status;
2958 
2959 	/* update the urb's actual_length and give back to the core */
2960 	if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2961 		process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2962 	else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2963 		process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2964 	else
2965 		process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2966 	return 0;
2967 
2968 check_endpoint_halted:
2969 	if (xhci_halted_host_endpoint(ep_ctx, trb_comp_code))
2970 		xhci_handle_halted_endpoint(xhci, ep, td, EP_HARD_RESET);
2971 
2972 	return 0;
2973 
2974 debug_finding_td:
2975 	xhci_err(xhci, "Event dma %pad for ep %d status %d not part of TD at %016llx - %016llx\n",
2976 		 &ep_trb_dma, ep_index, trb_comp_code,
2977 		 (unsigned long long)xhci_trb_virt_to_dma(td->start_seg, td->start_trb),
2978 		 (unsigned long long)xhci_trb_virt_to_dma(td->end_seg, td->end_trb));
2979 
2980 	xhci_for_each_ring_seg(ep_ring->first_seg, ep_seg)
2981 		xhci_warn(xhci, "Ring seg %u dma %pad\n", ep_seg->num, &ep_seg->dma);
2982 
2983 	return -ESHUTDOWN;
2984 
2985 err_out:
2986 	xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2987 		 (unsigned long long) xhci_trb_virt_to_dma(
2988 			 ir->event_ring->deq_seg,
2989 			 ir->event_ring->dequeue),
2990 		 lower_32_bits(le64_to_cpu(event->buffer)),
2991 		 upper_32_bits(le64_to_cpu(event->buffer)),
2992 		 le32_to_cpu(event->transfer_len),
2993 		 le32_to_cpu(event->flags));
2994 	return -ENODEV;
2995 }
2996 
2997 /*
2998  * This function handles one OS-owned event on the event ring. It may drop
2999  * xhci->lock between event processing (e.g. to pass up port status changes).
3000  */
xhci_handle_event_trb(struct xhci_hcd * xhci,struct xhci_interrupter * ir,union xhci_trb * event)3001 static int xhci_handle_event_trb(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
3002 				 union xhci_trb *event)
3003 {
3004 	u32 trb_type;
3005 
3006 	trace_xhci_handle_event(ir->event_ring, &event->generic,
3007 				xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3008 						     ir->event_ring->dequeue));
3009 
3010 	/*
3011 	 * Barrier between reading the TRB_CYCLE (valid) flag before, and any
3012 	 * speculative reads of the event's flags/data below.
3013 	 */
3014 	rmb();
3015 	trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
3016 	/* FIXME: Handle more event types. */
3017 
3018 	switch (trb_type) {
3019 	case TRB_COMPLETION:
3020 		handle_cmd_completion(xhci, &event->event_cmd);
3021 		break;
3022 	case TRB_PORT_STATUS:
3023 		handle_port_status(xhci, event);
3024 		break;
3025 	case TRB_TRANSFER:
3026 		handle_tx_event(xhci, ir, &event->trans_event);
3027 		break;
3028 	case TRB_DEV_NOTE:
3029 		handle_device_notification(xhci, event);
3030 		break;
3031 	default:
3032 		if (trb_type >= TRB_VENDOR_DEFINED_LOW)
3033 			handle_vendor_event(xhci, event, trb_type);
3034 		else
3035 			xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
3036 	}
3037 	/* Any of the above functions may drop and re-acquire the lock, so check
3038 	 * to make sure a watchdog timer didn't mark the host as non-responsive.
3039 	 */
3040 	if (xhci->xhc_state & XHCI_STATE_DYING) {
3041 		xhci_dbg(xhci, "xHCI host dying, returning from event handler.\n");
3042 		return -ENODEV;
3043 	}
3044 
3045 	return 0;
3046 }
3047 
3048 /*
3049  * Update Event Ring Dequeue Pointer:
3050  * - When all events have finished
3051  * - To avoid "Event Ring Full Error" condition
3052  */
xhci_update_erst_dequeue(struct xhci_hcd * xhci,struct xhci_interrupter * ir,bool clear_ehb)3053 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
3054 				     struct xhci_interrupter *ir,
3055 				     bool clear_ehb)
3056 {
3057 	u64 temp_64;
3058 	dma_addr_t deq;
3059 
3060 	temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3061 	deq = xhci_trb_virt_to_dma(ir->event_ring->deq_seg,
3062 				   ir->event_ring->dequeue);
3063 	if (deq == 0)
3064 		xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
3065 	/*
3066 	 * Per 4.9.4, Software writes to the ERDP register shall always advance
3067 	 * the Event Ring Dequeue Pointer value.
3068 	 */
3069 	if ((temp_64 & ERST_PTR_MASK) == (deq & ERST_PTR_MASK) && !clear_ehb)
3070 		return;
3071 
3072 	/* Update HC event ring dequeue pointer */
3073 	temp_64 = ir->event_ring->deq_seg->num & ERST_DESI_MASK;
3074 	temp_64 |= deq & ERST_PTR_MASK;
3075 
3076 	/* Clear the event handler busy flag (RW1C) */
3077 	if (clear_ehb)
3078 		temp_64 |= ERST_EHB;
3079 	xhci_write_64(xhci, temp_64, &ir->ir_set->erst_dequeue);
3080 }
3081 
3082 /* Clear the interrupt pending bit for a specific interrupter. */
xhci_clear_interrupt_pending(struct xhci_interrupter * ir)3083 static void xhci_clear_interrupt_pending(struct xhci_interrupter *ir)
3084 {
3085 	if (!ir->ip_autoclear) {
3086 		u32 irq_pending;
3087 
3088 		irq_pending = readl(&ir->ir_set->irq_pending);
3089 		irq_pending |= IMAN_IP;
3090 		writel(irq_pending, &ir->ir_set->irq_pending);
3091 	}
3092 }
3093 
3094 /*
3095  * Handle all OS-owned events on an interrupter event ring. It may drop
3096  * and reaquire xhci->lock between event processing.
3097  */
xhci_handle_events(struct xhci_hcd * xhci,struct xhci_interrupter * ir)3098 static int xhci_handle_events(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
3099 {
3100 	int event_loop = 0;
3101 	int err;
3102 	u64 temp;
3103 
3104 	xhci_clear_interrupt_pending(ir);
3105 
3106 	/* Event ring hasn't been allocated yet. */
3107 	if (!ir->event_ring || !ir->event_ring->dequeue) {
3108 		xhci_err(xhci, "ERROR interrupter event ring not ready\n");
3109 		return -ENOMEM;
3110 	}
3111 
3112 	if (xhci->xhc_state & XHCI_STATE_DYING ||
3113 	    xhci->xhc_state & XHCI_STATE_HALTED) {
3114 		xhci_dbg(xhci, "xHCI dying, ignoring interrupt. Shouldn't IRQs be disabled?\n");
3115 
3116 		/* Clear the event handler busy flag (RW1C) */
3117 		temp = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
3118 		xhci_write_64(xhci, temp | ERST_EHB, &ir->ir_set->erst_dequeue);
3119 		return -ENODEV;
3120 	}
3121 
3122 	/* Process all OS owned event TRBs on this event ring */
3123 	while (unhandled_event_trb(ir->event_ring)) {
3124 		err = xhci_handle_event_trb(xhci, ir, ir->event_ring->dequeue);
3125 
3126 		/*
3127 		 * If half a segment of events have been handled in one go then
3128 		 * update ERDP, and force isoc trbs to interrupt more often
3129 		 */
3130 		if (event_loop++ > TRBS_PER_SEGMENT / 2) {
3131 			xhci_update_erst_dequeue(xhci, ir, false);
3132 
3133 			if (ir->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3134 				ir->isoc_bei_interval = ir->isoc_bei_interval / 2;
3135 
3136 			event_loop = 0;
3137 		}
3138 
3139 		/* Update SW event ring dequeue pointer */
3140 		inc_deq(xhci, ir->event_ring);
3141 
3142 		if (err)
3143 			break;
3144 	}
3145 
3146 	xhci_update_erst_dequeue(xhci, ir, true);
3147 
3148 	return 0;
3149 }
3150 
3151 /*
3152  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3153  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
3154  * indicators of an event TRB error, but we check the status *first* to be safe.
3155  */
xhci_irq(struct usb_hcd * hcd)3156 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3157 {
3158 	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3159 	irqreturn_t ret = IRQ_HANDLED;
3160 	u32 status;
3161 
3162 	spin_lock(&xhci->lock);
3163 	/* Check if the xHC generated the interrupt, or the irq is shared */
3164 	status = readl(&xhci->op_regs->status);
3165 	if (status == ~(u32)0) {
3166 		xhci_hc_died(xhci);
3167 		goto out;
3168 	}
3169 
3170 	if (!(status & STS_EINT)) {
3171 		ret = IRQ_NONE;
3172 		goto out;
3173 	}
3174 
3175 	if (status & STS_HCE) {
3176 		xhci_warn(xhci, "WARNING: Host Controller Error\n");
3177 		goto out;
3178 	}
3179 
3180 	if (status & STS_FATAL) {
3181 		xhci_warn(xhci, "WARNING: Host System Error\n");
3182 		xhci_halt(xhci);
3183 		goto out;
3184 	}
3185 
3186 	/*
3187 	 * Clear the op reg interrupt status first,
3188 	 * so we can receive interrupts from other MSI-X interrupters.
3189 	 * Write 1 to clear the interrupt status.
3190 	 */
3191 	status |= STS_EINT;
3192 	writel(status, &xhci->op_regs->status);
3193 
3194 	/* This is the handler of the primary interrupter */
3195 	xhci_handle_events(xhci, xhci->interrupters[0]);
3196 out:
3197 	spin_unlock(&xhci->lock);
3198 
3199 	return ret;
3200 }
3201 
xhci_msi_irq(int irq,void * hcd)3202 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3203 {
3204 	return xhci_irq(hcd);
3205 }
3206 EXPORT_SYMBOL_GPL(xhci_msi_irq);
3207 
3208 /****		Endpoint Ring Operations	****/
3209 
3210 /*
3211  * Generic function for queueing a TRB on a ring.
3212  * The caller must have checked to make sure there's room on the ring.
3213  *
3214  * @more_trbs_coming:	Will you enqueue more TRBs before calling
3215  *			prepare_transfer()?
3216  */
queue_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming,u32 field1,u32 field2,u32 field3,u32 field4)3217 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3218 		bool more_trbs_coming,
3219 		u32 field1, u32 field2, u32 field3, u32 field4)
3220 {
3221 	struct xhci_generic_trb *trb;
3222 
3223 	trb = &ring->enqueue->generic;
3224 	trb->field[0] = cpu_to_le32(field1);
3225 	trb->field[1] = cpu_to_le32(field2);
3226 	trb->field[2] = cpu_to_le32(field3);
3227 	/* make sure TRB is fully written before giving it to the controller */
3228 	wmb();
3229 	trb->field[3] = cpu_to_le32(field4);
3230 
3231 	trace_xhci_queue_trb(ring, trb,
3232 			     xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue));
3233 
3234 	inc_enq(xhci, ring, more_trbs_coming);
3235 }
3236 
3237 /*
3238  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3239  * expand ring if it start to be full.
3240  */
prepare_ring(struct xhci_hcd * xhci,struct xhci_ring * ep_ring,u32 ep_state,unsigned int num_trbs,gfp_t mem_flags)3241 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3242 		u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3243 {
3244 	unsigned int new_segs = 0;
3245 
3246 	/* Make sure the endpoint has been added to xHC schedule */
3247 	switch (ep_state) {
3248 	case EP_STATE_DISABLED:
3249 		/*
3250 		 * USB core changed config/interfaces without notifying us,
3251 		 * or hardware is reporting the wrong state.
3252 		 */
3253 		xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3254 		return -ENOENT;
3255 	case EP_STATE_ERROR:
3256 		xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3257 		/* FIXME event handling code for error needs to clear it */
3258 		/* XXX not sure if this should be -ENOENT or not */
3259 		return -EINVAL;
3260 	case EP_STATE_HALTED:
3261 		xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3262 		break;
3263 	case EP_STATE_STOPPED:
3264 	case EP_STATE_RUNNING:
3265 		break;
3266 	default:
3267 		xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3268 		/*
3269 		 * FIXME issue Configure Endpoint command to try to get the HC
3270 		 * back into a known state.
3271 		 */
3272 		return -EINVAL;
3273 	}
3274 
3275 	if (ep_ring != xhci->cmd_ring) {
3276 		new_segs = xhci_ring_expansion_needed(xhci, ep_ring, num_trbs);
3277 	} else if (xhci_num_trbs_free(ep_ring) <= num_trbs) {
3278 		xhci_err(xhci, "Do not support expand command ring\n");
3279 		return -ENOMEM;
3280 	}
3281 
3282 	if (new_segs) {
3283 		xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3284 				"ERROR no room on ep ring, try ring expansion");
3285 		if (xhci_ring_expansion(xhci, ep_ring, new_segs, mem_flags)) {
3286 			xhci_err(xhci, "Ring expansion failed\n");
3287 			return -ENOMEM;
3288 		}
3289 	}
3290 
3291 	/* Ensure that new TRBs won't overwrite a link */
3292 	if (trb_is_link(ep_ring->enqueue))
3293 		inc_enq_past_link(xhci, ep_ring, 0);
3294 
3295 	if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3296 		xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3297 		return -EINVAL;
3298 	}
3299 
3300 	return 0;
3301 }
3302 
prepare_transfer(struct xhci_hcd * xhci,struct xhci_virt_device * xdev,unsigned int ep_index,unsigned int stream_id,unsigned int num_trbs,struct urb * urb,unsigned int td_index,gfp_t mem_flags)3303 static int prepare_transfer(struct xhci_hcd *xhci,
3304 		struct xhci_virt_device *xdev,
3305 		unsigned int ep_index,
3306 		unsigned int stream_id,
3307 		unsigned int num_trbs,
3308 		struct urb *urb,
3309 		unsigned int td_index,
3310 		gfp_t mem_flags)
3311 {
3312 	int ret;
3313 	struct urb_priv *urb_priv;
3314 	struct xhci_td	*td;
3315 	struct xhci_ring *ep_ring;
3316 	struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3317 
3318 	ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3319 					      stream_id);
3320 	if (!ep_ring) {
3321 		xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3322 				stream_id);
3323 		return -EINVAL;
3324 	}
3325 
3326 	ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3327 			   num_trbs, mem_flags);
3328 	if (ret)
3329 		return ret;
3330 
3331 	urb_priv = urb->hcpriv;
3332 	td = &urb_priv->td[td_index];
3333 
3334 	INIT_LIST_HEAD(&td->td_list);
3335 	INIT_LIST_HEAD(&td->cancelled_td_list);
3336 
3337 	if (td_index == 0) {
3338 		ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3339 		if (unlikely(ret))
3340 			return ret;
3341 	}
3342 
3343 	td->urb = urb;
3344 	/* Add this TD to the tail of the endpoint ring's TD list */
3345 	list_add_tail(&td->td_list, &ep_ring->td_list);
3346 	td->start_seg = ep_ring->enq_seg;
3347 	td->start_trb = ep_ring->enqueue;
3348 
3349 	return 0;
3350 }
3351 
count_trbs(u64 addr,u64 len)3352 unsigned int count_trbs(u64 addr, u64 len)
3353 {
3354 	unsigned int num_trbs;
3355 
3356 	num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3357 			TRB_MAX_BUFF_SIZE);
3358 	if (num_trbs == 0)
3359 		num_trbs++;
3360 
3361 	return num_trbs;
3362 }
3363 
count_trbs_needed(struct urb * urb)3364 static inline unsigned int count_trbs_needed(struct urb *urb)
3365 {
3366 	return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3367 }
3368 
count_sg_trbs_needed(struct urb * urb)3369 static unsigned int count_sg_trbs_needed(struct urb *urb)
3370 {
3371 	struct scatterlist *sg;
3372 	unsigned int i, len, full_len, num_trbs = 0;
3373 
3374 	full_len = urb->transfer_buffer_length;
3375 
3376 	for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3377 		len = sg_dma_len(sg);
3378 		num_trbs += count_trbs(sg_dma_address(sg), len);
3379 		len = min_t(unsigned int, len, full_len);
3380 		full_len -= len;
3381 		if (full_len == 0)
3382 			break;
3383 	}
3384 
3385 	return num_trbs;
3386 }
3387 
count_isoc_trbs_needed(struct urb * urb,int i)3388 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3389 {
3390 	u64 addr, len;
3391 
3392 	addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3393 	len = urb->iso_frame_desc[i].length;
3394 
3395 	return count_trbs(addr, len);
3396 }
3397 
check_trb_math(struct urb * urb,int running_total)3398 static void check_trb_math(struct urb *urb, int running_total)
3399 {
3400 	if (unlikely(running_total != urb->transfer_buffer_length))
3401 		dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3402 				"queued %#x (%d), asked for %#x (%d)\n",
3403 				__func__,
3404 				urb->ep->desc.bEndpointAddress,
3405 				running_total, running_total,
3406 				urb->transfer_buffer_length,
3407 				urb->transfer_buffer_length);
3408 }
3409 
giveback_first_trb(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index,unsigned int stream_id,int start_cycle,struct xhci_generic_trb * start_trb)3410 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3411 		unsigned int ep_index, unsigned int stream_id, int start_cycle,
3412 		struct xhci_generic_trb *start_trb)
3413 {
3414 	/*
3415 	 * Pass all the TRBs to the hardware at once and make sure this write
3416 	 * isn't reordered.
3417 	 */
3418 	wmb();
3419 	if (start_cycle)
3420 		start_trb->field[3] |= cpu_to_le32(start_cycle);
3421 	else
3422 		start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3423 	xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3424 }
3425 
check_interval(struct urb * urb,struct xhci_ep_ctx * ep_ctx)3426 static void check_interval(struct urb *urb, struct xhci_ep_ctx *ep_ctx)
3427 {
3428 	int xhci_interval;
3429 	int ep_interval;
3430 
3431 	xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3432 	ep_interval = urb->interval;
3433 
3434 	/* Convert to microframes */
3435 	if (urb->dev->speed == USB_SPEED_LOW ||
3436 			urb->dev->speed == USB_SPEED_FULL)
3437 		ep_interval *= 8;
3438 
3439 	/* FIXME change this to a warning and a suggestion to use the new API
3440 	 * to set the polling interval (once the API is added).
3441 	 */
3442 	if (xhci_interval != ep_interval) {
3443 		dev_dbg_ratelimited(&urb->dev->dev,
3444 				"Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3445 				ep_interval, str_plural(ep_interval),
3446 				xhci_interval, str_plural(xhci_interval));
3447 		urb->interval = xhci_interval;
3448 		/* Convert back to frames for LS/FS devices */
3449 		if (urb->dev->speed == USB_SPEED_LOW ||
3450 				urb->dev->speed == USB_SPEED_FULL)
3451 			urb->interval /= 8;
3452 	}
3453 }
3454 
3455 /*
3456  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3457  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3458  * (comprised of sg list entries) can take several service intervals to
3459  * transmit.
3460  */
xhci_queue_intr_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3461 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3462 		struct urb *urb, int slot_id, unsigned int ep_index)
3463 {
3464 	struct xhci_ep_ctx *ep_ctx;
3465 
3466 	ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3467 	check_interval(urb, ep_ctx);
3468 
3469 	return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3470 }
3471 
3472 /*
3473  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3474  * packets remaining in the TD (*not* including this TRB).
3475  *
3476  * Total TD packet count = total_packet_count =
3477  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3478  *
3479  * Packets transferred up to and including this TRB = packets_transferred =
3480  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3481  *
3482  * TD size = total_packet_count - packets_transferred
3483  *
3484  * For xHCI 0.96 and older, TD size field should be the remaining bytes
3485  * including this TRB, right shifted by 10
3486  *
3487  * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3488  * This is taken care of in the TRB_TD_SIZE() macro
3489  *
3490  * The last TRB in a TD must have the TD size set to zero.
3491  */
xhci_td_remainder(struct xhci_hcd * xhci,int transferred,int trb_buff_len,unsigned int td_total_len,struct urb * urb,bool more_trbs_coming)3492 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3493 			      int trb_buff_len, unsigned int td_total_len,
3494 			      struct urb *urb, bool more_trbs_coming)
3495 {
3496 	u32 maxp, total_packet_count;
3497 
3498 	/* MTK xHCI 0.96 contains some features from 1.0 */
3499 	if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3500 		return ((td_total_len - transferred) >> 10);
3501 
3502 	/* One TRB with a zero-length data packet. */
3503 	if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3504 	    trb_buff_len == td_total_len)
3505 		return 0;
3506 
3507 	/* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3508 	if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3509 		trb_buff_len = 0;
3510 
3511 	maxp = usb_endpoint_maxp(&urb->ep->desc);
3512 	total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3513 
3514 	/* Queueing functions don't count the current TRB into transferred */
3515 	return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3516 }
3517 
3518 
xhci_align_td(struct xhci_hcd * xhci,struct urb * urb,u32 enqd_len,u32 * trb_buff_len,struct xhci_segment * seg)3519 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3520 			 u32 *trb_buff_len, struct xhci_segment *seg)
3521 {
3522 	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
3523 	unsigned int unalign;
3524 	unsigned int max_pkt;
3525 	u32 new_buff_len;
3526 	size_t len;
3527 
3528 	max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3529 	unalign = (enqd_len + *trb_buff_len) % max_pkt;
3530 
3531 	/* we got lucky, last normal TRB data on segment is packet aligned */
3532 	if (unalign == 0)
3533 		return 0;
3534 
3535 	xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3536 		 unalign, *trb_buff_len);
3537 
3538 	/* is the last nornal TRB alignable by splitting it */
3539 	if (*trb_buff_len > unalign) {
3540 		*trb_buff_len -= unalign;
3541 		xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3542 		return 0;
3543 	}
3544 
3545 	/*
3546 	 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3547 	 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3548 	 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3549 	 */
3550 	new_buff_len = max_pkt - (enqd_len % max_pkt);
3551 
3552 	if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3553 		new_buff_len = (urb->transfer_buffer_length - enqd_len);
3554 
3555 	/* create a max max_pkt sized bounce buffer pointed to by last trb */
3556 	if (usb_urb_dir_out(urb)) {
3557 		if (urb->num_sgs) {
3558 			len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3559 						 seg->bounce_buf, new_buff_len, enqd_len);
3560 			if (len != new_buff_len)
3561 				xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3562 					  len, new_buff_len);
3563 		} else {
3564 			memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3565 		}
3566 
3567 		seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3568 						 max_pkt, DMA_TO_DEVICE);
3569 	} else {
3570 		seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3571 						 max_pkt, DMA_FROM_DEVICE);
3572 	}
3573 
3574 	if (dma_mapping_error(dev, seg->bounce_dma)) {
3575 		/* try without aligning. Some host controllers survive */
3576 		xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3577 		return 0;
3578 	}
3579 	*trb_buff_len = new_buff_len;
3580 	seg->bounce_len = new_buff_len;
3581 	seg->bounce_offs = enqd_len;
3582 
3583 	xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3584 
3585 	return 1;
3586 }
3587 
3588 /* This is very similar to what ehci-q.c qtd_fill() does */
xhci_queue_bulk_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3589 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3590 		struct urb *urb, int slot_id, unsigned int ep_index)
3591 {
3592 	struct xhci_ring *ring;
3593 	struct urb_priv *urb_priv;
3594 	struct xhci_td *td;
3595 	struct xhci_generic_trb *start_trb;
3596 	struct scatterlist *sg = NULL;
3597 	bool more_trbs_coming = true;
3598 	bool need_zero_pkt = false;
3599 	bool first_trb = true;
3600 	unsigned int num_trbs;
3601 	unsigned int start_cycle, num_sgs = 0;
3602 	unsigned int enqd_len, block_len, trb_buff_len, full_len;
3603 	int sent_len, ret;
3604 	u32 field, length_field, remainder;
3605 	u64 addr, send_addr;
3606 
3607 	ring = xhci_urb_to_transfer_ring(xhci, urb);
3608 	if (!ring)
3609 		return -EINVAL;
3610 
3611 	full_len = urb->transfer_buffer_length;
3612 	/* If we have scatter/gather list, we use it. */
3613 	if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3614 		num_sgs = urb->num_mapped_sgs;
3615 		sg = urb->sg;
3616 		addr = (u64) sg_dma_address(sg);
3617 		block_len = sg_dma_len(sg);
3618 		num_trbs = count_sg_trbs_needed(urb);
3619 	} else {
3620 		num_trbs = count_trbs_needed(urb);
3621 		addr = (u64) urb->transfer_dma;
3622 		block_len = full_len;
3623 	}
3624 	ret = prepare_transfer(xhci, xhci->devs[slot_id],
3625 			ep_index, urb->stream_id,
3626 			num_trbs, urb, 0, mem_flags);
3627 	if (unlikely(ret < 0))
3628 		return ret;
3629 
3630 	urb_priv = urb->hcpriv;
3631 
3632 	/* Deal with URB_ZERO_PACKET - need one more td/trb */
3633 	if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3634 		need_zero_pkt = true;
3635 
3636 	td = &urb_priv->td[0];
3637 
3638 	/*
3639 	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3640 	 * until we've finished creating all the other TRBs.  The ring's cycle
3641 	 * state may change as we enqueue the other TRBs, so save it too.
3642 	 */
3643 	start_trb = &ring->enqueue->generic;
3644 	start_cycle = ring->cycle_state;
3645 	send_addr = addr;
3646 
3647 	/* Queue the TRBs, even if they are zero-length */
3648 	for (enqd_len = 0; first_trb || enqd_len < full_len;
3649 			enqd_len += trb_buff_len) {
3650 		field = TRB_TYPE(TRB_NORMAL);
3651 
3652 		/* TRB buffer should not cross 64KB boundaries */
3653 		trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3654 		trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3655 
3656 		if (enqd_len + trb_buff_len > full_len)
3657 			trb_buff_len = full_len - enqd_len;
3658 
3659 		/* Don't change the cycle bit of the first TRB until later */
3660 		if (first_trb) {
3661 			first_trb = false;
3662 			if (start_cycle == 0)
3663 				field |= TRB_CYCLE;
3664 		} else
3665 			field |= ring->cycle_state;
3666 
3667 		/* Chain all the TRBs together; clear the chain bit in the last
3668 		 * TRB to indicate it's the last TRB in the chain.
3669 		 */
3670 		if (enqd_len + trb_buff_len < full_len) {
3671 			field |= TRB_CHAIN;
3672 			if (trb_is_link(ring->enqueue + 1)) {
3673 				if (xhci_align_td(xhci, urb, enqd_len,
3674 						  &trb_buff_len,
3675 						  ring->enq_seg)) {
3676 					send_addr = ring->enq_seg->bounce_dma;
3677 					/* assuming TD won't span 2 segs */
3678 					td->bounce_seg = ring->enq_seg;
3679 				}
3680 			}
3681 		}
3682 		if (enqd_len + trb_buff_len >= full_len) {
3683 			field &= ~TRB_CHAIN;
3684 			field |= TRB_IOC;
3685 			more_trbs_coming = false;
3686 			td->end_trb = ring->enqueue;
3687 			td->end_seg = ring->enq_seg;
3688 			if (xhci_urb_suitable_for_idt(urb)) {
3689 				memcpy(&send_addr, urb->transfer_buffer,
3690 				       trb_buff_len);
3691 				le64_to_cpus(&send_addr);
3692 				field |= TRB_IDT;
3693 			}
3694 		}
3695 
3696 		/* Only set interrupt on short packet for IN endpoints */
3697 		if (usb_urb_dir_in(urb))
3698 			field |= TRB_ISP;
3699 
3700 		/* Set the TRB length, TD size, and interrupter fields. */
3701 		remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3702 					      full_len, urb, more_trbs_coming);
3703 
3704 		length_field = TRB_LEN(trb_buff_len) |
3705 			TRB_TD_SIZE(remainder) |
3706 			TRB_INTR_TARGET(0);
3707 
3708 		queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3709 				lower_32_bits(send_addr),
3710 				upper_32_bits(send_addr),
3711 				length_field,
3712 				field);
3713 		addr += trb_buff_len;
3714 		sent_len = trb_buff_len;
3715 
3716 		while (sg && sent_len >= block_len) {
3717 			/* New sg entry */
3718 			--num_sgs;
3719 			sent_len -= block_len;
3720 			sg = sg_next(sg);
3721 			if (num_sgs != 0 && sg) {
3722 				block_len = sg_dma_len(sg);
3723 				addr = (u64) sg_dma_address(sg);
3724 				addr += sent_len;
3725 			}
3726 		}
3727 		block_len -= sent_len;
3728 		send_addr = addr;
3729 	}
3730 
3731 	if (need_zero_pkt) {
3732 		ret = prepare_transfer(xhci, xhci->devs[slot_id],
3733 				       ep_index, urb->stream_id,
3734 				       1, urb, 1, mem_flags);
3735 		urb_priv->td[1].end_trb = ring->enqueue;
3736 		urb_priv->td[1].end_seg = ring->enq_seg;
3737 		field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3738 		queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3739 	}
3740 
3741 	check_trb_math(urb, enqd_len);
3742 	giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3743 			start_cycle, start_trb);
3744 	return 0;
3745 }
3746 
3747 /* Caller must have locked xhci->lock */
xhci_queue_ctrl_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3748 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3749 		struct urb *urb, int slot_id, unsigned int ep_index)
3750 {
3751 	struct xhci_ring *ep_ring;
3752 	int num_trbs;
3753 	int ret;
3754 	struct usb_ctrlrequest *setup;
3755 	struct xhci_generic_trb *start_trb;
3756 	int start_cycle;
3757 	u32 field;
3758 	struct urb_priv *urb_priv;
3759 	struct xhci_td *td;
3760 
3761 	ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3762 	if (!ep_ring)
3763 		return -EINVAL;
3764 
3765 	/*
3766 	 * Need to copy setup packet into setup TRB, so we can't use the setup
3767 	 * DMA address.
3768 	 */
3769 	if (!urb->setup_packet)
3770 		return -EINVAL;
3771 
3772 	if ((xhci->quirks & XHCI_ETRON_HOST) &&
3773 	    urb->dev->speed >= USB_SPEED_SUPER) {
3774 		/*
3775 		 * If next available TRB is the Link TRB in the ring segment then
3776 		 * enqueue a No Op TRB, this can prevent the Setup and Data Stage
3777 		 * TRB to be breaked by the Link TRB.
3778 		 */
3779 		if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue + 1)) {
3780 			field = TRB_TYPE(TRB_TR_NOOP) | ep_ring->cycle_state;
3781 			queue_trb(xhci, ep_ring, false, 0, 0,
3782 					TRB_INTR_TARGET(0), field);
3783 		}
3784 	}
3785 
3786 	/* 1 TRB for setup, 1 for status */
3787 	num_trbs = 2;
3788 	/*
3789 	 * Don't need to check if we need additional event data and normal TRBs,
3790 	 * since data in control transfers will never get bigger than 16MB
3791 	 * XXX: can we get a buffer that crosses 64KB boundaries?
3792 	 */
3793 	if (urb->transfer_buffer_length > 0)
3794 		num_trbs++;
3795 	ret = prepare_transfer(xhci, xhci->devs[slot_id],
3796 			ep_index, urb->stream_id,
3797 			num_trbs, urb, 0, mem_flags);
3798 	if (ret < 0)
3799 		return ret;
3800 
3801 	urb_priv = urb->hcpriv;
3802 	td = &urb_priv->td[0];
3803 
3804 	/*
3805 	 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3806 	 * until we've finished creating all the other TRBs.  The ring's cycle
3807 	 * state may change as we enqueue the other TRBs, so save it too.
3808 	 */
3809 	start_trb = &ep_ring->enqueue->generic;
3810 	start_cycle = ep_ring->cycle_state;
3811 
3812 	/* Queue setup TRB - see section 6.4.1.2.1 */
3813 	/* FIXME better way to translate setup_packet into two u32 fields? */
3814 	setup = (struct usb_ctrlrequest *) urb->setup_packet;
3815 	field = 0;
3816 	field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3817 	if (start_cycle == 0)
3818 		field |= 0x1;
3819 
3820 	/* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3821 	if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3822 		if (urb->transfer_buffer_length > 0) {
3823 			if (setup->bRequestType & USB_DIR_IN)
3824 				field |= TRB_TX_TYPE(TRB_DATA_IN);
3825 			else
3826 				field |= TRB_TX_TYPE(TRB_DATA_OUT);
3827 		}
3828 	}
3829 
3830 	queue_trb(xhci, ep_ring, true,
3831 		  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3832 		  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3833 		  TRB_LEN(8) | TRB_INTR_TARGET(0),
3834 		  /* Immediate data in pointer */
3835 		  field);
3836 
3837 	/* If there's data, queue data TRBs */
3838 	/* Only set interrupt on short packet for IN endpoints */
3839 	if (usb_urb_dir_in(urb))
3840 		field = TRB_ISP | TRB_TYPE(TRB_DATA);
3841 	else
3842 		field = TRB_TYPE(TRB_DATA);
3843 
3844 	if (urb->transfer_buffer_length > 0) {
3845 		u32 length_field, remainder;
3846 		u64 addr;
3847 
3848 		if (xhci_urb_suitable_for_idt(urb)) {
3849 			memcpy(&addr, urb->transfer_buffer,
3850 			       urb->transfer_buffer_length);
3851 			le64_to_cpus(&addr);
3852 			field |= TRB_IDT;
3853 		} else {
3854 			addr = (u64) urb->transfer_dma;
3855 		}
3856 
3857 		remainder = xhci_td_remainder(xhci, 0,
3858 				urb->transfer_buffer_length,
3859 				urb->transfer_buffer_length,
3860 				urb, 1);
3861 		length_field = TRB_LEN(urb->transfer_buffer_length) |
3862 				TRB_TD_SIZE(remainder) |
3863 				TRB_INTR_TARGET(0);
3864 		if (setup->bRequestType & USB_DIR_IN)
3865 			field |= TRB_DIR_IN;
3866 		queue_trb(xhci, ep_ring, true,
3867 				lower_32_bits(addr),
3868 				upper_32_bits(addr),
3869 				length_field,
3870 				field | ep_ring->cycle_state);
3871 	}
3872 
3873 	/* Save the DMA address of the last TRB in the TD */
3874 	td->end_trb = ep_ring->enqueue;
3875 	td->end_seg = ep_ring->enq_seg;
3876 
3877 	/* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3878 	/* If the device sent data, the status stage is an OUT transfer */
3879 	if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3880 		field = 0;
3881 	else
3882 		field = TRB_DIR_IN;
3883 	queue_trb(xhci, ep_ring, false,
3884 			0,
3885 			0,
3886 			TRB_INTR_TARGET(0),
3887 			/* Event on completion */
3888 			field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3889 
3890 	giveback_first_trb(xhci, slot_id, ep_index, 0,
3891 			start_cycle, start_trb);
3892 	return 0;
3893 }
3894 
3895 /*
3896  * The transfer burst count field of the isochronous TRB defines the number of
3897  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3898  * devices can burst up to bMaxBurst number of packets per service interval.
3899  * This field is zero based, meaning a value of zero in the field means one
3900  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3901  * zero.  Only xHCI 1.0 host controllers support this field.
3902  */
xhci_get_burst_count(struct xhci_hcd * xhci,struct urb * urb,unsigned int total_packet_count)3903 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3904 		struct urb *urb, unsigned int total_packet_count)
3905 {
3906 	unsigned int max_burst;
3907 
3908 	if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3909 		return 0;
3910 
3911 	max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3912 	return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3913 }
3914 
3915 /*
3916  * Returns the number of packets in the last "burst" of packets.  This field is
3917  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3918  * the last burst packet count is equal to the total number of packets in the
3919  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3920  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3921  * contain 1 to (bMaxBurst + 1) packets.
3922  */
xhci_get_last_burst_packet_count(struct xhci_hcd * xhci,struct urb * urb,unsigned int total_packet_count)3923 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3924 		struct urb *urb, unsigned int total_packet_count)
3925 {
3926 	unsigned int max_burst;
3927 	unsigned int residue;
3928 
3929 	if (xhci->hci_version < 0x100)
3930 		return 0;
3931 
3932 	if (urb->dev->speed >= USB_SPEED_SUPER) {
3933 		/* bMaxBurst is zero based: 0 means 1 packet per burst */
3934 		max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3935 		residue = total_packet_count % (max_burst + 1);
3936 		/* If residue is zero, the last burst contains (max_burst + 1)
3937 		 * number of packets, but the TLBPC field is zero-based.
3938 		 */
3939 		if (residue == 0)
3940 			return max_burst;
3941 		return residue - 1;
3942 	}
3943 	if (total_packet_count == 0)
3944 		return 0;
3945 	return total_packet_count - 1;
3946 }
3947 
3948 /*
3949  * Calculates Frame ID field of the isochronous TRB identifies the
3950  * target frame that the Interval associated with this Isochronous
3951  * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3952  *
3953  * Returns actual frame id on success, negative value on error.
3954  */
xhci_get_isoc_frame_id(struct xhci_hcd * xhci,struct urb * urb,int index)3955 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3956 		struct urb *urb, int index)
3957 {
3958 	int start_frame, ist, ret = 0;
3959 	int start_frame_id, end_frame_id, current_frame_id;
3960 
3961 	if (urb->dev->speed == USB_SPEED_LOW ||
3962 			urb->dev->speed == USB_SPEED_FULL)
3963 		start_frame = urb->start_frame + index * urb->interval;
3964 	else
3965 		start_frame = (urb->start_frame + index * urb->interval) >> 3;
3966 
3967 	/* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3968 	 *
3969 	 * If bit [3] of IST is cleared to '0', software can add a TRB no
3970 	 * later than IST[2:0] Microframes before that TRB is scheduled to
3971 	 * be executed.
3972 	 * If bit [3] of IST is set to '1', software can add a TRB no later
3973 	 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3974 	 */
3975 	ist = HCS_IST(xhci->hcs_params2) & 0x7;
3976 	if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3977 		ist <<= 3;
3978 
3979 	/* Software shall not schedule an Isoch TD with a Frame ID value that
3980 	 * is less than the Start Frame ID or greater than the End Frame ID,
3981 	 * where:
3982 	 *
3983 	 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3984 	 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3985 	 *
3986 	 * Both the End Frame ID and Start Frame ID values are calculated
3987 	 * in microframes. When software determines the valid Frame ID value;
3988 	 * The End Frame ID value should be rounded down to the nearest Frame
3989 	 * boundary, and the Start Frame ID value should be rounded up to the
3990 	 * nearest Frame boundary.
3991 	 */
3992 	current_frame_id = readl(&xhci->run_regs->microframe_index);
3993 	start_frame_id = roundup(current_frame_id + ist + 1, 8);
3994 	end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3995 
3996 	start_frame &= 0x7ff;
3997 	start_frame_id = (start_frame_id >> 3) & 0x7ff;
3998 	end_frame_id = (end_frame_id >> 3) & 0x7ff;
3999 
4000 	if (start_frame_id < end_frame_id) {
4001 		if (start_frame > end_frame_id ||
4002 				start_frame < start_frame_id)
4003 			ret = -EINVAL;
4004 	} else if (start_frame_id > end_frame_id) {
4005 		if ((start_frame > end_frame_id &&
4006 				start_frame < start_frame_id))
4007 			ret = -EINVAL;
4008 	} else {
4009 			ret = -EINVAL;
4010 	}
4011 
4012 	if (index == 0) {
4013 		if (ret == -EINVAL || start_frame == start_frame_id) {
4014 			start_frame = start_frame_id + 1;
4015 			if (urb->dev->speed == USB_SPEED_LOW ||
4016 					urb->dev->speed == USB_SPEED_FULL)
4017 				urb->start_frame = start_frame;
4018 			else
4019 				urb->start_frame = start_frame << 3;
4020 			ret = 0;
4021 		}
4022 	}
4023 
4024 	if (ret) {
4025 		xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
4026 				start_frame, current_frame_id, index,
4027 				start_frame_id, end_frame_id);
4028 		xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
4029 		return ret;
4030 	}
4031 
4032 	return start_frame;
4033 }
4034 
4035 /* Check if we should generate event interrupt for a TD in an isoc URB */
trb_block_event_intr(struct xhci_hcd * xhci,int num_tds,int i,struct xhci_interrupter * ir)4036 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i,
4037 				 struct xhci_interrupter *ir)
4038 {
4039 	if (xhci->hci_version < 0x100)
4040 		return false;
4041 	/* always generate an event interrupt for the last TD */
4042 	if (i == num_tds - 1)
4043 		return false;
4044 	/*
4045 	 * If AVOID_BEI is set the host handles full event rings poorly,
4046 	 * generate an event at least every 8th TD to clear the event ring
4047 	 */
4048 	if (i && ir->isoc_bei_interval && xhci->quirks & XHCI_AVOID_BEI)
4049 		return !!(i % ir->isoc_bei_interval);
4050 
4051 	return true;
4052 }
4053 
4054 /* This is for isoc transfer */
xhci_queue_isoc_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)4055 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
4056 		struct urb *urb, int slot_id, unsigned int ep_index)
4057 {
4058 	struct xhci_interrupter *ir;
4059 	struct xhci_ring *ep_ring;
4060 	struct urb_priv *urb_priv;
4061 	struct xhci_td *td;
4062 	int num_tds, trbs_per_td;
4063 	struct xhci_generic_trb *start_trb;
4064 	bool first_trb;
4065 	int start_cycle;
4066 	u32 field, length_field;
4067 	int running_total, trb_buff_len, td_len, td_remain_len, ret;
4068 	u64 start_addr, addr;
4069 	int i, j;
4070 	bool more_trbs_coming;
4071 	struct xhci_virt_ep *xep;
4072 	int frame_id;
4073 
4074 	xep = &xhci->devs[slot_id]->eps[ep_index];
4075 	ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
4076 	ir = xhci->interrupters[0];
4077 
4078 	num_tds = urb->number_of_packets;
4079 	if (num_tds < 1) {
4080 		xhci_dbg(xhci, "Isoc URB with zero packets?\n");
4081 		return -EINVAL;
4082 	}
4083 	start_addr = (u64) urb->transfer_dma;
4084 	start_trb = &ep_ring->enqueue->generic;
4085 	start_cycle = ep_ring->cycle_state;
4086 
4087 	urb_priv = urb->hcpriv;
4088 	/* Queue the TRBs for each TD, even if they are zero-length */
4089 	for (i = 0; i < num_tds; i++) {
4090 		unsigned int total_pkt_count, max_pkt;
4091 		unsigned int burst_count, last_burst_pkt_count;
4092 		u32 sia_frame_id;
4093 
4094 		first_trb = true;
4095 		running_total = 0;
4096 		addr = start_addr + urb->iso_frame_desc[i].offset;
4097 		td_len = urb->iso_frame_desc[i].length;
4098 		td_remain_len = td_len;
4099 		max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4100 		total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4101 
4102 		/* A zero-length transfer still involves at least one packet. */
4103 		if (total_pkt_count == 0)
4104 			total_pkt_count++;
4105 		burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4106 		last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4107 							urb, total_pkt_count);
4108 
4109 		trbs_per_td = count_isoc_trbs_needed(urb, i);
4110 
4111 		ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4112 				urb->stream_id, trbs_per_td, urb, i, mem_flags);
4113 		if (ret < 0) {
4114 			if (i == 0)
4115 				return ret;
4116 			goto cleanup;
4117 		}
4118 		td = &urb_priv->td[i];
4119 		/* use SIA as default, if frame id is used overwrite it */
4120 		sia_frame_id = TRB_SIA;
4121 		if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4122 		    HCC_CFC(xhci->hcc_params)) {
4123 			frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4124 			if (frame_id >= 0)
4125 				sia_frame_id = TRB_FRAME_ID(frame_id);
4126 		}
4127 		/*
4128 		 * Set isoc specific data for the first TRB in a TD.
4129 		 * Prevent HW from getting the TRBs by keeping the cycle state
4130 		 * inverted in the first TDs isoc TRB.
4131 		 */
4132 		field = TRB_TYPE(TRB_ISOC) |
4133 			TRB_TLBPC(last_burst_pkt_count) |
4134 			sia_frame_id |
4135 			(i ? ep_ring->cycle_state : !start_cycle);
4136 
4137 		/* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4138 		if (!xep->use_extended_tbc)
4139 			field |= TRB_TBC(burst_count);
4140 
4141 		/* fill the rest of the TRB fields, and remaining normal TRBs */
4142 		for (j = 0; j < trbs_per_td; j++) {
4143 			u32 remainder = 0;
4144 
4145 			/* only first TRB is isoc, overwrite otherwise */
4146 			if (!first_trb)
4147 				field = TRB_TYPE(TRB_NORMAL) |
4148 					ep_ring->cycle_state;
4149 
4150 			/* Only set interrupt on short packet for IN EPs */
4151 			if (usb_urb_dir_in(urb))
4152 				field |= TRB_ISP;
4153 
4154 			/* Set the chain bit for all except the last TRB  */
4155 			if (j < trbs_per_td - 1) {
4156 				more_trbs_coming = true;
4157 				field |= TRB_CHAIN;
4158 			} else {
4159 				more_trbs_coming = false;
4160 				td->end_trb = ep_ring->enqueue;
4161 				td->end_seg = ep_ring->enq_seg;
4162 				field |= TRB_IOC;
4163 				if (trb_block_event_intr(xhci, num_tds, i, ir))
4164 					field |= TRB_BEI;
4165 			}
4166 			/* Calculate TRB length */
4167 			trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4168 			if (trb_buff_len > td_remain_len)
4169 				trb_buff_len = td_remain_len;
4170 
4171 			/* Set the TRB length, TD size, & interrupter fields. */
4172 			remainder = xhci_td_remainder(xhci, running_total,
4173 						   trb_buff_len, td_len,
4174 						   urb, more_trbs_coming);
4175 
4176 			length_field = TRB_LEN(trb_buff_len) |
4177 				TRB_INTR_TARGET(0);
4178 
4179 			/* xhci 1.1 with ETE uses TD Size field for TBC */
4180 			if (first_trb && xep->use_extended_tbc)
4181 				length_field |= TRB_TD_SIZE_TBC(burst_count);
4182 			else
4183 				length_field |= TRB_TD_SIZE(remainder);
4184 			first_trb = false;
4185 
4186 			queue_trb(xhci, ep_ring, more_trbs_coming,
4187 				lower_32_bits(addr),
4188 				upper_32_bits(addr),
4189 				length_field,
4190 				field);
4191 			running_total += trb_buff_len;
4192 
4193 			addr += trb_buff_len;
4194 			td_remain_len -= trb_buff_len;
4195 		}
4196 
4197 		/* Check TD length */
4198 		if (running_total != td_len) {
4199 			xhci_err(xhci, "ISOC TD length unmatch\n");
4200 			ret = -EINVAL;
4201 			goto cleanup;
4202 		}
4203 	}
4204 
4205 	/* store the next frame id */
4206 	if (HCC_CFC(xhci->hcc_params))
4207 		xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4208 
4209 	if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4210 		if (xhci->quirks & XHCI_AMD_PLL_FIX)
4211 			usb_amd_quirk_pll_disable();
4212 	}
4213 	xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4214 
4215 	giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4216 			start_cycle, start_trb);
4217 	return 0;
4218 cleanup:
4219 	/* Clean up a partially enqueued isoc transfer. */
4220 
4221 	for (i--; i >= 0; i--)
4222 		list_del_init(&urb_priv->td[i].td_list);
4223 
4224 	/* Use the first TD as a temporary variable to turn the TDs we've queued
4225 	 * into No-ops with a software-owned cycle bit. That way the hardware
4226 	 * won't accidentally start executing bogus TDs when we partially
4227 	 * overwrite them.  td->start_trb and td->start_seg are already set.
4228 	 */
4229 	urb_priv->td[0].end_trb = ep_ring->enqueue;
4230 	/* Every TRB except the first & last will have its cycle bit flipped. */
4231 	td_to_noop(&urb_priv->td[0], true);
4232 
4233 	/* Reset the ring enqueue back to the first TRB and its cycle bit. */
4234 	ep_ring->enqueue = urb_priv->td[0].start_trb;
4235 	ep_ring->enq_seg = urb_priv->td[0].start_seg;
4236 	ep_ring->cycle_state = start_cycle;
4237 	usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4238 	return ret;
4239 }
4240 
4241 /*
4242  * Check transfer ring to guarantee there is enough room for the urb.
4243  * Update ISO URB start_frame and interval.
4244  * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4245  * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4246  * Contiguous Frame ID is not supported by HC.
4247  */
xhci_queue_isoc_tx_prepare(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)4248 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4249 		struct urb *urb, int slot_id, unsigned int ep_index)
4250 {
4251 	struct xhci_virt_device *xdev;
4252 	struct xhci_ring *ep_ring;
4253 	struct xhci_ep_ctx *ep_ctx;
4254 	int start_frame;
4255 	int num_tds, num_trbs, i;
4256 	int ret;
4257 	struct xhci_virt_ep *xep;
4258 	int ist;
4259 
4260 	xdev = xhci->devs[slot_id];
4261 	xep = &xhci->devs[slot_id]->eps[ep_index];
4262 	ep_ring = xdev->eps[ep_index].ring;
4263 	ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4264 
4265 	num_trbs = 0;
4266 	num_tds = urb->number_of_packets;
4267 	for (i = 0; i < num_tds; i++)
4268 		num_trbs += count_isoc_trbs_needed(urb, i);
4269 
4270 	/* Check the ring to guarantee there is enough room for the whole urb.
4271 	 * Do not insert any td of the urb to the ring if the check failed.
4272 	 */
4273 	ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4274 			   num_trbs, mem_flags);
4275 	if (ret)
4276 		return ret;
4277 
4278 	/*
4279 	 * Check interval value. This should be done before we start to
4280 	 * calculate the start frame value.
4281 	 */
4282 	check_interval(urb, ep_ctx);
4283 
4284 	/* Calculate the start frame and put it in urb->start_frame. */
4285 	if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4286 		if (GET_EP_CTX_STATE(ep_ctx) ==	EP_STATE_RUNNING) {
4287 			urb->start_frame = xep->next_frame_id;
4288 			goto skip_start_over;
4289 		}
4290 	}
4291 
4292 	start_frame = readl(&xhci->run_regs->microframe_index);
4293 	start_frame &= 0x3fff;
4294 	/*
4295 	 * Round up to the next frame and consider the time before trb really
4296 	 * gets scheduled by hardare.
4297 	 */
4298 	ist = HCS_IST(xhci->hcs_params2) & 0x7;
4299 	if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4300 		ist <<= 3;
4301 	start_frame += ist + XHCI_CFC_DELAY;
4302 	start_frame = roundup(start_frame, 8);
4303 
4304 	/*
4305 	 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4306 	 * is greate than 8 microframes.
4307 	 */
4308 	if (urb->dev->speed == USB_SPEED_LOW ||
4309 			urb->dev->speed == USB_SPEED_FULL) {
4310 		start_frame = roundup(start_frame, urb->interval << 3);
4311 		urb->start_frame = start_frame >> 3;
4312 	} else {
4313 		start_frame = roundup(start_frame, urb->interval);
4314 		urb->start_frame = start_frame;
4315 	}
4316 
4317 skip_start_over:
4318 
4319 	return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4320 }
4321 
4322 /****		Command Ring Operations		****/
4323 
4324 /* Generic function for queueing a command TRB on the command ring.
4325  * Check to make sure there's room on the command ring for one command TRB.
4326  * Also check that there's room reserved for commands that must not fail.
4327  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4328  * then only check for the number of reserved spots.
4329  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4330  * because the command event handler may want to resubmit a failed command.
4331  */
queue_command(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 field1,u32 field2,u32 field3,u32 field4,bool command_must_succeed)4332 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4333 			 u32 field1, u32 field2,
4334 			 u32 field3, u32 field4, bool command_must_succeed)
4335 {
4336 	int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4337 	int ret;
4338 
4339 	if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4340 		(xhci->xhc_state & XHCI_STATE_HALTED)) {
4341 		xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4342 		return -ESHUTDOWN;
4343 	}
4344 
4345 	if (!command_must_succeed)
4346 		reserved_trbs++;
4347 
4348 	ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4349 			reserved_trbs, GFP_ATOMIC);
4350 	if (ret < 0) {
4351 		xhci_err(xhci, "ERR: No room for command on command ring\n");
4352 		if (command_must_succeed)
4353 			xhci_err(xhci, "ERR: Reserved TRB counting for "
4354 					"unfailable commands failed.\n");
4355 		return ret;
4356 	}
4357 
4358 	cmd->command_trb = xhci->cmd_ring->enqueue;
4359 
4360 	/* if there are no other commands queued we start the timeout timer */
4361 	if (list_empty(&xhci->cmd_list)) {
4362 		xhci->current_cmd = cmd;
4363 		xhci_mod_cmd_timer(xhci);
4364 	}
4365 
4366 	list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4367 
4368 	queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4369 			field4 | xhci->cmd_ring->cycle_state);
4370 	return 0;
4371 }
4372 
4373 /* Queue a slot enable or disable request on the command ring */
xhci_queue_slot_control(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 trb_type,u32 slot_id)4374 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4375 		u32 trb_type, u32 slot_id)
4376 {
4377 	return queue_command(xhci, cmd, 0, 0, 0,
4378 			TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4379 }
4380 
4381 /* Queue an address device command TRB */
xhci_queue_address_device(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,enum xhci_setup_dev setup)4382 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4383 		dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4384 {
4385 	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4386 			upper_32_bits(in_ctx_ptr), 0,
4387 			TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4388 			| (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4389 }
4390 
xhci_queue_vendor_command(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 field1,u32 field2,u32 field3,u32 field4)4391 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4392 		u32 field1, u32 field2, u32 field3, u32 field4)
4393 {
4394 	return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4395 }
4396 
4397 /* Queue a reset device command TRB */
xhci_queue_reset_device(struct xhci_hcd * xhci,struct xhci_command * cmd,u32 slot_id)4398 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4399 		u32 slot_id)
4400 {
4401 	return queue_command(xhci, cmd, 0, 0, 0,
4402 			TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4403 			false);
4404 }
4405 
4406 /* Queue a configure endpoint command TRB */
xhci_queue_configure_endpoint(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,bool command_must_succeed)4407 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4408 		struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4409 		u32 slot_id, bool command_must_succeed)
4410 {
4411 	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4412 			upper_32_bits(in_ctx_ptr), 0,
4413 			TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4414 			command_must_succeed);
4415 }
4416 
4417 /* Queue an evaluate context command TRB */
xhci_queue_evaluate_context(struct xhci_hcd * xhci,struct xhci_command * cmd,dma_addr_t in_ctx_ptr,u32 slot_id,bool command_must_succeed)4418 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4419 		dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4420 {
4421 	return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4422 			upper_32_bits(in_ctx_ptr), 0,
4423 			TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4424 			command_must_succeed);
4425 }
4426 
4427 /*
4428  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4429  * activity on an endpoint that is about to be suspended.
4430  */
xhci_queue_stop_endpoint(struct xhci_hcd * xhci,struct xhci_command * cmd,int slot_id,unsigned int ep_index,int suspend)4431 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4432 			     int slot_id, unsigned int ep_index, int suspend)
4433 {
4434 	u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4435 	u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index);
4436 	u32 type = TRB_TYPE(TRB_STOP_RING);
4437 	u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4438 
4439 	return queue_command(xhci, cmd, 0, 0, 0,
4440 			trb_slot_id | trb_ep_index | type | trb_suspend, false);
4441 }
4442 
xhci_queue_reset_ep(struct xhci_hcd * xhci,struct xhci_command * cmd,int slot_id,unsigned int ep_index,enum xhci_ep_reset_type reset_type)4443 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4444 			int slot_id, unsigned int ep_index,
4445 			enum xhci_ep_reset_type reset_type)
4446 {
4447 	u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4448 	u32 trb_ep_index = EP_INDEX_FOR_TRB(ep_index);
4449 	u32 type = TRB_TYPE(TRB_RESET_EP);
4450 
4451 	if (reset_type == EP_SOFT_RESET)
4452 		type |= TRB_TSP;
4453 
4454 	return queue_command(xhci, cmd, 0, 0, 0,
4455 			trb_slot_id | trb_ep_index | type, false);
4456 }
4457