1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip UFS Host Controller driver
4 *
5 * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/gpio.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_wakeup.h>
15 #include <linux/regmap.h>
16 #include <linux/reset.h>
17
18 #include <ufs/ufshcd.h>
19 #include <ufs/unipro.h>
20 #include "ufshcd-pltfrm.h"
21 #include "ufs-rockchip.h"
22
ufs_rockchip_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)23 static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
24 enum ufs_notify_change_status status)
25 {
26 int err = 0;
27
28 if (status == POST_CHANGE) {
29 err = ufshcd_dme_reset(hba);
30 if (err)
31 return err;
32
33 err = ufshcd_dme_enable(hba);
34 if (err)
35 return err;
36
37 return ufshcd_vops_phy_initialization(hba);
38 }
39
40 return 0;
41 }
42
ufs_rockchip_set_pm_lvl(struct ufs_hba * hba)43 static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
44 {
45 hba->rpm_lvl = UFS_PM_LVL_5;
46 hba->spm_lvl = UFS_PM_LVL_5;
47 }
48
ufs_rockchip_rk3576_phy_init(struct ufs_hba * hba)49 static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
50 {
51 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
52
53 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
54 /* enable the mphy DME_SET cfg */
55 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE);
56 for (int i = 0; i < 2; i++) {
57 /* Configuration M - TX */
58 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06);
59 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02);
60 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44);
61 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6);
62 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07);
63 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93);
64 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9);
65 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00);
66 /* Configuration M - RX */
67 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06);
68 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, SEL_RX_LANE0 + i), 0x00);
69 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE, SEL_RX_LANE0 + i), 0x58);
70 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE1, SEL_RX_LANE0 + i), 0x8c);
71 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE2, SEL_RX_LANE0 + i), 0x02);
72 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_OPTION, SEL_RX_LANE0 + i), 0xf6);
73 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_POWER_SAVING_CTRL, SEL_RX_LANE0 + i), 0x69);
74 }
75
76 /* disable the mphy DME_SET cfg */
77 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE);
78
79 ufs_sys_writel(host->mphy_base, 0x80, CMN_REG23);
80 ufs_sys_writel(host->mphy_base, 0xB5, TRSV0_REG14);
81 ufs_sys_writel(host->mphy_base, 0xB5, TRSV1_REG14);
82
83 ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG15);
84 ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG15);
85
86 ufs_sys_writel(host->mphy_base, 0x38, TRSV0_REG08);
87 ufs_sys_writel(host->mphy_base, 0x38, TRSV1_REG08);
88
89 ufs_sys_writel(host->mphy_base, 0x50, TRSV0_REG29);
90 ufs_sys_writel(host->mphy_base, 0x50, TRSV1_REG29);
91
92 ufs_sys_writel(host->mphy_base, 0x80, TRSV0_REG2E);
93 ufs_sys_writel(host->mphy_base, 0x80, TRSV1_REG2E);
94
95 ufs_sys_writel(host->mphy_base, 0x18, TRSV0_REG3C);
96 ufs_sys_writel(host->mphy_base, 0x18, TRSV1_REG3C);
97
98 ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG16);
99 ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG16);
100
101 ufs_sys_writel(host->mphy_base, 0x20, TRSV0_REG17);
102 ufs_sys_writel(host->mphy_base, 0x20, TRSV1_REG17);
103
104 ufs_sys_writel(host->mphy_base, 0xC0, TRSV0_REG18);
105 ufs_sys_writel(host->mphy_base, 0xC0, TRSV1_REG18);
106
107 ufs_sys_writel(host->mphy_base, 0x03, CMN_REG25);
108
109 ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG3D);
110 ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG3D);
111
112 ufs_sys_writel(host->mphy_base, 0xC0, CMN_REG23);
113 udelay(1);
114 ufs_sys_writel(host->mphy_base, 0x00, CMN_REG23);
115
116 usleep_range(200, 250);
117 /* start link up */
118 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
119 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
120 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
121 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
122 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
123 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
124
125 return 0;
126 }
127
ufs_rockchip_common_init(struct ufs_hba * hba)128 static int ufs_rockchip_common_init(struct ufs_hba *hba)
129 {
130 struct device *dev = hba->dev;
131 struct platform_device *pdev = to_platform_device(dev);
132 struct ufs_rockchip_host *host;
133 int err;
134
135 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
136 if (!host)
137 return -ENOMEM;
138
139 host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
140 if (IS_ERR(host->ufs_sys_ctrl))
141 return dev_err_probe(dev, PTR_ERR(host->ufs_sys_ctrl),
142 "Failed to map HCI system control registers\n");
143
144 host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
145 if (IS_ERR(host->ufs_phy_ctrl))
146 return dev_err_probe(dev, PTR_ERR(host->ufs_phy_ctrl),
147 "Failed to map mphy system control registers\n");
148
149 host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
150 if (IS_ERR(host->mphy_base))
151 return dev_err_probe(dev, PTR_ERR(host->mphy_base),
152 "Failed to map mphy base registers\n");
153
154 host->rst = devm_reset_control_array_get_exclusive(dev);
155 if (IS_ERR(host->rst))
156 return dev_err_probe(dev, PTR_ERR(host->rst),
157 "failed to get reset control\n");
158
159 reset_control_assert(host->rst);
160 udelay(1);
161 reset_control_deassert(host->rst);
162
163 host->ref_out_clk = devm_clk_get_enabled(dev, "ref_out");
164 if (IS_ERR(host->ref_out_clk))
165 return dev_err_probe(dev, PTR_ERR(host->ref_out_clk),
166 "ref_out clock unavailable\n");
167
168 host->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
169 if (IS_ERR(host->rst_gpio))
170 return dev_err_probe(dev, PTR_ERR(host->rst_gpio),
171 "failed to get reset gpio\n");
172
173 err = devm_clk_bulk_get_all_enabled(dev, &host->clks);
174 if (err < 0)
175 return dev_err_probe(dev, err, "failed to enable clocks\n");
176
177 host->hba = hba;
178
179 ufshcd_set_variant(hba, host);
180
181 return 0;
182 }
183
ufs_rockchip_rk3576_init(struct ufs_hba * hba)184 static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
185 {
186 struct device *dev = hba->dev;
187 int ret;
188
189 hba->quirks = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
190
191 /* Enable BKOPS when suspend */
192 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
193 /* Enable putting device into deep sleep */
194 hba->caps |= UFSHCD_CAP_DEEPSLEEP;
195 /* Enable devfreq of UFS */
196 hba->caps |= UFSHCD_CAP_CLK_SCALING;
197 /* Enable WriteBooster */
198 hba->caps |= UFSHCD_CAP_WB_EN;
199
200 /* Set the default desired pm level in case no users set via sysfs */
201 ufs_rockchip_set_pm_lvl(hba);
202
203 ret = ufs_rockchip_common_init(hba);
204 if (ret)
205 return dev_err_probe(dev, ret, "ufs common init fail\n");
206
207 return 0;
208 }
209
ufs_rockchip_device_reset(struct ufs_hba * hba)210 static int ufs_rockchip_device_reset(struct ufs_hba *hba)
211 {
212 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
213
214 gpiod_set_value_cansleep(host->rst_gpio, 1);
215 usleep_range(20, 25);
216
217 gpiod_set_value_cansleep(host->rst_gpio, 0);
218 usleep_range(20, 25);
219
220 return 0;
221 }
222
223 static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
224 .name = "rk3576",
225 .init = ufs_rockchip_rk3576_init,
226 .device_reset = ufs_rockchip_device_reset,
227 .hce_enable_notify = ufs_rockchip_hce_enable_notify,
228 .phy_initialization = ufs_rockchip_rk3576_phy_init,
229 };
230
231 static const struct of_device_id ufs_rockchip_of_match[] = {
232 { .compatible = "rockchip,rk3576-ufshc", .data = &ufs_hba_rk3576_vops },
233 { },
234 };
235 MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
236
ufs_rockchip_probe(struct platform_device * pdev)237 static int ufs_rockchip_probe(struct platform_device *pdev)
238 {
239 struct device *dev = &pdev->dev;
240 const struct ufs_hba_variant_ops *vops;
241 int err;
242
243 vops = device_get_match_data(dev);
244 if (!vops)
245 return dev_err_probe(dev, -ENODATA, "ufs_hba_variant_ops not defined.\n");
246
247 err = ufshcd_pltfrm_init(pdev, vops);
248 if (err)
249 return dev_err_probe(dev, err, "ufshcd_pltfrm_init failed\n");
250
251 return 0;
252 }
253
ufs_rockchip_remove(struct platform_device * pdev)254 static void ufs_rockchip_remove(struct platform_device *pdev)
255 {
256 ufshcd_pltfrm_remove(pdev);
257 }
258
259 #ifdef CONFIG_PM
ufs_rockchip_runtime_suspend(struct device * dev)260 static int ufs_rockchip_runtime_suspend(struct device *dev)
261 {
262 struct ufs_hba *hba = dev_get_drvdata(dev);
263 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
264
265 clk_disable_unprepare(host->ref_out_clk);
266
267 /* Do not power down the genpd if rpm_lvl is less than level 5 */
268 dev_pm_genpd_rpm_always_on(dev, hba->rpm_lvl < UFS_PM_LVL_5);
269
270 return ufshcd_runtime_suspend(dev);
271 }
272
ufs_rockchip_runtime_resume(struct device * dev)273 static int ufs_rockchip_runtime_resume(struct device *dev)
274 {
275 struct ufs_hba *hba = dev_get_drvdata(dev);
276 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
277 int err;
278
279 err = clk_prepare_enable(host->ref_out_clk);
280 if (err) {
281 dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
282 return err;
283 }
284
285 reset_control_assert(host->rst);
286 udelay(1);
287 reset_control_deassert(host->rst);
288
289 return ufshcd_runtime_resume(dev);
290 }
291 #endif
292
293 #ifdef CONFIG_PM_SLEEP
ufs_rockchip_system_suspend(struct device * dev)294 static int ufs_rockchip_system_suspend(struct device *dev)
295 {
296 struct ufs_hba *hba = dev_get_drvdata(dev);
297 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
298 int err;
299
300 /*
301 * If spm_lvl is less than level 5, it means we need to keep the host
302 * controller in powered-on state. So device_set_awake_path() is
303 * calling pm core to notify the genpd provider to meet this requirement
304 */
305 if (hba->spm_lvl < UFS_PM_LVL_5)
306 device_set_awake_path(dev);
307
308 err = ufshcd_system_suspend(dev);
309 if (err) {
310 dev_err(hba->dev, "UFSHCD system suspend failed %d\n", err);
311 return err;
312 }
313
314 clk_disable_unprepare(host->ref_out_clk);
315
316 return 0;
317 }
318
ufs_rockchip_system_resume(struct device * dev)319 static int ufs_rockchip_system_resume(struct device *dev)
320 {
321 struct ufs_hba *hba = dev_get_drvdata(dev);
322 struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
323 int err;
324
325 err = clk_prepare_enable(host->ref_out_clk);
326 if (err) {
327 dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
328 return err;
329 }
330
331 return ufshcd_system_resume(dev);
332 }
333 #endif
334
335 static const struct dev_pm_ops ufs_rockchip_pm_ops = {
336 SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_system_suspend, ufs_rockchip_system_resume)
337 SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL)
338 .prepare = ufshcd_suspend_prepare,
339 .complete = ufshcd_resume_complete,
340 };
341
342 static struct platform_driver ufs_rockchip_pltform = {
343 .probe = ufs_rockchip_probe,
344 .remove = ufs_rockchip_remove,
345 .driver = {
346 .name = "ufshcd-rockchip",
347 .pm = &ufs_rockchip_pm_ops,
348 .of_match_table = ufs_rockchip_of_match,
349 },
350 };
351 module_platform_driver(ufs_rockchip_pltform);
352
353 MODULE_LICENSE("GPL");
354 MODULE_DESCRIPTION("Rockchip UFS Host Driver");
355