1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Balsam CHIHI <bchihi@baylibre.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/debugfs.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21
22 #include "../thermal_hwmon.h"
23
24 #define LVTS_MONCTL0(__base) (__base + 0x0000)
25 #define LVTS_MONCTL1(__base) (__base + 0x0004)
26 #define LVTS_MONCTL2(__base) (__base + 0x0008)
27 #define LVTS_MONINT(__base) (__base + 0x000C)
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010)
29 #define LVTS_MONIDET0(__base) (__base + 0x0014)
30 #define LVTS_MONIDET1(__base) (__base + 0x0018)
31 #define LVTS_MONIDET2(__base) (__base + 0x001C)
32 #define LVTS_MONIDET3(__base) (__base + 0x0020)
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024)
34 #define LVTS_HTHRE(__base) (__base + 0x0028)
35 #define LVTS_OFFSETH(__base) (__base + 0x0030)
36 #define LVTS_OFFSETL(__base) (__base + 0x0034)
37 #define LVTS_MSRCTL0(__base) (__base + 0x0038)
38 #define LVTS_MSRCTL1(__base) (__base + 0x003C)
39 #define LVTS_TSSEL(__base) (__base + 0x0040)
40 #define LVTS_CALSCALE(__base) (__base + 0x0048)
41 #define LVTS_ID(__base) (__base + 0x004C)
42 #define LVTS_CONFIG(__base) (__base + 0x0050)
43 #define LVTS_EDATA00(__base) (__base + 0x0054)
44 #define LVTS_EDATA01(__base) (__base + 0x0058)
45 #define LVTS_EDATA02(__base) (__base + 0x005C)
46 #define LVTS_EDATA03(__base) (__base + 0x0060)
47 #define LVTS_MSR0(__base) (__base + 0x0090)
48 #define LVTS_MSR1(__base) (__base + 0x0094)
49 #define LVTS_MSR2(__base) (__base + 0x0098)
50 #define LVTS_MSR3(__base) (__base + 0x009C)
51 #define LVTS_IMMD0(__base) (__base + 0x00A0)
52 #define LVTS_IMMD1(__base) (__base + 0x00A4)
53 #define LVTS_IMMD2(__base) (__base + 0x00A8)
54 #define LVTS_IMMD3(__base) (__base + 0x00AC)
55 #define LVTS_PROTCTL(__base) (__base + 0x00C0)
56 #define LVTS_PROTTA(__base) (__base + 0x00C4)
57 #define LVTS_PROTTB(__base) (__base + 0x00C8)
58 #define LVTS_PROTTC(__base) (__base + 0x00CC)
59 #define LVTS_CLKEN(__base) (__base + 0x00E4)
60
61 #define LVTS_PERIOD_UNIT 0
62 #define LVTS_GROUP_INTERVAL 0
63 #define LVTS_FILTER_INTERVAL 0
64 #define LVTS_SENSOR_INTERVAL 0
65 #define LVTS_HW_FILTER 0x0
66 #define LVTS_TSSEL_CONF 0x13121110
67 #define LVTS_CALSCALE_CONF 0x300
68
69 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3)
70 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8)
71 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2 BIT(13)
72 #define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3 BIT(25)
73 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0 BIT(2)
74 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1 BIT(7)
75 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2 BIT(12)
76 #define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3 BIT(24)
77
78 #define LVTS_INT_SENSOR0 0x0009001F
79 #define LVTS_INT_SENSOR1 0x001203E0
80 #define LVTS_INT_SENSOR2 0x00247C00
81 #define LVTS_INT_SENSOR3 0x1FC00000
82
83 #define LVTS_SENSOR_MAX 4
84 #define LVTS_GOLDEN_TEMP_MAX 62
85 #define LVTS_GOLDEN_TEMP_DEFAULT 50
86 #define LVTS_COEFF_A_MT8195 -250460
87 #define LVTS_COEFF_B_MT8195 250460
88 #define LVTS_COEFF_A_MT7988 -204650
89 #define LVTS_COEFF_B_MT7988 204650
90
91 #define LVTS_MSR_IMMEDIATE_MODE 0
92 #define LVTS_MSR_FILTERED_MODE 1
93
94 #define LVTS_MSR_READ_TIMEOUT_US 400
95 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
96
97 #define LVTS_MINIMUM_THRESHOLD 20000
98
99 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
100 static int golden_temp_offset;
101
102 struct lvts_sensor_data {
103 int dt_id;
104 u8 cal_offsets[3];
105 };
106
107 struct lvts_ctrl_data {
108 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
109 u8 valid_sensor_mask;
110 int offset;
111 int mode;
112 };
113
114 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \
115 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \
116 ((s1) ? BIT(1) : 0) | \
117 ((s2) ? BIT(2) : 0) | \
118 ((s3) ? BIT(3) : 0))
119
120 #define lvts_for_each_valid_sensor(i, lvts_ctrl) \
121 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \
122 if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \
123 continue; \
124 else
125
126 struct lvts_data {
127 const struct lvts_ctrl_data *lvts_ctrl;
128 int num_lvts_ctrl;
129 int temp_factor;
130 int temp_offset;
131 int gt_calib_bit_offset;
132 unsigned int def_calibration;
133 };
134
135 struct lvts_sensor {
136 struct thermal_zone_device *tz;
137 void __iomem *msr;
138 void __iomem *base;
139 int id;
140 int dt_id;
141 int low_thresh;
142 int high_thresh;
143 };
144
145 struct lvts_ctrl {
146 struct lvts_sensor sensors[LVTS_SENSOR_MAX];
147 const struct lvts_data *lvts_data;
148 u32 calibration[LVTS_SENSOR_MAX];
149 u8 valid_sensor_mask;
150 int mode;
151 void __iomem *base;
152 int low_thresh;
153 int high_thresh;
154 };
155
156 struct lvts_domain {
157 struct lvts_ctrl *lvts_ctrl;
158 struct reset_control *reset;
159 struct clk *clk;
160 int num_lvts_ctrl;
161 void __iomem *base;
162 size_t calib_len;
163 u8 *calib;
164 #ifdef CONFIG_DEBUG_FS
165 struct dentry *dom_dentry;
166 #endif
167 };
168
169 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
170
171 #define LVTS_DEBUG_FS_REGS(__reg) \
172 { \
173 .name = __stringify(__reg), \
174 .offset = __reg(0), \
175 }
176
177 static const struct debugfs_reg32 lvts_regs[] = {
178 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
179 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
180 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
181 LVTS_DEBUG_FS_REGS(LVTS_MONINT),
182 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
183 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
184 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
185 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
186 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
187 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
188 LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
189 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
190 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
191 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
192 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
193 LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
194 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
195 LVTS_DEBUG_FS_REGS(LVTS_ID),
196 LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
197 LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
198 LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
199 LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
200 LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
201 LVTS_DEBUG_FS_REGS(LVTS_MSR0),
202 LVTS_DEBUG_FS_REGS(LVTS_MSR1),
203 LVTS_DEBUG_FS_REGS(LVTS_MSR2),
204 LVTS_DEBUG_FS_REGS(LVTS_MSR3),
205 LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
206 LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
207 LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
208 LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
209 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
210 LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
211 LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
212 LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
213 LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
214 };
215
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)216 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
217 {
218 struct debugfs_regset32 *regset;
219 struct lvts_ctrl *lvts_ctrl;
220 struct dentry *dentry;
221 char name[64];
222 int i;
223
224 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
225 if (IS_ERR(lvts_td->dom_dentry))
226 return 0;
227
228 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
229
230 lvts_ctrl = &lvts_td->lvts_ctrl[i];
231
232 sprintf(name, "controller%d", i);
233 dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
234 if (IS_ERR(dentry))
235 continue;
236
237 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
238 if (!regset)
239 continue;
240
241 regset->base = lvts_ctrl->base;
242 regset->regs = lvts_regs;
243 regset->nregs = ARRAY_SIZE(lvts_regs);
244
245 debugfs_create_regset32("registers", 0400, dentry, regset);
246 }
247
248 return 0;
249 }
250
lvts_debugfs_exit(struct lvts_domain * lvts_td)251 static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
252 {
253 debugfs_remove_recursive(lvts_td->dom_dentry);
254 }
255
256 #else
257
lvts_debugfs_init(struct device * dev,struct lvts_domain * lvts_td)258 static inline int lvts_debugfs_init(struct device *dev,
259 struct lvts_domain *lvts_td)
260 {
261 return 0;
262 }
263
lvts_debugfs_exit(struct lvts_domain * lvts_td)264 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
265
266 #endif
267
lvts_raw_to_temp(u32 raw_temp,int temp_factor)268 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
269 {
270 int temperature;
271
272 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
273 temperature += golden_temp_offset;
274
275 return temperature;
276 }
277
lvts_temp_to_raw(int temperature,int temp_factor)278 static u32 lvts_temp_to_raw(int temperature, int temp_factor)
279 {
280 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
281
282 raw_temp = div_s64(raw_temp, -temp_factor);
283
284 return raw_temp;
285 }
286
lvts_get_temp(struct thermal_zone_device * tz,int * temp)287 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
288 {
289 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
290 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
291 sensors[lvts_sensor->id]);
292 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
293 void __iomem *msr = lvts_sensor->msr;
294 u32 value;
295 int rc;
296
297 /*
298 * Measurement registers:
299 *
300 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
301 *
302 * Bits:
303 *
304 * 32-17: Unused
305 * 16 : Valid temperature
306 * 15-0 : Raw temperature
307 */
308 rc = readl_poll_timeout(msr, value, value & BIT(16),
309 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US);
310
311 /*
312 * As the thermal zone temperature will read before the
313 * hardware sensor is fully initialized, we have to check the
314 * validity of the temperature returned when reading the
315 * measurement register. The thermal controller will set the
316 * valid bit temperature only when it is totally initialized.
317 *
318 * Otherwise, we may end up with garbage values out of the
319 * functionning temperature and directly jump to a system
320 * shutdown.
321 */
322 if (rc)
323 return -EAGAIN;
324
325 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
326
327 return 0;
328 }
329
lvts_update_irq_mask(struct lvts_ctrl * lvts_ctrl)330 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
331 {
332 static const u32 high_offset_inten_masks[] = {
333 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0,
334 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1,
335 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2,
336 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3,
337 };
338 static const u32 low_offset_inten_masks[] = {
339 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0,
340 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1,
341 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2,
342 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3,
343 };
344 u32 value = 0;
345 int i;
346
347 value = readl(LVTS_MONINT(lvts_ctrl->base));
348
349 lvts_for_each_valid_sensor(i, lvts_ctrl) {
350 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
351 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) {
352 /*
353 * The minimum threshold needs to be configured in the
354 * OFFSETL register to get working interrupts, but we
355 * don't actually want to generate interrupts when
356 * crossing it.
357 */
358 if (lvts_ctrl->low_thresh == -INT_MAX) {
359 value &= ~low_offset_inten_masks[i];
360 value |= high_offset_inten_masks[i];
361 } else {
362 value |= low_offset_inten_masks[i] | high_offset_inten_masks[i];
363 }
364 } else {
365 value &= ~(low_offset_inten_masks[i] | high_offset_inten_masks[i]);
366 }
367 }
368
369 writel(value, LVTS_MONINT(lvts_ctrl->base));
370 }
371
lvts_should_update_thresh(struct lvts_ctrl * lvts_ctrl,int high)372 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
373 {
374 int i;
375
376 if (high > lvts_ctrl->high_thresh)
377 return true;
378
379 lvts_for_each_valid_sensor(i, lvts_ctrl)
380 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
381 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
382 return false;
383
384 return true;
385 }
386
lvts_set_trips(struct thermal_zone_device * tz,int low,int high)387 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
388 {
389 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
390 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
391 sensors[lvts_sensor->id]);
392 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
393 void __iomem *base = lvts_sensor->base;
394 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
395 lvts_data->temp_factor);
396 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
397 bool should_update_thresh;
398
399 lvts_sensor->low_thresh = low;
400 lvts_sensor->high_thresh = high;
401
402 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
403 if (should_update_thresh) {
404 lvts_ctrl->high_thresh = high;
405 lvts_ctrl->low_thresh = low;
406 }
407 lvts_update_irq_mask(lvts_ctrl);
408
409 if (!should_update_thresh)
410 return 0;
411
412 /*
413 * Low offset temperature threshold
414 *
415 * LVTS_OFFSETL
416 *
417 * Bits:
418 *
419 * 14-0 : Raw temperature for threshold
420 */
421 pr_debug("%s: Setting low limit temperature interrupt: %d\n",
422 thermal_zone_device_type(tz), low);
423 writel(raw_low, LVTS_OFFSETL(base));
424
425 /*
426 * High offset temperature threshold
427 *
428 * LVTS_OFFSETH
429 *
430 * Bits:
431 *
432 * 14-0 : Raw temperature for threshold
433 */
434 pr_debug("%s: Setting high limit temperature interrupt: %d\n",
435 thermal_zone_device_type(tz), high);
436 writel(raw_high, LVTS_OFFSETH(base));
437
438 return 0;
439 }
440
lvts_ctrl_irq_handler(struct lvts_ctrl * lvts_ctrl)441 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
442 {
443 irqreturn_t iret = IRQ_NONE;
444 u32 value;
445 static const u32 masks[] = {
446 LVTS_INT_SENSOR0,
447 LVTS_INT_SENSOR1,
448 LVTS_INT_SENSOR2,
449 LVTS_INT_SENSOR3
450 };
451 int i;
452
453 /*
454 * Interrupt monitoring status
455 *
456 * LVTS_MONINTST
457 *
458 * Bits:
459 *
460 * 31 : Interrupt for stage 3
461 * 30 : Interrupt for stage 2
462 * 29 : Interrupt for state 1
463 * 28 : Interrupt using filter on sensor 3
464 *
465 * 27 : Interrupt using immediate on sensor 3
466 * 26 : Interrupt normal to hot on sensor 3
467 * 25 : Interrupt high offset on sensor 3
468 * 24 : Interrupt low offset on sensor 3
469 *
470 * 23 : Interrupt hot threshold on sensor 3
471 * 22 : Interrupt cold threshold on sensor 3
472 * 21 : Interrupt using filter on sensor 2
473 * 20 : Interrupt using filter on sensor 1
474 *
475 * 19 : Interrupt using filter on sensor 0
476 * 18 : Interrupt using immediate on sensor 2
477 * 17 : Interrupt using immediate on sensor 1
478 * 16 : Interrupt using immediate on sensor 0
479 *
480 * 15 : Interrupt device access timeout interrupt
481 * 14 : Interrupt normal to hot on sensor 2
482 * 13 : Interrupt high offset interrupt on sensor 2
483 * 12 : Interrupt low offset interrupt on sensor 2
484 *
485 * 11 : Interrupt hot threshold on sensor 2
486 * 10 : Interrupt cold threshold on sensor 2
487 * 9 : Interrupt normal to hot on sensor 1
488 * 8 : Interrupt high offset interrupt on sensor 1
489 *
490 * 7 : Interrupt low offset interrupt on sensor 1
491 * 6 : Interrupt hot threshold on sensor 1
492 * 5 : Interrupt cold threshold on sensor 1
493 * 4 : Interrupt normal to hot on sensor 0
494 *
495 * 3 : Interrupt high offset interrupt on sensor 0
496 * 2 : Interrupt low offset interrupt on sensor 0
497 * 1 : Interrupt hot threshold on sensor 0
498 * 0 : Interrupt cold threshold on sensor 0
499 *
500 * We are interested in the sensor(s) responsible of the
501 * interrupt event. We update the thermal framework with the
502 * thermal zone associated with the sensor. The framework will
503 * take care of the rest whatever the kind of interrupt, we
504 * are only interested in which sensor raised the interrupt.
505 *
506 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
507 * => 0x1FC00000
508 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
509 * => 0x00247C00
510 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
511 * => 0X001203E0
512 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
513 * => 0x0009001F
514 */
515 value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
516
517 /*
518 * Let's figure out which sensors raised the interrupt
519 *
520 * NOTE: the masks array must be ordered with the index
521 * corresponding to the sensor id eg. index=0, mask for
522 * sensor0.
523 */
524 for (i = 0; i < ARRAY_SIZE(masks); i++) {
525
526 if (!(value & masks[i]))
527 continue;
528
529 thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
530 THERMAL_TRIP_VIOLATED);
531 iret = IRQ_HANDLED;
532 }
533
534 /*
535 * Write back to clear the interrupt status (W1C)
536 */
537 writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
538
539 return iret;
540 }
541
542 /*
543 * Temperature interrupt handler. Even if the driver supports more
544 * interrupt modes, we use the interrupt when the temperature crosses
545 * the hot threshold the way up and the way down (modulo the
546 * hysteresis).
547 *
548 * Each thermal domain has a couple of interrupts, one for hardware
549 * reset and another one for all the thermal events happening on the
550 * different sensors.
551 *
552 * The interrupt is configured for thermal events when crossing the
553 * hot temperature limit. At each interrupt, we check in every
554 * controller if there is an interrupt pending.
555 */
lvts_irq_handler(int irq,void * data)556 static irqreturn_t lvts_irq_handler(int irq, void *data)
557 {
558 struct lvts_domain *lvts_td = data;
559 irqreturn_t aux, iret = IRQ_NONE;
560 int i;
561
562 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
563
564 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
565 if (aux != IRQ_HANDLED)
566 continue;
567
568 iret = IRQ_HANDLED;
569 }
570
571 return iret;
572 }
573
574 static struct thermal_zone_device_ops lvts_ops = {
575 .get_temp = lvts_get_temp,
576 .set_trips = lvts_set_trips,
577 };
578
lvts_sensor_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data)579 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
580 const struct lvts_ctrl_data *lvts_ctrl_data)
581 {
582 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
583
584 void __iomem *msr_regs[] = {
585 LVTS_MSR0(lvts_ctrl->base),
586 LVTS_MSR1(lvts_ctrl->base),
587 LVTS_MSR2(lvts_ctrl->base),
588 LVTS_MSR3(lvts_ctrl->base)
589 };
590
591 void __iomem *imm_regs[] = {
592 LVTS_IMMD0(lvts_ctrl->base),
593 LVTS_IMMD1(lvts_ctrl->base),
594 LVTS_IMMD2(lvts_ctrl->base),
595 LVTS_IMMD3(lvts_ctrl->base)
596 };
597
598 int i;
599
600 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
601
602 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
603
604 /*
605 * At this point, we don't know which id matches which
606 * sensor. Let's set arbitrally the id from the index.
607 */
608 lvts_sensor[i].id = i;
609
610 /*
611 * The thermal zone registration will set the trip
612 * point interrupt in the thermal controller
613 * register. But this one will be reset in the
614 * initialization after. So we need to post pone the
615 * thermal zone creation after the controller is
616 * setup. For this reason, we store the device tree
617 * node id from the data in the sensor structure
618 */
619 lvts_sensor[i].dt_id = dt_id;
620
621 /*
622 * We assign the base address of the thermal
623 * controller as a back pointer. So it will be
624 * accessible from the different thermal framework ops
625 * as we pass the lvts_sensor pointer as thermal zone
626 * private data.
627 */
628 lvts_sensor[i].base = lvts_ctrl->base;
629
630 /*
631 * Each sensor has its own register address to read from.
632 */
633 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
634 imm_regs[i] : msr_regs[i];
635
636 lvts_sensor[i].low_thresh = INT_MIN;
637 lvts_sensor[i].high_thresh = INT_MIN;
638 };
639
640 lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask;
641
642 return 0;
643 }
644
645 /*
646 * The efuse blob values follows the sensor enumeration per thermal
647 * controller. The decoding of the stream is as follow:
648 *
649 * MT8192 :
650 * Stream index map for MCU Domain mt8192 :
651 *
652 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
653 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
654 *
655 * <-----sensor#2-----> <-----sensor#3----->
656 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
657 *
658 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
659 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
660 *
661 * Stream index map for AP Domain mt8192 :
662 *
663 * <-----sensor#0-----> <-----sensor#1----->
664 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
665 *
666 * <-----sensor#2-----> <-----sensor#3----->
667 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
668 *
669 * <-----sensor#4-----> <-----sensor#5----->
670 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
671 *
672 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
673 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
674 *
675 * MT8195 :
676 * Stream index map for MCU Domain mt8195 :
677 *
678 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
679 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
680 *
681 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
682 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
683 *
684 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
685 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
686 *
687 * Stream index map for AP Domain mt8195 :
688 *
689 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
690 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
691 *
692 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
693 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
694 *
695 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
696 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
697 *
698 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
699 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
700 *
701 * Note: In some cases, values don't strictly follow a little endian ordering.
702 * The data description gives byte offsets constituting each calibration value
703 * for each sensor.
704 */
lvts_calibration_init(struct device * dev,struct lvts_ctrl * lvts_ctrl,const struct lvts_ctrl_data * lvts_ctrl_data,u8 * efuse_calibration,size_t calib_len)705 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
706 const struct lvts_ctrl_data *lvts_ctrl_data,
707 u8 *efuse_calibration,
708 size_t calib_len)
709 {
710 int i;
711 u32 gt;
712
713 /* A zero value for gt means that device has invalid efuse data */
714 gt = (((u32 *)efuse_calibration)[0] >> lvts_ctrl->lvts_data->gt_calib_bit_offset) & 0xff;
715
716 lvts_for_each_valid_sensor(i, lvts_ctrl_data) {
717 const struct lvts_sensor_data *sensor =
718 &lvts_ctrl_data->lvts_sensor[i];
719
720 if (sensor->cal_offsets[0] >= calib_len ||
721 sensor->cal_offsets[1] >= calib_len ||
722 sensor->cal_offsets[2] >= calib_len)
723 return -EINVAL;
724
725 if (gt) {
726 lvts_ctrl->calibration[i] =
727 (efuse_calibration[sensor->cal_offsets[0]] << 0) +
728 (efuse_calibration[sensor->cal_offsets[1]] << 8) +
729 (efuse_calibration[sensor->cal_offsets[2]] << 16);
730 } else if (lvts_ctrl->lvts_data->def_calibration) {
731 lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration;
732 } else {
733 dev_err(dev, "efuse contains invalid calibration data and no default given.\n");
734 return -ENODATA;
735 }
736 }
737
738 return 0;
739 }
740
741 /*
742 * The efuse bytes stream can be split into different chunk of
743 * nvmems. This function reads and concatenate those into a single
744 * buffer so it can be read sequentially when initializing the
745 * calibration data.
746 */
lvts_calibration_read(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)747 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
748 const struct lvts_data *lvts_data)
749 {
750 struct device_node *np = dev_of_node(dev);
751 struct nvmem_cell *cell;
752 struct property *prop;
753 const char *cell_name;
754
755 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
756 size_t len;
757 u8 *efuse;
758
759 cell = of_nvmem_cell_get(np, cell_name);
760 if (IS_ERR(cell)) {
761 dev_err(dev, "Failed to get cell '%s'\n", cell_name);
762 return PTR_ERR(cell);
763 }
764
765 efuse = nvmem_cell_read(cell, &len);
766
767 nvmem_cell_put(cell);
768
769 if (IS_ERR(efuse)) {
770 dev_err(dev, "Failed to read cell '%s'\n", cell_name);
771 return PTR_ERR(efuse);
772 }
773
774 lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
775 lvts_td->calib_len + len, GFP_KERNEL);
776 if (!lvts_td->calib) {
777 kfree(efuse);
778 return -ENOMEM;
779 }
780
781 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
782
783 lvts_td->calib_len += len;
784
785 kfree(efuse);
786 }
787
788 return 0;
789 }
790
lvts_golden_temp_init(struct device * dev,u8 * calib,const struct lvts_data * lvts_data)791 static int lvts_golden_temp_init(struct device *dev, u8 *calib,
792 const struct lvts_data *lvts_data)
793 {
794 u32 gt;
795
796 /*
797 * The golden temp information is contained in the first 32-bit
798 * word of efuse data at a specific bit offset.
799 */
800 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff;
801
802 /* A zero value for gt means that device has invalid efuse data */
803 if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
804 golden_temp = gt;
805
806 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset;
807
808 dev_info(dev, "%sgolden temp=%d\n", gt ? "" : "fake ", golden_temp);
809
810 return 0;
811 }
812
lvts_ctrl_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)813 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
814 const struct lvts_data *lvts_data)
815 {
816 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
817 struct lvts_ctrl *lvts_ctrl;
818 int i, ret;
819
820 /*
821 * Create the calibration bytes stream from efuse data
822 */
823 ret = lvts_calibration_read(dev, lvts_td, lvts_data);
824 if (ret)
825 return ret;
826
827 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data);
828 if (ret)
829 return ret;
830
831 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
832 if (!lvts_ctrl)
833 return -ENOMEM;
834
835 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
836
837 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
838 lvts_ctrl[i].lvts_data = lvts_data;
839
840 ret = lvts_sensor_init(dev, &lvts_ctrl[i],
841 &lvts_data->lvts_ctrl[i]);
842 if (ret)
843 return ret;
844
845 ret = lvts_calibration_init(dev, &lvts_ctrl[i],
846 &lvts_data->lvts_ctrl[i],
847 lvts_td->calib,
848 lvts_td->calib_len);
849 if (ret)
850 return ret;
851
852 /*
853 * The mode the ctrl will use to read the temperature
854 * (filtered or immediate)
855 */
856 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
857
858 lvts_ctrl[i].low_thresh = INT_MIN;
859 lvts_ctrl[i].high_thresh = INT_MIN;
860 }
861
862 /*
863 * We no longer need the efuse bytes stream, let's free it
864 */
865 devm_kfree(dev, lvts_td->calib);
866
867 lvts_td->lvts_ctrl = lvts_ctrl;
868 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
869
870 return 0;
871 }
872
lvts_ctrl_monitor_enable(struct device * dev,struct lvts_ctrl * lvts_ctrl,bool enable)873 static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_ctrl, bool enable)
874 {
875 /*
876 * Bitmaps to enable each sensor on filtered mode in the MONCTL0
877 * register.
878 */
879 static const u8 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
880 u32 sensor_map = 0;
881 int i;
882
883 if (lvts_ctrl->mode != LVTS_MSR_FILTERED_MODE)
884 return;
885
886 if (enable) {
887 lvts_for_each_valid_sensor(i, lvts_ctrl)
888 sensor_map |= sensor_filt_bitmap[i];
889 }
890
891 /*
892 * Bits:
893 * 9: Single point access flow
894 * 0-3: Enable sensing point 0-3
895 */
896 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
897 }
898
899 /*
900 * At this point the configuration register is the only place in the
901 * driver where we write multiple values. Per hardware constraint,
902 * each write in the configuration register must be separated by a
903 * delay of 2 us.
904 */
lvts_write_config(struct lvts_ctrl * lvts_ctrl,u32 * cmds,int nr_cmds)905 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
906 {
907 int i;
908
909 /*
910 * Configuration register
911 */
912 for (i = 0; i < nr_cmds; i++) {
913 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
914 usleep_range(2, 4);
915 }
916 }
917
lvts_irq_init(struct lvts_ctrl * lvts_ctrl)918 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
919 {
920 /*
921 * LVTS_PROTCTL : Thermal Protection Sensor Selection
922 *
923 * Bits:
924 *
925 * 19-18 : Sensor to base the protection on
926 * 17-16 : Strategy:
927 * 00 : Average of 4 sensors
928 * 01 : Max of 4 sensors
929 * 10 : Selected sensor with bits 19-18
930 * 11 : Reserved
931 */
932
933 /*
934 * LVTS_PROTTA : Stage 1 temperature threshold
935 * LVTS_PROTTB : Stage 2 temperature threshold
936 * LVTS_PROTTC : Stage 3 temperature threshold
937 *
938 * Bits:
939 *
940 * 14-0: Raw temperature threshold
941 *
942 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
943 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
944 * writel(0x0, LVTS_PROTTC(lvts_ctrl->base));
945 */
946
947 /*
948 * LVTS_MONINT : Interrupt configuration register
949 *
950 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
951 * register, except we set the bits to enable the interrupt.
952 */
953 writel(0, LVTS_MONINT(lvts_ctrl->base));
954
955 return 0;
956 }
957
lvts_domain_reset(struct device * dev,struct reset_control * reset)958 static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
959 {
960 int ret;
961
962 ret = reset_control_assert(reset);
963 if (ret)
964 return ret;
965
966 return reset_control_deassert(reset);
967 }
968
969 /*
970 * Enable or disable the clocks of a specified thermal controller
971 */
lvts_ctrl_set_enable(struct lvts_ctrl * lvts_ctrl,int enable)972 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
973 {
974 /*
975 * LVTS_CLKEN : Internal LVTS clock
976 *
977 * Bits:
978 *
979 * 0 : enable / disable clock
980 */
981 writel(enable, LVTS_CLKEN(lvts_ctrl->base));
982
983 return 0;
984 }
985
lvts_ctrl_connect(struct device * dev,struct lvts_ctrl * lvts_ctrl)986 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
987 {
988 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
989
990 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
991
992 /*
993 * LVTS_ID : Get ID and status of the thermal controller
994 *
995 * Bits:
996 *
997 * 0-5 : thermal controller id
998 * 7 : thermal controller connection is valid
999 */
1000 id = readl(LVTS_ID(lvts_ctrl->base));
1001 if (!(id & BIT(7)))
1002 return -EIO;
1003
1004 return 0;
1005 }
1006
lvts_ctrl_initialize(struct device * dev,struct lvts_ctrl * lvts_ctrl)1007 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1008 {
1009 /*
1010 * Write device mask: 0xC1030000
1011 */
1012 u32 cmds[] = {
1013 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
1014 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
1015 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
1016 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
1017 };
1018
1019 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
1020
1021 return 0;
1022 }
1023
lvts_ctrl_calibrate(struct device * dev,struct lvts_ctrl * lvts_ctrl)1024 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1025 {
1026 int i;
1027 void __iomem *lvts_edata[] = {
1028 LVTS_EDATA00(lvts_ctrl->base),
1029 LVTS_EDATA01(lvts_ctrl->base),
1030 LVTS_EDATA02(lvts_ctrl->base),
1031 LVTS_EDATA03(lvts_ctrl->base)
1032 };
1033
1034 /*
1035 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
1036 *
1037 * Bits:
1038 *
1039 * 20-0 : Efuse value for normalization data
1040 */
1041 for (i = 0; i < LVTS_SENSOR_MAX; i++)
1042 writel(lvts_ctrl->calibration[i], lvts_edata[i]);
1043
1044 return 0;
1045 }
1046
lvts_ctrl_configure(struct device * dev,struct lvts_ctrl * lvts_ctrl)1047 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1048 {
1049 u32 value;
1050
1051 /*
1052 * LVTS_TSSEL : Sensing point index numbering
1053 *
1054 * Bits:
1055 *
1056 * 31-24: ADC Sense 3
1057 * 23-16: ADC Sense 2
1058 * 15-8 : ADC Sense 1
1059 * 7-0 : ADC Sense 0
1060 */
1061 value = LVTS_TSSEL_CONF;
1062 writel(value, LVTS_TSSEL(lvts_ctrl->base));
1063
1064 /*
1065 * LVTS_CALSCALE : ADC voltage round
1066 */
1067 value = 0x300;
1068 value = LVTS_CALSCALE_CONF;
1069
1070 /*
1071 * LVTS_MSRCTL0 : Sensor filtering strategy
1072 *
1073 * Filters:
1074 *
1075 * 000 : One sample
1076 * 001 : Avg 2 samples
1077 * 010 : 4 samples, drop min and max, avg 2 samples
1078 * 011 : 6 samples, drop min and max, avg 4 samples
1079 * 100 : 10 samples, drop min and max, avg 8 samples
1080 * 101 : 18 samples, drop min and max, avg 16 samples
1081 *
1082 * Bits:
1083 *
1084 * 0-2 : Sensor0 filter
1085 * 3-5 : Sensor1 filter
1086 * 6-8 : Sensor2 filter
1087 * 9-11 : Sensor3 filter
1088 */
1089 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
1090 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
1091 writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
1092
1093 /*
1094 * LVTS_MONCTL1 : Period unit and group interval configuration
1095 *
1096 * The clock source of LVTS thermal controller is 26MHz.
1097 *
1098 * The period unit is a time base for all the interval delays
1099 * specified in the registers. By default we use 12. The time
1100 * conversion is done by multiplying by 256 and 1/26.10^6
1101 *
1102 * An interval delay multiplied by the period unit gives the
1103 * duration in seconds.
1104 *
1105 * - Filter interval delay is a delay between two samples of
1106 * the same sensor.
1107 *
1108 * - Sensor interval delay is a delay between two samples of
1109 * different sensors.
1110 *
1111 * - Group interval delay is a delay between different rounds.
1112 *
1113 * For example:
1114 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
1115 * and two sensors, TS1 and TS2, are in a LVTS thermal controller
1116 * and then
1117 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
1118 * Filter interval delay = 1 * Period unit = 118.149us
1119 * Sensor interval delay = 2 * Period unit = 236.298us
1120 * Group interval delay = 1 * Period unit = 118.149us
1121 *
1122 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
1123 * <--> Filter interval delay
1124 * <--> Sensor interval delay
1125 * <--> Group interval delay
1126 * Bits:
1127 * 29 - 20 : Group interval
1128 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1129 * or an interrupt everytime the hot threshold is crossed (0)
1130 * 9 - 0 : Period unit
1131 *
1132 */
1133 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1134 writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1135
1136 /*
1137 * LVTS_MONCTL2 : Filtering and sensor interval
1138 *
1139 * Bits:
1140 *
1141 * 25-16 : Interval unit in PERIOD_UNIT between sample on
1142 * the same sensor, filter interval
1143 * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1144 *
1145 */
1146 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1147 writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1148
1149 return lvts_irq_init(lvts_ctrl);
1150 }
1151
lvts_ctrl_start(struct device * dev,struct lvts_ctrl * lvts_ctrl)1152 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1153 {
1154 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1155 struct thermal_zone_device *tz;
1156 u32 sensor_map = 0;
1157 int i;
1158 /*
1159 * Bitmaps to enable each sensor on immediate and filtered modes, as
1160 * described in MSRCTL1 and MONCTL0 registers below, respectively.
1161 */
1162 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
1163 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1164
1165 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
1166 sensor_imm_bitmap : sensor_filt_bitmap;
1167
1168 lvts_for_each_valid_sensor(i, lvts_ctrl) {
1169
1170 int dt_id = lvts_sensors[i].dt_id;
1171
1172 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1173 &lvts_ops);
1174 if (IS_ERR(tz)) {
1175 /*
1176 * This thermal zone is not described in the
1177 * device tree. It is not an error from the
1178 * thermal OF code POV, we just continue.
1179 */
1180 if (PTR_ERR(tz) == -ENODEV)
1181 continue;
1182
1183 return PTR_ERR(tz);
1184 }
1185
1186 devm_thermal_add_hwmon_sysfs(dev, tz);
1187
1188 /*
1189 * The thermal zone pointer will be needed in the
1190 * interrupt handler, we store it in the sensor
1191 * structure. The thermal domain structure will be
1192 * passed to the interrupt handler private data as the
1193 * interrupt is shared for all the controller
1194 * belonging to the thermal domain.
1195 */
1196 lvts_sensors[i].tz = tz;
1197
1198 /*
1199 * This sensor was correctly associated with a thermal
1200 * zone, let's set the corresponding bit in the sensor
1201 * map, so we can enable the temperature monitoring in
1202 * the hardware thermal controller.
1203 */
1204 sensor_map |= sensor_bitmap[i];
1205 }
1206
1207 /*
1208 * The initialization of the thermal zones give us
1209 * which sensor point to enable. If any thermal zone
1210 * was not described in the device tree, it won't be
1211 * enabled here in the sensor map.
1212 */
1213 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
1214 /*
1215 * LVTS_MSRCTL1 : Measurement control
1216 *
1217 * Bits:
1218 *
1219 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
1220 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
1221 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
1222 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
1223 *
1224 * That configuration will ignore the filtering and the delays
1225 * introduced in MONCTL1 and MONCTL2
1226 */
1227 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
1228 } else {
1229 /*
1230 * Bits:
1231 * 9: Single point access flow
1232 * 0-3: Enable sensing point 0-3
1233 */
1234 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1235 }
1236
1237 return 0;
1238 }
1239
lvts_domain_init(struct device * dev,struct lvts_domain * lvts_td,const struct lvts_data * lvts_data)1240 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1241 const struct lvts_data *lvts_data)
1242 {
1243 struct lvts_ctrl *lvts_ctrl;
1244 int i, ret;
1245
1246 ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1247 if (ret)
1248 return ret;
1249
1250 ret = lvts_domain_reset(dev, lvts_td->reset);
1251 if (ret) {
1252 dev_dbg(dev, "Failed to reset domain");
1253 return ret;
1254 }
1255
1256 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1257
1258 lvts_ctrl = &lvts_td->lvts_ctrl[i];
1259
1260 /*
1261 * Initialization steps:
1262 *
1263 * - Enable the clock
1264 * - Connect to the LVTS
1265 * - Initialize the LVTS
1266 * - Prepare the calibration data
1267 * - Select monitored sensors
1268 * [ Configure sampling ]
1269 * [ Configure the interrupt ]
1270 * - Start measurement
1271 */
1272 ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1273 if (ret) {
1274 dev_dbg(dev, "Failed to enable LVTS clock");
1275 return ret;
1276 }
1277
1278 ret = lvts_ctrl_connect(dev, lvts_ctrl);
1279 if (ret) {
1280 dev_dbg(dev, "Failed to connect to LVTS controller");
1281 return ret;
1282 }
1283
1284 ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1285 if (ret) {
1286 dev_dbg(dev, "Failed to initialize controller");
1287 return ret;
1288 }
1289
1290 ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1291 if (ret) {
1292 dev_dbg(dev, "Failed to calibrate controller");
1293 return ret;
1294 }
1295
1296 ret = lvts_ctrl_configure(dev, lvts_ctrl);
1297 if (ret) {
1298 dev_dbg(dev, "Failed to configure controller");
1299 return ret;
1300 }
1301
1302 ret = lvts_ctrl_start(dev, lvts_ctrl);
1303 if (ret) {
1304 dev_dbg(dev, "Failed to start controller");
1305 return ret;
1306 }
1307 }
1308
1309 return lvts_debugfs_init(dev, lvts_td);
1310 }
1311
lvts_probe(struct platform_device * pdev)1312 static int lvts_probe(struct platform_device *pdev)
1313 {
1314 const struct lvts_data *lvts_data;
1315 struct lvts_domain *lvts_td;
1316 struct device *dev = &pdev->dev;
1317 struct resource *res;
1318 int irq, ret;
1319
1320 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1321 if (!lvts_td)
1322 return -ENOMEM;
1323
1324 lvts_data = of_device_get_match_data(dev);
1325 if (!lvts_data)
1326 return -ENODEV;
1327
1328 lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1329 if (IS_ERR(lvts_td->clk))
1330 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1331
1332 res = platform_get_mem_or_io(pdev, 0);
1333 if (!res)
1334 return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1335
1336 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1337 if (IS_ERR(lvts_td->base))
1338 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1339
1340 lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
1341 if (IS_ERR(lvts_td->reset))
1342 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1343
1344 irq = platform_get_irq(pdev, 0);
1345 if (irq < 0)
1346 return irq;
1347
1348 golden_temp_offset = lvts_data->temp_offset;
1349
1350 ret = lvts_domain_init(dev, lvts_td, lvts_data);
1351 if (ret)
1352 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1353
1354 /*
1355 * At this point the LVTS is initialized and enabled. We can
1356 * safely enable the interrupt.
1357 */
1358 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1359 IRQF_ONESHOT, dev_name(dev), lvts_td);
1360 if (ret)
1361 return dev_err_probe(dev, ret, "Failed to request interrupt\n");
1362
1363 platform_set_drvdata(pdev, lvts_td);
1364
1365 return 0;
1366 }
1367
lvts_remove(struct platform_device * pdev)1368 static void lvts_remove(struct platform_device *pdev)
1369 {
1370 struct lvts_domain *lvts_td;
1371 int i;
1372
1373 lvts_td = platform_get_drvdata(pdev);
1374
1375 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1376 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1377
1378 lvts_debugfs_exit(lvts_td);
1379 }
1380
1381 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
1382 {
1383 .lvts_sensor = {
1384 { .dt_id = MT7988_CPU_0,
1385 .cal_offsets = { 0x00, 0x01, 0x02 } },
1386 { .dt_id = MT7988_CPU_1,
1387 .cal_offsets = { 0x04, 0x05, 0x06 } },
1388 { .dt_id = MT7988_ETH2P5G_0,
1389 .cal_offsets = { 0x08, 0x09, 0x0a } },
1390 { .dt_id = MT7988_ETH2P5G_1,
1391 .cal_offsets = { 0x0c, 0x0d, 0x0e } }
1392 },
1393 VALID_SENSOR_MAP(1, 1, 1, 1),
1394 .offset = 0x0,
1395 },
1396 {
1397 .lvts_sensor = {
1398 { .dt_id = MT7988_TOPS_0,
1399 .cal_offsets = { 0x14, 0x15, 0x16 } },
1400 { .dt_id = MT7988_TOPS_1,
1401 .cal_offsets = { 0x18, 0x19, 0x1a } },
1402 { .dt_id = MT7988_ETHWARP_0,
1403 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1404 { .dt_id = MT7988_ETHWARP_1,
1405 .cal_offsets = { 0x20, 0x21, 0x22 } }
1406 },
1407 VALID_SENSOR_MAP(1, 1, 1, 1),
1408 .offset = 0x100,
1409 }
1410 };
1411
lvts_suspend(struct device * dev)1412 static int lvts_suspend(struct device *dev)
1413 {
1414 struct lvts_domain *lvts_td;
1415 int i;
1416
1417 lvts_td = dev_get_drvdata(dev);
1418
1419 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1420 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], false);
1421 usleep_range(100, 200);
1422 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1423 }
1424
1425 clk_disable_unprepare(lvts_td->clk);
1426
1427 return 0;
1428 }
1429
lvts_resume(struct device * dev)1430 static int lvts_resume(struct device *dev)
1431 {
1432 struct lvts_domain *lvts_td;
1433 int i, ret;
1434
1435 lvts_td = dev_get_drvdata(dev);
1436
1437 ret = clk_prepare_enable(lvts_td->clk);
1438 if (ret)
1439 return ret;
1440
1441 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1442 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
1443 usleep_range(100, 200);
1444 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], true);
1445 }
1446
1447 return 0;
1448 }
1449
1450 /*
1451 * The MT8186 calibration data is stored as packed 3-byte little-endian
1452 * values using a weird layout that makes sense only when viewed as a 32-bit
1453 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and
1454 * y = byte number where the LSB is y=0. We then have:
1455 *
1456 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0]
1457 *
1458 * However, when considering a byte stream, those appear as follows:
1459 *
1460 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0]
1461 *
1462 * Hence the rather confusing offsets provided below.
1463 */
1464 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = {
1465 {
1466 .lvts_sensor = {
1467 { .dt_id = MT8186_LITTLE_CPU0,
1468 .cal_offsets = { 5, 6, 7 } },
1469 { .dt_id = MT8186_LITTLE_CPU1,
1470 .cal_offsets = { 10, 11, 4 } },
1471 { .dt_id = MT8186_LITTLE_CPU2,
1472 .cal_offsets = { 15, 8, 9 } },
1473 { .dt_id = MT8186_CAM,
1474 .cal_offsets = { 12, 13, 14 } }
1475 },
1476 VALID_SENSOR_MAP(1, 1, 1, 1),
1477 .offset = 0x0,
1478 },
1479 {
1480 .lvts_sensor = {
1481 { .dt_id = MT8186_BIG_CPU0,
1482 .cal_offsets = { 22, 23, 16 } },
1483 { .dt_id = MT8186_BIG_CPU1,
1484 .cal_offsets = { 27, 20, 21 } }
1485 },
1486 VALID_SENSOR_MAP(1, 1, 0, 0),
1487 .offset = 0x100,
1488 },
1489 {
1490 .lvts_sensor = {
1491 { .dt_id = MT8186_NNA,
1492 .cal_offsets = { 29, 30, 31 } },
1493 { .dt_id = MT8186_ADSP,
1494 .cal_offsets = { 34, 35, 28 } },
1495 { .dt_id = MT8186_GPU,
1496 .cal_offsets = { 39, 32, 33 } }
1497 },
1498 VALID_SENSOR_MAP(1, 1, 1, 0),
1499 .offset = 0x200,
1500 }
1501 };
1502
1503 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = {
1504 {
1505 .lvts_sensor = {
1506 { .dt_id = MT8188_MCU_LITTLE_CPU0,
1507 .cal_offsets = { 22, 23, 24 } },
1508 { .dt_id = MT8188_MCU_LITTLE_CPU1,
1509 .cal_offsets = { 25, 26, 27 } },
1510 { .dt_id = MT8188_MCU_LITTLE_CPU2,
1511 .cal_offsets = { 28, 29, 30 } },
1512 { .dt_id = MT8188_MCU_LITTLE_CPU3,
1513 .cal_offsets = { 31, 32, 33 } },
1514 },
1515 VALID_SENSOR_MAP(1, 1, 1, 1),
1516 .offset = 0x0,
1517 },
1518 {
1519 .lvts_sensor = {
1520 { .dt_id = MT8188_MCU_BIG_CPU0,
1521 .cal_offsets = { 34, 35, 36 } },
1522 { .dt_id = MT8188_MCU_BIG_CPU1,
1523 .cal_offsets = { 37, 38, 39 } },
1524 },
1525 VALID_SENSOR_MAP(1, 1, 0, 0),
1526 .offset = 0x100,
1527 }
1528 };
1529
1530 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = {
1531 {
1532 .lvts_sensor = {
1533
1534 { /* unused */ },
1535 { .dt_id = MT8188_AP_APU,
1536 .cal_offsets = { 40, 41, 42 } },
1537 },
1538 VALID_SENSOR_MAP(0, 1, 0, 0),
1539 .offset = 0x0,
1540 },
1541 {
1542 .lvts_sensor = {
1543 { .dt_id = MT8188_AP_GPU0,
1544 .cal_offsets = { 43, 44, 45 } },
1545 { .dt_id = MT8188_AP_GPU1,
1546 .cal_offsets = { 46, 47, 48 } },
1547 { .dt_id = MT8188_AP_ADSP,
1548 .cal_offsets = { 49, 50, 51 } },
1549 },
1550 VALID_SENSOR_MAP(1, 1, 1, 0),
1551 .offset = 0x100,
1552 },
1553 {
1554 .lvts_sensor = {
1555 { .dt_id = MT8188_AP_VDO,
1556 .cal_offsets = { 52, 53, 54 } },
1557 { .dt_id = MT8188_AP_INFRA,
1558 .cal_offsets = { 55, 56, 57 } },
1559 },
1560 VALID_SENSOR_MAP(1, 1, 0, 0),
1561 .offset = 0x200,
1562 },
1563 {
1564 .lvts_sensor = {
1565 { .dt_id = MT8188_AP_CAM1,
1566 .cal_offsets = { 58, 59, 60 } },
1567 { .dt_id = MT8188_AP_CAM2,
1568 .cal_offsets = { 61, 62, 63 } },
1569 },
1570 VALID_SENSOR_MAP(1, 1, 0, 0),
1571 .offset = 0x300,
1572 }
1573 };
1574
1575 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
1576 {
1577 .lvts_sensor = {
1578 { .dt_id = MT8192_MCU_BIG_CPU0,
1579 .cal_offsets = { 0x04, 0x05, 0x06 } },
1580 { .dt_id = MT8192_MCU_BIG_CPU1,
1581 .cal_offsets = { 0x08, 0x09, 0x0a } }
1582 },
1583 VALID_SENSOR_MAP(1, 1, 0, 0),
1584 .offset = 0x0,
1585 .mode = LVTS_MSR_FILTERED_MODE,
1586 },
1587 {
1588 .lvts_sensor = {
1589 { .dt_id = MT8192_MCU_BIG_CPU2,
1590 .cal_offsets = { 0x0c, 0x0d, 0x0e } },
1591 { .dt_id = MT8192_MCU_BIG_CPU3,
1592 .cal_offsets = { 0x10, 0x11, 0x12 } }
1593 },
1594 VALID_SENSOR_MAP(1, 1, 0, 0),
1595 .offset = 0x100,
1596 .mode = LVTS_MSR_FILTERED_MODE,
1597 },
1598 {
1599 .lvts_sensor = {
1600 { .dt_id = MT8192_MCU_LITTLE_CPU0,
1601 .cal_offsets = { 0x14, 0x15, 0x16 } },
1602 { .dt_id = MT8192_MCU_LITTLE_CPU1,
1603 .cal_offsets = { 0x18, 0x19, 0x1a } },
1604 { .dt_id = MT8192_MCU_LITTLE_CPU2,
1605 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1606 { .dt_id = MT8192_MCU_LITTLE_CPU3,
1607 .cal_offsets = { 0x20, 0x21, 0x22 } }
1608 },
1609 VALID_SENSOR_MAP(1, 1, 1, 1),
1610 .offset = 0x200,
1611 .mode = LVTS_MSR_FILTERED_MODE,
1612 }
1613 };
1614
1615 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
1616 {
1617 .lvts_sensor = {
1618 { .dt_id = MT8192_AP_VPU0,
1619 .cal_offsets = { 0x24, 0x25, 0x26 } },
1620 { .dt_id = MT8192_AP_VPU1,
1621 .cal_offsets = { 0x28, 0x29, 0x2a } }
1622 },
1623 VALID_SENSOR_MAP(1, 1, 0, 0),
1624 .offset = 0x0,
1625 },
1626 {
1627 .lvts_sensor = {
1628 { .dt_id = MT8192_AP_GPU0,
1629 .cal_offsets = { 0x2c, 0x2d, 0x2e } },
1630 { .dt_id = MT8192_AP_GPU1,
1631 .cal_offsets = { 0x30, 0x31, 0x32 } }
1632 },
1633 VALID_SENSOR_MAP(1, 1, 0, 0),
1634 .offset = 0x100,
1635 },
1636 {
1637 .lvts_sensor = {
1638 { .dt_id = MT8192_AP_INFRA,
1639 .cal_offsets = { 0x34, 0x35, 0x36 } },
1640 { .dt_id = MT8192_AP_CAM,
1641 .cal_offsets = { 0x38, 0x39, 0x3a } },
1642 },
1643 VALID_SENSOR_MAP(1, 1, 0, 0),
1644 .offset = 0x200,
1645 },
1646 {
1647 .lvts_sensor = {
1648 { .dt_id = MT8192_AP_MD0,
1649 .cal_offsets = { 0x3c, 0x3d, 0x3e } },
1650 { .dt_id = MT8192_AP_MD1,
1651 .cal_offsets = { 0x40, 0x41, 0x42 } },
1652 { .dt_id = MT8192_AP_MD2,
1653 .cal_offsets = { 0x44, 0x45, 0x46 } }
1654 },
1655 VALID_SENSOR_MAP(1, 1, 1, 0),
1656 .offset = 0x300,
1657 }
1658 };
1659
1660 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
1661 {
1662 .lvts_sensor = {
1663 { .dt_id = MT8195_MCU_BIG_CPU0,
1664 .cal_offsets = { 0x04, 0x05, 0x06 } },
1665 { .dt_id = MT8195_MCU_BIG_CPU1,
1666 .cal_offsets = { 0x07, 0x08, 0x09 } }
1667 },
1668 VALID_SENSOR_MAP(1, 1, 0, 0),
1669 .offset = 0x0,
1670 },
1671 {
1672 .lvts_sensor = {
1673 { .dt_id = MT8195_MCU_BIG_CPU2,
1674 .cal_offsets = { 0x0d, 0x0e, 0x0f } },
1675 { .dt_id = MT8195_MCU_BIG_CPU3,
1676 .cal_offsets = { 0x10, 0x11, 0x12 } }
1677 },
1678 VALID_SENSOR_MAP(1, 1, 0, 0),
1679 .offset = 0x100,
1680 },
1681 {
1682 .lvts_sensor = {
1683 { .dt_id = MT8195_MCU_LITTLE_CPU0,
1684 .cal_offsets = { 0x16, 0x17, 0x18 } },
1685 { .dt_id = MT8195_MCU_LITTLE_CPU1,
1686 .cal_offsets = { 0x19, 0x1a, 0x1b } },
1687 { .dt_id = MT8195_MCU_LITTLE_CPU2,
1688 .cal_offsets = { 0x1c, 0x1d, 0x1e } },
1689 { .dt_id = MT8195_MCU_LITTLE_CPU3,
1690 .cal_offsets = { 0x1f, 0x20, 0x21 } }
1691 },
1692 VALID_SENSOR_MAP(1, 1, 1, 1),
1693 .offset = 0x200,
1694 }
1695 };
1696
1697 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
1698 {
1699 .lvts_sensor = {
1700 { .dt_id = MT8195_AP_VPU0,
1701 .cal_offsets = { 0x25, 0x26, 0x27 } },
1702 { .dt_id = MT8195_AP_VPU1,
1703 .cal_offsets = { 0x28, 0x29, 0x2a } }
1704 },
1705 VALID_SENSOR_MAP(1, 1, 0, 0),
1706 .offset = 0x0,
1707 },
1708 {
1709 .lvts_sensor = {
1710 { .dt_id = MT8195_AP_GPU0,
1711 .cal_offsets = { 0x2e, 0x2f, 0x30 } },
1712 { .dt_id = MT8195_AP_GPU1,
1713 .cal_offsets = { 0x31, 0x32, 0x33 } }
1714 },
1715 VALID_SENSOR_MAP(1, 1, 0, 0),
1716 .offset = 0x100,
1717 },
1718 {
1719 .lvts_sensor = {
1720 { .dt_id = MT8195_AP_VDEC,
1721 .cal_offsets = { 0x37, 0x38, 0x39 } },
1722 { .dt_id = MT8195_AP_IMG,
1723 .cal_offsets = { 0x3a, 0x3b, 0x3c } },
1724 { .dt_id = MT8195_AP_INFRA,
1725 .cal_offsets = { 0x3d, 0x3e, 0x3f } }
1726 },
1727 VALID_SENSOR_MAP(1, 1, 1, 0),
1728 .offset = 0x200,
1729 },
1730 {
1731 .lvts_sensor = {
1732 { .dt_id = MT8195_AP_CAM0,
1733 .cal_offsets = { 0x43, 0x44, 0x45 } },
1734 { .dt_id = MT8195_AP_CAM1,
1735 .cal_offsets = { 0x46, 0x47, 0x48 } }
1736 },
1737 VALID_SENSOR_MAP(1, 1, 0, 0),
1738 .offset = 0x300,
1739 }
1740 };
1741
1742 static const struct lvts_data mt7988_lvts_ap_data = {
1743 .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
1744 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
1745 .temp_factor = LVTS_COEFF_A_MT7988,
1746 .temp_offset = LVTS_COEFF_B_MT7988,
1747 .gt_calib_bit_offset = 24,
1748 };
1749
1750 static const struct lvts_data mt8186_lvts_data = {
1751 .lvts_ctrl = mt8186_lvts_data_ctrl,
1752 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
1753 .temp_factor = LVTS_COEFF_A_MT7988,
1754 .temp_offset = LVTS_COEFF_B_MT7988,
1755 .gt_calib_bit_offset = 24,
1756 .def_calibration = 19000,
1757 };
1758
1759 static const struct lvts_data mt8188_lvts_mcu_data = {
1760 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl,
1761 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
1762 .temp_factor = LVTS_COEFF_A_MT8195,
1763 .temp_offset = LVTS_COEFF_B_MT8195,
1764 .gt_calib_bit_offset = 20,
1765 .def_calibration = 35000,
1766 };
1767
1768 static const struct lvts_data mt8188_lvts_ap_data = {
1769 .lvts_ctrl = mt8188_lvts_ap_data_ctrl,
1770 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
1771 .temp_factor = LVTS_COEFF_A_MT8195,
1772 .temp_offset = LVTS_COEFF_B_MT8195,
1773 .gt_calib_bit_offset = 20,
1774 .def_calibration = 35000,
1775 };
1776
1777 static const struct lvts_data mt8192_lvts_mcu_data = {
1778 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
1779 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
1780 .temp_factor = LVTS_COEFF_A_MT8195,
1781 .temp_offset = LVTS_COEFF_B_MT8195,
1782 .gt_calib_bit_offset = 24,
1783 .def_calibration = 35000,
1784 };
1785
1786 static const struct lvts_data mt8192_lvts_ap_data = {
1787 .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
1788 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
1789 .temp_factor = LVTS_COEFF_A_MT8195,
1790 .temp_offset = LVTS_COEFF_B_MT8195,
1791 .gt_calib_bit_offset = 24,
1792 .def_calibration = 35000,
1793 };
1794
1795 static const struct lvts_data mt8195_lvts_mcu_data = {
1796 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1797 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1798 .temp_factor = LVTS_COEFF_A_MT8195,
1799 .temp_offset = LVTS_COEFF_B_MT8195,
1800 .gt_calib_bit_offset = 24,
1801 .def_calibration = 35000,
1802 };
1803
1804 static const struct lvts_data mt8195_lvts_ap_data = {
1805 .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1806 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1807 .temp_factor = LVTS_COEFF_A_MT8195,
1808 .temp_offset = LVTS_COEFF_B_MT8195,
1809 .gt_calib_bit_offset = 24,
1810 .def_calibration = 35000,
1811 };
1812
1813 static const struct of_device_id lvts_of_match[] = {
1814 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
1815 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data },
1816 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data },
1817 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data },
1818 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
1819 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
1820 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
1821 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
1822 {},
1823 };
1824 MODULE_DEVICE_TABLE(of, lvts_of_match);
1825
1826 static const struct dev_pm_ops lvts_pm_ops = {
1827 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
1828 };
1829
1830 static struct platform_driver lvts_driver = {
1831 .probe = lvts_probe,
1832 .remove = lvts_remove,
1833 .driver = {
1834 .name = "mtk-lvts-thermal",
1835 .of_match_table = lvts_of_match,
1836 .pm = &lvts_pm_ops,
1837 },
1838 };
1839 module_platform_driver(lvts_driver);
1840
1841 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
1842 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
1843 MODULE_LICENSE("GPL");
1844