1 // SPDX-License-Identifier: GPL-2.0
2 
3 /***************************************************************************
4  *   copyright            : (C) 2001, 2002 by Frank Mori Hess
5  ***************************************************************************/
6 
7 #define dev_fmt(fmt) KBUILD_MODNAME ": " fmt
8 
9 #include "board.h"
10 #include <linux/ioport.h>
11 #include <linux/sched.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <asm/dma.h>
15 #include <linux/bitops.h>
16 #include <linux/pci.h>
17 #include <linux/pci_ids.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/delay.h>
22 
23 MODULE_LICENSE("GPL");
24 MODULE_DESCRIPTION("GPIB library code for NEC uPD7210");
25 
nec7210_enable_eos(struct gpib_board * board,struct nec7210_priv * priv,uint8_t eos_byte,int compare_8_bits)26 int nec7210_enable_eos(struct gpib_board *board, struct nec7210_priv *priv, uint8_t eos_byte,
27 		       int compare_8_bits)
28 {
29 	write_byte(priv, eos_byte, EOSR);
30 	priv->auxa_bits |= HR_REOS;
31 	if (compare_8_bits)
32 		priv->auxa_bits |= HR_BIN;
33 	else
34 		priv->auxa_bits &= ~HR_BIN;
35 	write_byte(priv, priv->auxa_bits, AUXMR);
36 	return 0;
37 }
38 EXPORT_SYMBOL(nec7210_enable_eos);
39 
nec7210_disable_eos(struct gpib_board * board,struct nec7210_priv * priv)40 void nec7210_disable_eos(struct gpib_board *board, struct nec7210_priv *priv)
41 {
42 	priv->auxa_bits &= ~HR_REOS;
43 	write_byte(priv, priv->auxa_bits, AUXMR);
44 }
45 EXPORT_SYMBOL(nec7210_disable_eos);
46 
nec7210_parallel_poll(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * result)47 int nec7210_parallel_poll(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *result)
48 {
49 	int ret;
50 
51 	clear_bit(COMMAND_READY_BN, &priv->state);
52 
53 	// execute parallel poll
54 	write_byte(priv, AUX_EPP, AUXMR);
55 	// wait for result FIXME: support timeouts
56 	ret = wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state));
57 	if (ret) {
58 		dev_dbg(board->gpib_dev, "gpib: parallel poll interrupted\n");
59 		return -ERESTARTSYS;
60 	}
61 	*result = read_byte(priv, CPTR);
62 
63 	return 0;
64 }
65 EXPORT_SYMBOL(nec7210_parallel_poll);
66 
nec7210_parallel_poll_configure(struct gpib_board * board,struct nec7210_priv * priv,unsigned int configuration)67 void nec7210_parallel_poll_configure(struct gpib_board *board,
68 				     struct nec7210_priv *priv, unsigned int configuration)
69 {
70 	write_byte(priv, PPR | configuration, AUXMR);
71 }
72 EXPORT_SYMBOL(nec7210_parallel_poll_configure);
73 
nec7210_parallel_poll_response(struct gpib_board * board,struct nec7210_priv * priv,int ist)74 void nec7210_parallel_poll_response(struct gpib_board *board, struct nec7210_priv *priv, int ist)
75 {
76 	if (ist)
77 		write_byte(priv, AUX_SPPF, AUXMR);
78 	else
79 		write_byte(priv, AUX_CPPF, AUXMR);
80 }
81 EXPORT_SYMBOL(nec7210_parallel_poll_response);
82 /* This is really only adequate for chips that do a 488.2 style reqt/reqf
83  * based on bit 6 of the SPMR (see chapter 11.3.3 of 488.2). For simpler chips that simply
84  * set rsv directly based on bit 6, we either need to do more hardware setup to expose
85  * the 488.2 capability (for example with NI chips), or we need to implement the
86  * 488.2 set srv state machine in the driver (if that is even viable).
87  */
nec7210_serial_poll_response(struct gpib_board * board,struct nec7210_priv * priv,uint8_t status)88 void nec7210_serial_poll_response(struct gpib_board *board,
89 				  struct nec7210_priv *priv, uint8_t status)
90 {
91 	unsigned long flags;
92 
93 	spin_lock_irqsave(&board->spinlock, flags);
94 	if (status & request_service_bit) {
95 		priv->srq_pending = 1;
96 		clear_bit(SPOLL_NUM, &board->status);
97 
98 	} else {
99 		priv->srq_pending = 0;
100 	}
101 	write_byte(priv, status, SPMR);
102 	spin_unlock_irqrestore(&board->spinlock, flags);
103 }
104 EXPORT_SYMBOL(nec7210_serial_poll_response);
105 
nec7210_serial_poll_status(struct gpib_board * board,struct nec7210_priv * priv)106 uint8_t nec7210_serial_poll_status(struct gpib_board *board, struct nec7210_priv *priv)
107 {
108 	return read_byte(priv, SPSR);
109 }
110 EXPORT_SYMBOL(nec7210_serial_poll_status);
111 
nec7210_primary_address(const struct gpib_board * board,struct nec7210_priv * priv,unsigned int address)112 int nec7210_primary_address(const struct gpib_board *board, struct nec7210_priv *priv,
113 			    unsigned int address)
114 {
115 	// put primary address in address0
116 	write_byte(priv, address & ADDRESS_MASK, ADR);
117 	return 0;
118 }
119 EXPORT_SYMBOL(nec7210_primary_address);
120 
nec7210_secondary_address(const struct gpib_board * board,struct nec7210_priv * priv,unsigned int address,int enable)121 int nec7210_secondary_address(const struct gpib_board *board, struct nec7210_priv *priv,
122 			      unsigned int address, int enable)
123 {
124 	if (enable) {
125 		// put secondary address in address1
126 		write_byte(priv, HR_ARS | (address & ADDRESS_MASK), ADR);
127 		// go to address mode 2
128 		priv->reg_bits[ADMR] &= ~HR_ADM0;
129 		priv->reg_bits[ADMR] |= HR_ADM1;
130 	} else {
131 		// disable address1 register
132 		write_byte(priv, HR_ARS | HR_DT | HR_DL, ADR);
133 		// go to address mode 1
134 		priv->reg_bits[ADMR] |= HR_ADM0;
135 		priv->reg_bits[ADMR] &= ~HR_ADM1;
136 	}
137 	write_byte(priv, priv->reg_bits[ADMR], ADMR);
138 	return 0;
139 }
140 EXPORT_SYMBOL(nec7210_secondary_address);
141 
update_talker_state(struct nec7210_priv * priv,unsigned int address_status_bits)142 static void update_talker_state(struct nec7210_priv *priv, unsigned int address_status_bits)
143 {
144 	if ((address_status_bits & HR_TA)) {
145 		if ((address_status_bits & HR_NATN)) {
146 			if (address_status_bits & HR_SPMS)
147 				priv->talker_state = serial_poll_active;
148 			else
149 				priv->talker_state = talker_active;
150 		} else {
151 			priv->talker_state = talker_addressed;
152 		}
153 	} else {
154 		priv->talker_state = talker_idle;
155 	}
156 }
157 
update_listener_state(struct nec7210_priv * priv,unsigned int address_status_bits)158 static void update_listener_state(struct nec7210_priv *priv, unsigned int address_status_bits)
159 {
160 	if (address_status_bits & HR_LA) {
161 		if ((address_status_bits & HR_NATN))
162 			priv->listener_state = listener_active;
163 		else
164 			priv->listener_state = listener_addressed;
165 	} else {
166 		priv->listener_state = listener_idle;
167 	}
168 }
169 
nec7210_update_status_nolock(struct gpib_board * board,struct nec7210_priv * priv)170 unsigned int nec7210_update_status_nolock(struct gpib_board *board, struct nec7210_priv *priv)
171 {
172 	int address_status_bits;
173 	u8 spoll_status;
174 
175 	if (!priv)
176 		return 0;
177 
178 	address_status_bits = read_byte(priv, ADSR);
179 	if (address_status_bits & HR_CIC)
180 		set_bit(CIC_NUM, &board->status);
181 	else
182 		clear_bit(CIC_NUM, &board->status);
183 	// check for talker/listener addressed
184 	update_talker_state(priv, address_status_bits);
185 	if (priv->talker_state == talker_active || priv->talker_state == talker_addressed)
186 		set_bit(TACS_NUM, &board->status);
187 	else
188 		clear_bit(TACS_NUM, &board->status);
189 	update_listener_state(priv, address_status_bits);
190 	if (priv->listener_state == listener_active ||
191 	    priv->listener_state == listener_addressed)
192 		set_bit(LACS_NUM, &board->status);
193 	else
194 		clear_bit(LACS_NUM, &board->status);
195 	if (address_status_bits & HR_NATN)
196 		clear_bit(ATN_NUM, &board->status);
197 	else
198 		set_bit(ATN_NUM, &board->status);
199 	spoll_status = nec7210_serial_poll_status(board, priv);
200 	if (priv->srq_pending && (spoll_status & request_service_bit) == 0) {
201 		priv->srq_pending = 0;
202 		set_bit(SPOLL_NUM, &board->status);
203 	}
204 
205 	/* we rely on the interrupt handler to set the
206 	 * rest of the status bits
207 	 */
208 
209 	return board->status;
210 }
211 EXPORT_SYMBOL(nec7210_update_status_nolock);
212 
nec7210_update_status(struct gpib_board * board,struct nec7210_priv * priv,unsigned int clear_mask)213 unsigned int nec7210_update_status(struct gpib_board *board, struct nec7210_priv *priv,
214 				   unsigned int clear_mask)
215 {
216 	unsigned long flags;
217 	unsigned int retval;
218 
219 	spin_lock_irqsave(&board->spinlock, flags);
220 	board->status &= ~clear_mask;
221 	retval = nec7210_update_status_nolock(board, priv);
222 	spin_unlock_irqrestore(&board->spinlock, flags);
223 
224 	return retval;
225 }
226 EXPORT_SYMBOL(nec7210_update_status);
227 
nec7210_set_reg_bits(struct nec7210_priv * priv,unsigned int reg,unsigned int mask,unsigned int bits)228 unsigned int nec7210_set_reg_bits(struct nec7210_priv *priv, unsigned int reg,
229 				  unsigned int mask, unsigned int bits)
230 {
231 	priv->reg_bits[reg] &= ~mask;
232 	priv->reg_bits[reg] |= mask & bits;
233 	write_byte(priv, priv->reg_bits[reg], reg);
234 	return priv->reg_bits[reg];
235 }
236 EXPORT_SYMBOL(nec7210_set_reg_bits);
237 
nec7210_set_handshake_mode(struct gpib_board * board,struct nec7210_priv * priv,int mode)238 void nec7210_set_handshake_mode(struct gpib_board *board, struct nec7210_priv *priv, int mode)
239 {
240 	unsigned long flags;
241 
242 	mode &= HR_HANDSHAKE_MASK;
243 
244 	spin_lock_irqsave(&board->spinlock, flags);
245 	if ((priv->auxa_bits & HR_HANDSHAKE_MASK) != mode) {
246 		priv->auxa_bits &= ~HR_HANDSHAKE_MASK;
247 		priv->auxa_bits |= mode;
248 		write_byte(priv, priv->auxa_bits, AUXMR);
249 	}
250 	spin_unlock_irqrestore(&board->spinlock, flags);
251 }
252 EXPORT_SYMBOL(nec7210_set_handshake_mode);
253 
nec7210_read_data_in(struct gpib_board * board,struct nec7210_priv * priv,int * end)254 uint8_t nec7210_read_data_in(struct gpib_board *board, struct nec7210_priv *priv, int *end)
255 {
256 	unsigned long flags;
257 	u8 data;
258 
259 	spin_lock_irqsave(&board->spinlock, flags);
260 	data = read_byte(priv, DIR);
261 	clear_bit(READ_READY_BN, &priv->state);
262 	if (test_and_clear_bit(RECEIVED_END_BN, &priv->state))
263 		*end = 1;
264 	else
265 		*end = 0;
266 	spin_unlock_irqrestore(&board->spinlock, flags);
267 
268 	return data;
269 }
270 EXPORT_SYMBOL(nec7210_read_data_in);
271 
nec7210_take_control(struct gpib_board * board,struct nec7210_priv * priv,int syncronous)272 int nec7210_take_control(struct gpib_board *board, struct nec7210_priv *priv, int syncronous)
273 {
274 	int i;
275 	const int timeout = 100;
276 	int retval = 0;
277 	unsigned int adsr_bits = 0;
278 
279 	if (syncronous)
280 		write_byte(priv, AUX_TCS, AUXMR);
281 	else
282 		write_byte(priv, AUX_TCA, AUXMR);
283 	// busy wait until ATN is asserted
284 	for (i = 0; i < timeout; i++) {
285 		adsr_bits = read_byte(priv, ADSR);
286 		if ((adsr_bits & HR_NATN) == 0)
287 			break;
288 		udelay(1);
289 	}
290 	if (i == timeout)
291 		return -ETIMEDOUT;
292 
293 	clear_bit(WRITE_READY_BN, &priv->state);
294 
295 	return retval;
296 }
297 EXPORT_SYMBOL(nec7210_take_control);
298 
nec7210_go_to_standby(struct gpib_board * board,struct nec7210_priv * priv)299 int nec7210_go_to_standby(struct gpib_board *board, struct nec7210_priv *priv)
300 {
301 	int i;
302 	const int timeout = 1000;
303 	unsigned int adsr_bits = 0;
304 	int retval = 0;
305 
306 	write_byte(priv, AUX_GTS, AUXMR);
307 	// busy wait until ATN is released
308 	for (i = 0; i < timeout; i++) {
309 		adsr_bits = read_byte(priv, ADSR);
310 		if (adsr_bits & HR_NATN)
311 			break;
312 		udelay(1);
313 	}
314 	// if busy wait has failed, try sleeping
315 	if (i == timeout) {
316 		for (i = 0; i < HZ; i++) {
317 			set_current_state(TASK_INTERRUPTIBLE);
318 			if (schedule_timeout(1))
319 				return -ERESTARTSYS;
320 			adsr_bits = read_byte(priv, ADSR);
321 			if (adsr_bits & HR_NATN)
322 				break;
323 		}
324 		if (i == HZ)
325 			return -ETIMEDOUT;
326 	}
327 
328 	clear_bit(COMMAND_READY_BN, &priv->state);
329 	return retval;
330 }
331 EXPORT_SYMBOL(nec7210_go_to_standby);
332 
nec7210_request_system_control(struct gpib_board * board,struct nec7210_priv * priv,int request_control)333 void nec7210_request_system_control(struct gpib_board *board, struct nec7210_priv *priv,
334 				    int request_control)
335 {
336 	if (request_control == 0) {
337 		write_byte(priv, AUX_CREN, AUXMR);
338 		write_byte(priv, AUX_CIFC, AUXMR);
339 		write_byte(priv, AUX_DSC, AUXMR);
340 	}
341 }
342 EXPORT_SYMBOL(nec7210_request_system_control);
343 
nec7210_interface_clear(struct gpib_board * board,struct nec7210_priv * priv,int assert)344 void nec7210_interface_clear(struct gpib_board *board, struct nec7210_priv *priv, int assert)
345 {
346 	if (assert)
347 		write_byte(priv, AUX_SIFC, AUXMR);
348 	else
349 		write_byte(priv, AUX_CIFC, AUXMR);
350 }
351 EXPORT_SYMBOL(nec7210_interface_clear);
352 
nec7210_remote_enable(struct gpib_board * board,struct nec7210_priv * priv,int enable)353 void nec7210_remote_enable(struct gpib_board *board, struct nec7210_priv *priv, int enable)
354 {
355 	if (enable)
356 		write_byte(priv, AUX_SREN, AUXMR);
357 	else
358 		write_byte(priv, AUX_CREN, AUXMR);
359 }
360 EXPORT_SYMBOL(nec7210_remote_enable);
361 
nec7210_release_rfd_holdoff(struct gpib_board * board,struct nec7210_priv * priv)362 void nec7210_release_rfd_holdoff(struct gpib_board *board, struct nec7210_priv *priv)
363 {
364 	unsigned long flags;
365 
366 	spin_lock_irqsave(&board->spinlock, flags);
367 	if (test_bit(RFD_HOLDOFF_BN, &priv->state) &&
368 	    test_bit(READ_READY_BN, &priv->state) == 0) {
369 		write_byte(priv, AUX_FH, AUXMR);
370 		clear_bit(RFD_HOLDOFF_BN, &priv->state);
371 	}
372 	spin_unlock_irqrestore(&board->spinlock, flags);
373 }
374 EXPORT_SYMBOL(nec7210_release_rfd_holdoff);
375 
nec7210_t1_delay(struct gpib_board * board,struct nec7210_priv * priv,unsigned int nano_sec)376 int nec7210_t1_delay(struct gpib_board *board, struct nec7210_priv *priv,
377 		     unsigned int nano_sec)
378 {
379 	unsigned int retval;
380 
381 	if (nano_sec <= 500) {
382 		priv->auxb_bits |= HR_TRI;
383 		retval = 500;
384 	} else {
385 		priv->auxb_bits &= ~HR_TRI;
386 		retval = 2000;
387 	}
388 	write_byte(priv, priv->auxb_bits, AUXMR);
389 
390 	return retval;
391 }
392 EXPORT_SYMBOL(nec7210_t1_delay);
393 
nec7210_return_to_local(const struct gpib_board * board,struct nec7210_priv * priv)394 void nec7210_return_to_local(const struct gpib_board *board, struct nec7210_priv *priv)
395 {
396 	write_byte(priv, AUX_RTL, AUXMR);
397 }
398 EXPORT_SYMBOL(nec7210_return_to_local);
399 
nec7210_atn_has_changed(struct gpib_board * board,struct nec7210_priv * priv)400 static inline short nec7210_atn_has_changed(struct gpib_board *board, struct nec7210_priv *priv)
401 {
402 	short address_status_bits = read_byte(priv, ADSR);
403 
404 	if (address_status_bits & HR_NATN) {
405 		if (test_bit(ATN_NUM, &board->status))
406 			return 1;
407 		else
408 			return 0;
409 	} else	{
410 		if (test_bit(ATN_NUM, &board->status))
411 			return 0;
412 		else
413 			return 1;
414 	}
415 	return -1;
416 }
417 
nec7210_command(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,size_t * bytes_written)418 int nec7210_command(struct gpib_board *board, struct nec7210_priv *priv, uint8_t
419 		    *buffer, size_t length, size_t *bytes_written)
420 {
421 	int retval = 0;
422 	unsigned long flags;
423 
424 	*bytes_written = 0;
425 
426 	clear_bit(BUS_ERROR_BN, &priv->state);
427 
428 	while (*bytes_written < length)	{
429 		if (wait_event_interruptible(board->wait,
430 					     test_bit(COMMAND_READY_BN, &priv->state) ||
431 					     test_bit(BUS_ERROR_BN, &priv->state) ||
432 					     test_bit(TIMO_NUM, &board->status))) {
433 			dev_dbg(board->gpib_dev, "command wait interrupted\n");
434 			retval = -ERESTARTSYS;
435 			break;
436 		}
437 		if (test_bit(TIMO_NUM, &board->status))
438 			break;
439 		if (test_and_clear_bit(BUS_ERROR_BN, &priv->state))
440 			break;
441 		spin_lock_irqsave(&board->spinlock, flags);
442 		clear_bit(COMMAND_READY_BN, &priv->state);
443 		write_byte(priv, buffer[*bytes_written], CDOR);
444 		spin_unlock_irqrestore(&board->spinlock, flags);
445 
446 		++(*bytes_written);
447 
448 		if (need_resched())
449 			schedule();
450 	}
451 	// wait for last byte to get sent
452 	if (wait_event_interruptible(board->wait, test_bit(COMMAND_READY_BN, &priv->state) ||
453 				     test_bit(BUS_ERROR_BN, &priv->state) ||
454 				     test_bit(TIMO_NUM, &board->status)))
455 		retval = -ERESTARTSYS;
456 
457 	if (test_bit(TIMO_NUM, &board->status))
458 		retval = -ETIMEDOUT;
459 
460 	if (test_and_clear_bit(BUS_ERROR_BN, &priv->state))
461 		retval = -EIO;
462 
463 	return retval;
464 }
465 EXPORT_SYMBOL(nec7210_command);
466 
pio_read(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)467 static int pio_read(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *buffer,
468 		    size_t length, int *end, size_t *bytes_read)
469 {
470 	ssize_t retval = 0;
471 
472 	*bytes_read = 0;
473 	*end = 0;
474 
475 	while (*bytes_read < length) {
476 		if (wait_event_interruptible(board->wait,
477 					     test_bit(READ_READY_BN, &priv->state) ||
478 					     test_bit(DEV_CLEAR_BN, &priv->state) ||
479 					     test_bit(TIMO_NUM, &board->status))) {
480 			retval = -ERESTARTSYS;
481 			break;
482 		}
483 		if (test_bit(READ_READY_BN, &priv->state)) {
484 			if (*bytes_read == 0)	{
485 				/* We set the handshake mode here because we know
486 				 * no new bytes will arrive (it has already arrived
487 				 * and is awaiting being read out of the chip) while we are changing
488 				 * modes.  This ensures we can reliably keep track
489 				 * of the holdoff state.
490 				 */
491 				nec7210_set_handshake_mode(board, priv, HR_HLDA);
492 			}
493 			buffer[(*bytes_read)++] = nec7210_read_data_in(board, priv, end);
494 			if (*end)
495 				break;
496 		}
497 		if (test_bit(TIMO_NUM, &board->status)) {
498 			retval = -ETIMEDOUT;
499 			break;
500 		}
501 		if (test_bit(DEV_CLEAR_BN, &priv->state)) {
502 			retval = -EINTR;
503 			break;
504 		}
505 
506 		if (*bytes_read < length)
507 			nec7210_release_rfd_holdoff(board, priv);
508 
509 		if (need_resched())
510 			schedule();
511 	}
512 	return retval;
513 }
514 
515 #ifdef NEC_DMA
__dma_read(struct gpib_board * board,struct nec7210_priv * priv,size_t length)516 static ssize_t __dma_read(struct gpib_board *board, struct nec7210_priv *priv, size_t length)
517 {
518 	ssize_t retval = 0;
519 	size_t count = 0;
520 	unsigned long flags, dma_irq_flags;
521 
522 	if (length == 0)
523 		return 0;
524 
525 	spin_lock_irqsave(&board->spinlock, flags);
526 
527 	dma_irq_flags = claim_dma_lock();
528 	disable_dma(priv->dma_channel);
529 	/* program dma controller */
530 	clear_dma_ff(priv->dma_channel);
531 	set_dma_count(priv->dma_channel, length);
532 	set_dma_addr(priv->dma_channel, priv->dma_buffer_addr);
533 	set_dma_mode(priv->dma_channel, DMA_MODE_READ);
534 	release_dma_lock(dma_irq_flags);
535 
536 	enable_dma(priv->dma_channel);
537 
538 	set_bit(DMA_READ_IN_PROGRESS_BN, &priv->state);
539 	clear_bit(READ_READY_BN, &priv->state);
540 
541 	// enable nec7210 dma
542 	nec7210_set_reg_bits(priv, IMR2, HR_DMAI, HR_DMAI);
543 
544 	spin_unlock_irqrestore(&board->spinlock, flags);
545 
546 	// wait for data to transfer
547 	if (wait_event_interruptible(board->wait,
548 				     test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state) == 0 ||
549 				     test_bit(DEV_CLEAR_BN, &priv->state) ||
550 				     test_bit(TIMO_NUM, &board->status)))
551 		retval = -ERESTARTSYS;
552 
553 	if (test_bit(TIMO_NUM, &board->status))
554 		retval = -ETIMEDOUT;
555 	if (test_bit(DEV_CLEAR_BN, &priv->state))
556 		retval = -EINTR;
557 
558 	// disable nec7210 dma
559 	nec7210_set_reg_bits(priv, IMR2, HR_DMAI, 0);
560 
561 	// record how many bytes we transferred
562 	flags = claim_dma_lock();
563 	clear_dma_ff(priv->dma_channel);
564 	disable_dma(priv->dma_channel);
565 	count += length - get_dma_residue(priv->dma_channel);
566 	release_dma_lock(flags);
567 
568 	return retval ? retval : count;
569 }
570 
dma_read(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length)571 static ssize_t dma_read(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *buffer,
572 			size_t length)
573 {
574 	size_t remain = length;
575 	size_t transfer_size;
576 	ssize_t retval = 0;
577 
578 	while (remain > 0) {
579 		transfer_size = (priv->dma_buffer_length < remain) ?
580 			priv->dma_buffer_length : remain;
581 		retval = __dma_read(board, priv, transfer_size);
582 		if (retval < 0)
583 			break;
584 		memcpy(buffer, priv->dma_buffer, transfer_size);
585 		remain -= retval;
586 		buffer += retval;
587 		if (test_bit(RECEIVED_END_BN, &priv->state))
588 			break;
589 	}
590 
591 	if (retval < 0)
592 		return retval;
593 
594 	return length - remain;
595 }
596 #endif
597 
nec7210_read(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int * end,size_t * bytes_read)598 int nec7210_read(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *buffer,
599 		 size_t length, int *end, size_t *bytes_read)
600 {
601 	ssize_t retval = 0;
602 
603 	*end = 0;
604 	*bytes_read = 0;
605 
606 	if (length == 0)
607 		return 0;
608 
609 	clear_bit(DEV_CLEAR_BN, &priv->state); // XXX wrong
610 
611 	nec7210_release_rfd_holdoff(board, priv);
612 
613 	retval = pio_read(board, priv, buffer, length, end, bytes_read);
614 
615 	return retval;
616 }
617 EXPORT_SYMBOL(nec7210_read);
618 
pio_write_wait(struct gpib_board * board,struct nec7210_priv * priv,short wake_on_lacs,short wake_on_atn,short wake_on_bus_error)619 static int pio_write_wait(struct gpib_board *board, struct nec7210_priv *priv,
620 			  short wake_on_lacs, short wake_on_atn, short wake_on_bus_error)
621 {
622 	// wait until byte is ready to be sent
623 	if (wait_event_interruptible(board->wait,
624 				     (test_bit(TACS_NUM, &board->status) &&
625 				      test_bit(WRITE_READY_BN, &priv->state)) ||
626 				     test_bit(DEV_CLEAR_BN, &priv->state) ||
627 				     (wake_on_bus_error && test_bit(BUS_ERROR_BN, &priv->state)) ||
628 				     (wake_on_lacs && test_bit(LACS_NUM, &board->status)) ||
629 				     (wake_on_atn && test_bit(ATN_NUM, &board->status)) ||
630 				     test_bit(TIMO_NUM, &board->status)))
631 		return -ERESTARTSYS;
632 
633 	if (test_bit(TIMO_NUM, &board->status))
634 		return -ETIMEDOUT;
635 
636 	if (test_bit(DEV_CLEAR_BN, &priv->state))
637 		return -EINTR;
638 
639 	if (wake_on_bus_error && test_and_clear_bit(BUS_ERROR_BN, &priv->state))
640 		return -EIO;
641 
642 	return 0;
643 }
644 
pio_write(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,size_t * bytes_written)645 static int pio_write(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *buffer,
646 		     size_t length, size_t *bytes_written)
647 {
648 	size_t last_count = 0;
649 	ssize_t retval = 0;
650 	unsigned long flags;
651 	const int max_bus_errors = (length > 1000) ? length : 1000;
652 	int bus_error_count = 0;
653 	*bytes_written = 0;
654 
655 	clear_bit(BUS_ERROR_BN, &priv->state);
656 
657 	while (*bytes_written < length) {
658 		if (need_resched())
659 			schedule();
660 
661 		retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210);
662 		if (retval == -EIO) {
663 			/* resend last byte on bus error */
664 			*bytes_written = last_count;
665 			/* we can get unrecoverable bus errors,
666 			 * so give up after a while
667 			 */
668 			bus_error_count++;
669 			if (bus_error_count > max_bus_errors)
670 				return retval;
671 			continue;
672 		} else {
673 			if (retval < 0)
674 				return retval;
675 		}
676 		spin_lock_irqsave(&board->spinlock, flags);
677 		clear_bit(BUS_ERROR_BN, &priv->state);
678 		clear_bit(WRITE_READY_BN, &priv->state);
679 		last_count = *bytes_written;
680 		write_byte(priv, buffer[(*bytes_written)++], CDOR);
681 		spin_unlock_irqrestore(&board->spinlock, flags);
682 	}
683 	retval = pio_write_wait(board, priv, 1, 1, priv->type == NEC7210);
684 	return retval;
685 }
686 
687 #ifdef NEC_DMA
__dma_write(struct gpib_board * board,struct nec7210_priv * priv,dma_addr_t address,size_t length)688 static ssize_t __dma_write(struct gpib_board *board, struct nec7210_priv *priv, dma_addr_t address,
689 			   size_t length)
690 {
691 	unsigned long flags, dma_irq_flags;
692 	int residue = 0;
693 	int retval = 0;
694 
695 	spin_lock_irqsave(&board->spinlock, flags);
696 
697 	/* program dma controller */
698 	dma_irq_flags = claim_dma_lock();
699 	disable_dma(priv->dma_channel);
700 	clear_dma_ff(priv->dma_channel);
701 	set_dma_count(priv->dma_channel, length);
702 	set_dma_addr(priv->dma_channel, address);
703 	set_dma_mode(priv->dma_channel, DMA_MODE_WRITE);
704 	enable_dma(priv->dma_channel);
705 	release_dma_lock(dma_irq_flags);
706 
707 	// enable board's dma for output
708 	nec7210_set_reg_bits(priv, IMR2, HR_DMAO, HR_DMAO);
709 
710 	clear_bit(WRITE_READY_BN, &priv->state);
711 	set_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state);
712 
713 	spin_unlock_irqrestore(&board->spinlock, flags);
714 
715 	// suspend until message is sent
716 	if (wait_event_interruptible(board->wait,
717 				     test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0 ||
718 				     test_bit(BUS_ERROR_BN, &priv->state) ||
719 				     test_bit(DEV_CLEAR_BN, &priv->state) ||
720 				     test_bit(TIMO_NUM, &board->status)))
721 		retval = -ERESTARTSYS;
722 
723 	if (test_bit(TIMO_NUM, &board->status))
724 		retval = -ETIMEDOUT;
725 	if (test_and_clear_bit(DEV_CLEAR_BN, &priv->state))
726 		retval = -EINTR;
727 	if (test_and_clear_bit(BUS_ERROR_BN, &priv->state))
728 		retval = -EIO;
729 
730 	// disable board's dma
731 	nec7210_set_reg_bits(priv, IMR2, HR_DMAO, 0);
732 
733 	dma_irq_flags = claim_dma_lock();
734 	clear_dma_ff(priv->dma_channel);
735 	disable_dma(priv->dma_channel);
736 	residue = get_dma_residue(priv->dma_channel);
737 	release_dma_lock(dma_irq_flags);
738 
739 	if (residue)
740 		retval = -EPIPE;
741 
742 	return retval ? retval : length;
743 }
744 
dma_write(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length)745 static ssize_t dma_write(struct gpib_board *board, struct nec7210_priv *priv, uint8_t *buffer,
746 			 size_t length)
747 {
748 	size_t remain = length;
749 	size_t transfer_size;
750 	ssize_t retval = 0;
751 
752 	while (remain > 0) {
753 		transfer_size = (priv->dma_buffer_length < remain) ?
754 			priv->dma_buffer_length : remain;
755 		memcpy(priv->dma_buffer, buffer, transfer_size);
756 		retval = __dma_write(board, priv, priv->dma_buffer_addr, transfer_size);
757 		if (retval < 0)
758 			break;
759 		remain -= retval;
760 		buffer += retval;
761 	}
762 
763 	if (retval < 0)
764 		return retval;
765 
766 	return length - remain;
767 }
768 #endif
nec7210_write(struct gpib_board * board,struct nec7210_priv * priv,uint8_t * buffer,size_t length,int send_eoi,size_t * bytes_written)769 int nec7210_write(struct gpib_board *board, struct nec7210_priv *priv,
770 		  uint8_t *buffer, size_t length, int send_eoi,
771 		  size_t *bytes_written)
772 {
773 	int retval = 0;
774 
775 	*bytes_written = 0;
776 
777 	clear_bit(DEV_CLEAR_BN, &priv->state); //XXX
778 
779 	if (send_eoi)
780 		length-- ; /* save the last byte for sending EOI */
781 
782 	if (length > 0)	{
783 		// isa dma transfer
784 		if (0 /*priv->dma_channel*/) {
785 /*
786  * dma writes are unreliable since they can't recover from bus errors
787  * (which happen when ATN is asserted in the middle of a write)
788  */
789 #ifdef NEC_DMA
790 			retval = dma_write(board, priv, buffer, length);
791 			if (retval < 0)
792 				return retval;
793 			count += retval;
794 #endif
795 		} else {	// PIO transfer
796 			size_t num_bytes;
797 
798 			retval = pio_write(board, priv, buffer, length, &num_bytes);
799 
800 			*bytes_written += num_bytes;
801 			if (retval < 0)
802 				return retval;
803 		}
804 	}
805 	if (send_eoi) {
806 		size_t num_bytes;
807 
808 		/* We need to wait to make sure we will immediately be able to write the data byte
809 		 * into the chip before sending the associated AUX_SEOI command.  This is really
810 		 * only needed for length==1 since otherwise the earlier calls to pio_write
811 		 * will have dont the wait already.
812 		 */
813 		retval = pio_write_wait(board, priv, 0, 0, priv->type == NEC7210);
814 		if (retval < 0)
815 			return retval;
816 		/*send EOI */
817 		write_byte(priv, AUX_SEOI, AUXMR);
818 
819 		retval = pio_write(board, priv, &buffer[*bytes_written], 1, &num_bytes);
820 		*bytes_written += num_bytes;
821 		if (retval < 0)
822 			return retval;
823 	}
824 
825 	return retval;
826 }
827 EXPORT_SYMBOL(nec7210_write);
828 
829 /*
830  *  interrupt service routine
831  */
nec7210_interrupt(struct gpib_board * board,struct nec7210_priv * priv)832 irqreturn_t nec7210_interrupt(struct gpib_board *board, struct nec7210_priv *priv)
833 {
834 	int status1, status2;
835 
836 	// read interrupt status (also clears status)
837 	status1 = read_byte(priv, ISR1);
838 	status2 = read_byte(priv, ISR2);
839 
840 	return nec7210_interrupt_have_status(board, priv, status1, status2);
841 }
842 EXPORT_SYMBOL(nec7210_interrupt);
843 
nec7210_interrupt_have_status(struct gpib_board * board,struct nec7210_priv * priv,int status1,int status2)844 irqreturn_t nec7210_interrupt_have_status(struct gpib_board *board,
845 					  struct nec7210_priv *priv, int status1, int status2)
846 {
847 #ifdef NEC_DMA
848 	unsigned long dma_flags;
849 #endif
850 	int retval = IRQ_NONE;
851 
852 	// record service request in status
853 	if (status2 & HR_SRQI)
854 		set_bit(SRQI_NUM, &board->status);
855 
856 	// change in lockout status
857 	if (status2 & HR_LOKC) {
858 		if (status2 & HR_LOK)
859 			set_bit(LOK_NUM, &board->status);
860 		else
861 			clear_bit(LOK_NUM, &board->status);
862 	}
863 
864 	// change in remote status
865 	if (status2 & HR_REMC) {
866 		if (status2 & HR_REM)
867 			set_bit(REM_NUM, &board->status);
868 		else
869 			clear_bit(REM_NUM, &board->status);
870 	}
871 
872 	// record reception of END
873 	if (status1 & HR_END) {
874 		set_bit(RECEIVED_END_BN, &priv->state);
875 		if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDE)
876 			set_bit(RFD_HOLDOFF_BN, &priv->state);
877 	}
878 
879 	// get incoming data in PIO mode
880 	if ((status1 & HR_DI)) {
881 		set_bit(READ_READY_BN, &priv->state);
882 		if ((priv->auxa_bits & HR_HANDSHAKE_MASK) == HR_HLDA)
883 			set_bit(RFD_HOLDOFF_BN, &priv->state);
884 	}
885 #ifdef NEC_DMA
886 	// check for dma read transfer complete
887 	if (test_bit(DMA_READ_IN_PROGRESS_BN, &priv->state)) {
888 		dma_flags = claim_dma_lock();
889 		disable_dma(priv->dma_channel);
890 		clear_dma_ff(priv->dma_channel);
891 		if ((status1 & HR_END) || get_dma_residue(priv->dma_channel) == 0)
892 			clear_bit(DMA_READ_IN_PROGRESS_BN, &priv->state);
893 		else
894 			enable_dma(priv->dma_channel);
895 		release_dma_lock(dma_flags);
896 	}
897 #endif
898 	if ((status1 & HR_DO)) {
899 		if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state) == 0)
900 			set_bit(WRITE_READY_BN, &priv->state);
901 #ifdef NEC_DMA
902 		if (test_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state)) {	// write data, isa dma mode
903 			// check if dma transfer is complete
904 			dma_flags = claim_dma_lock();
905 			disable_dma(priv->dma_channel);
906 			clear_dma_ff(priv->dma_channel);
907 			if (get_dma_residue(priv->dma_channel) == 0) {
908 				clear_bit(DMA_WRITE_IN_PROGRESS_BN, &priv->state);
909 			// XXX race? byte may still be in CDOR reg
910 			} else {
911 				clear_bit(WRITE_READY_BN, &priv->state);
912 				enable_dma(priv->dma_channel);
913 			}
914 			release_dma_lock(dma_flags);
915 		}
916 #endif
917 	}
918 
919 	// outgoing command can be sent
920 	if (status2 & HR_CO)
921 		set_bit(COMMAND_READY_BN, &priv->state);
922 
923 	// command pass through received
924 	if (status1 & HR_CPT)
925 		write_byte(priv, AUX_NVAL, AUXMR);
926 
927 	if (status1 & HR_ERR)
928 		set_bit(BUS_ERROR_BN, &priv->state);
929 
930 	if (status1 & HR_DEC) {
931 		unsigned short address_status_bits = read_byte(priv, ADSR);
932 
933 		// ignore device clear events if we are controller in charge
934 		if ((address_status_bits & HR_CIC) == 0) {
935 			push_gpib_event(board, EventDevClr);
936 			set_bit(DEV_CLEAR_BN, &priv->state);
937 		}
938 	}
939 
940 	if (status1 & HR_DET)
941 		push_gpib_event(board, EventDevTrg);
942 
943 	// Addressing status has changed
944 	if (status2 & HR_ADSC)
945 		set_bit(ADR_CHANGE_BN, &priv->state);
946 
947 	if ((status1 & priv->reg_bits[IMR1]) ||
948 	    (status2 & (priv->reg_bits[IMR2] & IMR2_ENABLE_INTR_MASK)) ||
949 	    nec7210_atn_has_changed(board, priv))	{
950 		nec7210_update_status_nolock(board, priv);
951 		dev_dbg(board->gpib_dev, "minor %i, stat %lx, isr1 0x%x, imr1 0x%x, isr2 0x%x, imr2 0x%x\n",
952 			board->minor, board->status, status1, priv->reg_bits[IMR1], status2,
953 			     priv->reg_bits[IMR2]);
954 		wake_up_interruptible(&board->wait); /* wake up sleeping process */
955 		retval = IRQ_HANDLED;
956 	}
957 
958 	return retval;
959 }
960 EXPORT_SYMBOL(nec7210_interrupt_have_status);
961 
nec7210_board_reset(struct nec7210_priv * priv,const struct gpib_board * board)962 void nec7210_board_reset(struct nec7210_priv *priv, const struct gpib_board *board)
963 {
964 	/* 7210 chip reset */
965 	write_byte(priv, AUX_CR, AUXMR);
966 
967 	/* disable all interrupts */
968 	priv->reg_bits[IMR1] = 0;
969 	write_byte(priv, priv->reg_bits[IMR1], IMR1);
970 	priv->reg_bits[IMR2] = 0;
971 	write_byte(priv, priv->reg_bits[IMR2], IMR2);
972 	write_byte(priv, 0, SPMR);
973 
974 	/* clear registers by reading */
975 	read_byte(priv, CPTR);
976 	read_byte(priv, ISR1);
977 	read_byte(priv, ISR2);
978 
979 	/* parallel poll unconfigure */
980 	write_byte(priv, PPR | HR_PPU, AUXMR);
981 
982 	priv->reg_bits[ADMR] = HR_TRM0 | HR_TRM1;
983 
984 	priv->auxa_bits = AUXRA | HR_HLDA;
985 	write_byte(priv, priv->auxa_bits, AUXMR);
986 
987 	write_byte(priv, AUXRE | 0, AUXMR);
988 
989 	/* set INT pin to active high, enable command pass through of unknown commands */
990 	priv->auxb_bits = AUXRB | HR_CPTE;
991 	write_byte(priv, priv->auxb_bits, AUXMR);
992 	write_byte(priv, AUXRE, AUXMR);
993 }
994 EXPORT_SYMBOL(nec7210_board_reset);
995 
nec7210_board_online(struct nec7210_priv * priv,const struct gpib_board * board)996 void nec7210_board_online(struct nec7210_priv *priv, const struct gpib_board *board)
997 {
998 	/* set GPIB address */
999 	nec7210_primary_address(board, priv, board->pad);
1000 	nec7210_secondary_address(board, priv, board->sad, board->sad >= 0);
1001 
1002 	// enable interrupts
1003 	priv->reg_bits[IMR1] = HR_ERRIE | HR_DECIE | HR_ENDIE |
1004 		HR_DETIE | HR_CPTIE | HR_DOIE | HR_DIIE;
1005 	priv->reg_bits[IMR2] = IMR2_ENABLE_INTR_MASK;
1006 	write_byte(priv, priv->reg_bits[IMR1], IMR1);
1007 	write_byte(priv, priv->reg_bits[IMR2], IMR2);
1008 
1009 	write_byte(priv, AUX_PON, AUXMR);
1010 }
1011 EXPORT_SYMBOL(nec7210_board_online);
1012 
1013 #ifdef CONFIG_HAS_IOPORT
1014 /* wrappers for io */
nec7210_ioport_read_byte(struct nec7210_priv * priv,unsigned int register_num)1015 uint8_t nec7210_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num)
1016 {
1017 	return inb(priv->iobase + register_num * priv->offset);
1018 }
1019 EXPORT_SYMBOL(nec7210_ioport_read_byte);
1020 
nec7210_ioport_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1021 void nec7210_ioport_write_byte(struct nec7210_priv *priv, uint8_t data, unsigned int register_num)
1022 {
1023 	if (register_num == AUXMR)
1024 		/* locking makes absolutely sure noone accesses the
1025 		 * AUXMR register faster than once per microsecond
1026 		 */
1027 		nec7210_locking_ioport_write_byte(priv, data, register_num);
1028 	else
1029 		outb(data, priv->iobase + register_num * priv->offset);
1030 }
1031 EXPORT_SYMBOL(nec7210_ioport_write_byte);
1032 
1033 /* locking variants of io wrappers, for chips that page-in registers */
nec7210_locking_ioport_read_byte(struct nec7210_priv * priv,unsigned int register_num)1034 uint8_t nec7210_locking_ioport_read_byte(struct nec7210_priv *priv, unsigned int register_num)
1035 {
1036 	u8 retval;
1037 	unsigned long flags;
1038 
1039 	spin_lock_irqsave(&priv->register_page_lock, flags);
1040 	retval = inb(priv->iobase + register_num * priv->offset);
1041 	spin_unlock_irqrestore(&priv->register_page_lock, flags);
1042 	return retval;
1043 }
1044 EXPORT_SYMBOL(nec7210_locking_ioport_read_byte);
1045 
nec7210_locking_ioport_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1046 void nec7210_locking_ioport_write_byte(struct nec7210_priv *priv, uint8_t data,
1047 				       unsigned int register_num)
1048 {
1049 	unsigned long flags;
1050 
1051 	spin_lock_irqsave(&priv->register_page_lock, flags);
1052 	if (register_num == AUXMR)
1053 		udelay(1);
1054 	outb(data, priv->iobase + register_num * priv->offset);
1055 	spin_unlock_irqrestore(&priv->register_page_lock, flags);
1056 }
1057 EXPORT_SYMBOL(nec7210_locking_ioport_write_byte);
1058 #endif
1059 
nec7210_iomem_read_byte(struct nec7210_priv * priv,unsigned int register_num)1060 uint8_t nec7210_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num)
1061 {
1062 	return readb(priv->mmiobase + register_num * priv->offset);
1063 }
1064 EXPORT_SYMBOL(nec7210_iomem_read_byte);
1065 
nec7210_iomem_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1066 void nec7210_iomem_write_byte(struct nec7210_priv *priv, uint8_t data, unsigned int register_num)
1067 {
1068 	if (register_num == AUXMR)
1069 		/* locking makes absolutely sure noone accesses the
1070 		 * AUXMR register faster than once per microsecond
1071 		 */
1072 		nec7210_locking_iomem_write_byte(priv, data, register_num);
1073 	else
1074 		writeb(data, priv->mmiobase + register_num * priv->offset);
1075 }
1076 EXPORT_SYMBOL(nec7210_iomem_write_byte);
1077 
nec7210_locking_iomem_read_byte(struct nec7210_priv * priv,unsigned int register_num)1078 uint8_t nec7210_locking_iomem_read_byte(struct nec7210_priv *priv, unsigned int register_num)
1079 {
1080 	u8 retval;
1081 	unsigned long flags;
1082 
1083 	spin_lock_irqsave(&priv->register_page_lock, flags);
1084 	retval = readb(priv->mmiobase + register_num * priv->offset);
1085 	spin_unlock_irqrestore(&priv->register_page_lock, flags);
1086 	return retval;
1087 }
1088 EXPORT_SYMBOL(nec7210_locking_iomem_read_byte);
1089 
nec7210_locking_iomem_write_byte(struct nec7210_priv * priv,uint8_t data,unsigned int register_num)1090 void nec7210_locking_iomem_write_byte(struct nec7210_priv *priv, uint8_t data,
1091 				      unsigned int register_num)
1092 {
1093 	unsigned long flags;
1094 
1095 	spin_lock_irqsave(&priv->register_page_lock, flags);
1096 	if (register_num == AUXMR)
1097 		udelay(1);
1098 	writeb(data, priv->mmiobase + register_num * priv->offset);
1099 	spin_unlock_irqrestore(&priv->register_page_lock, flags);
1100 }
1101 EXPORT_SYMBOL(nec7210_locking_iomem_write_byte);
1102 
nec7210_init_module(void)1103 static int __init nec7210_init_module(void)
1104 {
1105 	return 0;
1106 }
1107 
nec7210_exit_module(void)1108 static void __exit nec7210_exit_module(void)
1109 {
1110 }
1111 
1112 module_init(nec7210_init_module);
1113 module_exit(nec7210_exit_module);
1114