1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 //      Jaswinder Singh <jassi.brar@samsung.com>
5 
6 #include <linux/bitops.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_data/spi-s3c64xx.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/spi/spi.h>
21 #include <linux/types.h>
22 
23 #define MAX_SPI_PORTS		12
24 #define S3C64XX_SPI_QUIRK_CS_AUTO	(1 << 1)
25 #define AUTOSUSPEND_TIMEOUT	2000
26 
27 /* Registers and bit-fields */
28 
29 #define S3C64XX_SPI_CH_CFG		0x00
30 #define S3C64XX_SPI_CLK_CFG		0x04
31 #define S3C64XX_SPI_MODE_CFG		0x08
32 #define S3C64XX_SPI_CS_REG		0x0C
33 #define S3C64XX_SPI_INT_EN		0x10
34 #define S3C64XX_SPI_STATUS		0x14
35 #define S3C64XX_SPI_TX_DATA		0x18
36 #define S3C64XX_SPI_RX_DATA		0x1C
37 #define S3C64XX_SPI_PACKET_CNT		0x20
38 #define S3C64XX_SPI_PENDING_CLR		0x24
39 #define S3C64XX_SPI_SWAP_CFG		0x28
40 #define S3C64XX_SPI_FB_CLK		0x2C
41 
42 #define S3C64XX_SPI_CH_HS_EN		(1<<6)	/* High Speed Enable */
43 #define S3C64XX_SPI_CH_SW_RST		(1<<5)
44 #define S3C64XX_SPI_CH_SLAVE		(1<<4)
45 #define S3C64XX_SPI_CPOL_L		(1<<3)
46 #define S3C64XX_SPI_CPHA_B		(1<<2)
47 #define S3C64XX_SPI_CH_RXCH_ON		(1<<1)
48 #define S3C64XX_SPI_CH_TXCH_ON		(1<<0)
49 
50 #define S3C64XX_SPI_CLKSEL_SRCMSK	(3<<9)
51 #define S3C64XX_SPI_CLKSEL_SRCSHFT	9
52 #define S3C64XX_SPI_ENCLK_ENABLE	(1<<8)
53 #define S3C64XX_SPI_PSR_MASK		0xff
54 
55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE		(0<<29)
56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD	(1<<29)
57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD		(2<<29)
58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK		(3<<29)
59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE		(0<<17)
60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD	(1<<17)
61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD		(2<<17)
62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK		(3<<17)
63 #define S3C64XX_SPI_MODE_RX_RDY_LVL		GENMASK(16, 11)
64 #define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT	11
65 #define S3C64XX_SPI_MODE_SELF_LOOPBACK		(1<<3)
66 #define S3C64XX_SPI_MODE_RXDMA_ON		(1<<2)
67 #define S3C64XX_SPI_MODE_TXDMA_ON		(1<<1)
68 #define S3C64XX_SPI_MODE_4BURST			(1<<0)
69 
70 #define S3C64XX_SPI_CS_NSC_CNT_2		(2<<4)
71 #define S3C64XX_SPI_CS_AUTO			(1<<1)
72 #define S3C64XX_SPI_CS_SIG_INACT		(1<<0)
73 
74 #define S3C64XX_SPI_INT_TRAILING_EN		(1<<6)
75 #define S3C64XX_SPI_INT_RX_OVERRUN_EN		(1<<5)
76 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN		(1<<4)
77 #define S3C64XX_SPI_INT_TX_OVERRUN_EN		(1<<3)
78 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN		(1<<2)
79 #define S3C64XX_SPI_INT_RX_FIFORDY_EN		(1<<1)
80 #define S3C64XX_SPI_INT_TX_FIFORDY_EN		(1<<0)
81 
82 #define S3C64XX_SPI_ST_RX_FIFO_RDY_V2		GENMASK(23, 15)
83 #define S3C64XX_SPI_ST_TX_FIFO_RDY_V2		GENMASK(14, 6)
84 #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT	6
85 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR		(1<<5)
86 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR		(1<<4)
87 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR		(1<<3)
88 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR		(1<<2)
89 #define S3C64XX_SPI_ST_RX_FIFORDY		(1<<1)
90 #define S3C64XX_SPI_ST_TX_FIFORDY		(1<<0)
91 
92 #define S3C64XX_SPI_PACKET_CNT_EN		(1<<16)
93 #define S3C64XX_SPI_PACKET_CNT_MASK		GENMASK(15, 0)
94 
95 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR		(1<<4)
96 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR		(1<<3)
97 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR		(1<<2)
98 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR		(1<<1)
99 #define S3C64XX_SPI_PND_TRAILING_CLR		(1<<0)
100 
101 #define S3C64XX_SPI_SWAP_RX_HALF_WORD		(1<<7)
102 #define S3C64XX_SPI_SWAP_RX_BYTE		(1<<6)
103 #define S3C64XX_SPI_SWAP_RX_BIT			(1<<5)
104 #define S3C64XX_SPI_SWAP_RX_EN			(1<<4)
105 #define S3C64XX_SPI_SWAP_TX_HALF_WORD		(1<<3)
106 #define S3C64XX_SPI_SWAP_TX_BYTE		(1<<2)
107 #define S3C64XX_SPI_SWAP_TX_BIT			(1<<1)
108 #define S3C64XX_SPI_SWAP_TX_EN			(1<<0)
109 
110 #define S3C64XX_SPI_FBCLK_MSK			(3<<0)
111 
112 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
113 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
114 				(1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
115 #define TX_FIFO_LVL(v, sdd)	(((v) & (sdd)->tx_fifomask) >>		\
116 				 __ffs((sdd)->tx_fifomask))
117 #define RX_FIFO_LVL(v, sdd)	(((v) & (sdd)->rx_fifomask) >>		\
118 				 __ffs((sdd)->rx_fifomask))
119 #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1)
120 
121 #define S3C64XX_SPI_MAX_TRAILCNT	0x3ff
122 #define S3C64XX_SPI_TRAILCNT_OFF	19
123 
124 #define S3C64XX_SPI_POLLING_SIZE	32
125 
126 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
127 #define is_polling(x)	(x->cntrlr_info->polling)
128 
129 #define RXBUSY    (1<<2)
130 #define TXBUSY    (1<<3)
131 
132 struct s3c64xx_spi_dma_data {
133 	struct dma_chan *ch;
134 	dma_cookie_t cookie;
135 	enum dma_transfer_direction direction;
136 };
137 
138 /**
139  * struct s3c64xx_spi_port_config - SPI Controller hardware info
140  * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead.
141  * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead.
142  * @fifo_depth: depth of the FIFOs. Used by compatibles where all the instances
143  *              of the IP define the same FIFO depth. It has higher precedence
144  *              than the FIFO depth specified via DT.
145  * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
146  *               length and position.
147  * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
148  *               length and position.
149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
150  * @clk_div: Internal clock divider
151  * @quirks: Bitmask of known quirks
152  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
153  * @clk_from_cmu: True, if the controller does not include a clock mux and
154  *	prescaler unit.
155  * @clk_ioclk: True if clock is present on this device
156  * @has_loopback: True if loopback mode can be supported
157  * @use_32bit_io: True if the SoC allows only 32-bit register accesses.
158  *
159  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
160  * differ in some aspects such as the size of the fifo and spi bus clock
161  * setup. Such differences are specified to the driver using this structure
162  * which is provided as driver data to the driver.
163  */
164 struct s3c64xx_spi_port_config {
165 	int	fifo_lvl_mask[MAX_SPI_PORTS];
166 	int	rx_lvl_offset;
167 	unsigned int fifo_depth;
168 	u32	rx_fifomask;
169 	u32	tx_fifomask;
170 	int	tx_st_done;
171 	int	quirks;
172 	int	clk_div;
173 	bool	high_speed;
174 	bool	clk_from_cmu;
175 	bool	clk_ioclk;
176 	bool	has_loopback;
177 	bool	use_32bit_io;
178 };
179 
180 /**
181  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
182  * @clk: Pointer to the spi clock.
183  * @src_clk: Pointer to the clock used to generate SPI signals.
184  * @ioclk: Pointer to the i/o clock between host and target
185  * @pdev: Pointer to device's platform device data
186  * @host: Pointer to the SPI Protocol host.
187  * @cntrlr_info: Platform specific data for the controller this driver manages.
188  * @lock: Controller specific lock.
189  * @state: Set of FLAGS to indicate status.
190  * @sfr_start: BUS address of SPI controller regs.
191  * @regs: Pointer to ioremap'ed controller registers.
192  * @xfer_completion: To indicate completion of xfer task.
193  * @cur_mode: Stores the active configuration of the controller.
194  * @cur_bpw: Stores the active bits per word settings.
195  * @cur_speed: Current clock speed
196  * @rx_dma: Local receive DMA data (e.g. chan and direction)
197  * @tx_dma: Local transmit DMA data (e.g. chan and direction)
198  * @port_conf: Local SPI port configuration data
199  * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead.
200  * @fifo_depth: depth of the FIFO.
201  * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's
202  *               length and position.
203  * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's
204  *               length and position.
205  */
206 struct s3c64xx_spi_driver_data {
207 	void __iomem                    *regs;
208 	struct clk                      *clk;
209 	struct clk                      *src_clk;
210 	struct clk                      *ioclk;
211 	struct platform_device          *pdev;
212 	struct spi_controller           *host;
213 	struct s3c64xx_spi_info         *cntrlr_info;
214 	spinlock_t                      lock;
215 	unsigned long                   sfr_start;
216 	struct completion               xfer_completion;
217 	unsigned                        state;
218 	unsigned                        cur_mode, cur_bpw;
219 	unsigned                        cur_speed;
220 	struct s3c64xx_spi_dma_data	rx_dma;
221 	struct s3c64xx_spi_dma_data	tx_dma;
222 	const struct s3c64xx_spi_port_config	*port_conf;
223 	unsigned int			port_id;
224 	unsigned int			fifo_depth;
225 	u32				rx_fifomask;
226 	u32				tx_fifomask;
227 };
228 
s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data * sdd)229 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
230 {
231 	void __iomem *regs = sdd->regs;
232 	unsigned long loops;
233 	u32 val;
234 
235 	writel(0, regs + S3C64XX_SPI_PACKET_CNT);
236 
237 	val = readl(regs + S3C64XX_SPI_CH_CFG);
238 	val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
239 	writel(val, regs + S3C64XX_SPI_CH_CFG);
240 
241 	val = readl(regs + S3C64XX_SPI_CH_CFG);
242 	val |= S3C64XX_SPI_CH_SW_RST;
243 	val &= ~S3C64XX_SPI_CH_HS_EN;
244 	writel(val, regs + S3C64XX_SPI_CH_CFG);
245 
246 	/* Flush TxFIFO*/
247 	loops = msecs_to_loops(1);
248 	do {
249 		val = readl(regs + S3C64XX_SPI_STATUS);
250 	} while (TX_FIFO_LVL(val, sdd) && --loops);
251 
252 	if (loops == 0)
253 		dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
254 
255 	/* Flush RxFIFO*/
256 	loops = msecs_to_loops(1);
257 	do {
258 		val = readl(regs + S3C64XX_SPI_STATUS);
259 		if (RX_FIFO_LVL(val, sdd))
260 			readl(regs + S3C64XX_SPI_RX_DATA);
261 		else
262 			break;
263 	} while (--loops);
264 
265 	if (loops == 0)
266 		dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
267 
268 	val = readl(regs + S3C64XX_SPI_CH_CFG);
269 	val &= ~S3C64XX_SPI_CH_SW_RST;
270 	writel(val, regs + S3C64XX_SPI_CH_CFG);
271 
272 	val = readl(regs + S3C64XX_SPI_MODE_CFG);
273 	val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
274 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
275 }
276 
s3c64xx_spi_dmacb(void * data)277 static void s3c64xx_spi_dmacb(void *data)
278 {
279 	struct s3c64xx_spi_driver_data *sdd;
280 	struct s3c64xx_spi_dma_data *dma = data;
281 	unsigned long flags;
282 
283 	if (dma->direction == DMA_DEV_TO_MEM)
284 		sdd = container_of(data,
285 			struct s3c64xx_spi_driver_data, rx_dma);
286 	else
287 		sdd = container_of(data,
288 			struct s3c64xx_spi_driver_data, tx_dma);
289 
290 	spin_lock_irqsave(&sdd->lock, flags);
291 
292 	if (dma->direction == DMA_DEV_TO_MEM) {
293 		sdd->state &= ~RXBUSY;
294 		if (!(sdd->state & TXBUSY))
295 			complete(&sdd->xfer_completion);
296 	} else {
297 		sdd->state &= ~TXBUSY;
298 		if (!(sdd->state & RXBUSY))
299 			complete(&sdd->xfer_completion);
300 	}
301 
302 	spin_unlock_irqrestore(&sdd->lock, flags);
303 }
304 
s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data * dma,struct sg_table * sgt)305 static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma,
306 			       struct sg_table *sgt)
307 {
308 	struct s3c64xx_spi_driver_data *sdd;
309 	struct dma_slave_config config;
310 	struct dma_async_tx_descriptor *desc;
311 	int ret;
312 
313 	memset(&config, 0, sizeof(config));
314 
315 	if (dma->direction == DMA_DEV_TO_MEM) {
316 		sdd = container_of((void *)dma,
317 			struct s3c64xx_spi_driver_data, rx_dma);
318 		config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
319 		config.src_addr_width = sdd->cur_bpw / 8;
320 		config.src_maxburst = 1;
321 	} else {
322 		sdd = container_of((void *)dma,
323 			struct s3c64xx_spi_driver_data, tx_dma);
324 		config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
325 		config.dst_addr_width = sdd->cur_bpw / 8;
326 		config.dst_maxburst = 1;
327 	}
328 	config.direction = dma->direction;
329 	ret = dmaengine_slave_config(dma->ch, &config);
330 	if (ret)
331 		return ret;
332 
333 	desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
334 				       dma->direction, DMA_PREP_INTERRUPT);
335 	if (!desc) {
336 		dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
337 			dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
338 		return -ENOMEM;
339 	}
340 
341 	desc->callback = s3c64xx_spi_dmacb;
342 	desc->callback_param = dma;
343 
344 	dma->cookie = dmaengine_submit(desc);
345 	ret = dma_submit_error(dma->cookie);
346 	if (ret) {
347 		dev_err(&sdd->pdev->dev, "DMA submission failed");
348 		return ret;
349 	}
350 
351 	dma_async_issue_pending(dma->ch);
352 	return 0;
353 }
354 
s3c64xx_spi_set_cs(struct spi_device * spi,bool enable)355 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
356 {
357 	struct s3c64xx_spi_driver_data *sdd =
358 					spi_controller_get_devdata(spi->controller);
359 
360 	if (sdd->cntrlr_info->no_cs)
361 		return;
362 
363 	if (enable) {
364 		if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
365 			writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
366 		} else {
367 			u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
368 
369 			ssel |= (S3C64XX_SPI_CS_AUTO |
370 						S3C64XX_SPI_CS_NSC_CNT_2);
371 			writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
372 		}
373 	} else {
374 		if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
375 			writel(S3C64XX_SPI_CS_SIG_INACT,
376 			       sdd->regs + S3C64XX_SPI_CS_REG);
377 	}
378 }
379 
s3c64xx_spi_prepare_transfer(struct spi_controller * spi)380 static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi)
381 {
382 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
383 
384 	if (is_polling(sdd))
385 		return 0;
386 
387 	/* Requests DMA channels */
388 	sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx");
389 	if (IS_ERR(sdd->rx_dma.ch)) {
390 		dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n");
391 		sdd->rx_dma.ch = NULL;
392 		return 0;
393 	}
394 
395 	sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx");
396 	if (IS_ERR(sdd->tx_dma.ch)) {
397 		dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n");
398 		dma_release_channel(sdd->rx_dma.ch);
399 		sdd->tx_dma.ch = NULL;
400 		sdd->rx_dma.ch = NULL;
401 		return 0;
402 	}
403 
404 	spi->dma_rx = sdd->rx_dma.ch;
405 	spi->dma_tx = sdd->tx_dma.ch;
406 
407 	return 0;
408 }
409 
s3c64xx_spi_unprepare_transfer(struct spi_controller * spi)410 static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi)
411 {
412 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi);
413 
414 	if (is_polling(sdd))
415 		return 0;
416 
417 	/* Releases DMA channels if they are allocated */
418 	if (sdd->rx_dma.ch && sdd->tx_dma.ch) {
419 		dma_release_channel(sdd->rx_dma.ch);
420 		dma_release_channel(sdd->tx_dma.ch);
421 		sdd->rx_dma.ch = NULL;
422 		sdd->tx_dma.ch = NULL;
423 	}
424 
425 	return 0;
426 }
427 
s3c64xx_spi_can_dma(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)428 static bool s3c64xx_spi_can_dma(struct spi_controller *host,
429 				struct spi_device *spi,
430 				struct spi_transfer *xfer)
431 {
432 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
433 
434 	if (sdd->rx_dma.ch && sdd->tx_dma.ch)
435 		return xfer->len >= sdd->fifo_depth;
436 
437 	return false;
438 }
439 
s3c64xx_iowrite8_32_rep(volatile void __iomem * addr,const void * buffer,unsigned int count)440 static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr,
441 				    const void *buffer, unsigned int count)
442 {
443 	if (count) {
444 		const u8 *buf = buffer;
445 
446 		do {
447 			__raw_writel(*buf++, addr);
448 		} while (--count);
449 	}
450 }
451 
s3c64xx_iowrite16_32_rep(volatile void __iomem * addr,const void * buffer,unsigned int count)452 static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr,
453 				     const void *buffer, unsigned int count)
454 {
455 	if (count) {
456 		const u16 *buf = buffer;
457 
458 		do {
459 			__raw_writel(*buf++, addr);
460 		} while (--count);
461 	}
462 }
463 
s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer)464 static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd,
465 				struct spi_transfer *xfer)
466 {
467 	void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA;
468 	const void *buf = xfer->tx_buf;
469 	unsigned int len = xfer->len;
470 
471 	switch (sdd->cur_bpw) {
472 	case 32:
473 		iowrite32_rep(addr, buf, len / 4);
474 		break;
475 	case 16:
476 		if (sdd->port_conf->use_32bit_io)
477 			s3c64xx_iowrite16_32_rep(addr, buf, len / 2);
478 		else
479 			iowrite16_rep(addr, buf, len / 2);
480 		break;
481 	default:
482 		if (sdd->port_conf->use_32bit_io)
483 			s3c64xx_iowrite8_32_rep(addr, buf, len);
484 		else
485 			iowrite8_rep(addr, buf, len);
486 		break;
487 	}
488 }
489 
s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer,int dma_mode)490 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
491 				    struct spi_transfer *xfer, int dma_mode)
492 {
493 	void __iomem *regs = sdd->regs;
494 	u32 modecfg, chcfg;
495 	int ret = 0;
496 
497 	modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
498 	modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
499 
500 	chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
501 	chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
502 
503 	if (dma_mode) {
504 		chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
505 	} else {
506 		/* Always shift in data in FIFO, even if xfer is Tx only,
507 		 * this helps setting PCKT_CNT value for generating clocks
508 		 * as exactly needed.
509 		 */
510 		chcfg |= S3C64XX_SPI_CH_RXCH_ON;
511 		writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
512 					| S3C64XX_SPI_PACKET_CNT_EN,
513 					regs + S3C64XX_SPI_PACKET_CNT);
514 	}
515 
516 	if (xfer->tx_buf != NULL) {
517 		sdd->state |= TXBUSY;
518 		chcfg |= S3C64XX_SPI_CH_TXCH_ON;
519 		if (dma_mode) {
520 			modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
521 			ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
522 		} else {
523 			s3c64xx_iowrite_rep(sdd, xfer);
524 		}
525 	}
526 
527 	if (xfer->rx_buf != NULL) {
528 		sdd->state |= RXBUSY;
529 
530 		if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
531 					&& !(sdd->cur_mode & SPI_CPHA))
532 			chcfg |= S3C64XX_SPI_CH_HS_EN;
533 
534 		if (dma_mode) {
535 			modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
536 			chcfg |= S3C64XX_SPI_CH_RXCH_ON;
537 			writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
538 					| S3C64XX_SPI_PACKET_CNT_EN,
539 					regs + S3C64XX_SPI_PACKET_CNT);
540 			ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
541 		}
542 	}
543 
544 	if (ret)
545 		return ret;
546 
547 	writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
548 	writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
549 
550 	return 0;
551 }
552 
s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data * sdd,int timeout_ms)553 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
554 					int timeout_ms)
555 {
556 	void __iomem *regs = sdd->regs;
557 	unsigned long val = 1;
558 	u32 status;
559 	u32 max_fifo = sdd->fifo_depth;
560 
561 	if (timeout_ms)
562 		val = msecs_to_loops(timeout_ms);
563 
564 	do {
565 		status = readl(regs + S3C64XX_SPI_STATUS);
566 	} while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
567 
568 	/* return the actual received data length */
569 	return RX_FIFO_LVL(status, sdd);
570 }
571 
s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer)572 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
573 				struct spi_transfer *xfer)
574 {
575 	void __iomem *regs = sdd->regs;
576 	unsigned long val;
577 	u32 status;
578 	int ms;
579 
580 	/* millisecs to xfer 'len' bytes @ 'cur_speed' */
581 	ms = xfer->len * 8 * 1000 / sdd->cur_speed;
582 	ms += 30;               /* some tolerance */
583 	ms = max(ms, 100);      /* minimum timeout */
584 
585 	val = msecs_to_jiffies(ms) + 10;
586 	val = wait_for_completion_timeout(&sdd->xfer_completion, val);
587 
588 	/*
589 	 * If the previous xfer was completed within timeout, then
590 	 * proceed further else return -ETIMEDOUT.
591 	 * DmaTx returns after simply writing data in the FIFO,
592 	 * w/o waiting for real transmission on the bus to finish.
593 	 * DmaRx returns only after Dma read data from FIFO which
594 	 * needs bus transmission to finish, so we don't worry if
595 	 * Xfer involved Rx(with or without Tx).
596 	 */
597 	if (val && !xfer->rx_buf) {
598 		val = msecs_to_loops(10);
599 		status = readl(regs + S3C64XX_SPI_STATUS);
600 		while ((TX_FIFO_LVL(status, sdd)
601 			|| !S3C64XX_SPI_ST_TX_DONE(status, sdd))
602 		       && --val) {
603 			cpu_relax();
604 			status = readl(regs + S3C64XX_SPI_STATUS);
605 		}
606 
607 	}
608 
609 	/* If timed out while checking rx/tx status return error */
610 	if (!val)
611 		return -ETIMEDOUT;
612 
613 	return 0;
614 }
615 
s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer,bool use_irq)616 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
617 				struct spi_transfer *xfer, bool use_irq)
618 {
619 	void __iomem *regs = sdd->regs;
620 	unsigned long val;
621 	u32 status;
622 	int loops;
623 	u32 cpy_len;
624 	u8 *buf;
625 	int ms;
626 	unsigned long time_us;
627 
628 	/* microsecs to xfer 'len' bytes @ 'cur_speed' */
629 	time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed;
630 	ms = (time_us / 1000);
631 	ms += 10; /* some tolerance */
632 
633 	/* sleep during signal transfer time */
634 	status = readl(regs + S3C64XX_SPI_STATUS);
635 	if (RX_FIFO_LVL(status, sdd) < xfer->len)
636 		usleep_range(time_us / 2, time_us);
637 
638 	if (use_irq) {
639 		val = msecs_to_jiffies(ms);
640 		if (!wait_for_completion_timeout(&sdd->xfer_completion, val))
641 			return -ETIMEDOUT;
642 	}
643 
644 	val = msecs_to_loops(ms);
645 	do {
646 		status = readl(regs + S3C64XX_SPI_STATUS);
647 	} while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
648 
649 	if (!val)
650 		return -EIO;
651 
652 	/* If it was only Tx */
653 	if (!xfer->rx_buf) {
654 		sdd->state &= ~TXBUSY;
655 		return 0;
656 	}
657 
658 	/*
659 	 * If the receive length is bigger than the controller fifo
660 	 * size, calculate the loops and read the fifo as many times.
661 	 * loops = length / max fifo size (calculated by using the
662 	 * fifo mask).
663 	 * For any size less than the fifo size the below code is
664 	 * executed atleast once.
665 	 */
666 	loops = xfer->len / sdd->fifo_depth;
667 	buf = xfer->rx_buf;
668 	do {
669 		/* wait for data to be received in the fifo */
670 		cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
671 						       (loops ? ms : 0));
672 
673 		switch (sdd->cur_bpw) {
674 		case 32:
675 			ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
676 				     buf, cpy_len / 4);
677 			break;
678 		case 16:
679 			ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
680 				     buf, cpy_len / 2);
681 			break;
682 		default:
683 			ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
684 				    buf, cpy_len);
685 			break;
686 		}
687 
688 		buf = buf + cpy_len;
689 	} while (loops--);
690 	sdd->state &= ~RXBUSY;
691 
692 	return 0;
693 }
694 
s3c64xx_spi_config(struct s3c64xx_spi_driver_data * sdd)695 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
696 {
697 	void __iomem *regs = sdd->regs;
698 	int ret;
699 	u32 val;
700 	int div = sdd->port_conf->clk_div;
701 
702 	/* Disable Clock */
703 	if (!sdd->port_conf->clk_from_cmu) {
704 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
705 		val &= ~S3C64XX_SPI_ENCLK_ENABLE;
706 		writel(val, regs + S3C64XX_SPI_CLK_CFG);
707 	}
708 
709 	/* Set Polarity and Phase */
710 	val = readl(regs + S3C64XX_SPI_CH_CFG);
711 	val &= ~(S3C64XX_SPI_CH_SLAVE |
712 			S3C64XX_SPI_CPOL_L |
713 			S3C64XX_SPI_CPHA_B);
714 
715 	if (sdd->cur_mode & SPI_CPOL)
716 		val |= S3C64XX_SPI_CPOL_L;
717 
718 	if (sdd->cur_mode & SPI_CPHA)
719 		val |= S3C64XX_SPI_CPHA_B;
720 
721 	writel(val, regs + S3C64XX_SPI_CH_CFG);
722 
723 	/* Set Channel & DMA Mode */
724 	val = readl(regs + S3C64XX_SPI_MODE_CFG);
725 	val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
726 			| S3C64XX_SPI_MODE_CH_TSZ_MASK);
727 
728 	switch (sdd->cur_bpw) {
729 	case 32:
730 		val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
731 		val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
732 		break;
733 	case 16:
734 		val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
735 		val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
736 		break;
737 	default:
738 		val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
739 		val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
740 		break;
741 	}
742 
743 	if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback)
744 		val |= S3C64XX_SPI_MODE_SELF_LOOPBACK;
745 	else
746 		val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK;
747 
748 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
749 
750 	if (sdd->port_conf->clk_from_cmu) {
751 		ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div);
752 		if (ret)
753 			return ret;
754 		sdd->cur_speed = clk_get_rate(sdd->src_clk) / div;
755 	} else {
756 		/* Configure Clock */
757 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
758 		val &= ~S3C64XX_SPI_PSR_MASK;
759 		val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1)
760 				& S3C64XX_SPI_PSR_MASK);
761 		writel(val, regs + S3C64XX_SPI_CLK_CFG);
762 
763 		/* Enable Clock */
764 		val = readl(regs + S3C64XX_SPI_CLK_CFG);
765 		val |= S3C64XX_SPI_ENCLK_ENABLE;
766 		writel(val, regs + S3C64XX_SPI_CLK_CFG);
767 	}
768 
769 	return 0;
770 }
771 
772 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
773 
s3c64xx_spi_prepare_message(struct spi_controller * host,struct spi_message * msg)774 static int s3c64xx_spi_prepare_message(struct spi_controller *host,
775 				       struct spi_message *msg)
776 {
777 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
778 	struct spi_device *spi = msg->spi;
779 	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
780 
781 	/* Configure feedback delay */
782 	if (!cs)
783 		/* No delay if not defined */
784 		writel(0, sdd->regs + S3C64XX_SPI_FB_CLK);
785 	else
786 		writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
787 
788 	return 0;
789 }
790 
s3c64xx_spi_max_transfer_size(struct spi_device * spi)791 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
792 {
793 	struct spi_controller *ctlr = spi->controller;
794 
795 	return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
796 }
797 
s3c64xx_spi_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)798 static int s3c64xx_spi_transfer_one(struct spi_controller *host,
799 				    struct spi_device *spi,
800 				    struct spi_transfer *xfer)
801 {
802 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
803 	const unsigned int fifo_len = sdd->fifo_depth;
804 	const void *tx_buf = NULL;
805 	void *rx_buf = NULL;
806 	int target_len = 0, origin_len = 0;
807 	int use_dma = 0;
808 	bool use_irq = false;
809 	int status;
810 	u32 speed;
811 	u8 bpw;
812 	unsigned long flags;
813 	u32 rdy_lv;
814 	u32 val;
815 
816 	reinit_completion(&sdd->xfer_completion);
817 
818 	/* Only BPW and Speed may change across transfers */
819 	bpw = xfer->bits_per_word;
820 	speed = xfer->speed_hz;
821 
822 	if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
823 		sdd->cur_bpw = bpw;
824 		sdd->cur_speed = speed;
825 		sdd->cur_mode = spi->mode;
826 		status = s3c64xx_spi_config(sdd);
827 		if (status)
828 			return status;
829 	}
830 
831 	if (!is_polling(sdd) && xfer->len >= fifo_len &&
832 	    sdd->rx_dma.ch && sdd->tx_dma.ch) {
833 		use_dma = 1;
834 	} else if (xfer->len >= fifo_len) {
835 		tx_buf = xfer->tx_buf;
836 		rx_buf = xfer->rx_buf;
837 		origin_len = xfer->len;
838 		target_len = xfer->len;
839 		xfer->len = fifo_len - 1;
840 	}
841 
842 	do {
843 		/* transfer size is greater than 32, change to IRQ mode */
844 		if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE)
845 			use_irq = true;
846 
847 		if (use_irq) {
848 			reinit_completion(&sdd->xfer_completion);
849 
850 			rdy_lv = xfer->len;
851 			/* Setup RDY_FIFO trigger Level
852 			 * RDY_LVL =
853 			 * fifo_lvl up to 64 byte -> N bytes
854 			 *               128 byte -> RDY_LVL * 2 bytes
855 			 *               256 byte -> RDY_LVL * 4 bytes
856 			 */
857 			if (fifo_len == 128)
858 				rdy_lv /= 2;
859 			else if (fifo_len == 256)
860 				rdy_lv /= 4;
861 
862 			val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG);
863 			val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL;
864 			val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT);
865 			writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG);
866 
867 			/* Enable FIFO_RDY_EN IRQ */
868 			val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
869 			writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN),
870 					sdd->regs + S3C64XX_SPI_INT_EN);
871 
872 		}
873 
874 		spin_lock_irqsave(&sdd->lock, flags);
875 
876 		/* Pending only which is to be done */
877 		sdd->state &= ~RXBUSY;
878 		sdd->state &= ~TXBUSY;
879 
880 		/* Start the signals */
881 		s3c64xx_spi_set_cs(spi, true);
882 
883 		status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
884 
885 		spin_unlock_irqrestore(&sdd->lock, flags);
886 
887 		if (status) {
888 			dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
889 			break;
890 		}
891 
892 		if (use_dma)
893 			status = s3c64xx_wait_for_dma(sdd, xfer);
894 		else
895 			status = s3c64xx_wait_for_pio(sdd, xfer, use_irq);
896 
897 		if (status) {
898 			dev_err(&spi->dev,
899 				"I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
900 				xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
901 				(sdd->state & RXBUSY) ? 'f' : 'p',
902 				(sdd->state & TXBUSY) ? 'f' : 'p',
903 				xfer->len, use_dma ? 1 : 0, status);
904 
905 			if (use_dma) {
906 				struct dma_tx_state s;
907 
908 				if (xfer->tx_buf && (sdd->state & TXBUSY)) {
909 					dmaengine_pause(sdd->tx_dma.ch);
910 					dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
911 					dmaengine_terminate_all(sdd->tx_dma.ch);
912 					dev_err(&spi->dev, "TX residue: %d\n", s.residue);
913 
914 				}
915 				if (xfer->rx_buf && (sdd->state & RXBUSY)) {
916 					dmaengine_pause(sdd->rx_dma.ch);
917 					dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
918 					dmaengine_terminate_all(sdd->rx_dma.ch);
919 					dev_err(&spi->dev, "RX residue: %d\n", s.residue);
920 				}
921 			}
922 		} else {
923 			s3c64xx_flush_fifo(sdd);
924 		}
925 		if (target_len > 0) {
926 			target_len -= xfer->len;
927 
928 			if (xfer->tx_buf)
929 				xfer->tx_buf += xfer->len;
930 
931 			if (xfer->rx_buf)
932 				xfer->rx_buf += xfer->len;
933 
934 			if (target_len >= fifo_len)
935 				xfer->len = fifo_len - 1;
936 			else
937 				xfer->len = target_len;
938 		}
939 	} while (target_len > 0);
940 
941 	if (origin_len) {
942 		/* Restore original xfer buffers and length */
943 		xfer->tx_buf = tx_buf;
944 		xfer->rx_buf = rx_buf;
945 		xfer->len = origin_len;
946 	}
947 
948 	return status;
949 }
950 
s3c64xx_get_target_ctrldata(struct spi_device * spi)951 static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata(
952 				struct spi_device *spi)
953 {
954 	struct s3c64xx_spi_csinfo *cs;
955 	struct device_node *target_np;
956 	u32 fb_delay = 0;
957 
958 	target_np = spi->dev.of_node;
959 	if (!target_np) {
960 		dev_err(&spi->dev, "device node not found\n");
961 		return ERR_PTR(-EINVAL);
962 	}
963 
964 	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
965 	if (!cs)
966 		return ERR_PTR(-ENOMEM);
967 
968 	struct device_node *data_np __free(device_node) =
969 			of_get_child_by_name(target_np, "controller-data");
970 	if (!data_np) {
971 		dev_info(&spi->dev, "feedback delay set to default (0)\n");
972 		return cs;
973 	}
974 
975 	of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
976 	cs->fb_delay = fb_delay;
977 	return cs;
978 }
979 
980 /*
981  * Here we only check the validity of requested configuration
982  * and save the configuration in a local data-structure.
983  * The controller is actually configured only just before we
984  * get a message to transfer.
985  */
s3c64xx_spi_setup(struct spi_device * spi)986 static int s3c64xx_spi_setup(struct spi_device *spi)
987 {
988 	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
989 	struct s3c64xx_spi_driver_data *sdd;
990 	int err;
991 	int div;
992 
993 	sdd = spi_controller_get_devdata(spi->controller);
994 	if (spi->dev.of_node) {
995 		cs = s3c64xx_get_target_ctrldata(spi);
996 		spi->controller_data = cs;
997 	}
998 
999 	/* NULL is fine, we just avoid using the FB delay (=0) */
1000 	if (IS_ERR(cs)) {
1001 		dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0));
1002 		return -ENODEV;
1003 	}
1004 
1005 	if (!spi_get_ctldata(spi))
1006 		spi_set_ctldata(spi, cs);
1007 
1008 	pm_runtime_get_sync(&sdd->pdev->dev);
1009 
1010 	div = sdd->port_conf->clk_div;
1011 
1012 	/* Check if we can provide the requested rate */
1013 	if (!sdd->port_conf->clk_from_cmu) {
1014 		u32 psr, speed;
1015 
1016 		/* Max possible */
1017 		speed = clk_get_rate(sdd->src_clk) / div / (0 + 1);
1018 
1019 		if (spi->max_speed_hz > speed)
1020 			spi->max_speed_hz = speed;
1021 
1022 		psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;
1023 		psr &= S3C64XX_SPI_PSR_MASK;
1024 		if (psr == S3C64XX_SPI_PSR_MASK)
1025 			psr--;
1026 
1027 		speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
1028 		if (spi->max_speed_hz < speed) {
1029 			if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1030 				psr++;
1031 			} else {
1032 				err = -EINVAL;
1033 				goto setup_exit;
1034 			}
1035 		}
1036 
1037 		speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);
1038 		if (spi->max_speed_hz >= speed) {
1039 			spi->max_speed_hz = speed;
1040 		} else {
1041 			dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1042 				spi->max_speed_hz);
1043 			err = -EINVAL;
1044 			goto setup_exit;
1045 		}
1046 	}
1047 
1048 	pm_runtime_mark_last_busy(&sdd->pdev->dev);
1049 	pm_runtime_put_autosuspend(&sdd->pdev->dev);
1050 	s3c64xx_spi_set_cs(spi, false);
1051 
1052 	return 0;
1053 
1054 setup_exit:
1055 	pm_runtime_mark_last_busy(&sdd->pdev->dev);
1056 	pm_runtime_put_autosuspend(&sdd->pdev->dev);
1057 	/* setup() returns with device de-selected */
1058 	s3c64xx_spi_set_cs(spi, false);
1059 
1060 	spi_set_ctldata(spi, NULL);
1061 
1062 	/* This was dynamically allocated on the DT path */
1063 	if (spi->dev.of_node)
1064 		kfree(cs);
1065 
1066 	return err;
1067 }
1068 
s3c64xx_spi_cleanup(struct spi_device * spi)1069 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1070 {
1071 	struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1072 
1073 	/* This was dynamically allocated on the DT path */
1074 	if (spi->dev.of_node)
1075 		kfree(cs);
1076 
1077 	spi_set_ctldata(spi, NULL);
1078 }
1079 
s3c64xx_spi_irq(int irq,void * data)1080 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1081 {
1082 	struct s3c64xx_spi_driver_data *sdd = data;
1083 	struct spi_controller *spi = sdd->host;
1084 	unsigned int val, clr = 0;
1085 
1086 	val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1087 
1088 	if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1089 		clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1090 		dev_err(&spi->dev, "RX overrun\n");
1091 	}
1092 	if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1093 		clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1094 		dev_err(&spi->dev, "RX underrun\n");
1095 	}
1096 	if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1097 		clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1098 		dev_err(&spi->dev, "TX overrun\n");
1099 	}
1100 	if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1101 		clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1102 		dev_err(&spi->dev, "TX underrun\n");
1103 	}
1104 
1105 	if (val & S3C64XX_SPI_ST_RX_FIFORDY) {
1106 		complete(&sdd->xfer_completion);
1107 		/* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */
1108 		val = readl(sdd->regs + S3C64XX_SPI_INT_EN);
1109 		writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN),
1110 				sdd->regs + S3C64XX_SPI_INT_EN);
1111 	}
1112 
1113 	/* Clear the pending irq by setting and then clearing it */
1114 	writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1115 	writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1116 
1117 	return IRQ_HANDLED;
1118 }
1119 
s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data * sdd)1120 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
1121 {
1122 	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1123 	void __iomem *regs = sdd->regs;
1124 	unsigned int val;
1125 
1126 	sdd->cur_speed = 0;
1127 
1128 	if (sci->no_cs)
1129 		writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
1130 	else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
1131 		writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
1132 
1133 	/* Disable Interrupts - we use Polling if not DMA mode */
1134 	writel(0, regs + S3C64XX_SPI_INT_EN);
1135 
1136 	if (!sdd->port_conf->clk_from_cmu)
1137 		writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1138 				regs + S3C64XX_SPI_CLK_CFG);
1139 	writel(0, regs + S3C64XX_SPI_MODE_CFG);
1140 	writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1141 
1142 	/* Clear any irq pending bits, should set and clear the bits */
1143 	val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1144 		S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1145 		S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1146 		S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1147 	writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1148 	writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1149 
1150 	writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1151 
1152 	val = readl(regs + S3C64XX_SPI_MODE_CFG);
1153 	val &= ~S3C64XX_SPI_MODE_4BURST;
1154 	val |= (S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1155 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
1156 
1157 	s3c64xx_flush_fifo(sdd);
1158 }
1159 
1160 #ifdef CONFIG_OF
s3c64xx_spi_parse_dt(struct device * dev)1161 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1162 {
1163 	struct s3c64xx_spi_info *sci;
1164 	u32 temp;
1165 
1166 	sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1167 	if (!sci)
1168 		return ERR_PTR(-ENOMEM);
1169 
1170 	if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1171 		dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1172 		sci->src_clk_nr = 0;
1173 	} else {
1174 		sci->src_clk_nr = temp;
1175 	}
1176 
1177 	if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1178 		dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1179 		sci->num_cs = 1;
1180 	} else {
1181 		sci->num_cs = temp;
1182 	}
1183 
1184 	sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1185 	sci->polling = !of_property_present(dev->of_node, "dmas");
1186 
1187 	return sci;
1188 }
1189 #else
s3c64xx_spi_parse_dt(struct device * dev)1190 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1191 {
1192 	return dev_get_platdata(dev);
1193 }
1194 #endif
1195 
s3c64xx_spi_get_port_config(struct platform_device * pdev)1196 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1197 						struct platform_device *pdev)
1198 {
1199 #ifdef CONFIG_OF
1200 	if (pdev->dev.of_node)
1201 		return of_device_get_match_data(&pdev->dev);
1202 #endif
1203 	return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1204 }
1205 
s3c64xx_spi_set_port_id(struct platform_device * pdev,struct s3c64xx_spi_driver_data * sdd)1206 static int s3c64xx_spi_set_port_id(struct platform_device *pdev,
1207 				   struct s3c64xx_spi_driver_data *sdd)
1208 {
1209 	const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf;
1210 	int ret;
1211 
1212 	if (port_conf->rx_fifomask && port_conf->tx_fifomask)
1213 		return 0;
1214 
1215 	if (pdev->dev.of_node) {
1216 		ret = of_alias_get_id(pdev->dev.of_node, "spi");
1217 		if (ret < 0)
1218 			return dev_err_probe(&pdev->dev, ret,
1219 					     "Failed to get alias id\n");
1220 		sdd->port_id = ret;
1221 	} else {
1222 		if (pdev->id < 0)
1223 			return dev_err_probe(&pdev->dev, -EINVAL,
1224 					     "Negative platform ID is not allowed\n");
1225 		sdd->port_id = pdev->id;
1226 	}
1227 
1228 	return 0;
1229 }
1230 
s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data * sdd)1231 static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd)
1232 {
1233 	const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf;
1234 
1235 	if (port_conf->rx_fifomask)
1236 		sdd->rx_fifomask = port_conf->rx_fifomask;
1237 	else
1238 		sdd->rx_fifomask = FIFO_LVL_MASK(sdd) <<
1239 			port_conf->rx_lvl_offset;
1240 
1241 	if (port_conf->tx_fifomask)
1242 		sdd->tx_fifomask = port_conf->tx_fifomask;
1243 	else
1244 		sdd->tx_fifomask = FIFO_LVL_MASK(sdd) <<
1245 			S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT;
1246 }
1247 
s3c64xx_spi_probe(struct platform_device * pdev)1248 static int s3c64xx_spi_probe(struct platform_device *pdev)
1249 {
1250 	struct resource	*mem_res;
1251 	struct s3c64xx_spi_driver_data *sdd;
1252 	struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1253 	struct spi_controller *host;
1254 	int ret, irq;
1255 	char clk_name[16];
1256 
1257 	if (!sci && pdev->dev.of_node) {
1258 		sci = s3c64xx_spi_parse_dt(&pdev->dev);
1259 		if (IS_ERR(sci))
1260 			return PTR_ERR(sci);
1261 	}
1262 
1263 	if (!sci)
1264 		return dev_err_probe(&pdev->dev, -ENODEV,
1265 				     "Platform_data missing!\n");
1266 
1267 	irq = platform_get_irq(pdev, 0);
1268 	if (irq < 0)
1269 		return irq;
1270 
1271 	host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd));
1272 	if (!host)
1273 		return dev_err_probe(&pdev->dev, -ENOMEM,
1274 				     "Unable to allocate SPI Host\n");
1275 
1276 	platform_set_drvdata(pdev, host);
1277 
1278 	sdd = spi_controller_get_devdata(host);
1279 	sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1280 	sdd->host = host;
1281 	sdd->cntrlr_info = sci;
1282 	sdd->pdev = pdev;
1283 
1284 	ret = s3c64xx_spi_set_port_id(pdev, sdd);
1285 	if (ret)
1286 		return ret;
1287 
1288 	if (sdd->port_conf->fifo_depth)
1289 		sdd->fifo_depth = sdd->port_conf->fifo_depth;
1290 	else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth",
1291 				      &sdd->fifo_depth))
1292 		sdd->fifo_depth = FIFO_DEPTH(sdd);
1293 
1294 	s3c64xx_spi_set_fifomask(sdd);
1295 
1296 	sdd->cur_bpw = 8;
1297 
1298 	sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1299 	sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1300 
1301 	host->dev.of_node = pdev->dev.of_node;
1302 	host->bus_num = -1;
1303 	host->setup = s3c64xx_spi_setup;
1304 	host->cleanup = s3c64xx_spi_cleanup;
1305 	host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1306 	host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1307 	host->prepare_message = s3c64xx_spi_prepare_message;
1308 	host->transfer_one = s3c64xx_spi_transfer_one;
1309 	host->max_transfer_size = s3c64xx_spi_max_transfer_size;
1310 	host->num_chipselect = sci->num_cs;
1311 	host->use_gpio_descriptors = true;
1312 	host->dma_alignment = 8;
1313 	host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1314 				   SPI_BPW_MASK(8);
1315 	/* the spi->mode bits understood by this driver: */
1316 	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1317 	if (sdd->port_conf->has_loopback)
1318 		host->mode_bits |= SPI_LOOP;
1319 	host->auto_runtime_pm = true;
1320 	if (!is_polling(sdd))
1321 		host->can_dma = s3c64xx_spi_can_dma;
1322 
1323 	sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res);
1324 	if (IS_ERR(sdd->regs))
1325 		return PTR_ERR(sdd->regs);
1326 	sdd->sfr_start = mem_res->start;
1327 
1328 	if (sci->cfg_gpio && sci->cfg_gpio())
1329 		return dev_err_probe(&pdev->dev, -EBUSY,
1330 				     "Unable to config gpio\n");
1331 
1332 	/* Setup clocks */
1333 	sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi");
1334 	if (IS_ERR(sdd->clk))
1335 		return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk),
1336 				     "Unable to acquire clock 'spi'\n");
1337 
1338 	sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1339 	sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name);
1340 	if (IS_ERR(sdd->src_clk))
1341 		return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk),
1342 				     "Unable to acquire clock '%s'\n",
1343 				     clk_name);
1344 
1345 	if (sdd->port_conf->clk_ioclk) {
1346 		sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk");
1347 		if (IS_ERR(sdd->ioclk))
1348 			return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk),
1349 					     "Unable to acquire 'ioclk'\n");
1350 	}
1351 
1352 	pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1353 	pm_runtime_use_autosuspend(&pdev->dev);
1354 	pm_runtime_set_active(&pdev->dev);
1355 	pm_runtime_enable(&pdev->dev);
1356 	pm_runtime_get_sync(&pdev->dev);
1357 
1358 	/* Setup Default Mode */
1359 	s3c64xx_spi_hwinit(sdd);
1360 
1361 	spin_lock_init(&sdd->lock);
1362 	init_completion(&sdd->xfer_completion);
1363 
1364 	ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1365 				"spi-s3c64xx", sdd);
1366 	if (ret != 0) {
1367 		dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1368 			irq, ret);
1369 		goto err_pm_put;
1370 	}
1371 
1372 	writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1373 	       S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1374 	       sdd->regs + S3C64XX_SPI_INT_EN);
1375 
1376 	ret = devm_spi_register_controller(&pdev->dev, host);
1377 	if (ret != 0) {
1378 		dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret);
1379 		goto err_pm_put;
1380 	}
1381 
1382 	dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n",
1383 		host->bus_num, host->num_chipselect);
1384 	dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1385 		mem_res, sdd->fifo_depth);
1386 
1387 	pm_runtime_mark_last_busy(&pdev->dev);
1388 	pm_runtime_put_autosuspend(&pdev->dev);
1389 
1390 	return 0;
1391 
1392 err_pm_put:
1393 	pm_runtime_put_noidle(&pdev->dev);
1394 	pm_runtime_disable(&pdev->dev);
1395 	pm_runtime_set_suspended(&pdev->dev);
1396 
1397 	return ret;
1398 }
1399 
s3c64xx_spi_remove(struct platform_device * pdev)1400 static void s3c64xx_spi_remove(struct platform_device *pdev)
1401 {
1402 	struct spi_controller *host = platform_get_drvdata(pdev);
1403 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1404 
1405 	pm_runtime_get_sync(&pdev->dev);
1406 
1407 	writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1408 
1409 	if (!is_polling(sdd)) {
1410 		dma_release_channel(sdd->rx_dma.ch);
1411 		dma_release_channel(sdd->tx_dma.ch);
1412 	}
1413 
1414 	pm_runtime_put_noidle(&pdev->dev);
1415 	pm_runtime_disable(&pdev->dev);
1416 	pm_runtime_set_suspended(&pdev->dev);
1417 }
1418 
1419 #ifdef CONFIG_PM_SLEEP
s3c64xx_spi_suspend(struct device * dev)1420 static int s3c64xx_spi_suspend(struct device *dev)
1421 {
1422 	struct spi_controller *host = dev_get_drvdata(dev);
1423 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1424 	int ret;
1425 
1426 	ret = spi_controller_suspend(host);
1427 	if (ret)
1428 		return ret;
1429 
1430 	ret = pm_runtime_force_suspend(dev);
1431 	if (ret < 0)
1432 		return ret;
1433 
1434 	sdd->cur_speed = 0; /* Output Clock is stopped */
1435 
1436 	return 0;
1437 }
1438 
s3c64xx_spi_resume(struct device * dev)1439 static int s3c64xx_spi_resume(struct device *dev)
1440 {
1441 	struct spi_controller *host = dev_get_drvdata(dev);
1442 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1443 	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1444 	int ret;
1445 
1446 	if (sci->cfg_gpio)
1447 		sci->cfg_gpio();
1448 
1449 	ret = pm_runtime_force_resume(dev);
1450 	if (ret < 0)
1451 		return ret;
1452 
1453 	return spi_controller_resume(host);
1454 }
1455 #endif /* CONFIG_PM_SLEEP */
1456 
1457 #ifdef CONFIG_PM
s3c64xx_spi_runtime_suspend(struct device * dev)1458 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1459 {
1460 	struct spi_controller *host = dev_get_drvdata(dev);
1461 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1462 
1463 	clk_disable_unprepare(sdd->clk);
1464 	clk_disable_unprepare(sdd->src_clk);
1465 	clk_disable_unprepare(sdd->ioclk);
1466 
1467 	return 0;
1468 }
1469 
s3c64xx_spi_runtime_resume(struct device * dev)1470 static int s3c64xx_spi_runtime_resume(struct device *dev)
1471 {
1472 	struct spi_controller *host = dev_get_drvdata(dev);
1473 	struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host);
1474 	int ret;
1475 
1476 	if (sdd->port_conf->clk_ioclk) {
1477 		ret = clk_prepare_enable(sdd->ioclk);
1478 		if (ret != 0)
1479 			return ret;
1480 	}
1481 
1482 	ret = clk_prepare_enable(sdd->src_clk);
1483 	if (ret != 0)
1484 		goto err_disable_ioclk;
1485 
1486 	ret = clk_prepare_enable(sdd->clk);
1487 	if (ret != 0)
1488 		goto err_disable_src_clk;
1489 
1490 	s3c64xx_spi_hwinit(sdd);
1491 
1492 	writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1493 	       S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1494 	       sdd->regs + S3C64XX_SPI_INT_EN);
1495 
1496 	return 0;
1497 
1498 err_disable_src_clk:
1499 	clk_disable_unprepare(sdd->src_clk);
1500 err_disable_ioclk:
1501 	clk_disable_unprepare(sdd->ioclk);
1502 
1503 	return ret;
1504 }
1505 #endif /* CONFIG_PM */
1506 
1507 static const struct dev_pm_ops s3c64xx_spi_pm = {
1508 	SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1509 	SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1510 			   s3c64xx_spi_runtime_resume, NULL)
1511 };
1512 
1513 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1514 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1515 	.fifo_lvl_mask	= { 0x7f },
1516 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1517 	.rx_lvl_offset	= 13,
1518 	.tx_st_done	= 21,
1519 	.clk_div	= 2,
1520 	.high_speed	= true,
1521 };
1522 
1523 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1524 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1525 	.fifo_lvl_mask	= { 0x7f, 0x7F },
1526 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1527 	.rx_lvl_offset	= 13,
1528 	.tx_st_done	= 21,
1529 	.clk_div	= 2,
1530 };
1531 
1532 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1533 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1534 	.fifo_lvl_mask	= { 0x1ff, 0x7F },
1535 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1536 	.rx_lvl_offset	= 15,
1537 	.tx_st_done	= 25,
1538 	.clk_div	= 2,
1539 	.high_speed	= true,
1540 };
1541 
1542 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1543 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1544 	.fifo_lvl_mask	= { 0x1ff, 0x7F, 0x7F },
1545 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1546 	.rx_lvl_offset	= 15,
1547 	.tx_st_done	= 25,
1548 	.clk_div	= 2,
1549 	.high_speed	= true,
1550 	.clk_from_cmu	= true,
1551 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1552 };
1553 
1554 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1555 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1556 	.fifo_lvl_mask	= { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1557 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1558 	.rx_lvl_offset	= 15,
1559 	.tx_st_done	= 25,
1560 	.clk_div	= 2,
1561 	.high_speed	= true,
1562 	.clk_from_cmu	= true,
1563 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1564 };
1565 
1566 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1567 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1568 	.fifo_lvl_mask	= { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1569 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1570 	.rx_lvl_offset	= 15,
1571 	.tx_st_done	= 25,
1572 	.clk_div	= 2,
1573 	.high_speed	= true,
1574 	.clk_from_cmu	= true,
1575 	.clk_ioclk	= true,
1576 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1577 };
1578 
1579 static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
1580 	.fifo_depth	= 64,
1581 	.rx_fifomask	= S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
1582 	.tx_fifomask	= S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
1583 	.tx_st_done	= 25,
1584 	.clk_div	= 4,
1585 	.high_speed	= true,
1586 	.clk_from_cmu	= true,
1587 	.has_loopback	= true,
1588 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1589 };
1590 
1591 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
1592 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1593 	.fifo_lvl_mask	= { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
1594 			    0x7f, 0x7f, 0x7f, 0x7f},
1595 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1596 	.rx_lvl_offset	= 15,
1597 	.tx_st_done	= 25,
1598 	.clk_div	= 4,
1599 	.high_speed	= true,
1600 	.clk_from_cmu	= true,
1601 	.clk_ioclk	= true,
1602 	.has_loopback	= true,
1603 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1604 };
1605 
1606 static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
1607 	/* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
1608 	.fifo_lvl_mask	= { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
1609 	/* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
1610 	.rx_lvl_offset	= 15,
1611 	.tx_st_done	= 25,
1612 	.clk_div	= 2,
1613 	.high_speed	= true,
1614 	.clk_from_cmu	= true,
1615 	.clk_ioclk	= false,
1616 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1617 };
1618 
1619 static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
1620 	.fifo_depth	= 64,
1621 	.rx_fifomask	= S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
1622 	.tx_fifomask	= S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
1623 	.tx_st_done	= 25,
1624 	.clk_div	= 4,
1625 	.high_speed	= true,
1626 	.clk_from_cmu	= true,
1627 	.has_loopback	= true,
1628 	.use_32bit_io	= true,
1629 	.quirks		= S3C64XX_SPI_QUIRK_CS_AUTO,
1630 };
1631 
1632 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1633 	{
1634 		.name		= "s3c2443-spi",
1635 		.driver_data	= (kernel_ulong_t)&s3c2443_spi_port_config,
1636 	}, {
1637 		.name		= "s3c6410-spi",
1638 		.driver_data	= (kernel_ulong_t)&s3c6410_spi_port_config,
1639 	},
1640 	{ },
1641 };
1642 MODULE_DEVICE_TABLE(platform, s3c64xx_spi_driver_ids);
1643 
1644 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1645 	{ .compatible = "google,gs101-spi",
1646 			.data = &gs101_spi_port_config,
1647 	},
1648 	{ .compatible = "samsung,s3c2443-spi",
1649 			.data = &s3c2443_spi_port_config,
1650 	},
1651 	{ .compatible = "samsung,s3c6410-spi",
1652 			.data = &s3c6410_spi_port_config,
1653 	},
1654 	{ .compatible = "samsung,s5pv210-spi",
1655 			.data = &s5pv210_spi_port_config,
1656 	},
1657 	{ .compatible = "samsung,exynos4210-spi",
1658 			.data = &exynos4_spi_port_config,
1659 	},
1660 	{ .compatible = "samsung,exynos7-spi",
1661 			.data = &exynos7_spi_port_config,
1662 	},
1663 	{ .compatible = "samsung,exynos5433-spi",
1664 			.data = &exynos5433_spi_port_config,
1665 	},
1666 	{ .compatible = "samsung,exynos850-spi",
1667 			.data = &exynos850_spi_port_config,
1668 	},
1669 	{ .compatible = "samsung,exynosautov9-spi",
1670 			.data = &exynosautov9_spi_port_config,
1671 	},
1672 	{ .compatible = "tesla,fsd-spi",
1673 			.data = &fsd_spi_port_config,
1674 	},
1675 	{ },
1676 };
1677 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1678 
1679 static struct platform_driver s3c64xx_spi_driver = {
1680 	.driver = {
1681 		.name	= "s3c64xx-spi",
1682 		.pm = &s3c64xx_spi_pm,
1683 		.of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1684 	},
1685 	.probe = s3c64xx_spi_probe,
1686 	.remove = s3c64xx_spi_remove,
1687 	.id_table = s3c64xx_spi_driver_ids,
1688 };
1689 MODULE_ALIAS("platform:s3c64xx-spi");
1690 
1691 module_platform_driver(s3c64xx_spi_driver);
1692 
1693 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1694 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1695 MODULE_LICENSE("GPL");
1696