1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/debugfs.h>
11 #include <linux/of.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 #include <linux/slab.h>
17 #include <linux/pm_wakeirq.h>
18 #include <linux/slimbus.h>
19 #include <linux/soundwire/sdw.h>
20 #include <linux/soundwire/sdw_registers.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include "bus.h"
24
25 #define SWRM_COMP_SW_RESET 0x008
26 #define SWRM_COMP_STATUS 0x014
27 #define SWRM_LINK_MANAGER_EE 0x018
28 #define SWRM_EE_CPU 1
29 #define SWRM_FRM_GEN_ENABLED BIT(0)
30 #define SWRM_VERSION_1_3_0 0x01030000
31 #define SWRM_VERSION_1_5_1 0x01050001
32 #define SWRM_VERSION_1_7_0 0x01070000
33 #define SWRM_VERSION_2_0_0 0x02000000
34 #define SWRM_COMP_HW_VERSION 0x00
35 #define SWRM_COMP_CFG_ADDR 0x04
36 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
37 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
38 #define SWRM_COMP_PARAMS 0x100
39 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
40 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
43 #define SWRM_COMP_MASTER_ID 0x104
44 #define SWRM_V1_3_INTERRUPT_STATUS 0x200
45 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000
46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
48 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
49 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
50 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
51 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
53 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
54 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
55 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
56 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
57 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
58 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11)
59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12)
60 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
61 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
62 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
63 #define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED BIT(19)
64 #define SWRM_INTERRUPT_MAX 17
65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
66 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208
67 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
68 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
69 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
70 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
71 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
72 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
73 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
74 #define SWRM_CMD_FIFO_CMD 0x308
75 #define SWRM_CMD_FIFO_FLUSH 0x1
76 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
77 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
78 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
79 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
80 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
82 #define SWRM_RD_WR_CMD_RETRIES 0x7
83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
85 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
86 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
92 #define SWRM_MCP_BUS_CTRL 0x1044
93 #define SWRM_MCP_BUS_CLK_START BIT(1)
94 #define SWRM_MCP_CFG_ADDR 0x1048
95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
96 #define SWRM_DEF_CMD_NO_PINGS 0x1f
97 #define SWRM_MCP_STATUS 0x104C
98 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
99 #define SWRM_MCP_SLV_STATUS 0x1090
100 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
101 #define SWRM_MCP_SLV_STATUS_SZ 2
102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
110 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
112
113 #define SWRM_V2_0_CLK_CTRL 0x5060
114 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
115 #define SWRM_V2_0_LINK_STATUS 0x5064
116
117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
120 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
121 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
122 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
123 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
124
125 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
126 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
127
128 #define MAX_FREQ_NUM 1
129 #define TIMEOUT_MS 100
130 #define QCOM_SWRM_MAX_RD_LEN 0x1
131 #define QCOM_SDW_MAX_PORTS 14
132 #define DEFAULT_CLK_FREQ 9600000
133 #define SWRM_MAX_DAIS 0xF
134 #define SWR_INVALID_PARAM 0xFF
135 #define SWR_HSTOP_MAX_VAL 0xF
136 #define SWR_HSTART_MIN_VAL 0x0
137 #define SWR_BROADCAST_CMD_ID 0x0F
138 #define SWR_MAX_CMD_ID 14
139 #define MAX_FIFO_RD_RETRY 3
140 #define SWR_OVERFLOW_RETRY_COUNT 30
141 #define SWRM_LINK_STATUS_RETRY_CNT 100
142
143 enum {
144 MASTER_ID_WSA = 1,
145 MASTER_ID_RX,
146 MASTER_ID_TX
147 };
148
149 struct qcom_swrm_port_config {
150 u16 si;
151 u8 off1;
152 u8 off2;
153 u8 bp_mode;
154 u8 hstart;
155 u8 hstop;
156 u8 word_length;
157 u8 blk_group_count;
158 u8 lane_control;
159 u8 ch_mask;
160 };
161
162 /*
163 * Internal IDs for different register layouts. Only few registers differ per
164 * each variant, so the list of IDs below does not include all of registers.
165 */
166 enum {
167 SWRM_REG_FRAME_GEN_ENABLED,
168 SWRM_REG_INTERRUPT_STATUS,
169 SWRM_REG_INTERRUPT_MASK_ADDR,
170 SWRM_REG_INTERRUPT_CLEAR,
171 SWRM_REG_INTERRUPT_CPU_EN,
172 SWRM_REG_CMD_FIFO_WR_CMD,
173 SWRM_REG_CMD_FIFO_RD_CMD,
174 SWRM_REG_CMD_FIFO_STATUS,
175 SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
176 };
177
178 struct qcom_swrm_ctrl {
179 struct sdw_bus bus;
180 struct device *dev;
181 struct regmap *regmap;
182 u32 max_reg;
183 const unsigned int *reg_layout;
184 void __iomem *mmio;
185 struct reset_control *audio_cgcr;
186 #ifdef CONFIG_DEBUG_FS
187 struct dentry *debugfs;
188 #endif
189 struct completion broadcast;
190 struct completion enumeration;
191 /* Port alloc/free lock */
192 struct mutex port_lock;
193 struct clk *hclk;
194 int irq;
195 unsigned int version;
196 int wake_irq;
197 int num_din_ports;
198 int num_dout_ports;
199 int cols_index;
200 int rows_index;
201 unsigned long port_mask;
202 u32 intr_mask;
203 u8 rcmd_id;
204 u8 wcmd_id;
205 /* Port numbers are 1 - 14 */
206 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1];
207 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
208 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
209 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
211 u32 slave_status;
212 u32 wr_fifo_depth;
213 u32 rd_fifo_depth;
214 bool clock_stop_not_supported;
215 };
216
217 struct qcom_swrm_data {
218 u32 default_cols;
219 u32 default_rows;
220 bool sw_clk_gate_required;
221 u32 max_reg;
222 const unsigned int *reg_layout;
223 };
224
225 static const unsigned int swrm_v1_3_reg_layout[] = {
226 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
227 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
228 [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
229 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
230 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
231 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
232 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
233 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
234 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
235 };
236
237 static const struct qcom_swrm_data swrm_v1_3_data = {
238 .default_rows = 48,
239 .default_cols = 16,
240 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
241 .reg_layout = swrm_v1_3_reg_layout,
242 };
243
244 static const struct qcom_swrm_data swrm_v1_5_data = {
245 .default_rows = 50,
246 .default_cols = 16,
247 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
248 .reg_layout = swrm_v1_3_reg_layout,
249 };
250
251 static const struct qcom_swrm_data swrm_v1_6_data = {
252 .default_rows = 50,
253 .default_cols = 16,
254 .sw_clk_gate_required = true,
255 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
256 .reg_layout = swrm_v1_3_reg_layout,
257 };
258
259 static const unsigned int swrm_v2_0_reg_layout[] = {
260 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
261 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
262 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
263 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
264 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
265 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
266 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
267 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
268 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
269 };
270
271 static const struct qcom_swrm_data swrm_v2_0_data = {
272 .default_rows = 50,
273 .default_cols = 16,
274 .sw_clk_gate_required = true,
275 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
276 .reg_layout = swrm_v2_0_reg_layout,
277 };
278
279 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
280
qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl * ctrl,int reg,u32 * val)281 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
282 u32 *val)
283 {
284 struct regmap *wcd_regmap = ctrl->regmap;
285 int ret;
286
287 /* pg register + offset */
288 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
289 (u8 *)®, 4);
290 if (ret < 0)
291 return SDW_CMD_FAIL;
292
293 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
294 val, 4);
295 if (ret < 0)
296 return SDW_CMD_FAIL;
297
298 return SDW_CMD_OK;
299 }
300
qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl * ctrl,int reg,int val)301 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
302 int reg, int val)
303 {
304 struct regmap *wcd_regmap = ctrl->regmap;
305 int ret;
306 /* pg register + offset */
307 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
308 (u8 *)&val, 4);
309 if (ret)
310 return SDW_CMD_FAIL;
311
312 /* write address register */
313 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
314 (u8 *)®, 4);
315 if (ret)
316 return SDW_CMD_FAIL;
317
318 return SDW_CMD_OK;
319 }
320
qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl * ctrl,int reg,u32 * val)321 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
322 u32 *val)
323 {
324 *val = readl(ctrl->mmio + reg);
325 return SDW_CMD_OK;
326 }
327
qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl * ctrl,int reg,int val)328 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
329 int val)
330 {
331 writel(val, ctrl->mmio + reg);
332 return SDW_CMD_OK;
333 }
334
swrm_get_packed_reg_val(u8 * cmd_id,u8 cmd_data,u8 dev_addr,u16 reg_addr)335 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
336 u8 dev_addr, u16 reg_addr)
337 {
338 u32 val;
339 u8 id = *cmd_id;
340
341 if (id != SWR_BROADCAST_CMD_ID) {
342 if (id < SWR_MAX_CMD_ID)
343 id += 1;
344 else
345 id = 0;
346 *cmd_id = id;
347 }
348 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
349
350 return val;
351 }
352
swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl * ctrl)353 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
354 {
355 u32 fifo_outstanding_data, value;
356 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
357
358 do {
359 /* Check for fifo underflow during read */
360 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
361 &value);
362 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
363
364 /* Check if read data is available in read fifo */
365 if (fifo_outstanding_data > 0)
366 return 0;
367
368 usleep_range(500, 510);
369 } while (fifo_retry_count--);
370
371 if (fifo_outstanding_data == 0) {
372 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
373 return -EIO;
374 }
375
376 return 0;
377 }
378
swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl * ctrl)379 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
380 {
381 u32 fifo_outstanding_cmds, value;
382 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
383
384 do {
385 /* Check for fifo overflow during write */
386 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
387 &value);
388 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
389
390 /* Check for space in write fifo before writing */
391 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
392 return 0;
393
394 usleep_range(500, 510);
395 } while (fifo_retry_count--);
396
397 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
398 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
399 return -EIO;
400 }
401
402 return 0;
403 }
404
swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl * ctrl)405 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
406 {
407 u32 fifo_outstanding_cmds, value;
408 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
409
410 /* Check for fifo overflow during write */
411 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
412 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
413
414 if (fifo_outstanding_cmds) {
415 while (fifo_retry_count) {
416 usleep_range(500, 510);
417 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
418 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
419 fifo_retry_count--;
420 if (fifo_outstanding_cmds == 0)
421 return true;
422 }
423 } else {
424 return true;
425 }
426
427
428 return false;
429 }
430
qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl * ctrl,u8 cmd_data,u8 dev_addr,u16 reg_addr)431 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
432 u8 dev_addr, u16 reg_addr)
433 {
434
435 u32 val;
436 int ret = 0;
437 u8 cmd_id = 0x0;
438
439 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
440 cmd_id = SWR_BROADCAST_CMD_ID;
441 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
442 dev_addr, reg_addr);
443 } else {
444 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
445 dev_addr, reg_addr);
446 }
447
448 if (swrm_wait_for_wr_fifo_avail(ctrl))
449 return SDW_CMD_FAIL_OTHER;
450
451 if (cmd_id == SWR_BROADCAST_CMD_ID)
452 reinit_completion(&ctrl->broadcast);
453
454 /* Its assumed that write is okay as we do not get any status back */
455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
456
457 if (ctrl->version <= SWRM_VERSION_1_3_0)
458 usleep_range(150, 155);
459
460 if (cmd_id == SWR_BROADCAST_CMD_ID) {
461 swrm_wait_for_wr_fifo_done(ctrl);
462 /*
463 * sleep for 10ms for MSM soundwire variant to allow broadcast
464 * command to complete.
465 */
466 ret = wait_for_completion_timeout(&ctrl->broadcast,
467 msecs_to_jiffies(TIMEOUT_MS));
468 if (!ret)
469 ret = SDW_CMD_IGNORED;
470 else
471 ret = SDW_CMD_OK;
472
473 } else {
474 ret = SDW_CMD_OK;
475 }
476 return ret;
477 }
478
qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl * ctrl,u8 dev_addr,u16 reg_addr,u32 len,u8 * rval)479 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
480 u8 dev_addr, u16 reg_addr,
481 u32 len, u8 *rval)
482 {
483 u32 cmd_data, cmd_id, val, retry_attempt = 0;
484
485 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
486
487 /*
488 * Check for outstanding cmd wrt. write fifo depth to avoid
489 * overflow as read will also increase write fifo cnt.
490 */
491 swrm_wait_for_wr_fifo_avail(ctrl);
492
493 /* wait for FIFO RD to complete to avoid overflow */
494 usleep_range(100, 105);
495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
496 /* wait for FIFO RD CMD complete to avoid overflow */
497 usleep_range(250, 255);
498
499 if (swrm_wait_for_rd_fifo_avail(ctrl))
500 return SDW_CMD_FAIL_OTHER;
501
502 do {
503 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
504 &cmd_data);
505 rval[0] = cmd_data & 0xFF;
506 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
507
508 if (cmd_id != ctrl->rcmd_id) {
509 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
510 /* wait 500 us before retry on fifo read failure */
511 usleep_range(500, 505);
512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
513 SWRM_CMD_FIFO_FLUSH);
514 ctrl->reg_write(ctrl,
515 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
516 val);
517 }
518 retry_attempt++;
519 } else {
520 return SDW_CMD_OK;
521 }
522
523 } while (retry_attempt < MAX_FIFO_RD_RETRY);
524
525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
526 dev_num: 0x%x, cmd_data: 0x%x\n",
527 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
528
529 return SDW_CMD_IGNORED;
530 }
531
qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl * ctrl)532 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
533 {
534 u32 val, status;
535 int dev_num;
536
537 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
538
539 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
540 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
541
542 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
543 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
544 return dev_num;
545 }
546 }
547
548 return -EINVAL;
549 }
550
qcom_swrm_get_device_status(struct qcom_swrm_ctrl * ctrl)551 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
552 {
553 u32 val;
554 int i;
555
556 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
557 ctrl->slave_status = val;
558
559 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
560 u32 s;
561
562 s = (val >> (i * 2));
563 s &= SWRM_MCP_SLV_STATUS_MASK;
564 ctrl->status[i] = s;
565 }
566 }
567
qcom_swrm_set_slave_dev_num(struct sdw_bus * bus,struct sdw_slave * slave,int devnum)568 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
569 struct sdw_slave *slave, int devnum)
570 {
571 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
572 u32 status;
573
574 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
575 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
576 status &= SWRM_MCP_SLV_STATUS_MASK;
577
578 if (status == SDW_SLAVE_ATTACHED) {
579 if (slave)
580 slave->dev_num = devnum;
581 mutex_lock(&bus->bus_lock);
582 set_bit(devnum, bus->assigned);
583 mutex_unlock(&bus->bus_lock);
584 }
585 }
586
qcom_swrm_enumerate(struct sdw_bus * bus)587 static int qcom_swrm_enumerate(struct sdw_bus *bus)
588 {
589 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
590 struct sdw_slave *slave, *_s;
591 struct sdw_slave_id id;
592 u32 val1, val2;
593 bool found;
594 u64 addr;
595 int i;
596 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
597
598 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
599 /* do not continue if the status is Not Present */
600 if (!ctrl->status[i])
601 continue;
602
603 /*SCP_Devid5 - Devid 4*/
604 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
605
606 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
607 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
608
609 if (!val1 && !val2)
610 break;
611
612 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
613 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
614 ((u64)buf1[0] << 40);
615
616 sdw_extract_slave_id(bus, addr, &id);
617 found = false;
618 ctrl->clock_stop_not_supported = false;
619 /* Now compare with entries */
620 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
621 if (sdw_compare_devid(slave, id) == 0) {
622 qcom_swrm_set_slave_dev_num(bus, slave, i);
623 if (slave->prop.clk_stop_mode1)
624 ctrl->clock_stop_not_supported = true;
625
626 found = true;
627 break;
628 }
629 }
630
631 if (!found) {
632 qcom_swrm_set_slave_dev_num(bus, NULL, i);
633 sdw_slave_add(bus, &id, NULL);
634 }
635 }
636
637 complete(&ctrl->enumeration);
638 return 0;
639 }
640
qcom_swrm_wake_irq_handler(int irq,void * dev_id)641 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
642 {
643 struct qcom_swrm_ctrl *ctrl = dev_id;
644 int ret;
645
646 ret = pm_runtime_get_sync(ctrl->dev);
647 if (ret < 0 && ret != -EACCES) {
648 dev_err_ratelimited(ctrl->dev,
649 "pm_runtime_get_sync failed in %s, ret %d\n",
650 __func__, ret);
651 pm_runtime_put_noidle(ctrl->dev);
652 return ret;
653 }
654
655 if (ctrl->wake_irq > 0) {
656 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
657 disable_irq_nosync(ctrl->wake_irq);
658 }
659
660 pm_runtime_mark_last_busy(ctrl->dev);
661 pm_runtime_put_autosuspend(ctrl->dev);
662
663 return IRQ_HANDLED;
664 }
665
qcom_swrm_irq_handler(int irq,void * dev_id)666 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
667 {
668 struct qcom_swrm_ctrl *ctrl = dev_id;
669 u32 value, intr_sts, intr_sts_masked, slave_status;
670 u32 i;
671 int devnum;
672 int ret = IRQ_HANDLED;
673 clk_prepare_enable(ctrl->hclk);
674
675 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
676 &intr_sts);
677 intr_sts_masked = intr_sts & ctrl->intr_mask;
678
679 do {
680 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
681 value = intr_sts_masked & BIT(i);
682 if (!value)
683 continue;
684
685 switch (value) {
686 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
687 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
688 if (devnum < 0) {
689 dev_err_ratelimited(ctrl->dev,
690 "no slave alert found.spurious interrupt\n");
691 } else {
692 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
693 }
694
695 break;
696 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
697 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
698 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
699 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
700 if (ctrl->slave_status == slave_status) {
701 dev_dbg(ctrl->dev, "Slave status not changed %x\n",
702 slave_status);
703 } else {
704 qcom_swrm_get_device_status(ctrl);
705 qcom_swrm_enumerate(&ctrl->bus);
706 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
707 }
708 break;
709 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
710 dev_err_ratelimited(ctrl->dev,
711 "%s: SWR bus clsh detected\n",
712 __func__);
713 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
714 ctrl->reg_write(ctrl,
715 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
716 ctrl->intr_mask);
717 break;
718 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
719 ctrl->reg_read(ctrl,
720 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
721 &value);
722 dev_err_ratelimited(ctrl->dev,
723 "%s: SWR read FIFO overflow fifo status 0x%x\n",
724 __func__, value);
725 break;
726 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
727 ctrl->reg_read(ctrl,
728 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
729 &value);
730 dev_err_ratelimited(ctrl->dev,
731 "%s: SWR read FIFO underflow fifo status 0x%x\n",
732 __func__, value);
733 break;
734 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
735 ctrl->reg_read(ctrl,
736 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
737 &value);
738 dev_err(ctrl->dev,
739 "%s: SWR write FIFO overflow fifo status %x\n",
740 __func__, value);
741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
742 break;
743 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
744 ctrl->reg_read(ctrl,
745 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
746 &value);
747 dev_err_ratelimited(ctrl->dev,
748 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
749 __func__, value);
750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
751 break;
752 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
753 dev_err_ratelimited(ctrl->dev,
754 "%s: SWR Port collision detected\n",
755 __func__);
756 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
757 ctrl->reg_write(ctrl,
758 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
759 ctrl->intr_mask);
760 break;
761 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
762 dev_err_ratelimited(ctrl->dev,
763 "%s: SWR read enable valid mismatch\n",
764 __func__);
765 ctrl->intr_mask &=
766 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
767 ctrl->reg_write(ctrl,
768 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
769 ctrl->intr_mask);
770 break;
771 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
772 complete(&ctrl->broadcast);
773 break;
774 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
775 break;
776 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
777 break;
778 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
779 break;
780 case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
781 ctrl->reg_read(ctrl,
782 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
783 &value);
784 dev_err(ctrl->dev,
785 "%s: SWR CMD ignored, fifo status %x\n",
786 __func__, value);
787
788 /* Wait 3.5ms to clear */
789 usleep_range(3500, 3505);
790 break;
791 default:
792 dev_err_ratelimited(ctrl->dev,
793 "%s: SWR unknown interrupt value: %d\n",
794 __func__, value);
795 ret = IRQ_NONE;
796 break;
797 }
798 }
799 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
800 intr_sts);
801 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
802 &intr_sts);
803 intr_sts_masked = intr_sts & ctrl->intr_mask;
804 } while (intr_sts_masked);
805
806 clk_disable_unprepare(ctrl->hclk);
807 return ret;
808 }
809
swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl * ctrl)810 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
811 {
812 int retry = SWRM_LINK_STATUS_RETRY_CNT;
813 int comp_sts;
814
815 do {
816 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
817 &comp_sts);
818 if (comp_sts & SWRM_FRM_GEN_ENABLED)
819 return true;
820
821 usleep_range(500, 510);
822 } while (retry--);
823
824 dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
825 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
826
827 return false;
828 }
829
qcom_swrm_init(struct qcom_swrm_ctrl * ctrl)830 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
831 {
832 u32 val;
833
834 /* Clear Rows and Cols */
835 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
836 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
837
838 reset_control_reset(ctrl->audio_cgcr);
839
840 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
841
842 /* Enable Auto enumeration */
843 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
844
845 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
846 /* Mask soundwire interrupts */
847 if (ctrl->version < SWRM_VERSION_2_0_0)
848 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
849 SWRM_INTERRUPT_STATUS_RMSK);
850
851 /* Configure No pings */
852 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
853 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
854 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
855
856 if (ctrl->version == SWRM_VERSION_1_7_0) {
857 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
858 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
859 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
860 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
861 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
862 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
863 SWRM_V2_0_CLK_CTRL_CLK_START);
864 } else {
865 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
866 }
867
868 /* Configure number of retries of a read/write cmd */
869 if (ctrl->version >= SWRM_VERSION_1_5_1) {
870 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
871 SWRM_RD_WR_CMD_RETRIES |
872 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
873 } else {
874 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
875 SWRM_RD_WR_CMD_RETRIES);
876 }
877
878 /* COMP Enable */
879 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
880
881 /* Set IRQ to PULSE */
882 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
883 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK);
884
885 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
886 0xFFFFFFFF);
887
888 /* enable CPU IRQs */
889 if (ctrl->mmio) {
890 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
891 SWRM_INTERRUPT_STATUS_RMSK);
892 }
893
894 /* Set IRQ to PULSE */
895 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
896 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
897 SWRM_COMP_CFG_ENABLE_MSK);
898
899 swrm_wait_for_frame_gen_enabled(ctrl);
900 ctrl->slave_status = 0;
901 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
902 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
903 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
904
905 return 0;
906 }
907
qcom_swrm_read_prop(struct sdw_bus * bus)908 static int qcom_swrm_read_prop(struct sdw_bus *bus)
909 {
910 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
911
912 if (ctrl->version >= SWRM_VERSION_2_0_0) {
913 bus->multi_link = true;
914 bus->hw_sync_min_links = 3;
915 }
916
917 return 0;
918 }
919
qcom_swrm_xfer_msg(struct sdw_bus * bus,struct sdw_msg * msg)920 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
921 struct sdw_msg *msg)
922 {
923 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
924 int ret, i, len;
925
926 if (msg->flags == SDW_MSG_FLAG_READ) {
927 for (i = 0; i < msg->len;) {
928 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
929 len = msg->len - i;
930 else
931 len = QCOM_SWRM_MAX_RD_LEN;
932
933 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
934 msg->addr + i, len,
935 &msg->buf[i]);
936 if (ret)
937 return ret;
938
939 i = i + len;
940 }
941 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
942 for (i = 0; i < msg->len; i++) {
943 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
944 msg->dev_num,
945 msg->addr + i);
946 if (ret)
947 return SDW_CMD_IGNORED;
948 }
949 }
950
951 return SDW_CMD_OK;
952 }
953
qcom_swrm_pre_bank_switch(struct sdw_bus * bus)954 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
955 {
956 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
957 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
958 u32 val;
959
960 ctrl->reg_read(ctrl, reg, &val);
961
962 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
963 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
964
965 return ctrl->reg_write(ctrl, reg, val);
966 }
967
qcom_swrm_port_params(struct sdw_bus * bus,struct sdw_port_params * p_params,unsigned int bank)968 static int qcom_swrm_port_params(struct sdw_bus *bus,
969 struct sdw_port_params *p_params,
970 unsigned int bank)
971 {
972 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
973
974 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
975 p_params->bps - 1);
976
977 }
978
qcom_swrm_transport_params(struct sdw_bus * bus,struct sdw_transport_params * params,enum sdw_reg_bank bank)979 static int qcom_swrm_transport_params(struct sdw_bus *bus,
980 struct sdw_transport_params *params,
981 enum sdw_reg_bank bank)
982 {
983 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
984 struct qcom_swrm_port_config *pcfg;
985 u32 value;
986 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
987 int ret;
988
989 pcfg = &ctrl->pconfig[params->port_num];
990
991 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
992 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
993 value |= pcfg->si & 0xff;
994
995 ret = ctrl->reg_write(ctrl, reg, value);
996 if (ret)
997 goto err;
998
999 if (pcfg->si > 0xff) {
1000 value = (pcfg->si >> 8) & 0xff;
1001 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
1002 ret = ctrl->reg_write(ctrl, reg, value);
1003 if (ret)
1004 goto err;
1005 }
1006
1007 if (pcfg->lane_control != SWR_INVALID_PARAM) {
1008 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
1009 value = pcfg->lane_control;
1010 ret = ctrl->reg_write(ctrl, reg, value);
1011 if (ret)
1012 goto err;
1013 }
1014
1015 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1016 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
1017 value = pcfg->blk_group_count;
1018 ret = ctrl->reg_write(ctrl, reg, value);
1019 if (ret)
1020 goto err;
1021 }
1022
1023 if (pcfg->hstart != SWR_INVALID_PARAM
1024 && pcfg->hstop != SWR_INVALID_PARAM) {
1025 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1026 value = (pcfg->hstop << 4) | pcfg->hstart;
1027 ret = ctrl->reg_write(ctrl, reg, value);
1028 } else {
1029 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1030 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1031 ret = ctrl->reg_write(ctrl, reg, value);
1032 }
1033
1034 if (ret)
1035 goto err;
1036
1037 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1038 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
1039 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1040 }
1041
1042 err:
1043 return ret;
1044 }
1045
qcom_swrm_port_enable(struct sdw_bus * bus,struct sdw_enable_ch * enable_ch,unsigned int bank)1046 static int qcom_swrm_port_enable(struct sdw_bus *bus,
1047 struct sdw_enable_ch *enable_ch,
1048 unsigned int bank)
1049 {
1050 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
1051 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1052 struct qcom_swrm_port_config *pcfg;
1053 u32 val;
1054
1055 pcfg = &ctrl->pconfig[enable_ch->port_num];
1056 ctrl->reg_read(ctrl, reg, &val);
1057 if (pcfg->ch_mask != SWR_INVALID_PARAM && pcfg->ch_mask != 0)
1058 enable_ch->ch_mask = pcfg->ch_mask;
1059
1060 if (enable_ch->enable)
1061 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1062 else
1063 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1064
1065 return ctrl->reg_write(ctrl, reg, val);
1066 }
1067
1068 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1069 .dpn_set_port_params = qcom_swrm_port_params,
1070 .dpn_set_port_transport_params = qcom_swrm_transport_params,
1071 .dpn_port_enable_ch = qcom_swrm_port_enable,
1072 };
1073
1074 static const struct sdw_master_ops qcom_swrm_ops = {
1075 .read_prop = qcom_swrm_read_prop,
1076 .xfer_msg = qcom_swrm_xfer_msg,
1077 .pre_bank_switch = qcom_swrm_pre_bank_switch,
1078 };
1079
qcom_swrm_compute_params(struct sdw_bus * bus,struct sdw_stream_runtime * stream)1080 static int qcom_swrm_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
1081 {
1082 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1083 struct sdw_master_runtime *m_rt;
1084 struct sdw_slave_runtime *s_rt;
1085 struct sdw_port_runtime *p_rt;
1086 struct qcom_swrm_port_config *pcfg;
1087 struct sdw_slave *slave;
1088 unsigned int m_port;
1089 int i = 1;
1090
1091 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1092 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1093 pcfg = &ctrl->pconfig[p_rt->num];
1094 p_rt->transport_params.port_num = p_rt->num;
1095 if (pcfg->word_length != SWR_INVALID_PARAM) {
1096 sdw_fill_port_params(&p_rt->port_params,
1097 p_rt->num, pcfg->word_length + 1,
1098 SDW_PORT_FLOW_MODE_ISOCH,
1099 SDW_PORT_DATA_MODE_NORMAL);
1100 }
1101
1102 }
1103
1104 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1105 slave = s_rt->slave;
1106 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1107 m_port = slave->m_port_map[p_rt->num];
1108 /* port config starts at offset 0 so -1 from actual port number */
1109 if (m_port)
1110 pcfg = &ctrl->pconfig[m_port];
1111 else
1112 pcfg = &ctrl->pconfig[i];
1113 p_rt->transport_params.port_num = p_rt->num;
1114 p_rt->transport_params.sample_interval =
1115 pcfg->si + 1;
1116 p_rt->transport_params.offset1 = pcfg->off1;
1117 p_rt->transport_params.offset2 = pcfg->off2;
1118 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1119 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1120
1121 p_rt->transport_params.hstart = pcfg->hstart;
1122 p_rt->transport_params.hstop = pcfg->hstop;
1123 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1124 if (pcfg->word_length != SWR_INVALID_PARAM) {
1125 sdw_fill_port_params(&p_rt->port_params,
1126 p_rt->num,
1127 pcfg->word_length + 1,
1128 SDW_PORT_FLOW_MODE_ISOCH,
1129 SDW_PORT_DATA_MODE_NORMAL);
1130 }
1131 i++;
1132 }
1133 }
1134 }
1135
1136 return 0;
1137 }
1138
1139 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1140 DEFAULT_CLK_FREQ,
1141 };
1142
qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl * ctrl,struct sdw_stream_runtime * stream)1143 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1144 struct sdw_stream_runtime *stream)
1145 {
1146 struct sdw_master_runtime *m_rt;
1147 struct sdw_port_runtime *p_rt;
1148 unsigned long *port_mask;
1149
1150 mutex_lock(&ctrl->port_lock);
1151
1152 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1153 port_mask = &ctrl->port_mask;
1154 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1155 clear_bit(p_rt->num, port_mask);
1156 }
1157
1158 mutex_unlock(&ctrl->port_lock);
1159 }
1160
qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl * ctrl,struct sdw_stream_runtime * stream,struct snd_pcm_hw_params * params,int direction)1161 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1162 struct sdw_stream_runtime *stream,
1163 struct snd_pcm_hw_params *params,
1164 int direction)
1165 {
1166 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
1167 struct sdw_stream_config sconfig;
1168 struct sdw_master_runtime *m_rt;
1169 struct sdw_slave_runtime *s_rt;
1170 struct sdw_port_runtime *p_rt;
1171 struct sdw_slave *slave;
1172 unsigned long *port_mask;
1173 int maxport, pn, nports = 0, ret = 0;
1174 unsigned int m_port;
1175
1176 if (direction == SNDRV_PCM_STREAM_CAPTURE)
1177 sconfig.direction = SDW_DATA_DIR_TX;
1178 else
1179 sconfig.direction = SDW_DATA_DIR_RX;
1180
1181 /* hw parameters will be ignored as we only support PDM */
1182 sconfig.ch_count = 1;
1183 sconfig.frame_rate = params_rate(params);
1184 sconfig.type = stream->type;
1185 sconfig.bps = 1;
1186
1187 mutex_lock(&ctrl->port_lock);
1188 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1189 /*
1190 * For streams with multiple masters:
1191 * Allocate ports only for devices connected to this master.
1192 * Such devices will have ports allocated by their own master
1193 * and its qcom_swrm_stream_alloc_ports() call.
1194 */
1195 if (ctrl->bus.id != m_rt->bus->id)
1196 continue;
1197
1198 port_mask = &ctrl->port_mask;
1199 maxport = ctrl->num_dout_ports + ctrl->num_din_ports;
1200
1201
1202 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1203 slave = s_rt->slave;
1204 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1205 m_port = slave->m_port_map[p_rt->num];
1206 /* Port numbers start from 1 - 14*/
1207 if (m_port)
1208 pn = m_port;
1209 else
1210 pn = find_first_zero_bit(port_mask, maxport);
1211
1212 if (pn > maxport) {
1213 dev_err(ctrl->dev, "All ports busy\n");
1214 ret = -EBUSY;
1215 goto out;
1216 }
1217 set_bit(pn, port_mask);
1218 pconfig[nports].num = pn;
1219 pconfig[nports].ch_mask = p_rt->ch_mask;
1220 nports++;
1221 }
1222 }
1223 }
1224
1225 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1226 nports, stream);
1227 out:
1228 mutex_unlock(&ctrl->port_lock);
1229
1230 return ret;
1231 }
1232
qcom_swrm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1233 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1234 struct snd_pcm_hw_params *params,
1235 struct snd_soc_dai *dai)
1236 {
1237 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1238 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1239 int ret;
1240
1241 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1242 substream->stream);
1243 if (ret)
1244 qcom_swrm_stream_free_ports(ctrl, sruntime);
1245
1246 return ret;
1247 }
1248
qcom_swrm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1249 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1250 struct snd_soc_dai *dai)
1251 {
1252 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1253 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1254
1255 qcom_swrm_stream_free_ports(ctrl, sruntime);
1256 sdw_stream_remove_master(&ctrl->bus, sruntime);
1257
1258 return 0;
1259 }
1260
qcom_swrm_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1261 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1262 void *stream, int direction)
1263 {
1264 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1265
1266 ctrl->sruntime[dai->id] = stream;
1267
1268 return 0;
1269 }
1270
qcom_swrm_get_sdw_stream(struct snd_soc_dai * dai,int direction)1271 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1272 {
1273 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1274
1275 return ctrl->sruntime[dai->id];
1276 }
1277
qcom_swrm_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1278 static int qcom_swrm_set_channel_map(struct snd_soc_dai *dai,
1279 unsigned int tx_num, const unsigned int *tx_slot,
1280 unsigned int rx_num, const unsigned int *rx_slot)
1281 {
1282 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1283 int i;
1284
1285 if (tx_slot) {
1286 for (i = 0; i < tx_num; i++)
1287 ctrl->pconfig[i].ch_mask = tx_slot[i];
1288 }
1289
1290 if (rx_slot) {
1291 for (i = 0; i < rx_num; i++)
1292 ctrl->pconfig[i].ch_mask = rx_slot[i];
1293 }
1294
1295 return 0;
1296 }
1297
qcom_swrm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1298 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1299 struct snd_soc_dai *dai)
1300 {
1301 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1302 int ret;
1303
1304 ret = pm_runtime_get_sync(ctrl->dev);
1305 if (ret < 0 && ret != -EACCES) {
1306 dev_err_ratelimited(ctrl->dev,
1307 "pm_runtime_get_sync failed in %s, ret %d\n",
1308 __func__, ret);
1309 pm_runtime_put_noidle(ctrl->dev);
1310 return ret;
1311 }
1312
1313 return 0;
1314 }
1315
qcom_swrm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1316 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1317 struct snd_soc_dai *dai)
1318 {
1319 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1320
1321 swrm_wait_for_wr_fifo_done(ctrl);
1322 pm_runtime_mark_last_busy(ctrl->dev);
1323 pm_runtime_put_autosuspend(ctrl->dev);
1324
1325 }
1326
1327 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1328 .hw_params = qcom_swrm_hw_params,
1329 .hw_free = qcom_swrm_hw_free,
1330 .startup = qcom_swrm_startup,
1331 .shutdown = qcom_swrm_shutdown,
1332 .set_stream = qcom_swrm_set_sdw_stream,
1333 .get_stream = qcom_swrm_get_sdw_stream,
1334 .set_channel_map = qcom_swrm_set_channel_map,
1335 };
1336
1337 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1338 .name = "soundwire",
1339 };
1340
qcom_swrm_register_dais(struct qcom_swrm_ctrl * ctrl)1341 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1342 {
1343 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1344 struct snd_soc_dai_driver *dais;
1345 struct snd_soc_pcm_stream *stream;
1346 struct device *dev = ctrl->dev;
1347 int i;
1348
1349 /* PDM dais are only tested for now */
1350 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1351 if (!dais)
1352 return -ENOMEM;
1353
1354 for (i = 0; i < num_dais; i++) {
1355 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1356 if (!dais[i].name)
1357 return -ENOMEM;
1358
1359 if (i < ctrl->num_dout_ports)
1360 stream = &dais[i].playback;
1361 else
1362 stream = &dais[i].capture;
1363
1364 stream->channels_min = 1;
1365 stream->channels_max = 1;
1366 stream->rates = SNDRV_PCM_RATE_48000;
1367 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1368
1369 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1370 dais[i].id = i;
1371 }
1372
1373 return devm_snd_soc_register_component(ctrl->dev,
1374 &qcom_swrm_dai_component,
1375 dais, num_dais);
1376 }
1377
qcom_swrm_get_port_config(struct qcom_swrm_ctrl * ctrl)1378 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1379 {
1380 struct device_node *np = ctrl->dev->of_node;
1381 u8 off1[QCOM_SDW_MAX_PORTS];
1382 u8 off2[QCOM_SDW_MAX_PORTS];
1383 u16 si[QCOM_SDW_MAX_PORTS];
1384 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1385 u8 hstart[QCOM_SDW_MAX_PORTS];
1386 u8 hstop[QCOM_SDW_MAX_PORTS];
1387 u8 word_length[QCOM_SDW_MAX_PORTS];
1388 u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1389 u8 lane_control[QCOM_SDW_MAX_PORTS];
1390 int i, ret, nports, val;
1391 bool si_16 = false;
1392
1393 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1394
1395 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1396 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1397
1398 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1399 if (ret)
1400 return ret;
1401
1402 if (val > ctrl->num_din_ports)
1403 return -EINVAL;
1404
1405 ctrl->num_din_ports = val;
1406
1407 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1408 if (ret)
1409 return ret;
1410
1411 if (val > ctrl->num_dout_ports)
1412 return -EINVAL;
1413
1414 ctrl->num_dout_ports = val;
1415
1416 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1417 if (nports > QCOM_SDW_MAX_PORTS)
1418 return -EINVAL;
1419
1420 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1421 set_bit(0, &ctrl->port_mask);
1422
1423 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1424 off1, nports);
1425 if (ret)
1426 return ret;
1427
1428 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1429 off2, nports);
1430 if (ret)
1431 return ret;
1432
1433 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1434 (u8 *)si, nports);
1435 if (ret) {
1436 ret = of_property_read_u16_array(np, "qcom,ports-sinterval",
1437 si, nports);
1438 if (ret)
1439 return ret;
1440 si_16 = true;
1441 }
1442
1443 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1444 bp_mode, nports);
1445 if (ret) {
1446 if (ctrl->version <= SWRM_VERSION_1_3_0)
1447 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1448 else
1449 return ret;
1450 }
1451
1452 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1453 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1454
1455 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1456 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1457
1458 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1459 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1460
1461 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1462 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1463
1464 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1465 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1466
1467 for (i = 0; i < nports; i++) {
1468 /* Valid port number range is from 1-14 */
1469 if (si_16)
1470 ctrl->pconfig[i + 1].si = si[i];
1471 else
1472 ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1473 ctrl->pconfig[i + 1].off1 = off1[i];
1474 ctrl->pconfig[i + 1].off2 = off2[i];
1475 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1476 ctrl->pconfig[i + 1].hstart = hstart[i];
1477 ctrl->pconfig[i + 1].hstop = hstop[i];
1478 ctrl->pconfig[i + 1].word_length = word_length[i];
1479 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1480 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1481 }
1482
1483 return 0;
1484 }
1485
1486 #ifdef CONFIG_DEBUG_FS
swrm_reg_show(struct seq_file * s_file,void * data)1487 static int swrm_reg_show(struct seq_file *s_file, void *data)
1488 {
1489 struct qcom_swrm_ctrl *ctrl = s_file->private;
1490 int reg, reg_val, ret;
1491
1492 ret = pm_runtime_get_sync(ctrl->dev);
1493 if (ret < 0 && ret != -EACCES) {
1494 dev_err_ratelimited(ctrl->dev,
1495 "pm_runtime_get_sync failed in %s, ret %d\n",
1496 __func__, ret);
1497 pm_runtime_put_noidle(ctrl->dev);
1498 return ret;
1499 }
1500
1501 for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1502 ctrl->reg_read(ctrl, reg, ®_val);
1503 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1504 }
1505 pm_runtime_mark_last_busy(ctrl->dev);
1506 pm_runtime_put_autosuspend(ctrl->dev);
1507
1508
1509 return 0;
1510 }
1511 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1512 #endif
1513
qcom_swrm_probe(struct platform_device * pdev)1514 static int qcom_swrm_probe(struct platform_device *pdev)
1515 {
1516 struct device *dev = &pdev->dev;
1517 struct sdw_master_prop *prop;
1518 struct sdw_bus_params *params;
1519 struct qcom_swrm_ctrl *ctrl;
1520 const struct qcom_swrm_data *data;
1521 int ret;
1522 u32 val;
1523
1524 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1525 if (!ctrl)
1526 return -ENOMEM;
1527
1528 data = of_device_get_match_data(dev);
1529 ctrl->max_reg = data->max_reg;
1530 ctrl->reg_layout = data->reg_layout;
1531 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1532 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1533 #if IS_REACHABLE(CONFIG_SLIMBUS)
1534 if (dev->parent->bus == &slimbus_bus) {
1535 #else
1536 if (false) {
1537 #endif
1538 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1539 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1540 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1541 if (!ctrl->regmap)
1542 return -EINVAL;
1543 } else {
1544 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1545 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1546 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1547 if (IS_ERR(ctrl->mmio))
1548 return PTR_ERR(ctrl->mmio);
1549 }
1550
1551 if (data->sw_clk_gate_required) {
1552 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1553 if (IS_ERR(ctrl->audio_cgcr)) {
1554 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1555 ret = PTR_ERR(ctrl->audio_cgcr);
1556 goto err_init;
1557 }
1558 }
1559
1560 ctrl->irq = of_irq_get(dev->of_node, 0);
1561 if (ctrl->irq < 0) {
1562 ret = ctrl->irq;
1563 goto err_init;
1564 }
1565
1566 ctrl->hclk = devm_clk_get(dev, "iface");
1567 if (IS_ERR(ctrl->hclk)) {
1568 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1569 goto err_init;
1570 }
1571
1572 clk_prepare_enable(ctrl->hclk);
1573
1574 ctrl->dev = dev;
1575 dev_set_drvdata(&pdev->dev, ctrl);
1576 mutex_init(&ctrl->port_lock);
1577 init_completion(&ctrl->broadcast);
1578 init_completion(&ctrl->enumeration);
1579
1580 ctrl->bus.ops = &qcom_swrm_ops;
1581 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1582 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1583 ctrl->bus.clk_stop_timeout = 300;
1584
1585 ret = qcom_swrm_get_port_config(ctrl);
1586 if (ret)
1587 goto err_clk;
1588
1589 params = &ctrl->bus.params;
1590 params->max_dr_freq = DEFAULT_CLK_FREQ;
1591 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1592 params->col = data->default_cols;
1593 params->row = data->default_rows;
1594 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1595 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1596 params->next_bank = !params->curr_bank;
1597
1598 prop = &ctrl->bus.prop;
1599 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1600 prop->num_clk_gears = 0;
1601 prop->num_clk_freq = MAX_FREQ_NUM;
1602 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1603 prop->default_col = data->default_cols;
1604 prop->default_row = data->default_rows;
1605
1606 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1607
1608 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1609 qcom_swrm_irq_handler,
1610 IRQF_TRIGGER_RISING |
1611 IRQF_ONESHOT,
1612 "soundwire", ctrl);
1613 if (ret) {
1614 dev_err(dev, "Failed to request soundwire irq\n");
1615 goto err_clk;
1616 }
1617
1618 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1619 if (ctrl->wake_irq > 0) {
1620 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1621 qcom_swrm_wake_irq_handler,
1622 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1623 "swr_wake_irq", ctrl);
1624 if (ret) {
1625 dev_err(dev, "Failed to request soundwire wake irq\n");
1626 goto err_init;
1627 }
1628 }
1629
1630 ctrl->bus.controller_id = -1;
1631
1632 if (ctrl->version > SWRM_VERSION_1_3_0) {
1633 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1634 ctrl->bus.controller_id = val;
1635 }
1636
1637 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1638 if (ret) {
1639 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1640 ret);
1641 goto err_clk;
1642 }
1643
1644 qcom_swrm_init(ctrl);
1645 wait_for_completion_timeout(&ctrl->enumeration,
1646 msecs_to_jiffies(TIMEOUT_MS));
1647 ret = qcom_swrm_register_dais(ctrl);
1648 if (ret)
1649 goto err_master_add;
1650
1651 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1652 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1653 ctrl->version & 0xffff);
1654
1655 pm_runtime_set_autosuspend_delay(dev, 3000);
1656 pm_runtime_use_autosuspend(dev);
1657 pm_runtime_mark_last_busy(dev);
1658 pm_runtime_set_active(dev);
1659 pm_runtime_enable(dev);
1660
1661 #ifdef CONFIG_DEBUG_FS
1662 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1663 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1664 &swrm_reg_fops);
1665 #endif
1666
1667 return 0;
1668
1669 err_master_add:
1670 sdw_bus_master_delete(&ctrl->bus);
1671 err_clk:
1672 clk_disable_unprepare(ctrl->hclk);
1673 err_init:
1674 return ret;
1675 }
1676
1677 static void qcom_swrm_remove(struct platform_device *pdev)
1678 {
1679 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1680
1681 sdw_bus_master_delete(&ctrl->bus);
1682 clk_disable_unprepare(ctrl->hclk);
1683 }
1684
1685 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1686 {
1687 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1688 int ret;
1689
1690 if (ctrl->wake_irq > 0) {
1691 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1692 disable_irq_nosync(ctrl->wake_irq);
1693 }
1694
1695 clk_prepare_enable(ctrl->hclk);
1696
1697 if (ctrl->clock_stop_not_supported) {
1698 reinit_completion(&ctrl->enumeration);
1699 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1700 usleep_range(100, 105);
1701
1702 qcom_swrm_init(ctrl);
1703
1704 usleep_range(100, 105);
1705 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1706 dev_err(ctrl->dev, "link failed to connect\n");
1707
1708 /* wait for hw enumeration to complete */
1709 wait_for_completion_timeout(&ctrl->enumeration,
1710 msecs_to_jiffies(TIMEOUT_MS));
1711 qcom_swrm_get_device_status(ctrl);
1712 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1713 } else {
1714 reset_control_reset(ctrl->audio_cgcr);
1715
1716 if (ctrl->version == SWRM_VERSION_1_7_0) {
1717 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1718 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1719 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1720 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1721 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1722 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1723 SWRM_V2_0_CLK_CTRL_CLK_START);
1724 } else {
1725 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1726 }
1727 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1728 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1729
1730 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1731 if (ctrl->version < SWRM_VERSION_2_0_0)
1732 ctrl->reg_write(ctrl,
1733 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1734 ctrl->intr_mask);
1735 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1736 ctrl->intr_mask);
1737
1738 usleep_range(100, 105);
1739 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1740 dev_err(ctrl->dev, "link failed to connect\n");
1741
1742 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1743 if (ret < 0)
1744 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1745 }
1746
1747 return 0;
1748 }
1749
1750 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1751 {
1752 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1753 int ret;
1754
1755 swrm_wait_for_wr_fifo_done(ctrl);
1756 if (!ctrl->clock_stop_not_supported) {
1757 /* Mask bus clash interrupt */
1758 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1759 if (ctrl->version < SWRM_VERSION_2_0_0)
1760 ctrl->reg_write(ctrl,
1761 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1762 ctrl->intr_mask);
1763 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1764 ctrl->intr_mask);
1765 /* Prepare slaves for clock stop */
1766 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1767 if (ret < 0 && ret != -ENODATA) {
1768 dev_err(dev, "prepare clock stop failed %d", ret);
1769 return ret;
1770 }
1771
1772 ret = sdw_bus_clk_stop(&ctrl->bus);
1773 if (ret < 0 && ret != -ENODATA) {
1774 dev_err(dev, "bus clock stop failed %d", ret);
1775 return ret;
1776 }
1777 }
1778
1779 clk_disable_unprepare(ctrl->hclk);
1780
1781 usleep_range(300, 305);
1782
1783 if (ctrl->wake_irq > 0) {
1784 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1785 enable_irq(ctrl->wake_irq);
1786 }
1787
1788 return 0;
1789 }
1790
1791 static const struct dev_pm_ops swrm_dev_pm_ops = {
1792 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1793 };
1794
1795 static const struct of_device_id qcom_swrm_of_match[] = {
1796 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1797 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1798 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1799 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1800 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1801 {/* sentinel */},
1802 };
1803
1804 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1805
1806 static struct platform_driver qcom_swrm_driver = {
1807 .probe = &qcom_swrm_probe,
1808 .remove = qcom_swrm_remove,
1809 .driver = {
1810 .name = "qcom-soundwire",
1811 .of_match_table = qcom_swrm_of_match,
1812 .pm = &swrm_dev_pm_ops,
1813 }
1814 };
1815 module_platform_driver(qcom_swrm_driver);
1816
1817 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1818 MODULE_LICENSE("GPL v2");
1819