1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
3
4 /*
5 * Bandwidth management algorithm based on 2^n gears
6 *
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/device.h>
11 #include <linux/module.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/slab.h>
14 #include <linux/soundwire/sdw.h>
15 #include "bus.h"
16
17 #define SDW_STRM_RATE_GROUPING 1
18
19 struct sdw_group_params {
20 unsigned int rate;
21 unsigned int lane;
22 int full_bw;
23 int payload_bw;
24 int hwidth;
25 };
26
27 struct sdw_group {
28 unsigned int count;
29 unsigned int max_size;
30 unsigned int *rates;
31 unsigned int *lanes;
32 };
33
sdw_compute_slave_ports(struct sdw_master_runtime * m_rt,struct sdw_transport_data * t_data)34 void sdw_compute_slave_ports(struct sdw_master_runtime *m_rt,
35 struct sdw_transport_data *t_data)
36 {
37 struct sdw_slave_runtime *s_rt = NULL;
38 struct sdw_port_runtime *p_rt;
39 int port_bo, sample_int;
40 unsigned int rate, bps, ch = 0;
41 unsigned int slave_total_ch;
42 struct sdw_bus_params *b_params = &m_rt->bus->params;
43
44 port_bo = t_data->block_offset;
45
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
47 rate = m_rt->stream->params.rate;
48 bps = m_rt->stream->params.bps;
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate);
50 slave_total_ch = 0;
51
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
53 if (p_rt->lane != t_data->lane)
54 continue;
55
56 ch = hweight32(p_rt->ch_mask);
57
58 sdw_fill_xport_params(&p_rt->transport_params,
59 p_rt->num, false,
60 SDW_BLK_GRP_CNT_1,
61 sample_int, port_bo, port_bo >> 8,
62 t_data->hstart,
63 t_data->hstop,
64 SDW_BLK_PKG_PER_PORT, p_rt->lane);
65
66 sdw_fill_port_params(&p_rt->port_params,
67 p_rt->num, bps,
68 SDW_PORT_FLOW_MODE_ISOCH,
69 b_params->s_data_mode);
70
71 port_bo += bps * ch;
72 slave_total_ch += ch;
73 }
74
75 if (m_rt->direction == SDW_DATA_DIR_TX &&
76 m_rt->ch_count == slave_total_ch) {
77 /*
78 * Slave devices were configured to access all channels
79 * of the stream, which indicates that they operate in
80 * 'mirror mode'. Make sure we reset the port offset for
81 * the next device in the list
82 */
83 port_bo = t_data->block_offset;
84 }
85 }
86 }
87 EXPORT_SYMBOL(sdw_compute_slave_ports);
88
sdw_compute_dp0_slave_ports(struct sdw_master_runtime * m_rt)89 static void sdw_compute_dp0_slave_ports(struct sdw_master_runtime *m_rt)
90 {
91 struct sdw_bus *bus = m_rt->bus;
92 struct sdw_slave_runtime *s_rt;
93 struct sdw_port_runtime *p_rt;
94
95 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
96 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
97 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, false,
98 SDW_BLK_GRP_CNT_1, bus->params.col, 0, 0, 1,
99 bus->params.col - 1, SDW_BLK_PKG_PER_PORT, 0x0);
100
101 sdw_fill_port_params(&p_rt->port_params, p_rt->num, bus->params.col - 1,
102 SDW_PORT_FLOW_MODE_ISOCH, SDW_PORT_DATA_MODE_NORMAL);
103 }
104 }
105 }
106
sdw_compute_dp0_master_ports(struct sdw_master_runtime * m_rt)107 static void sdw_compute_dp0_master_ports(struct sdw_master_runtime *m_rt)
108 {
109 struct sdw_port_runtime *p_rt;
110 struct sdw_bus *bus = m_rt->bus;
111
112 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
113 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num, false,
114 SDW_BLK_GRP_CNT_1, bus->params.col, 0, 0, 1,
115 bus->params.col - 1, SDW_BLK_PKG_PER_PORT, 0x0);
116
117 sdw_fill_port_params(&p_rt->port_params, p_rt->num, bus->params.col - 1,
118 SDW_PORT_FLOW_MODE_ISOCH, SDW_PORT_DATA_MODE_NORMAL);
119 }
120 }
121
sdw_compute_dp0_port_params(struct sdw_bus * bus)122 static void sdw_compute_dp0_port_params(struct sdw_bus *bus)
123 {
124 struct sdw_master_runtime *m_rt;
125
126 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
127 sdw_compute_dp0_master_ports(m_rt);
128 sdw_compute_dp0_slave_ports(m_rt);
129 }
130 }
131
sdw_compute_master_ports(struct sdw_master_runtime * m_rt,struct sdw_group_params * params,int * port_bo,int hstop)132 static void sdw_compute_master_ports(struct sdw_master_runtime *m_rt,
133 struct sdw_group_params *params,
134 int *port_bo, int hstop)
135 {
136 struct sdw_transport_data t_data = {0};
137 struct sdw_port_runtime *p_rt;
138 struct sdw_bus *bus = m_rt->bus;
139 struct sdw_bus_params *b_params = &bus->params;
140 int sample_int, hstart = 0;
141 unsigned int rate, bps, ch;
142
143 rate = m_rt->stream->params.rate;
144 bps = m_rt->stream->params.bps;
145 ch = m_rt->ch_count;
146 sample_int = (bus->params.curr_dr_freq / rate);
147
148 if (rate != params->rate)
149 return;
150
151 t_data.hstop = hstop;
152 hstart = hstop - params->hwidth + 1;
153 t_data.hstart = hstart;
154
155 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
156 if (p_rt->lane != params->lane)
157 continue;
158
159 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
160 false, SDW_BLK_GRP_CNT_1, sample_int,
161 *port_bo, (*port_bo) >> 8, hstart, hstop,
162 SDW_BLK_PKG_PER_PORT, p_rt->lane);
163
164 sdw_fill_port_params(&p_rt->port_params,
165 p_rt->num, bps,
166 SDW_PORT_FLOW_MODE_ISOCH,
167 b_params->m_data_mode);
168
169 /* Check for first entry */
170 if (!(p_rt == list_first_entry(&m_rt->port_list,
171 struct sdw_port_runtime,
172 port_node))) {
173 (*port_bo) += bps * ch;
174 continue;
175 }
176
177 t_data.hstart = hstart;
178 t_data.hstop = hstop;
179 t_data.block_offset = *port_bo;
180 t_data.sub_block_offset = 0;
181 (*port_bo) += bps * ch;
182 }
183
184 t_data.lane = params->lane;
185 sdw_compute_slave_ports(m_rt, &t_data);
186 }
187
_sdw_compute_port_params(struct sdw_bus * bus,struct sdw_group_params * params,int count)188 static void _sdw_compute_port_params(struct sdw_bus *bus,
189 struct sdw_group_params *params, int count)
190 {
191 struct sdw_master_runtime *m_rt;
192 int port_bo, i, l;
193 int hstop;
194
195 /* Run loop for all groups to compute transport parameters */
196 for (l = 0; l < SDW_MAX_LANES; l++) {
197 if (l > 0 && !bus->lane_used_bandwidth[l])
198 continue;
199 /* reset hstop for each lane */
200 hstop = bus->params.col - 1;
201 for (i = 0; i < count; i++) {
202 if (params[i].lane != l)
203 continue;
204 port_bo = 1;
205
206 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
207 sdw_compute_master_ports(m_rt, ¶ms[i], &port_bo, hstop);
208 }
209
210 hstop = hstop - params[i].hwidth;
211 }
212 }
213 }
214
sdw_compute_group_params(struct sdw_bus * bus,struct sdw_stream_runtime * stream,struct sdw_group_params * params,struct sdw_group * group)215 static int sdw_compute_group_params(struct sdw_bus *bus,
216 struct sdw_stream_runtime *stream,
217 struct sdw_group_params *params,
218 struct sdw_group *group)
219 {
220 struct sdw_master_runtime *m_rt;
221 struct sdw_port_runtime *p_rt;
222 int sel_col = bus->params.col;
223 unsigned int rate, bps, ch;
224 int i, l, column_needed;
225
226 /* Calculate bandwidth per group */
227 for (i = 0; i < group->count; i++) {
228 params[i].rate = group->rates[i];
229 params[i].lane = group->lanes[i];
230 params[i].full_bw = bus->params.curr_dr_freq / params[i].rate;
231 }
232
233 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
234 if (m_rt->stream == stream) {
235 /* Only runtime during prepare should be added */
236 if (stream->state != SDW_STREAM_CONFIGURED)
237 continue;
238 } else {
239 /*
240 * Include runtimes with running (ENABLED/PREPARED state) and
241 * paused (DISABLED state) streams
242 */
243 if (m_rt->stream->state != SDW_STREAM_ENABLED &&
244 m_rt->stream->state != SDW_STREAM_PREPARED &&
245 m_rt->stream->state != SDW_STREAM_DISABLED)
246 continue;
247 }
248 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
249 rate = m_rt->stream->params.rate;
250 bps = m_rt->stream->params.bps;
251 ch = hweight32(p_rt->ch_mask);
252
253 for (i = 0; i < group->count; i++) {
254 if (rate == params[i].rate && p_rt->lane == params[i].lane)
255 params[i].payload_bw += bps * ch;
256 }
257 }
258 }
259
260 for (l = 0; l < SDW_MAX_LANES; l++) {
261 if (l > 0 && !bus->lane_used_bandwidth[l])
262 continue;
263 /* reset column_needed for each lane */
264 column_needed = 0;
265 for (i = 0; i < group->count; i++) {
266 if (params[i].lane != l)
267 continue;
268
269 params[i].hwidth = (sel_col * params[i].payload_bw +
270 params[i].full_bw - 1) / params[i].full_bw;
271
272 column_needed += params[i].hwidth;
273 /* There is no control column for lane 1 and above */
274 if (column_needed > sel_col)
275 return -EINVAL;
276 /* Column 0 is control column on lane 0 */
277 if (params[i].lane == 0 && column_needed > sel_col - 1)
278 return -EINVAL;
279 }
280 }
281
282
283 return 0;
284 }
285
sdw_add_element_group_count(struct sdw_group * group,unsigned int rate,unsigned int lane)286 static int sdw_add_element_group_count(struct sdw_group *group,
287 unsigned int rate, unsigned int lane)
288 {
289 int num = group->count;
290 int i;
291
292 for (i = 0; i <= num; i++) {
293 if (rate == group->rates[i] && lane == group->lanes[i])
294 break;
295
296 if (i != num)
297 continue;
298
299 if (group->count >= group->max_size) {
300 unsigned int *rates;
301 unsigned int *lanes;
302
303 group->max_size += 1;
304 rates = krealloc(group->rates,
305 (sizeof(int) * group->max_size),
306 GFP_KERNEL);
307 if (!rates)
308 return -ENOMEM;
309
310 group->rates = rates;
311
312 lanes = krealloc(group->lanes,
313 (sizeof(int) * group->max_size),
314 GFP_KERNEL);
315 if (!lanes)
316 return -ENOMEM;
317
318 group->lanes = lanes;
319 }
320
321 group->rates[group->count] = rate;
322 group->lanes[group->count++] = lane;
323 }
324
325 return 0;
326 }
327
sdw_get_group_count(struct sdw_bus * bus,struct sdw_group * group)328 static int sdw_get_group_count(struct sdw_bus *bus,
329 struct sdw_group *group)
330 {
331 struct sdw_master_runtime *m_rt;
332 struct sdw_port_runtime *p_rt;
333 unsigned int rate;
334 int ret = 0;
335
336 group->count = 0;
337 group->max_size = SDW_STRM_RATE_GROUPING;
338 group->rates = kcalloc(group->max_size, sizeof(int), GFP_KERNEL);
339 if (!group->rates)
340 return -ENOMEM;
341
342 group->lanes = kcalloc(group->max_size, sizeof(int), GFP_KERNEL);
343 if (!group->lanes) {
344 kfree(group->rates);
345 group->rates = NULL;
346 return -ENOMEM;
347 }
348
349 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
350 if (m_rt->stream->state == SDW_STREAM_DEPREPARED)
351 continue;
352
353 rate = m_rt->stream->params.rate;
354 if (m_rt == list_first_entry(&bus->m_rt_list,
355 struct sdw_master_runtime,
356 bus_node)) {
357 group->rates[group->count++] = rate;
358 }
359 /*
360 * Different ports could use different lane, add group element
361 * even if m_rt is the first entry
362 */
363 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
364 ret = sdw_add_element_group_count(group, rate, p_rt->lane);
365 if (ret < 0) {
366 kfree(group->rates);
367 kfree(group->lanes);
368 return ret;
369 }
370 }
371 }
372
373 return ret;
374 }
375
376 /**
377 * sdw_compute_port_params: Compute transport and port parameters
378 *
379 * @bus: SDW Bus instance
380 * @stream: Soundwire stream
381 */
sdw_compute_port_params(struct sdw_bus * bus,struct sdw_stream_runtime * stream)382 static int sdw_compute_port_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
383 {
384 struct sdw_group_params *params = NULL;
385 struct sdw_group group;
386 int ret;
387
388 ret = sdw_get_group_count(bus, &group);
389 if (ret < 0)
390 return ret;
391
392 if (group.count == 0)
393 goto out;
394
395 params = kcalloc(group.count, sizeof(*params), GFP_KERNEL);
396 if (!params) {
397 ret = -ENOMEM;
398 goto out;
399 }
400
401 /* Compute transport parameters for grouped streams */
402 ret = sdw_compute_group_params(bus, stream, params, &group);
403 if (ret < 0)
404 goto free_params;
405
406 _sdw_compute_port_params(bus, params, group.count);
407
408 free_params:
409 kfree(params);
410 out:
411 kfree(group.rates);
412 kfree(group.lanes);
413
414 return ret;
415 }
416
sdw_select_row_col(struct sdw_bus * bus,int clk_freq)417 static int sdw_select_row_col(struct sdw_bus *bus, int clk_freq)
418 {
419 struct sdw_master_prop *prop = &bus->prop;
420 int r, c;
421
422 for (c = 0; c < SDW_FRAME_COLS; c++) {
423 for (r = 0; r < SDW_FRAME_ROWS; r++) {
424 if (sdw_rows[r] != prop->default_row ||
425 sdw_cols[c] != prop->default_col)
426 continue;
427
428 if (clk_freq * (sdw_cols[c] - 1) <
429 bus->params.bandwidth * sdw_cols[c])
430 continue;
431
432 bus->params.row = sdw_rows[r];
433 bus->params.col = sdw_cols[c];
434 return 0;
435 }
436 }
437
438 return -EINVAL;
439 }
440
is_clock_scaling_supported(struct sdw_bus * bus)441 static bool is_clock_scaling_supported(struct sdw_bus *bus)
442 {
443 struct sdw_master_runtime *m_rt;
444 struct sdw_slave_runtime *s_rt;
445
446 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node)
447 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node)
448 if (!is_clock_scaling_supported_by_slave(s_rt->slave))
449 return false;
450
451 return true;
452 }
453
454 /**
455 * is_lane_connected_to_all_peripherals: Check if the given manager lane connects to all peripherals
456 * So that all peripherals can use the manager lane.
457 *
458 * @m_rt: Manager runtime
459 * @lane: Lane number
460 */
is_lane_connected_to_all_peripherals(struct sdw_master_runtime * m_rt,unsigned int lane)461 static bool is_lane_connected_to_all_peripherals(struct sdw_master_runtime *m_rt, unsigned int lane)
462 {
463 struct sdw_slave_prop *slave_prop;
464 struct sdw_slave_runtime *s_rt;
465 int i;
466
467 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
468 slave_prop = &s_rt->slave->prop;
469 for (i = 1; i < SDW_MAX_LANES; i++) {
470 if (slave_prop->lane_maps[i] == lane) {
471 dev_dbg(&s_rt->slave->dev,
472 "M lane %d is connected to P lane %d\n",
473 lane, i);
474 break;
475 }
476 }
477 if (i == SDW_MAX_LANES) {
478 dev_dbg(&s_rt->slave->dev, "M lane %d is not connected\n", lane);
479 return false;
480 }
481 }
482 return true;
483 }
484
get_manager_lane(struct sdw_bus * bus,struct sdw_master_runtime * m_rt,struct sdw_slave_runtime * s_rt,unsigned int curr_dr_freq)485 static int get_manager_lane(struct sdw_bus *bus, struct sdw_master_runtime *m_rt,
486 struct sdw_slave_runtime *s_rt, unsigned int curr_dr_freq)
487 {
488 struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
489 struct sdw_port_runtime *m_p_rt;
490 unsigned int required_bandwidth;
491 int m_lane;
492 int l;
493
494 for (l = 1; l < SDW_MAX_LANES; l++) {
495 if (!slave_prop->lane_maps[l])
496 continue;
497
498 required_bandwidth = 0;
499 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) {
500 required_bandwidth += m_rt->stream->params.rate *
501 hweight32(m_p_rt->ch_mask) *
502 m_rt->stream->params.bps;
503 }
504 if (required_bandwidth <=
505 curr_dr_freq - bus->lane_used_bandwidth[l]) {
506 /* Check if m_lane is connected to all Peripherals */
507 if (!is_lane_connected_to_all_peripherals(m_rt,
508 slave_prop->lane_maps[l])) {
509 dev_dbg(bus->dev,
510 "Not all Peripherals are connected to M lane %d\n",
511 slave_prop->lane_maps[l]);
512 continue;
513 }
514 m_lane = slave_prop->lane_maps[l];
515 dev_dbg(&s_rt->slave->dev, "M lane %d is used\n", m_lane);
516 bus->lane_used_bandwidth[l] += required_bandwidth;
517 /*
518 * Use non-zero manager lane, subtract the lane 0
519 * bandwidth that is already calculated
520 */
521 bus->params.bandwidth -= required_bandwidth;
522 return m_lane;
523 }
524 }
525
526 /* No available multi lane found, only lane 0 can be used */
527 return 0;
528 }
529
530 /**
531 * sdw_compute_bus_params: Compute bus parameters
532 *
533 * @bus: SDW Bus instance
534 */
sdw_compute_bus_params(struct sdw_bus * bus)535 static int sdw_compute_bus_params(struct sdw_bus *bus)
536 {
537 struct sdw_master_prop *mstr_prop = &bus->prop;
538 struct sdw_slave_prop *slave_prop;
539 struct sdw_port_runtime *m_p_rt;
540 struct sdw_port_runtime *s_p_rt;
541 struct sdw_master_runtime *m_rt;
542 struct sdw_slave_runtime *s_rt;
543 unsigned int curr_dr_freq = 0;
544 int i, l, clk_values, ret;
545 bool is_gear = false;
546 int m_lane = 0;
547 u32 *clk_buf;
548
549 if (mstr_prop->num_clk_gears) {
550 clk_values = mstr_prop->num_clk_gears;
551 clk_buf = mstr_prop->clk_gears;
552 is_gear = true;
553 } else if (mstr_prop->num_clk_freq) {
554 clk_values = mstr_prop->num_clk_freq;
555 clk_buf = mstr_prop->clk_freq;
556 } else {
557 clk_values = 1;
558 clk_buf = NULL;
559 }
560
561 /* If dynamic scaling is not supported, don't try higher freq */
562 if (!is_clock_scaling_supported(bus))
563 clk_values = 1;
564
565 for (i = 0; i < clk_values; i++) {
566 if (!clk_buf)
567 curr_dr_freq = bus->params.max_dr_freq;
568 else
569 curr_dr_freq = (is_gear) ?
570 (bus->params.max_dr_freq >> clk_buf[i]) :
571 clk_buf[i] * SDW_DOUBLE_RATE_FACTOR;
572
573 if (curr_dr_freq * (mstr_prop->default_col - 1) >=
574 bus->params.bandwidth * mstr_prop->default_col)
575 break;
576
577 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
578 /*
579 * Get the first s_rt that will be used to find the available lane that
580 * can be used. No need to check all Peripherals because we can't use
581 * multi-lane if we can't find any available lane for the first Peripheral.
582 */
583 s_rt = list_first_entry(&m_rt->slave_rt_list,
584 struct sdw_slave_runtime, m_rt_node);
585
586 /*
587 * Find the available Manager lane that connected to the first Peripheral.
588 */
589 m_lane = get_manager_lane(bus, m_rt, s_rt, curr_dr_freq);
590 if (m_lane > 0)
591 goto out;
592 }
593
594 /*
595 * TODO: Check all the Slave(s) port(s) audio modes and find
596 * whether given clock rate is supported with glitchless
597 * transition.
598 */
599 }
600
601 if (i == clk_values) {
602 dev_err(bus->dev, "%s: could not find clock value for bandwidth %d\n",
603 __func__, bus->params.bandwidth);
604 return -EINVAL;
605 }
606 out:
607 /* multilane can be used */
608 if (m_lane > 0) {
609 /* Set Peripheral lanes */
610 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
611 slave_prop = &s_rt->slave->prop;
612 for (l = 1; l < SDW_MAX_LANES; l++) {
613 if (slave_prop->lane_maps[l] == m_lane) {
614 list_for_each_entry(s_p_rt, &s_rt->port_list, port_node) {
615 s_p_rt->lane = l;
616 dev_dbg(&s_rt->slave->dev,
617 "Set P lane %d for port %d\n",
618 l, s_p_rt->num);
619 }
620 break;
621 }
622 }
623 }
624 /*
625 * Set Manager lanes. Configure the last m_rt in bus->m_rt_list only since
626 * we don't want to touch other m_rts that are already working.
627 */
628 list_for_each_entry(m_p_rt, &m_rt->port_list, port_node) {
629 m_p_rt->lane = m_lane;
630 }
631 }
632
633 if (!mstr_prop->default_frame_rate || !mstr_prop->default_row)
634 return -EINVAL;
635
636 mstr_prop->default_col = curr_dr_freq / mstr_prop->default_frame_rate /
637 mstr_prop->default_row;
638
639 ret = sdw_select_row_col(bus, curr_dr_freq);
640 if (ret < 0) {
641 dev_err(bus->dev, "%s: could not find frame configuration for bus dr_freq %d\n",
642 __func__, curr_dr_freq);
643 return -EINVAL;
644 }
645
646 bus->params.curr_dr_freq = curr_dr_freq;
647 return 0;
648 }
649
650 /**
651 * sdw_compute_params: Compute bus, transport and port parameters
652 *
653 * @bus: SDW Bus instance
654 * @stream: Soundwire stream
655 */
sdw_compute_params(struct sdw_bus * bus,struct sdw_stream_runtime * stream)656 int sdw_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
657 {
658 int ret;
659
660 /* Computes clock frequency, frame shape and frame frequency */
661 ret = sdw_compute_bus_params(bus);
662 if (ret < 0)
663 return ret;
664
665 if (stream->type == SDW_STREAM_BPT) {
666 sdw_compute_dp0_port_params(bus);
667 return 0;
668 }
669
670 /* Compute transport and port params */
671 ret = sdw_compute_port_params(bus, stream);
672 if (ret < 0) {
673 dev_err(bus->dev, "Compute transport params failed: %d\n", ret);
674 return ret;
675 }
676
677 return 0;
678 }
679 EXPORT_SYMBOL(sdw_compute_params);
680
681 MODULE_LICENSE("Dual BSD/GPL");
682 MODULE_DESCRIPTION("SoundWire Generic Bandwidth Allocation");
683