1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas RZ/N1 Real Time Clock interface for Linux
4 *
5 * Copyright:
6 * - 2014 Renesas Electronics Europe Limited
7 * - 2022 Schneider Electric
8 *
9 * Authors:
10 * - Michel Pollet <buserror@gmail.com>
11 * - Miquel Raynal <miquel.raynal@bootlin.com>
12 */
13
14 #include <linux/bcd.h>
15 #include <linux/init.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/rtc.h>
22 #include <linux/spinlock.h>
23
24 #define RZN1_RTC_CTL0 0x00
25 #define RZN1_RTC_CTL0_SLSB_SUBU 0
26 #define RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
27 #define RZN1_RTC_CTL0_AMPM BIT(5)
28 #define RZN1_RTC_CTL0_CE BIT(7)
29
30 #define RZN1_RTC_CTL1 0x04
31 #define RZN1_RTC_CTL1_1SE BIT(3)
32 #define RZN1_RTC_CTL1_ALME BIT(4)
33
34 #define RZN1_RTC_CTL2 0x08
35 #define RZN1_RTC_CTL2_WAIT BIT(0)
36 #define RZN1_RTC_CTL2_WST BIT(1)
37 #define RZN1_RTC_CTL2_WUST BIT(5)
38 #define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST)
39
40 #define RZN1_RTC_TIME 0x30
41 #define RZN1_RTC_TIME_MIN_SHIFT 8
42 #define RZN1_RTC_TIME_HOUR_SHIFT 16
43 #define RZN1_RTC_CAL 0x34
44 #define RZN1_RTC_CAL_DAY_SHIFT 8
45 #define RZN1_RTC_CAL_MON_SHIFT 16
46 #define RZN1_RTC_CAL_YEAR_SHIFT 24
47
48 #define RZN1_RTC_SUBU 0x38
49 #define RZN1_RTC_SUBU_DEV BIT(7)
50 #define RZN1_RTC_SUBU_DECR BIT(6)
51
52 #define RZN1_RTC_ALM 0x40
53 #define RZN1_RTC_ALH 0x44
54 #define RZN1_RTC_ALW 0x48
55
56 #define RZN1_RTC_SECC 0x4c
57 #define RZN1_RTC_TIMEC 0x68
58 #define RZN1_RTC_CALC 0x6c
59
60 struct rzn1_rtc {
61 struct rtc_device *rtcdev;
62 void __iomem *base;
63 /*
64 * Protects access to RZN1_RTC_CTL1 reg. rtc_lock with threaded_irqs
65 * would introduce race conditions when switching interrupts because
66 * of potential sleeps
67 */
68 spinlock_t ctl1_access_lock;
69 struct rtc_time tm_alarm;
70 };
71
rzn1_rtc_get_time_snapshot(struct rzn1_rtc * rtc,struct rtc_time * tm)72 static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm)
73 {
74 u32 val;
75
76 val = readl(rtc->base + RZN1_RTC_TIMEC);
77 tm->tm_sec = bcd2bin(val);
78 tm->tm_min = bcd2bin(val >> RZN1_RTC_TIME_MIN_SHIFT);
79 tm->tm_hour = bcd2bin(val >> RZN1_RTC_TIME_HOUR_SHIFT);
80
81 val = readl(rtc->base + RZN1_RTC_CALC);
82 tm->tm_wday = val & 0x0f;
83 tm->tm_mday = bcd2bin(val >> RZN1_RTC_CAL_DAY_SHIFT);
84 tm->tm_mon = bcd2bin(val >> RZN1_RTC_CAL_MON_SHIFT) - 1;
85 tm->tm_year = bcd2bin(val >> RZN1_RTC_CAL_YEAR_SHIFT) + 100;
86 }
87
rzn1_rtc_read_time(struct device * dev,struct rtc_time * tm)88 static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm)
89 {
90 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
91 u32 val, secs;
92
93 /*
94 * The RTC was not started or is stopped and thus does not carry the
95 * proper time/date.
96 */
97 val = readl(rtc->base + RZN1_RTC_CTL2);
98 if (val & RZN1_RTC_CTL2_STOPPED)
99 return -EINVAL;
100
101 rzn1_rtc_get_time_snapshot(rtc, tm);
102 secs = readl(rtc->base + RZN1_RTC_SECC);
103 if (tm->tm_sec != bcd2bin(secs))
104 rzn1_rtc_get_time_snapshot(rtc, tm);
105
106 return 0;
107 }
108
rzn1_rtc_set_time(struct device * dev,struct rtc_time * tm)109 static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm)
110 {
111 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
112 u32 val;
113 int ret;
114
115 val = readl(rtc->base + RZN1_RTC_CTL2);
116 if (!(val & RZN1_RTC_CTL2_STOPPED)) {
117 /* Hold the counter if it was counting up */
118 writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2);
119
120 /* Wait for the counter to stop: two 32k clock cycles */
121 usleep_range(61, 100);
122 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
123 val & RZN1_RTC_CTL2_WST, 0, 100);
124 if (ret)
125 return ret;
126 }
127
128 val = bin2bcd(tm->tm_sec);
129 val |= bin2bcd(tm->tm_min) << RZN1_RTC_TIME_MIN_SHIFT;
130 val |= bin2bcd(tm->tm_hour) << RZN1_RTC_TIME_HOUR_SHIFT;
131 writel(val, rtc->base + RZN1_RTC_TIME);
132
133 val = tm->tm_wday;
134 val |= bin2bcd(tm->tm_mday) << RZN1_RTC_CAL_DAY_SHIFT;
135 val |= bin2bcd(tm->tm_mon + 1) << RZN1_RTC_CAL_MON_SHIFT;
136 val |= bin2bcd(tm->tm_year - 100) << RZN1_RTC_CAL_YEAR_SHIFT;
137 writel(val, rtc->base + RZN1_RTC_CAL);
138
139 writel(0, rtc->base + RZN1_RTC_CTL2);
140
141 return 0;
142 }
143
rzn1_rtc_alarm_irq(int irq,void * dev_id)144 static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id)
145 {
146 struct rzn1_rtc *rtc = dev_id;
147 u32 ctl1, set_irq_bits = 0;
148
149 if (rtc->tm_alarm.tm_sec == 0)
150 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
151 else
152 /* Switch to 1s interrupts */
153 set_irq_bits = RZN1_RTC_CTL1_1SE;
154
155 guard(spinlock)(&rtc->ctl1_access_lock);
156
157 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
158 ctl1 &= ~RZN1_RTC_CTL1_ALME;
159 ctl1 |= set_irq_bits;
160 writel(ctl1, rtc->base + RZN1_RTC_CTL1);
161
162 return IRQ_HANDLED;
163 }
164
rzn1_rtc_1s_irq(int irq,void * dev_id)165 static irqreturn_t rzn1_rtc_1s_irq(int irq, void *dev_id)
166 {
167 struct rzn1_rtc *rtc = dev_id;
168 u32 ctl1;
169
170 if (readl(rtc->base + RZN1_RTC_SECC) == bin2bcd(rtc->tm_alarm.tm_sec)) {
171 guard(spinlock)(&rtc->ctl1_access_lock);
172
173 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
174 ctl1 &= ~RZN1_RTC_CTL1_1SE;
175 writel(ctl1, rtc->base + RZN1_RTC_CTL1);
176
177 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
178 }
179
180 return IRQ_HANDLED;
181 }
182
rzn1_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)183 static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
184 {
185 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
186 struct rtc_time *tm = &rtc->tm_alarm, tm_now;
187 u32 ctl1;
188 int ret;
189
190 guard(spinlock_irqsave)(&rtc->ctl1_access_lock);
191
192 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
193
194 if (enable) {
195 /*
196 * Use alarm interrupt if alarm time is at least a minute away
197 * or less than a minute but in the next minute. Otherwise use
198 * 1 second interrupt to wait for the proper second
199 */
200 do {
201 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE);
202
203 ret = rzn1_rtc_read_time(dev, &tm_now);
204 if (ret)
205 return ret;
206
207 if (rtc_tm_sub(tm, &tm_now) > 59 || tm->tm_min != tm_now.tm_min)
208 ctl1 |= RZN1_RTC_CTL1_ALME;
209 else
210 ctl1 |= RZN1_RTC_CTL1_1SE;
211
212 writel(ctl1, rtc->base + RZN1_RTC_CTL1);
213 } while (readl(rtc->base + RZN1_RTC_SECC) != bin2bcd(tm_now.tm_sec));
214 } else {
215 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE);
216 writel(ctl1, rtc->base + RZN1_RTC_CTL1);
217 }
218
219 return 0;
220 }
221
rzn1_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)222 static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
223 {
224 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
225 struct rtc_time *tm = &alrm->time;
226 unsigned int min, hour, wday, delta_days;
227 time64_t alarm;
228 u32 ctl1;
229 int ret;
230
231 ret = rzn1_rtc_read_time(dev, tm);
232 if (ret)
233 return ret;
234
235 min = readl(rtc->base + RZN1_RTC_ALM);
236 hour = readl(rtc->base + RZN1_RTC_ALH);
237 wday = readl(rtc->base + RZN1_RTC_ALW);
238
239 tm->tm_sec = 0;
240 tm->tm_min = bcd2bin(min);
241 tm->tm_hour = bcd2bin(hour);
242 delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7;
243 tm->tm_wday = fls(wday) - 1;
244
245 if (delta_days) {
246 alarm = rtc_tm_to_time64(tm) + (delta_days * 86400);
247 rtc_time64_to_tm(alarm, tm);
248 }
249
250 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
251 alrm->enabled = !!(ctl1 & (RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE));
252
253 return 0;
254 }
255
rzn1_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)256 static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
257 {
258 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
259 struct rtc_time *tm = &alrm->time, tm_now;
260 unsigned long alarm, farest;
261 unsigned int days_ahead, wday;
262 int ret;
263
264 ret = rzn1_rtc_read_time(dev, &tm_now);
265 if (ret)
266 return ret;
267
268 /* We cannot set alarms more than one week ahead */
269 farest = rtc_tm_to_time64(&tm_now) + rtc->rtcdev->alarm_offset_max;
270 alarm = rtc_tm_to_time64(tm);
271 if (time_after(alarm, farest))
272 return -ERANGE;
273
274 /* Convert alarm day into week day */
275 days_ahead = tm->tm_mday - tm_now.tm_mday;
276 wday = (tm_now.tm_wday + days_ahead) % 7;
277
278 writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);
279 writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH);
280 writel(BIT(wday), rtc->base + RZN1_RTC_ALW);
281
282 rtc->tm_alarm = alrm->time;
283
284 rzn1_rtc_alarm_irq_enable(dev, alrm->enabled);
285
286 return 0;
287 }
288
rzn1_rtc_read_offset(struct device * dev,long * offset)289 static int rzn1_rtc_read_offset(struct device *dev, long *offset)
290 {
291 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
292 unsigned int ppb_per_step;
293 bool subtract;
294 u32 val;
295
296 val = readl(rtc->base + RZN1_RTC_SUBU);
297 ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051;
298 subtract = val & RZN1_RTC_SUBU_DECR;
299 val &= 0x3F;
300
301 if (!val)
302 *offset = 0;
303 else if (subtract)
304 *offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
305 else
306 *offset = (val - 1) * ppb_per_step;
307
308 return 0;
309 }
310
rzn1_rtc_set_offset(struct device * dev,long offset)311 static int rzn1_rtc_set_offset(struct device *dev, long offset)
312 {
313 struct rzn1_rtc *rtc = dev_get_drvdata(dev);
314 int stepsh, stepsl, steps;
315 u32 subu = 0, ctl2;
316 int ret;
317
318 /*
319 * Check which resolution mode (every 20 or 60s) can be used.
320 * Between 2 and 124 clock pulses can be added or substracted.
321 *
322 * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is
323 * close to 3051 ppb. In 60s mode, the resolution is closer to 1017.
324 */
325 stepsh = DIV_ROUND_CLOSEST(offset, 1017);
326 stepsl = DIV_ROUND_CLOSEST(offset, 3051);
327
328 if (stepsh >= -0x3E && stepsh <= 0x3E) {
329 /* 1017 ppb per step */
330 steps = stepsh;
331 subu |= RZN1_RTC_SUBU_DEV;
332 } else if (stepsl >= -0x3E && stepsl <= 0x3E) {
333 /* 3051 ppb per step */
334 steps = stepsl;
335 } else {
336 return -ERANGE;
337 }
338
339 if (!steps)
340 return 0;
341
342 if (steps > 0) {
343 subu |= steps + 1;
344 } else {
345 subu |= RZN1_RTC_SUBU_DECR;
346 subu |= (~(-steps - 1)) & 0x3F;
347 }
348
349 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,
350 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000);
351 if (ret)
352 return ret;
353
354 writel(subu, rtc->base + RZN1_RTC_SUBU);
355
356 return 0;
357 }
358
359 static const struct rtc_class_ops rzn1_rtc_ops = {
360 .read_time = rzn1_rtc_read_time,
361 .set_time = rzn1_rtc_set_time,
362 .read_alarm = rzn1_rtc_read_alarm,
363 .set_alarm = rzn1_rtc_set_alarm,
364 .alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
365 .read_offset = rzn1_rtc_read_offset,
366 .set_offset = rzn1_rtc_set_offset,
367 };
368
rzn1_rtc_probe(struct platform_device * pdev)369 static int rzn1_rtc_probe(struct platform_device *pdev)
370 {
371 struct rzn1_rtc *rtc;
372 int irq;
373 int ret;
374
375 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
376 if (!rtc)
377 return -ENOMEM;
378
379 platform_set_drvdata(pdev, rtc);
380
381 rtc->base = devm_platform_ioremap_resource(pdev, 0);
382 if (IS_ERR(rtc->base))
383 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n");
384
385 irq = platform_get_irq_byname(pdev, "alarm");
386 if (irq < 0)
387 return irq;
388
389 rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
390 if (IS_ERR(rtc->rtcdev))
391 return PTR_ERR(rtc->rtcdev);
392
393 rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
394 rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
395 rtc->rtcdev->alarm_offset_max = 7 * 86400;
396 rtc->rtcdev->ops = &rzn1_rtc_ops;
397
398 ret = devm_pm_runtime_enable(&pdev->dev);
399 if (ret < 0)
400 return ret;
401 ret = pm_runtime_resume_and_get(&pdev->dev);
402 if (ret < 0)
403 return ret;
404
405 /*
406 * Ensure the clock counter is enabled.
407 * Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
408 */
409 writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
410 rtc->base + RZN1_RTC_CTL0);
411
412 /* Disable all interrupts */
413 writel(0, rtc->base + RZN1_RTC_CTL1);
414
415 spin_lock_init(&rtc->ctl1_access_lock);
416
417 ret = devm_request_irq(&pdev->dev, irq, rzn1_rtc_alarm_irq, 0, "RZN1 RTC Alarm", rtc);
418 if (ret) {
419 dev_err(&pdev->dev, "RTC alarm interrupt not available\n");
420 goto dis_runtime_pm;
421 }
422
423 irq = platform_get_irq_byname_optional(pdev, "pps");
424 if (irq >= 0)
425 ret = devm_request_irq(&pdev->dev, irq, rzn1_rtc_1s_irq, 0, "RZN1 RTC 1s", rtc);
426
427 if (irq < 0 || ret) {
428 set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features);
429 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features);
430 dev_warn(&pdev->dev, "RTC pps interrupt not available. Alarm has only minute accuracy\n");
431 }
432
433 ret = devm_rtc_register_device(rtc->rtcdev);
434 if (ret)
435 goto dis_runtime_pm;
436
437 return 0;
438
439 dis_runtime_pm:
440 pm_runtime_put(&pdev->dev);
441
442 return ret;
443 }
444
rzn1_rtc_remove(struct platform_device * pdev)445 static void rzn1_rtc_remove(struct platform_device *pdev)
446 {
447 pm_runtime_put(&pdev->dev);
448 }
449
450 static const struct of_device_id rzn1_rtc_of_match[] = {
451 { .compatible = "renesas,rzn1-rtc" },
452 {},
453 };
454 MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match);
455
456 static struct platform_driver rzn1_rtc_driver = {
457 .probe = rzn1_rtc_probe,
458 .remove = rzn1_rtc_remove,
459 .driver = {
460 .name = "rzn1-rtc",
461 .of_match_table = rzn1_rtc_of_match,
462 },
463 };
464 module_platform_driver(rzn1_rtc_driver);
465
466 MODULE_AUTHOR("Michel Pollet <buserror@gmail.com>");
467 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com");
468 MODULE_DESCRIPTION("RZ/N1 RTC driver");
469 MODULE_LICENSE("GPL");
470