1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Sophgo SG2002 SoC pinctrl driver.
4 *
5 * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6 *
7 * This file is generated from vendor pinout definition.
8 */
9
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/of.h>
13
14 #include <linux/pinctrl/pinctrl.h>
15 #include <linux/pinctrl/pinmux.h>
16
17 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
18
19 #include "pinctrl-cv18xx.h"
20
21 enum SG2002_POWER_DOMAIN {
22 VDD18A_MIPI = 0,
23 VDD18A_USB_PLL_ETH = 1,
24 VDDIO_RTC = 2,
25 VDDIO_SD0_EMMC = 3,
26 VDDIO_SD1 = 4
27 };
28
29 static const char *const sg2002_power_domain_desc[] = {
30 [VDD18A_MIPI] = "VDD18A_MIPI",
31 [VDD18A_USB_PLL_ETH] = "VDD18A_USB_PLL_ETH",
32 [VDDIO_RTC] = "VDDIO_RTC",
33 [VDDIO_SD0_EMMC] = "VDDIO_SD0_EMMC",
34 [VDDIO_SD1] = "VDDIO_SD1",
35 };
36
sg2002_get_pull_up(const struct sophgo_pin * sp,const u32 * psmap)37 static int sg2002_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
38 {
39 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
40 u32 pstate = psmap[pin->power_domain];
41 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
42
43 if (type == IO_TYPE_1V8_ONLY)
44 return 79000;
45
46 if (type == IO_TYPE_1V8_OR_3V3) {
47 if (pstate == PIN_POWER_STATE_1V8)
48 return 60000;
49 if (pstate == PIN_POWER_STATE_3V3)
50 return 60000;
51
52 return -EINVAL;
53 }
54
55 return -ENOTSUPP;
56 }
57
sg2002_get_pull_down(const struct sophgo_pin * sp,const u32 * psmap)58 static int sg2002_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
59 {
60 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
61 u32 pstate = psmap[pin->power_domain];
62 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
63
64 if (type == IO_TYPE_1V8_ONLY)
65 return 87000;
66
67 if (type == IO_TYPE_1V8_OR_3V3) {
68 if (pstate == PIN_POWER_STATE_1V8)
69 return 61000;
70 if (pstate == PIN_POWER_STATE_3V3)
71 return 62000;
72
73 return -EINVAL;
74 }
75
76 return -ENOTSUPP;
77 }
78
79 static const u32 sg2002_1v8_oc_map[] = {
80 12800,
81 25300,
82 37400,
83 49000
84 };
85
86 static const u32 sg2002_18od33_1v8_oc_map[] = {
87 7800,
88 11700,
89 15500,
90 19200,
91 23000,
92 26600,
93 30200,
94 33700
95 };
96
97 static const u32 sg2002_18od33_3v3_oc_map[] = {
98 5500,
99 8200,
100 10800,
101 13400,
102 16100,
103 18700,
104 21200,
105 23700
106 };
107
108 static const u32 sg2002_eth_oc_map[] = {
109 15700,
110 17800
111 };
112
sg2002_get_oc_map(const struct sophgo_pin * sp,const u32 * psmap,const u32 ** map)113 static int sg2002_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
114 const u32 **map)
115 {
116 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
117 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
118 u32 pstate = psmap[pin->power_domain];
119
120 if (type == IO_TYPE_1V8_ONLY) {
121 *map = sg2002_1v8_oc_map;
122 return ARRAY_SIZE(sg2002_1v8_oc_map);
123 }
124
125 if (type == IO_TYPE_1V8_OR_3V3) {
126 if (pstate == PIN_POWER_STATE_1V8) {
127 *map = sg2002_18od33_1v8_oc_map;
128 return ARRAY_SIZE(sg2002_18od33_1v8_oc_map);
129 } else if (pstate == PIN_POWER_STATE_3V3) {
130 *map = sg2002_18od33_3v3_oc_map;
131 return ARRAY_SIZE(sg2002_18od33_3v3_oc_map);
132 }
133 }
134
135 if (type == IO_TYPE_ETH) {
136 *map = sg2002_eth_oc_map;
137 return ARRAY_SIZE(sg2002_eth_oc_map);
138 }
139
140 return -ENOTSUPP;
141 }
142
143 static const u32 sg2002_1v8_schmitt_map[] = {
144 0,
145 970000,
146 1040000
147 };
148
149 static const u32 sg2002_18od33_1v8_schmitt_map[] = {
150 0,
151 1070000
152 };
153
154 static const u32 sg2002_18od33_3v3_schmitt_map[] = {
155 0,
156 1100000
157 };
158
sg2002_get_schmitt_map(const struct sophgo_pin * sp,const u32 * psmap,const u32 ** map)159 static int sg2002_get_schmitt_map(const struct sophgo_pin *sp, const u32 *psmap,
160 const u32 **map)
161 {
162 const struct cv1800_pin *pin = sophgo_to_cv1800_pin(sp);
163 enum cv1800_pin_io_type type = cv1800_pin_io_type(pin);
164 u32 pstate = psmap[pin->power_domain];
165
166 if (type == IO_TYPE_1V8_ONLY) {
167 *map = sg2002_1v8_schmitt_map;
168 return ARRAY_SIZE(sg2002_1v8_schmitt_map);
169 }
170
171 if (type == IO_TYPE_1V8_OR_3V3) {
172 if (pstate == PIN_POWER_STATE_1V8) {
173 *map = sg2002_18od33_1v8_schmitt_map;
174 return ARRAY_SIZE(sg2002_18od33_1v8_schmitt_map);
175 } else if (pstate == PIN_POWER_STATE_3V3) {
176 *map = sg2002_18od33_3v3_schmitt_map;
177 return ARRAY_SIZE(sg2002_18od33_3v3_schmitt_map);
178 }
179 }
180
181 return -ENOTSUPP;
182 }
183
184 static const struct sophgo_vddio_cfg_ops sg2002_vddio_cfg_ops = {
185 .get_pull_up = sg2002_get_pull_up,
186 .get_pull_down = sg2002_get_pull_down,
187 .get_oc_map = sg2002_get_oc_map,
188 .get_schmitt_map = sg2002_get_schmitt_map,
189 };
190
191 static const struct pinctrl_pin_desc sg2002_pins[] = {
192 PINCTRL_PIN(PIN_AUD_AINL_MIC, "AUD_AINL_MIC"),
193 PINCTRL_PIN(PIN_AUD_AOUTR, "AUD_AOUTR"),
194 PINCTRL_PIN(PIN_SD0_CLK, "SD0_CLK"),
195 PINCTRL_PIN(PIN_SD0_CMD, "SD0_CMD"),
196 PINCTRL_PIN(PIN_SD0_D0, "SD0_D0"),
197 PINCTRL_PIN(PIN_SD0_D1, "SD0_D1"),
198 PINCTRL_PIN(PIN_SD0_D2, "SD0_D2"),
199 PINCTRL_PIN(PIN_SD0_D3, "SD0_D3"),
200 PINCTRL_PIN(PIN_SD0_CD, "SD0_CD"),
201 PINCTRL_PIN(PIN_SD0_PWR_EN, "SD0_PWR_EN"),
202 PINCTRL_PIN(PIN_SPK_EN, "SPK_EN"),
203 PINCTRL_PIN(PIN_UART0_TX, "UART0_TX"),
204 PINCTRL_PIN(PIN_UART0_RX, "UART0_RX"),
205 PINCTRL_PIN(PIN_EMMC_DAT2, "EMMC_DAT2"),
206 PINCTRL_PIN(PIN_EMMC_CLK, "EMMC_CLK"),
207 PINCTRL_PIN(PIN_EMMC_DAT0, "EMMC_DAT0"),
208 PINCTRL_PIN(PIN_EMMC_DAT3, "EMMC_DAT3"),
209 PINCTRL_PIN(PIN_EMMC_CMD, "EMMC_CMD"),
210 PINCTRL_PIN(PIN_EMMC_DAT1, "EMMC_DAT1"),
211 PINCTRL_PIN(PIN_JTAG_CPU_TMS, "JTAG_CPU_TMS"),
212 PINCTRL_PIN(PIN_JTAG_CPU_TCK, "JTAG_CPU_TCK"),
213 PINCTRL_PIN(PIN_IIC0_SCL, "IIC0_SCL"),
214 PINCTRL_PIN(PIN_IIC0_SDA, "IIC0_SDA"),
215 PINCTRL_PIN(PIN_AUX0, "AUX0"),
216 PINCTRL_PIN(PIN_GPIO_ZQ, "GPIO_ZQ"),
217 PINCTRL_PIN(PIN_PWR_VBAT_DET, "PWR_VBAT_DET"),
218 PINCTRL_PIN(PIN_PWR_RSTN, "PWR_RSTN"),
219 PINCTRL_PIN(PIN_PWR_SEQ1, "PWR_SEQ1"),
220 PINCTRL_PIN(PIN_PWR_SEQ2, "PWR_SEQ2"),
221 PINCTRL_PIN(PIN_PWR_WAKEUP0, "PWR_WAKEUP0"),
222 PINCTRL_PIN(PIN_PWR_BUTTON1, "PWR_BUTTON1"),
223 PINCTRL_PIN(PIN_XTAL_XIN, "XTAL_XIN"),
224 PINCTRL_PIN(PIN_PWR_GPIO0, "PWR_GPIO0"),
225 PINCTRL_PIN(PIN_PWR_GPIO1, "PWR_GPIO1"),
226 PINCTRL_PIN(PIN_PWR_GPIO2, "PWR_GPIO2"),
227 PINCTRL_PIN(PIN_SD1_D3, "SD1_D3"),
228 PINCTRL_PIN(PIN_SD1_D2, "SD1_D2"),
229 PINCTRL_PIN(PIN_SD1_D1, "SD1_D1"),
230 PINCTRL_PIN(PIN_SD1_D0, "SD1_D0"),
231 PINCTRL_PIN(PIN_SD1_CMD, "SD1_CMD"),
232 PINCTRL_PIN(PIN_SD1_CLK, "SD1_CLK"),
233 PINCTRL_PIN(PIN_PWM0_BUCK, "PWM0_BUCK"),
234 PINCTRL_PIN(PIN_ADC1, "ADC1"),
235 PINCTRL_PIN(PIN_USB_VBUS_DET, "USB_VBUS_DET"),
236 PINCTRL_PIN(PIN_ETH_TXP, "ETH_TXP"),
237 PINCTRL_PIN(PIN_ETH_TXM, "ETH_TXM"),
238 PINCTRL_PIN(PIN_ETH_RXP, "ETH_RXP"),
239 PINCTRL_PIN(PIN_ETH_RXM, "ETH_RXM"),
240 PINCTRL_PIN(PIN_GPIO_RTX, "GPIO_RTX"),
241 PINCTRL_PIN(PIN_MIPIRX4N, "MIPIRX4N"),
242 PINCTRL_PIN(PIN_MIPIRX4P, "MIPIRX4P"),
243 PINCTRL_PIN(PIN_MIPIRX3N, "MIPIRX3N"),
244 PINCTRL_PIN(PIN_MIPIRX3P, "MIPIRX3P"),
245 PINCTRL_PIN(PIN_MIPIRX2N, "MIPIRX2N"),
246 PINCTRL_PIN(PIN_MIPIRX2P, "MIPIRX2P"),
247 PINCTRL_PIN(PIN_MIPIRX1N, "MIPIRX1N"),
248 PINCTRL_PIN(PIN_MIPIRX1P, "MIPIRX1P"),
249 PINCTRL_PIN(PIN_MIPIRX0N, "MIPIRX0N"),
250 PINCTRL_PIN(PIN_MIPIRX0P, "MIPIRX0P"),
251 PINCTRL_PIN(PIN_MIPI_TXM2, "MIPI_TXM2"),
252 PINCTRL_PIN(PIN_MIPI_TXP2, "MIPI_TXP2"),
253 PINCTRL_PIN(PIN_MIPI_TXM1, "MIPI_TXM1"),
254 PINCTRL_PIN(PIN_MIPI_TXP1, "MIPI_TXP1"),
255 PINCTRL_PIN(PIN_MIPI_TXM0, "MIPI_TXM0"),
256 PINCTRL_PIN(PIN_MIPI_TXP0, "MIPI_TXP0"),
257 };
258
259 static const struct cv1800_pin sg2002_pin_data[ARRAY_SIZE(sg2002_pins)] = {
260 CV1800_FUNC_PIN(PIN_AUD_AINL_MIC, VDD18A_MIPI,
261 IO_TYPE_AUDIO,
262 CV1800_PINCONF_AREA_SYS, 0x1bc, 5),
263 CV1800_FUNC_PIN(PIN_AUD_AOUTR, VDD18A_MIPI,
264 IO_TYPE_AUDIO,
265 CV1800_PINCONF_AREA_SYS, 0x1c8, 6),
266 CV1800_GENERAL_PIN(PIN_SD0_CLK, VDDIO_SD0_EMMC,
267 IO_TYPE_1V8_OR_3V3,
268 CV1800_PINCONF_AREA_SYS, 0x01c, 7,
269 CV1800_PINCONF_AREA_SYS, 0xa00),
270 CV1800_GENERAL_PIN(PIN_SD0_CMD, VDDIO_SD0_EMMC,
271 IO_TYPE_1V8_OR_3V3,
272 CV1800_PINCONF_AREA_SYS, 0x020, 7,
273 CV1800_PINCONF_AREA_SYS, 0xa04),
274 CV1800_GENERAL_PIN(PIN_SD0_D0, VDDIO_SD0_EMMC,
275 IO_TYPE_1V8_OR_3V3,
276 CV1800_PINCONF_AREA_SYS, 0x024, 7,
277 CV1800_PINCONF_AREA_SYS, 0xa08),
278 CV1800_GENERAL_PIN(PIN_SD0_D1, VDDIO_SD0_EMMC,
279 IO_TYPE_1V8_OR_3V3,
280 CV1800_PINCONF_AREA_SYS, 0x028, 7,
281 CV1800_PINCONF_AREA_SYS, 0xa0c),
282 CV1800_GENERAL_PIN(PIN_SD0_D2, VDDIO_SD0_EMMC,
283 IO_TYPE_1V8_OR_3V3,
284 CV1800_PINCONF_AREA_SYS, 0x02c, 7,
285 CV1800_PINCONF_AREA_SYS, 0xa10),
286 CV1800_GENERAL_PIN(PIN_SD0_D3, VDDIO_SD0_EMMC,
287 IO_TYPE_1V8_OR_3V3,
288 CV1800_PINCONF_AREA_SYS, 0x030, 7,
289 CV1800_PINCONF_AREA_SYS, 0xa14),
290 CV1800_GENERAL_PIN(PIN_SD0_CD, VDDIO_SD0_EMMC,
291 IO_TYPE_1V8_OR_3V3,
292 CV1800_PINCONF_AREA_SYS, 0x034, 3,
293 CV1800_PINCONF_AREA_SYS, 0x900),
294 CV1800_GENERAL_PIN(PIN_SD0_PWR_EN, VDDIO_SD0_EMMC,
295 IO_TYPE_1V8_OR_3V3,
296 CV1800_PINCONF_AREA_SYS, 0x038, 3,
297 CV1800_PINCONF_AREA_SYS, 0x904),
298 CV1800_GENERAL_PIN(PIN_SPK_EN, VDDIO_SD0_EMMC,
299 IO_TYPE_1V8_OR_3V3,
300 CV1800_PINCONF_AREA_SYS, 0x03c, 3,
301 CV1800_PINCONF_AREA_SYS, 0x908),
302 CV1800_GENERAL_PIN(PIN_UART0_TX, VDDIO_SD0_EMMC,
303 IO_TYPE_1V8_OR_3V3,
304 CV1800_PINCONF_AREA_SYS, 0x040, 7,
305 CV1800_PINCONF_AREA_SYS, 0x90c),
306 CV1800_GENERAL_PIN(PIN_UART0_RX, VDDIO_SD0_EMMC,
307 IO_TYPE_1V8_OR_3V3,
308 CV1800_PINCONF_AREA_SYS, 0x044, 7,
309 CV1800_PINCONF_AREA_SYS, 0x910),
310 CV1800_GENERAL_PIN(PIN_EMMC_DAT2, VDDIO_SD0_EMMC,
311 IO_TYPE_1V8_OR_3V3,
312 CV1800_PINCONF_AREA_SYS, 0x04c, 3,
313 CV1800_PINCONF_AREA_SYS, 0x918),
314 CV1800_GENERAL_PIN(PIN_EMMC_CLK, VDDIO_SD0_EMMC,
315 IO_TYPE_1V8_OR_3V3,
316 CV1800_PINCONF_AREA_SYS, 0x050, 3,
317 CV1800_PINCONF_AREA_SYS, 0x91c),
318 CV1800_GENERAL_PIN(PIN_EMMC_DAT0, VDDIO_SD0_EMMC,
319 IO_TYPE_1V8_OR_3V3,
320 CV1800_PINCONF_AREA_SYS, 0x054, 3,
321 CV1800_PINCONF_AREA_SYS, 0x920),
322 CV1800_GENERAL_PIN(PIN_EMMC_DAT3, VDDIO_SD0_EMMC,
323 IO_TYPE_1V8_OR_3V3,
324 CV1800_PINCONF_AREA_SYS, 0x058, 3,
325 CV1800_PINCONF_AREA_SYS, 0x924),
326 CV1800_GENERAL_PIN(PIN_EMMC_CMD, VDDIO_SD0_EMMC,
327 IO_TYPE_1V8_OR_3V3,
328 CV1800_PINCONF_AREA_SYS, 0x05c, 3,
329 CV1800_PINCONF_AREA_SYS, 0x928),
330 CV1800_GENERAL_PIN(PIN_EMMC_DAT1, VDDIO_SD0_EMMC,
331 IO_TYPE_1V8_OR_3V3,
332 CV1800_PINCONF_AREA_SYS, 0x060, 3,
333 CV1800_PINCONF_AREA_SYS, 0x92c),
334 CV1800_GENERAL_PIN(PIN_JTAG_CPU_TMS, VDDIO_SD0_EMMC,
335 IO_TYPE_1V8_OR_3V3,
336 CV1800_PINCONF_AREA_SYS, 0x064, 7,
337 CV1800_PINCONF_AREA_SYS, 0x930),
338 CV1800_GENERAL_PIN(PIN_JTAG_CPU_TCK, VDDIO_SD0_EMMC,
339 IO_TYPE_1V8_OR_3V3,
340 CV1800_PINCONF_AREA_SYS, 0x068, 7,
341 CV1800_PINCONF_AREA_SYS, 0x934),
342 CV1800_GENERAL_PIN(PIN_IIC0_SCL, VDDIO_SD0_EMMC,
343 IO_TYPE_1V8_OR_3V3,
344 CV1800_PINCONF_AREA_SYS, 0x070, 7,
345 CV1800_PINCONF_AREA_SYS, 0x93c),
346 CV1800_GENERAL_PIN(PIN_IIC0_SDA, VDDIO_SD0_EMMC,
347 IO_TYPE_1V8_OR_3V3,
348 CV1800_PINCONF_AREA_SYS, 0x074, 7,
349 CV1800_PINCONF_AREA_SYS, 0x940),
350 CV1800_GENERAL_PIN(PIN_AUX0, VDDIO_SD0_EMMC,
351 IO_TYPE_1V8_OR_3V3,
352 CV1800_PINCONF_AREA_SYS, 0x078, 7,
353 CV1800_PINCONF_AREA_SYS, 0x944),
354 CV1800_GENERAL_PIN(PIN_GPIO_ZQ, VDDIO_RTC,
355 IO_TYPE_1V8_ONLY,
356 CV1800_PINCONF_AREA_SYS, 0x1d0, 4,
357 CV1800_PINCONF_AREA_RTC, 0x0e0),
358 CV1800_GENERAL_PIN(PIN_PWR_VBAT_DET, VDDIO_RTC,
359 IO_TYPE_1V8_ONLY,
360 CV1800_PINCONF_AREA_SYS, 0x07c, 0,
361 CV1800_PINCONF_AREA_RTC, 0x000),
362 CV1800_GENERAL_PIN(PIN_PWR_RSTN, VDDIO_RTC,
363 IO_TYPE_1V8_ONLY,
364 CV1800_PINCONF_AREA_SYS, 0x080, 0,
365 CV1800_PINCONF_AREA_RTC, 0x004),
366 CV1800_GENERAL_PIN(PIN_PWR_SEQ1, VDDIO_RTC,
367 IO_TYPE_1V8_ONLY,
368 CV1800_PINCONF_AREA_SYS, 0x084, 3,
369 CV1800_PINCONF_AREA_RTC, 0x008),
370 CV1800_GENERAL_PIN(PIN_PWR_SEQ2, VDDIO_RTC,
371 IO_TYPE_1V8_ONLY,
372 CV1800_PINCONF_AREA_SYS, 0x088, 3,
373 CV1800_PINCONF_AREA_RTC, 0x00c),
374 CV1800_GENERAL_PIN(PIN_PWR_WAKEUP0, VDDIO_RTC,
375 IO_TYPE_1V8_ONLY,
376 CV1800_PINCONF_AREA_SYS, 0x090, 7,
377 CV1800_PINCONF_AREA_RTC, 0x018),
378 CV1800_GENERAL_PIN(PIN_PWR_BUTTON1, VDDIO_RTC,
379 IO_TYPE_1V8_ONLY,
380 CV1800_PINCONF_AREA_SYS, 0x098, 7,
381 CV1800_PINCONF_AREA_RTC, 0x020),
382 CV1800_GENERAL_PIN(PIN_XTAL_XIN, VDDIO_RTC,
383 IO_TYPE_1V8_ONLY,
384 CV1800_PINCONF_AREA_SYS, 0x0a0, 0,
385 CV1800_PINCONF_AREA_RTC, 0x028),
386 CV1800_GENERAL_PIN(PIN_PWR_GPIO0, VDDIO_RTC,
387 IO_TYPE_1V8_ONLY,
388 CV1800_PINCONF_AREA_SYS, 0x0a4, 4,
389 CV1800_PINCONF_AREA_RTC, 0x02c),
390 CV1800_GENERAL_PIN(PIN_PWR_GPIO1, VDDIO_RTC,
391 IO_TYPE_1V8_ONLY,
392 CV1800_PINCONF_AREA_SYS, 0x0a8, 7,
393 CV1800_PINCONF_AREA_RTC, 0x030),
394 CV1800_GENERAL_PIN(PIN_PWR_GPIO2, VDDIO_RTC,
395 IO_TYPE_1V8_ONLY,
396 CV1800_PINCONF_AREA_SYS, 0x0ac, 7,
397 CV1800_PINCONF_AREA_RTC, 0x034),
398 CV1800_GENERAL_PIN(PIN_SD1_D3, VDDIO_SD1,
399 IO_TYPE_1V8_OR_3V3,
400 CV1800_PINCONF_AREA_SYS, 0x0d0, 7,
401 CV1800_PINCONF_AREA_RTC, 0x058),
402 CV1800_GENERAL_PIN(PIN_SD1_D2, VDDIO_SD1,
403 IO_TYPE_1V8_OR_3V3,
404 CV1800_PINCONF_AREA_SYS, 0x0d4, 7,
405 CV1800_PINCONF_AREA_RTC, 0x05c),
406 CV1800_GENERAL_PIN(PIN_SD1_D1, VDDIO_SD1,
407 IO_TYPE_1V8_OR_3V3,
408 CV1800_PINCONF_AREA_SYS, 0x0d8, 7,
409 CV1800_PINCONF_AREA_RTC, 0x060),
410 CV1800_GENERAL_PIN(PIN_SD1_D0, VDDIO_SD1,
411 IO_TYPE_1V8_OR_3V3,
412 CV1800_PINCONF_AREA_SYS, 0x0dc, 7,
413 CV1800_PINCONF_AREA_RTC, 0x064),
414 CV1800_GENERAL_PIN(PIN_SD1_CMD, VDDIO_SD1,
415 IO_TYPE_1V8_OR_3V3,
416 CV1800_PINCONF_AREA_SYS, 0x0e0, 7,
417 CV1800_PINCONF_AREA_RTC, 0x068),
418 CV1800_GENERAL_PIN(PIN_SD1_CLK, VDDIO_SD1,
419 IO_TYPE_1V8_OR_3V3,
420 CV1800_PINCONF_AREA_SYS, 0x0e4, 7,
421 CV1800_PINCONF_AREA_RTC, 0x06c),
422 CV1800_GENERAL_PIN(PIN_PWM0_BUCK, VDD18A_USB_PLL_ETH,
423 IO_TYPE_1V8_ONLY,
424 CV1800_PINCONF_AREA_SYS, 0x0ec, 3,
425 CV1800_PINCONF_AREA_SYS, 0x804),
426 CV1800_GENERAL_PIN(PIN_ADC1, VDD18A_USB_PLL_ETH,
427 IO_TYPE_1V8_ONLY,
428 CV1800_PINCONF_AREA_SYS, 0x0f8, 4,
429 CV1800_PINCONF_AREA_SYS, 0x810),
430 CV1800_GENERAL_PIN(PIN_USB_VBUS_DET, VDD18A_USB_PLL_ETH,
431 IO_TYPE_1V8_ONLY,
432 CV1800_PINCONF_AREA_SYS, 0x108, 5,
433 CV1800_PINCONF_AREA_SYS, 0x820),
434 CV1800_FUNC_PIN(PIN_ETH_TXP, VDD18A_USB_PLL_ETH,
435 IO_TYPE_ETH,
436 CV1800_PINCONF_AREA_SYS, 0x124, 7),
437 CV1800_FUNC_PIN(PIN_ETH_TXM, VDD18A_USB_PLL_ETH,
438 IO_TYPE_ETH,
439 CV1800_PINCONF_AREA_SYS, 0x128, 7),
440 CV1800_FUNC_PIN(PIN_ETH_RXP, VDD18A_USB_PLL_ETH,
441 IO_TYPE_ETH,
442 CV1800_PINCONF_AREA_SYS, 0x12c, 7),
443 CV1800_FUNC_PIN(PIN_ETH_RXM, VDD18A_USB_PLL_ETH,
444 IO_TYPE_ETH,
445 CV1800_PINCONF_AREA_SYS, 0x130, 7),
446 CV1800_GENERAL_PIN(PIN_GPIO_RTX, VDD18A_USB_PLL_ETH,
447 IO_TYPE_1V8_ONLY,
448 CV1800_PINCONF_AREA_SYS, 0x1cc, 5,
449 CV1800_PINCONF_AREA_SYS, 0xc8c),
450 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4N, VDD18A_MIPI,
451 IO_TYPE_1V8_ONLY,
452 CV1800_PINCONF_AREA_SYS, 0x16c, 7,
453 CV1800_PINCONF_AREA_SYS, 0x120, 7,
454 CV1800_PINCONF_AREA_SYS, 0xc38),
455 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX4P, VDD18A_MIPI,
456 IO_TYPE_1V8_ONLY,
457 CV1800_PINCONF_AREA_SYS, 0x170, 7,
458 CV1800_PINCONF_AREA_SYS, 0x11c, 7,
459 CV1800_PINCONF_AREA_SYS, 0xc3c),
460 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3N, VDD18A_MIPI,
461 IO_TYPE_1V8_ONLY,
462 CV1800_PINCONF_AREA_SYS, 0x174, 7,
463 CV1800_PINCONF_AREA_SYS, 0x114, 7,
464 CV1800_PINCONF_AREA_SYS, 0xc40),
465 CV1800_GENERATE_PIN_MUX2(PIN_MIPIRX3P, VDD18A_MIPI,
466 IO_TYPE_1V8_ONLY,
467 CV1800_PINCONF_AREA_SYS, 0x178, 7,
468 CV1800_PINCONF_AREA_SYS, 0x118, 7,
469 CV1800_PINCONF_AREA_SYS, 0xc44),
470 CV1800_GENERAL_PIN(PIN_MIPIRX2N, VDD18A_MIPI,
471 IO_TYPE_1V8_ONLY,
472 CV1800_PINCONF_AREA_SYS, 0x17c, 7,
473 CV1800_PINCONF_AREA_SYS, 0xc48),
474 CV1800_GENERAL_PIN(PIN_MIPIRX2P, VDD18A_MIPI,
475 IO_TYPE_1V8_ONLY,
476 CV1800_PINCONF_AREA_SYS, 0x180, 7,
477 CV1800_PINCONF_AREA_SYS, 0xc4c),
478 CV1800_GENERAL_PIN(PIN_MIPIRX1N, VDD18A_MIPI,
479 IO_TYPE_1V8_ONLY,
480 CV1800_PINCONF_AREA_SYS, 0x184, 7,
481 CV1800_PINCONF_AREA_SYS, 0xc50),
482 CV1800_GENERAL_PIN(PIN_MIPIRX1P, VDD18A_MIPI,
483 IO_TYPE_1V8_ONLY,
484 CV1800_PINCONF_AREA_SYS, 0x188, 7,
485 CV1800_PINCONF_AREA_SYS, 0xc54),
486 CV1800_GENERAL_PIN(PIN_MIPIRX0N, VDD18A_MIPI,
487 IO_TYPE_1V8_ONLY,
488 CV1800_PINCONF_AREA_SYS, 0x18c, 7,
489 CV1800_PINCONF_AREA_SYS, 0xc58),
490 CV1800_GENERAL_PIN(PIN_MIPIRX0P, VDD18A_MIPI,
491 IO_TYPE_1V8_ONLY,
492 CV1800_PINCONF_AREA_SYS, 0x190, 7,
493 CV1800_PINCONF_AREA_SYS, 0xc5c),
494 CV1800_GENERAL_PIN(PIN_MIPI_TXM2, VDD18A_MIPI,
495 IO_TYPE_1V8_ONLY,
496 CV1800_PINCONF_AREA_SYS, 0x1a4, 7,
497 CV1800_PINCONF_AREA_SYS, 0xc70),
498 CV1800_GENERAL_PIN(PIN_MIPI_TXP2, VDD18A_MIPI,
499 IO_TYPE_1V8_ONLY,
500 CV1800_PINCONF_AREA_SYS, 0x1a8, 7,
501 CV1800_PINCONF_AREA_SYS, 0xc74),
502 CV1800_GENERAL_PIN(PIN_MIPI_TXM1, VDD18A_MIPI,
503 IO_TYPE_1V8_ONLY,
504 CV1800_PINCONF_AREA_SYS, 0x1ac, 7,
505 CV1800_PINCONF_AREA_SYS, 0xc78),
506 CV1800_GENERAL_PIN(PIN_MIPI_TXP1, VDD18A_MIPI,
507 IO_TYPE_1V8_ONLY,
508 CV1800_PINCONF_AREA_SYS, 0x1b0, 7,
509 CV1800_PINCONF_AREA_SYS, 0xc7c),
510 CV1800_GENERAL_PIN(PIN_MIPI_TXM0, VDD18A_MIPI,
511 IO_TYPE_1V8_ONLY,
512 CV1800_PINCONF_AREA_SYS, 0x1b4, 7,
513 CV1800_PINCONF_AREA_SYS, 0xc80),
514 CV1800_GENERAL_PIN(PIN_MIPI_TXP0, VDD18A_MIPI,
515 IO_TYPE_1V8_ONLY,
516 CV1800_PINCONF_AREA_SYS, 0x1b8, 7,
517 CV1800_PINCONF_AREA_SYS, 0xc84),
518 };
519
520 static const struct sophgo_pinctrl_data sg2002_pindata = {
521 .pins = sg2002_pins,
522 .pindata = sg2002_pin_data,
523 .pdnames = sg2002_power_domain_desc,
524 .vddio_ops = &sg2002_vddio_cfg_ops,
525 .cfg_ops = &cv1800_cfg_ops,
526 .pctl_ops = &cv1800_pctrl_ops,
527 .pmx_ops = &cv1800_pmx_ops,
528 .pconf_ops = &cv1800_pconf_ops,
529 .npins = ARRAY_SIZE(sg2002_pins),
530 .npds = ARRAY_SIZE(sg2002_power_domain_desc),
531 .pinsize = sizeof(struct cv1800_pin),
532 };
533
534 static const struct of_device_id sg2002_pinctrl_ids[] = {
535 { .compatible = "sophgo,sg2002-pinctrl", .data = &sg2002_pindata },
536 { }
537 };
538 MODULE_DEVICE_TABLE(of, sg2002_pinctrl_ids);
539
540 static struct platform_driver sg2002_pinctrl_driver = {
541 .probe = sophgo_pinctrl_probe,
542 .driver = {
543 .name = "sg2002-pinctrl",
544 .suppress_bind_attrs = true,
545 .of_match_table = sg2002_pinctrl_ids,
546 },
547 };
548 module_platform_driver(sg2002_pinctrl_driver);
549
550 MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
551 MODULE_LICENSE("GPL");
552