1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2016-2020 Arm Limited
3 // CMN-600 Coherent Mesh Network PMU driver
4
5 #include <linux/acpi.h>
6 #include <linux/bitfield.h>
7 #include <linux/bitops.h>
8 #include <linux/debugfs.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/io-64-nonatomic-lo-hi.h>
12 #include <linux/kernel.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/perf_event.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/sort.h>
20
21 /* Common register stuff */
22 #define CMN_NODE_INFO 0x0000
23 #define CMN_NI_NODE_TYPE GENMASK_ULL(15, 0)
24 #define CMN_NI_NODE_ID GENMASK_ULL(31, 16)
25 #define CMN_NI_LOGICAL_ID GENMASK_ULL(47, 32)
26
27 #define CMN_CHILD_INFO 0x0080
28 #define CMN_CI_CHILD_COUNT GENMASK_ULL(15, 0)
29 #define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31, 16)
30
31 #define CMN_CHILD_NODE_ADDR GENMASK(29, 0)
32 #define CMN_CHILD_NODE_EXTERNAL BIT(31)
33
34 #define CMN_MAX_DIMENSION 12
35 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)
36 #define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1) * 4)
37
38 /* Currently XPs are the node type we can have most of; others top out at 128 */
39 #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS
40
41 /* The CFG node has various info besides the discovery tree */
42 #define CMN_CFGM_PERIPH_ID_01 0x0008
43 #define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7, 0)
44 #define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35, 32)
45 #define CMN_CFGM_PERIPH_ID_23 0x0010
46 #define CMN_CFGM_PID2_REVISION GENMASK_ULL(7, 4)
47
48 #define CMN_CFGM_INFO_GLOBAL 0x0900
49 #define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63)
50 #define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53, 52)
51 #define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51, 50)
52 #define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44)
53
54 #define CMN_CFGM_INFO_GLOBAL_1 0x0908
55 #define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3, 2)
56 #define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1, 0)
57
58 /* XPs also have some local topology info which has uses too */
59 #define CMN_MXP__CONNECT_INFO(p) (0x0008 + 8 * (p))
60 #define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5, 0)
61
62 #define CMN_MAX_PORTS 6
63 #define CI700_CONNECT_INFO_P2_5_OFFSET 0x10
64
65 /* PMU registers occupy the 3rd 4KB page of each node's region */
66 #define CMN_PMU_OFFSET 0x2000
67 /* ...except when they don't :( */
68 #define CMN_S3_DTM_OFFSET 0xa000
69 #define CMN_S3_PMU_OFFSET 0xd900
70
71 /* For most nodes, this is all there is */
72 #define CMN_PMU_EVENT_SEL 0x000
73 #define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44, 42)
74 #define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40, 39)
75 #define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38, 37)
76 #define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36, 35)
77 /* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */
78 #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34, 32)
79
80 /* Some types are designed to coexist with another device in the same node */
81 #define CMN_CCLA_PMU_EVENT_SEL 0x008
82 #define CMN_HNP_PMU_EVENT_SEL 0x008
83
84 /* DTMs live in the PMU space of XP registers */
85 #define CMN_DTM_WPn(n) (0x1A0 + (n) * 0x18)
86 #define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0x00)
87 #define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20, 19)
88 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18, 17)
89 #define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9)
90 #define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8)
91 #define CMN600_WPn_CONFIG_WP_COMBINE BIT(6)
92 #define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5)
93 #define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5, 4)
94 #define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3, 1)
95 #define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0)
96 #define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0x08)
97 #define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0x10)
98
99 #define CMN_DTM_PMU_CONFIG 0x210
100 #define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37, 32)
101 #define CMN__PMEVCNT0_INPUT_SEL_WP 0x00
102 #define CMN__PMEVCNT0_INPUT_SEL_XP 0x04
103 #define CMN__PMEVCNT0_INPUT_SEL_DEV 0x10
104 #define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18, 16)
105 #define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4)
106 #define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))
107 #define CMN__PMEVCNT23_COMBINED BIT(2)
108 #define CMN__PMEVCNT01_COMBINED BIT(1)
109 #define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0)
110
111 #define CMN_DTM_PMEVCNT 0x220
112
113 #define CMN_DTM_PMEVCNTSR 0x240
114
115 #define CMN650_DTM_UNIT_INFO 0x0910
116 #define CMN_DTM_UNIT_INFO 0x0960
117 #define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1, 0)
118
119 #define CMN_DTM_NUM_COUNTERS 4
120 /* Want more local counters? Why not replicate the whole DTM! Ugh... */
121 #define CMN_DTM_OFFSET(n) ((n) * 0x200)
122
123 /* The DTC node is where the magic happens */
124 #define CMN_DT_DTC_CTL 0x0a00
125 #define CMN_DT_DTC_CTL_DT_EN BIT(0)
126 #define CMN_DT_DTC_CTL_CG_DISABLE BIT(10)
127
128 /* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */
129 #define _CMN_DT_CNT_REG(n) ((((n) / 2) * 4 + (n) % 2) * 4)
130 #define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n))
131 #define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0x40)
132
133 #define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0x50 + _CMN_DT_CNT_REG(n))
134 #define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0x90)
135
136 #define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0x100)
137 #define CMN_DT_PMCR_PMU_EN BIT(0)
138 #define CMN_DT_PMCR_CNTR_RST BIT(5)
139 #define CMN_DT_PMCR_OVFL_INTR_EN BIT(6)
140
141 #define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0x118)
142 #define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0x120)
143
144 #define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0x128)
145 #define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)
146
147 #define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0x130)
148 #define CMN_DT_PMSRR_SS_REQ BIT(0)
149
150 #define CMN_DT_NUM_COUNTERS 8
151 #define CMN_MAX_DTCS 4
152
153 /*
154 * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles,
155 * so throwing away one bit to make overflow handling easy is no big deal.
156 */
157 #define CMN_COUNTER_INIT 0x80000000
158 /* Similarly for the 40-bit cycle counter */
159 #define CMN_CC_INIT 0x8000000000ULL
160
161
162 /* Event attributes */
163 #define CMN_CONFIG_TYPE GENMASK_ULL(15, 0)
164 #define CMN_CONFIG_EVENTID GENMASK_ULL(26, 16)
165 #define CMN_CONFIG_OCCUPID GENMASK_ULL(30, 27)
166 #define CMN_CONFIG_BYNODEID BIT_ULL(31)
167 #define CMN_CONFIG_NODEID GENMASK_ULL(47, 32)
168
169 #define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)
170 #define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)
171 #define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)
172 #define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)
173 #define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)
174
175 #define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30, 27)
176 #define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50, 48)
177 #define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55, 51)
178 #define CMN_CONFIG_WP_GRP GENMASK_ULL(57, 56)
179 #define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58)
180 #define CMN_CONFIG1_WP_VAL GENMASK_ULL(63, 0)
181 #define CMN_CONFIG2_WP_MASK GENMASK_ULL(63, 0)
182
183 #define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)
184 #define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)
185 #define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)
186 #define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)
187 #define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)
188 #define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)
189 #define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)
190
191 /* Made-up event IDs for watchpoint direction */
192 #define CMN_WP_UP 0
193 #define CMN_WP_DOWN 2
194
195
196 /* Internal values for encoding event support */
197 enum cmn_model {
198 CMN600 = 1,
199 CMN650 = 2,
200 CMN700 = 4,
201 CI700 = 8,
202 CMNS3 = 16,
203 /* ...and then we can use bitmap tricks for commonality */
204 CMN_ANY = -1,
205 NOT_CMN600 = -2,
206 CMN_650ON = CMN650 | CMN700 | CMNS3,
207 };
208
209 /* Actual part numbers and revision IDs defined by the hardware */
210 enum cmn_part {
211 PART_CMN600 = 0x434,
212 PART_CMN650 = 0x436,
213 PART_CMN700 = 0x43c,
214 PART_CI700 = 0x43a,
215 PART_CMN_S3 = 0x43e,
216 };
217
218 /* CMN-600 r0px shouldn't exist in silicon, thankfully */
219 enum cmn_revision {
220 REV_CMN600_R1P0,
221 REV_CMN600_R1P1,
222 REV_CMN600_R1P2,
223 REV_CMN600_R1P3,
224 REV_CMN600_R2P0,
225 REV_CMN600_R3P0,
226 REV_CMN600_R3P1,
227 REV_CMN650_R0P0 = 0,
228 REV_CMN650_R1P0,
229 REV_CMN650_R1P1,
230 REV_CMN650_R2P0,
231 REV_CMN650_R1P2,
232 REV_CMN700_R0P0 = 0,
233 REV_CMN700_R1P0,
234 REV_CMN700_R2P0,
235 REV_CMN700_R3P0,
236 REV_CI700_R0P0 = 0,
237 REV_CI700_R1P0,
238 REV_CI700_R2P0,
239 };
240
241 enum cmn_node_type {
242 CMN_TYPE_INVALID,
243 CMN_TYPE_DVM,
244 CMN_TYPE_CFG,
245 CMN_TYPE_DTC,
246 CMN_TYPE_HNI,
247 CMN_TYPE_HNF,
248 CMN_TYPE_XP,
249 CMN_TYPE_SBSX,
250 CMN_TYPE_MPAM_S,
251 CMN_TYPE_MPAM_NS,
252 CMN_TYPE_RNI,
253 CMN_TYPE_RND = 0xd,
254 CMN_TYPE_RNSAM = 0xf,
255 CMN_TYPE_MTSX,
256 CMN_TYPE_HNP,
257 CMN_TYPE_CXRA = 0x100,
258 CMN_TYPE_CXHA,
259 CMN_TYPE_CXLA,
260 CMN_TYPE_CCRA,
261 CMN_TYPE_CCHA,
262 CMN_TYPE_CCLA,
263 CMN_TYPE_CCLA_RNI,
264 CMN_TYPE_HNS = 0x200,
265 CMN_TYPE_HNS_MPAM_S,
266 CMN_TYPE_HNS_MPAM_NS,
267 CMN_TYPE_APB = 0x1000,
268 /* Not a real node type */
269 CMN_TYPE_WP = 0x7770
270 };
271
272 enum cmn_filter_select {
273 SEL_NONE = -1,
274 SEL_OCCUP1ID,
275 SEL_CLASS_OCCUP_ID,
276 SEL_CBUSY_SNTHROTTLE_SEL,
277 SEL_HBT_LBT_SEL,
278 SEL_SN_HOME_SEL,
279 SEL_MAX
280 };
281
282 struct arm_cmn_node {
283 void __iomem *pmu_base;
284 u16 id, logid;
285 enum cmn_node_type type;
286
287 /* XP properties really, but replicated to children for convenience */
288 u8 dtm;
289 s8 dtc;
290 u8 portid_bits:4;
291 u8 deviceid_bits:4;
292 /* DN/HN-F/CXHA */
293 struct {
294 u8 val : 4;
295 u8 count : 4;
296 } occupid[SEL_MAX];
297 union {
298 u8 event[4];
299 __le32 event_sel;
300 u16 event_w[4];
301 __le64 event_sel_w;
302 };
303 };
304
305 struct arm_cmn_dtm {
306 void __iomem *base;
307 u32 pmu_config_low;
308 union {
309 u8 input_sel[4];
310 __le32 pmu_config_high;
311 };
312 s8 wp_event[4];
313 };
314
315 struct arm_cmn_dtc {
316 void __iomem *base;
317 void __iomem *pmu_base;
318 int irq;
319 s8 irq_friend;
320 bool cc_active;
321
322 struct perf_event *counters[CMN_DT_NUM_COUNTERS];
323 struct perf_event *cycles;
324 };
325
326 #define CMN_STATE_DISABLED BIT(0)
327 #define CMN_STATE_TXN BIT(1)
328
329 struct arm_cmn {
330 struct device *dev;
331 void __iomem *base;
332 unsigned int state;
333
334 enum cmn_revision rev;
335 enum cmn_part part;
336 u8 mesh_x;
337 u8 mesh_y;
338 u16 num_xps;
339 u16 num_dns;
340 bool multi_dtm;
341 u8 ports_used;
342 struct {
343 unsigned int rsp_vc_num : 2;
344 unsigned int dat_vc_num : 2;
345 unsigned int snp_vc_num : 2;
346 unsigned int req_vc_num : 2;
347 };
348
349 struct arm_cmn_node *xps;
350 struct arm_cmn_node *dns;
351
352 struct arm_cmn_dtm *dtms;
353 struct arm_cmn_dtc *dtc;
354 unsigned int num_dtcs;
355
356 int cpu;
357 struct hlist_node cpuhp_node;
358
359 struct pmu pmu;
360 struct dentry *debug;
361 };
362
363 #define to_cmn(p) container_of(p, struct arm_cmn, pmu)
364
365 static int arm_cmn_hp_state;
366
367 struct arm_cmn_nodeid {
368 u8 port;
369 u8 dev;
370 };
371
arm_cmn_xyidbits(const struct arm_cmn * cmn)372 static int arm_cmn_xyidbits(const struct arm_cmn *cmn)
373 {
374 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1));
375 }
376
arm_cmn_nid(const struct arm_cmn_node * dn)377 static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn)
378 {
379 struct arm_cmn_nodeid nid;
380
381 nid.dev = dn->id & ((1U << dn->deviceid_bits) - 1);
382 nid.port = (dn->id >> dn->deviceid_bits) & ((1U << dn->portid_bits) - 1);
383 return nid;
384 }
385
arm_cmn_node_to_xp(const struct arm_cmn * cmn,const struct arm_cmn_node * dn)386 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,
387 const struct arm_cmn_node *dn)
388 {
389 int id = dn->id >> (dn->portid_bits + dn->deviceid_bits);
390 int bits = arm_cmn_xyidbits(cmn);
391 int x = id >> bits;
392 int y = id & ((1U << bits) - 1);
393
394 return cmn->xps + cmn->mesh_x * y + x;
395 }
arm_cmn_node(const struct arm_cmn * cmn,enum cmn_node_type type)396 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,
397 enum cmn_node_type type)
398 {
399 struct arm_cmn_node *dn;
400
401 for (dn = cmn->dns; dn->type; dn++)
402 if (dn->type == type)
403 return dn;
404 return NULL;
405 }
406
arm_cmn_model(const struct arm_cmn * cmn)407 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)
408 {
409 switch (cmn->part) {
410 case PART_CMN600:
411 return CMN600;
412 case PART_CMN650:
413 return CMN650;
414 case PART_CMN700:
415 return CMN700;
416 case PART_CI700:
417 return CI700;
418 case PART_CMN_S3:
419 return CMNS3;
420 default:
421 return 0;
422 };
423 }
424
arm_cmn_pmu_offset(const struct arm_cmn * cmn,const struct arm_cmn_node * dn)425 static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_cmn_node *dn)
426 {
427 if (cmn->part == PART_CMN_S3) {
428 if (dn->type == CMN_TYPE_XP)
429 return CMN_S3_DTM_OFFSET;
430 return CMN_S3_PMU_OFFSET;
431 }
432 return CMN_PMU_OFFSET;
433 }
434
arm_cmn_device_connect_info(const struct arm_cmn * cmn,const struct arm_cmn_node * xp,int port)435 static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,
436 const struct arm_cmn_node *xp, int port)
437 {
438 int offset = CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp);
439
440 if (port >= 2) {
441 if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)
442 return 0;
443 /*
444 * CI-700 may have extra ports, but still has the
445 * mesh_port_connect_info registers in the way.
446 */
447 if (cmn->part == PART_CI700)
448 offset += CI700_CONNECT_INFO_P2_5_OFFSET;
449 }
450
451 return readl_relaxed(xp->pmu_base + offset);
452 }
453
454 static struct dentry *arm_cmn_debugfs;
455
456 #ifdef CONFIG_DEBUG_FS
arm_cmn_device_type(u8 type)457 static const char *arm_cmn_device_type(u8 type)
458 {
459 switch(FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {
460 case 0x00: return " |";
461 case 0x01: return " RN-I |";
462 case 0x02: return " RN-D |";
463 case 0x04: return " RN-F_B |";
464 case 0x05: return "RN-F_B_E|";
465 case 0x06: return " RN-F_A |";
466 case 0x07: return "RN-F_A_E|";
467 case 0x08: return " HN-T |";
468 case 0x09: return " HN-I |";
469 case 0x0a: return " HN-D |";
470 case 0x0b: return " HN-P |";
471 case 0x0c: return " SN-F |";
472 case 0x0d: return " SBSX |";
473 case 0x0e: return " HN-F |";
474 case 0x0f: return " SN-F_E |";
475 case 0x10: return " SN-F_D |";
476 case 0x11: return " CXHA |";
477 case 0x12: return " CXRA |";
478 case 0x13: return " CXRH |";
479 case 0x14: return " RN-F_D |";
480 case 0x15: return "RN-F_D_E|";
481 case 0x16: return " RN-F_C |";
482 case 0x17: return "RN-F_C_E|";
483 case 0x18: return " RN-F_E |";
484 case 0x19: return "RN-F_E_E|";
485 case 0x1a: return " HN-S |";
486 case 0x1b: return " LCN |";
487 case 0x1c: return " MTSX |";
488 case 0x1d: return " HN-V |";
489 case 0x1e: return " CCG |";
490 case 0x20: return " RN-F_F |";
491 case 0x21: return "RN-F_F_E|";
492 case 0x22: return " SN-F_F |";
493 default: return " ???? |";
494 }
495 }
496
arm_cmn_show_logid(struct seq_file * s,const struct arm_cmn_node * xp,int p,int d)497 static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d)
498 {
499 struct arm_cmn *cmn = s->private;
500 struct arm_cmn_node *dn;
501 u16 id = xp->id | d | (p << xp->deviceid_bits);
502
503 for (dn = cmn->dns; dn->type; dn++) {
504 int pad = dn->logid < 10;
505
506 if (dn->type == CMN_TYPE_XP)
507 continue;
508 /* Ignore the extra components that will overlap on some ports */
509 if (dn->type < CMN_TYPE_HNI)
510 continue;
511
512 if (dn->id != id)
513 continue;
514
515 seq_printf(s, " %*c#%-*d |", pad + 1, ' ', 3 - pad, dn->logid);
516 return;
517 }
518 seq_puts(s, " |");
519 }
520
arm_cmn_map_show(struct seq_file * s,void * data)521 static int arm_cmn_map_show(struct seq_file *s, void *data)
522 {
523 struct arm_cmn *cmn = s->private;
524 int x, y, p, pmax = fls(cmn->ports_used);
525
526 seq_puts(s, " X");
527 for (x = 0; x < cmn->mesh_x; x++)
528 seq_printf(s, " %-2d ", x);
529 seq_puts(s, "\nY P D+");
530 y = cmn->mesh_y;
531 while (y--) {
532 int xp_base = cmn->mesh_x * y;
533 struct arm_cmn_node *xp = cmn->xps + xp_base;
534 u8 port[CMN_MAX_PORTS][CMN_MAX_DIMENSION];
535
536 for (x = 0; x < cmn->mesh_x; x++)
537 seq_puts(s, "--------+");
538
539 seq_printf(s, "\n%-2d |", y);
540 for (x = 0; x < cmn->mesh_x; x++) {
541 for (p = 0; p < CMN_MAX_PORTS; p++)
542 port[p][x] = arm_cmn_device_connect_info(cmn, xp + x, p);
543 seq_printf(s, " XP #%-3d|", xp_base + x);
544 }
545
546 seq_puts(s, "\n |");
547 for (x = 0; x < cmn->mesh_x; x++) {
548 s8 dtc = xp[x].dtc;
549
550 if (dtc < 0)
551 seq_puts(s, " DTC ?? |");
552 else
553 seq_printf(s, " DTC %d |", dtc);
554 }
555 seq_puts(s, "\n |");
556 for (x = 0; x < cmn->mesh_x; x++)
557 seq_puts(s, "........|");
558
559 for (p = 0; p < pmax; p++) {
560 seq_printf(s, "\n %d |", p);
561 for (x = 0; x < cmn->mesh_x; x++)
562 seq_puts(s, arm_cmn_device_type(port[p][x]));
563 seq_puts(s, "\n 0|");
564 for (x = 0; x < cmn->mesh_x; x++)
565 arm_cmn_show_logid(s, xp + x, p, 0);
566 seq_puts(s, "\n 1|");
567 for (x = 0; x < cmn->mesh_x; x++)
568 arm_cmn_show_logid(s, xp + x, p, 1);
569 }
570 seq_puts(s, "\n-----+");
571 }
572 for (x = 0; x < cmn->mesh_x; x++)
573 seq_puts(s, "--------+");
574 seq_puts(s, "\n");
575 return 0;
576 }
577 DEFINE_SHOW_ATTRIBUTE(arm_cmn_map);
578
arm_cmn_debugfs_init(struct arm_cmn * cmn,int id)579 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)
580 {
581 const char *name = "map";
582
583 if (id > 0)
584 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "map_%d", id);
585 if (!name)
586 return;
587
588 cmn->debug = debugfs_create_file(name, 0444, arm_cmn_debugfs, cmn, &arm_cmn_map_fops);
589 }
590 #else
arm_cmn_debugfs_init(struct arm_cmn * cmn,int id)591 static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}
592 #endif
593
594 struct arm_cmn_hw_event {
595 struct arm_cmn_node *dn;
596 u64 dtm_idx[DIV_ROUND_UP(CMN_MAX_NODES_PER_EVENT * 2, 64)];
597 s8 dtc_idx[CMN_MAX_DTCS];
598 u8 num_dns;
599 u8 dtm_offset;
600
601 /*
602 * WP config registers are divided to UP and DOWN events. We need to
603 * keep to track only one of them.
604 */
605 DECLARE_BITMAP(wp_idx, CMN_MAX_XPS);
606
607 bool wide_sel;
608 enum cmn_filter_select filter_sel;
609 };
610 static_assert(sizeof(struct arm_cmn_hw_event) <= offsetof(struct hw_perf_event, target));
611
612 #define for_each_hw_dn(hw, dn, i) \
613 for (i = 0, dn = hw->dn; i < hw->num_dns; i++, dn++)
614
615 /* @i is the DTC number, @idx is the counter index on that DTC */
616 #define for_each_hw_dtc_idx(hw, i, idx) \
617 for (int i = 0, idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0)
618
to_cmn_hw(struct perf_event * event)619 static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)
620 {
621 return (struct arm_cmn_hw_event *)&event->hw;
622 }
623
arm_cmn_set_index(u64 x[],unsigned int pos,unsigned int val)624 static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)
625 {
626 x[pos / 32] |= (u64)val << ((pos % 32) * 2);
627 }
628
arm_cmn_get_index(u64 x[],unsigned int pos)629 static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)
630 {
631 return (x[pos / 32] >> ((pos % 32) * 2)) & 3;
632 }
633
arm_cmn_set_wp_idx(unsigned long * wp_idx,unsigned int pos,bool val)634 static void arm_cmn_set_wp_idx(unsigned long *wp_idx, unsigned int pos, bool val)
635 {
636 if (val)
637 set_bit(pos, wp_idx);
638 }
639
arm_cmn_get_wp_idx(unsigned long * wp_idx,unsigned int pos)640 static unsigned int arm_cmn_get_wp_idx(unsigned long *wp_idx, unsigned int pos)
641 {
642 return test_bit(pos, wp_idx);
643 }
644
645 struct arm_cmn_event_attr {
646 struct device_attribute attr;
647 enum cmn_model model;
648 enum cmn_node_type type;
649 enum cmn_filter_select fsel;
650 u16 eventid;
651 u8 occupid;
652 };
653
654 struct arm_cmn_format_attr {
655 struct device_attribute attr;
656 u64 field;
657 int config;
658 };
659
660 #define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\
661 (&((struct arm_cmn_event_attr[]) {{ \
662 .attr = __ATTR(_name, 0444, arm_cmn_event_show, NULL), \
663 .model = _model, \
664 .type = _type, \
665 .eventid = _eventid, \
666 .occupid = _occupid, \
667 .fsel = _fsel, \
668 }})[0].attr.attr)
669 #define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \
670 _CMN_EVENT_ATTR(_model, _name, _type, _eventid, 0, SEL_NONE)
671
arm_cmn_event_show(struct device * dev,struct device_attribute * attr,char * buf)672 static ssize_t arm_cmn_event_show(struct device *dev,
673 struct device_attribute *attr, char *buf)
674 {
675 struct arm_cmn_event_attr *eattr;
676
677 eattr = container_of(attr, typeof(*eattr), attr);
678
679 if (eattr->type == CMN_TYPE_DTC)
680 return sysfs_emit(buf, "type=0x%x\n", eattr->type);
681
682 if (eattr->type == CMN_TYPE_WP)
683 return sysfs_emit(buf,
684 "type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n",
685 eattr->type, eattr->eventid);
686
687 if (eattr->fsel > SEL_NONE)
688 return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n",
689 eattr->type, eattr->eventid, eattr->occupid);
690
691 return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n", eattr->type,
692 eattr->eventid);
693 }
694
arm_cmn_event_attr_is_visible(struct kobject * kobj,struct attribute * attr,int unused)695 static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,
696 struct attribute *attr,
697 int unused)
698 {
699 struct device *dev = kobj_to_dev(kobj);
700 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
701 struct arm_cmn_event_attr *eattr;
702 enum cmn_node_type type;
703 u16 eventid;
704
705 eattr = container_of(attr, typeof(*eattr), attr.attr);
706
707 if (!(eattr->model & arm_cmn_model(cmn)))
708 return 0;
709
710 type = eattr->type;
711 eventid = eattr->eventid;
712
713 /* Watchpoints aren't nodes, so avoid confusion */
714 if (type == CMN_TYPE_WP)
715 return attr->mode;
716
717 /* Hide XP events for unused interfaces/channels */
718 if (type == CMN_TYPE_XP) {
719 unsigned int intf = (eventid >> 2) & 7;
720 unsigned int chan = eventid >> 5;
721
722 if ((intf & 4) && !(cmn->ports_used & BIT(intf & 3)))
723 return 0;
724
725 if (chan == 4 && cmn->part == PART_CMN600)
726 return 0;
727
728 if ((chan == 5 && cmn->rsp_vc_num < 2) ||
729 (chan == 6 && cmn->dat_vc_num < 2) ||
730 (chan == 7 && cmn->snp_vc_num < 2) ||
731 (chan == 8 && cmn->req_vc_num < 2))
732 return 0;
733 }
734
735 /* Revision-specific differences */
736 if (cmn->part == PART_CMN600) {
737 if (cmn->rev < REV_CMN600_R1P3) {
738 if (type == CMN_TYPE_CXRA && eventid > 0x10)
739 return 0;
740 }
741 if (cmn->rev < REV_CMN600_R1P2) {
742 if (type == CMN_TYPE_HNF && eventid == 0x1b)
743 return 0;
744 if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)
745 return 0;
746 }
747 } else if (cmn->part == PART_CMN650) {
748 if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {
749 if (type == CMN_TYPE_HNF && eventid > 0x22)
750 return 0;
751 if (type == CMN_TYPE_SBSX && eventid == 0x17)
752 return 0;
753 if (type == CMN_TYPE_RNI && eventid > 0x10)
754 return 0;
755 }
756 } else if (cmn->part == PART_CMN700) {
757 if (cmn->rev < REV_CMN700_R2P0) {
758 if (type == CMN_TYPE_HNF && eventid > 0x2c)
759 return 0;
760 if (type == CMN_TYPE_CCHA && eventid > 0x74)
761 return 0;
762 if (type == CMN_TYPE_CCLA && eventid > 0x27)
763 return 0;
764 }
765 if (cmn->rev < REV_CMN700_R1P0) {
766 if (type == CMN_TYPE_HNF && eventid > 0x2b)
767 return 0;
768 }
769 }
770
771 if (!arm_cmn_node(cmn, type))
772 return 0;
773
774 return attr->mode;
775 }
776
777 #define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \
778 _CMN_EVENT_ATTR(_model, dn_##_name, CMN_TYPE_DVM, _event, _occup, _fsel)
779 #define CMN_EVENT_DTC(_name) \
780 CMN_EVENT_ATTR(CMN_ANY, dtc_##_name, CMN_TYPE_DTC, 0)
781 #define CMN_EVENT_HNF(_model, _name, _event) \
782 CMN_EVENT_ATTR(_model, hnf_##_name, CMN_TYPE_HNF, _event)
783 #define CMN_EVENT_HNI(_name, _event) \
784 CMN_EVENT_ATTR(CMN_ANY, hni_##_name, CMN_TYPE_HNI, _event)
785 #define CMN_EVENT_HNP(_name, _event) \
786 CMN_EVENT_ATTR(CMN_ANY, hnp_##_name, CMN_TYPE_HNP, _event)
787 #define __CMN_EVENT_XP(_name, _event) \
788 CMN_EVENT_ATTR(CMN_ANY, mxp_##_name, CMN_TYPE_XP, _event)
789 #define CMN_EVENT_SBSX(_model, _name, _event) \
790 CMN_EVENT_ATTR(_model, sbsx_##_name, CMN_TYPE_SBSX, _event)
791 #define CMN_EVENT_RNID(_model, _name, _event) \
792 CMN_EVENT_ATTR(_model, rnid_##_name, CMN_TYPE_RNI, _event)
793 #define CMN_EVENT_MTSX(_name, _event) \
794 CMN_EVENT_ATTR(CMN_ANY, mtsx_##_name, CMN_TYPE_MTSX, _event)
795 #define CMN_EVENT_CXRA(_model, _name, _event) \
796 CMN_EVENT_ATTR(_model, cxra_##_name, CMN_TYPE_CXRA, _event)
797 #define CMN_EVENT_CXHA(_name, _event) \
798 CMN_EVENT_ATTR(CMN_ANY, cxha_##_name, CMN_TYPE_CXHA, _event)
799 #define CMN_EVENT_CCRA(_name, _event) \
800 CMN_EVENT_ATTR(CMN_ANY, ccra_##_name, CMN_TYPE_CCRA, _event)
801 #define CMN_EVENT_CCHA(_model, _name, _event) \
802 CMN_EVENT_ATTR(_model, ccha_##_name, CMN_TYPE_CCHA, _event)
803 #define CMN_EVENT_CCLA(_name, _event) \
804 CMN_EVENT_ATTR(CMN_ANY, ccla_##_name, CMN_TYPE_CCLA, _event)
805 #define CMN_EVENT_HNS(_name, _event) \
806 CMN_EVENT_ATTR(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
807
808 #define CMN_EVENT_DVM(_model, _name, _event) \
809 _CMN_EVENT_DVM(_model, _name, _event, 0, SEL_NONE)
810 #define CMN_EVENT_DVM_OCC(_model, _name, _event) \
811 _CMN_EVENT_DVM(_model, _name##_all, _event, 0, SEL_OCCUP1ID), \
812 _CMN_EVENT_DVM(_model, _name##_dvmop, _event, 1, SEL_OCCUP1ID), \
813 _CMN_EVENT_DVM(_model, _name##_dvmsync, _event, 2, SEL_OCCUP1ID)
814
815 #define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \
816 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_OCCUP1ID), \
817 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 1, SEL_OCCUP1ID), \
818 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 2, SEL_OCCUP1ID), \
819 _CMN_EVENT_ATTR(_model, _name##_atomic, _type, _event, 3, SEL_OCCUP1ID), \
820 _CMN_EVENT_ATTR(_model, _name##_stash, _type, _event, 4, SEL_OCCUP1ID)
821 #define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \
822 _CMN_EVENT_ATTR(_model, _name##_class0, _type, _event, 0, SEL_CLASS_OCCUP_ID), \
823 _CMN_EVENT_ATTR(_model, _name##_class1, _type, _event, 1, SEL_CLASS_OCCUP_ID), \
824 _CMN_EVENT_ATTR(_model, _name##_class2, _type, _event, 2, SEL_CLASS_OCCUP_ID), \
825 _CMN_EVENT_ATTR(_model, _name##_class3, _type, _event, 3, SEL_CLASS_OCCUP_ID)
826 #define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \
827 _CMN_EVENT_ATTR(_model, _name##_all, _type, _event, 0, SEL_CBUSY_SNTHROTTLE_SEL), \
828 _CMN_EVENT_ATTR(_model, _name##_group0_read, _type, _event, 1, SEL_CBUSY_SNTHROTTLE_SEL), \
829 _CMN_EVENT_ATTR(_model, _name##_group0_write, _type, _event, 2, SEL_CBUSY_SNTHROTTLE_SEL), \
830 _CMN_EVENT_ATTR(_model, _name##_group1_read, _type, _event, 3, SEL_CBUSY_SNTHROTTLE_SEL), \
831 _CMN_EVENT_ATTR(_model, _name##_group1_write, _type, _event, 4, SEL_CBUSY_SNTHROTTLE_SEL), \
832 _CMN_EVENT_ATTR(_model, _name##_read, _type, _event, 5, SEL_CBUSY_SNTHROTTLE_SEL), \
833 _CMN_EVENT_ATTR(_model, _name##_write, _type, _event, 6, SEL_CBUSY_SNTHROTTLE_SEL)
834
835 #define CMN_EVENT_HNF_OCC(_model, _name, _event) \
836 CMN_EVENT_HN_OCC(_model, hnf_##_name, CMN_TYPE_HNF, _event)
837 #define CMN_EVENT_HNF_CLS(_model, _name, _event) \
838 CMN_EVENT_HN_CLS(_model, hnf_##_name, CMN_TYPE_HNF, _event)
839 #define CMN_EVENT_HNF_SNT(_model, _name, _event) \
840 CMN_EVENT_HN_SNT(_model, hnf_##_name, CMN_TYPE_HNF, _event)
841
842 #define CMN_EVENT_HNS_OCC(_name, _event) \
843 CMN_EVENT_HN_OCC(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event), \
844 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_rxsnp, CMN_TYPE_HNS, _event, 5, SEL_OCCUP1ID), \
845 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 6, SEL_OCCUP1ID), \
846 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 7, SEL_OCCUP1ID)
847 #define CMN_EVENT_HNS_CLS( _name, _event) \
848 CMN_EVENT_HN_CLS(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
849 #define CMN_EVENT_HNS_SNT(_name, _event) \
850 CMN_EVENT_HN_SNT(CMN_ANY, hns_##_name, CMN_TYPE_HNS, _event)
851 #define CMN_EVENT_HNS_HBT(_name, _event) \
852 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_HBT_LBT_SEL), \
853 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_hbt, CMN_TYPE_HNS, _event, 1, SEL_HBT_LBT_SEL), \
854 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_lbt, CMN_TYPE_HNS, _event, 2, SEL_HBT_LBT_SEL)
855 #define CMN_EVENT_HNS_SNH(_name, _event) \
856 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_all, CMN_TYPE_HNS, _event, 0, SEL_SN_HOME_SEL), \
857 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_sn, CMN_TYPE_HNS, _event, 1, SEL_SN_HOME_SEL), \
858 _CMN_EVENT_ATTR(CMN_ANY, hns_##_name##_home, CMN_TYPE_HNS, _event, 2, SEL_SN_HOME_SEL)
859
860 #define _CMN_EVENT_XP_MESH(_name, _event) \
861 __CMN_EVENT_XP(e_##_name, (_event) | (0 << 2)), \
862 __CMN_EVENT_XP(w_##_name, (_event) | (1 << 2)), \
863 __CMN_EVENT_XP(n_##_name, (_event) | (2 << 2)), \
864 __CMN_EVENT_XP(s_##_name, (_event) | (3 << 2))
865
866 #define _CMN_EVENT_XP_PORT(_name, _event) \
867 __CMN_EVENT_XP(p0_##_name, (_event) | (4 << 2)), \
868 __CMN_EVENT_XP(p1_##_name, (_event) | (5 << 2)), \
869 __CMN_EVENT_XP(p2_##_name, (_event) | (6 << 2)), \
870 __CMN_EVENT_XP(p3_##_name, (_event) | (7 << 2))
871
872 #define _CMN_EVENT_XP(_name, _event) \
873 _CMN_EVENT_XP_MESH(_name, _event), \
874 _CMN_EVENT_XP_PORT(_name, _event)
875
876 /* Good thing there are only 3 fundamental XP events... */
877 #define CMN_EVENT_XP(_name, _event) \
878 _CMN_EVENT_XP(req_##_name, (_event) | (0 << 5)), \
879 _CMN_EVENT_XP(rsp_##_name, (_event) | (1 << 5)), \
880 _CMN_EVENT_XP(snp_##_name, (_event) | (2 << 5)), \
881 _CMN_EVENT_XP(dat_##_name, (_event) | (3 << 5)), \
882 _CMN_EVENT_XP(pub_##_name, (_event) | (4 << 5)), \
883 _CMN_EVENT_XP(rsp2_##_name, (_event) | (5 << 5)), \
884 _CMN_EVENT_XP(dat2_##_name, (_event) | (6 << 5)), \
885 _CMN_EVENT_XP(snp2_##_name, (_event) | (7 << 5)), \
886 _CMN_EVENT_XP(req2_##_name, (_event) | (8 << 5))
887
888 #define CMN_EVENT_XP_DAT(_name, _event) \
889 _CMN_EVENT_XP_PORT(dat_##_name, (_event) | (3 << 5)), \
890 _CMN_EVENT_XP_PORT(dat2_##_name, (_event) | (6 << 5))
891
892
893 static struct attribute *arm_cmn_event_attrs[] = {
894 CMN_EVENT_DTC(cycles),
895
896 /*
897 * DVM node events conflict with HN-I events in the equivalent PMU
898 * slot, but our lazy short-cut of using the DTM counter index for
899 * the PMU index as well happens to avoid that by construction.
900 */
901 CMN_EVENT_DVM(CMN600, rxreq_dvmop, 0x01),
902 CMN_EVENT_DVM(CMN600, rxreq_dvmsync, 0x02),
903 CMN_EVENT_DVM(CMN600, rxreq_dvmop_vmid_filtered, 0x03),
904 CMN_EVENT_DVM(CMN600, rxreq_retried, 0x04),
905 CMN_EVENT_DVM_OCC(CMN600, rxreq_trk_occupancy, 0x05),
906 CMN_EVENT_DVM(NOT_CMN600, dvmop_tlbi, 0x01),
907 CMN_EVENT_DVM(NOT_CMN600, dvmop_bpi, 0x02),
908 CMN_EVENT_DVM(NOT_CMN600, dvmop_pici, 0x03),
909 CMN_EVENT_DVM(NOT_CMN600, dvmop_vici, 0x04),
910 CMN_EVENT_DVM(NOT_CMN600, dvmsync, 0x05),
911 CMN_EVENT_DVM(NOT_CMN600, vmid_filtered, 0x06),
912 CMN_EVENT_DVM(NOT_CMN600, rndop_filtered, 0x07),
913 CMN_EVENT_DVM(NOT_CMN600, retry, 0x08),
914 CMN_EVENT_DVM(NOT_CMN600, txsnp_flitv, 0x09),
915 CMN_EVENT_DVM(NOT_CMN600, txsnp_stall, 0x0a),
916 CMN_EVENT_DVM(NOT_CMN600, trkfull, 0x0b),
917 CMN_EVENT_DVM_OCC(NOT_CMN600, trk_occupancy, 0x0c),
918 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_cxha, 0x0d),
919 CMN_EVENT_DVM_OCC(CMN700, trk_occupancy_pdn, 0x0e),
920 CMN_EVENT_DVM(CMN700, trk_alloc, 0x0f),
921 CMN_EVENT_DVM(CMN700, trk_cxha_alloc, 0x10),
922 CMN_EVENT_DVM(CMN700, trk_pdn_alloc, 0x11),
923 CMN_EVENT_DVM(CMN700, txsnp_stall_limit, 0x12),
924 CMN_EVENT_DVM(CMN700, rxsnp_stall_starv, 0x13),
925 CMN_EVENT_DVM(CMN700, txsnp_sync_stall_op, 0x14),
926
927 CMN_EVENT_HNF(CMN_ANY, cache_miss, 0x01),
928 CMN_EVENT_HNF(CMN_ANY, slc_sf_cache_access, 0x02),
929 CMN_EVENT_HNF(CMN_ANY, cache_fill, 0x03),
930 CMN_EVENT_HNF(CMN_ANY, pocq_retry, 0x04),
931 CMN_EVENT_HNF(CMN_ANY, pocq_reqs_recvd, 0x05),
932 CMN_EVENT_HNF(CMN_ANY, sf_hit, 0x06),
933 CMN_EVENT_HNF(CMN_ANY, sf_evictions, 0x07),
934 CMN_EVENT_HNF(CMN_ANY, dir_snoops_sent, 0x08),
935 CMN_EVENT_HNF(CMN_ANY, brd_snoops_sent, 0x09),
936 CMN_EVENT_HNF(CMN_ANY, slc_eviction, 0x0a),
937 CMN_EVENT_HNF(CMN_ANY, slc_fill_invalid_way, 0x0b),
938 CMN_EVENT_HNF(CMN_ANY, mc_retries, 0x0c),
939 CMN_EVENT_HNF(CMN_ANY, mc_reqs, 0x0d),
940 CMN_EVENT_HNF(CMN_ANY, qos_hh_retry, 0x0e),
941 CMN_EVENT_HNF_OCC(CMN_ANY, qos_pocq_occupancy, 0x0f),
942 CMN_EVENT_HNF(CMN_ANY, pocq_addrhaz, 0x10),
943 CMN_EVENT_HNF(CMN_ANY, pocq_atomic_addrhaz, 0x11),
944 CMN_EVENT_HNF(CMN_ANY, ld_st_swp_adq_full, 0x12),
945 CMN_EVENT_HNF(CMN_ANY, cmp_adq_full, 0x13),
946 CMN_EVENT_HNF(CMN_ANY, txdat_stall, 0x14),
947 CMN_EVENT_HNF(CMN_ANY, txrsp_stall, 0x15),
948 CMN_EVENT_HNF(CMN_ANY, seq_full, 0x16),
949 CMN_EVENT_HNF(CMN_ANY, seq_hit, 0x17),
950 CMN_EVENT_HNF(CMN_ANY, snp_sent, 0x18),
951 CMN_EVENT_HNF(CMN_ANY, sfbi_dir_snp_sent, 0x19),
952 CMN_EVENT_HNF(CMN_ANY, sfbi_brd_snp_sent, 0x1a),
953 CMN_EVENT_HNF(CMN_ANY, snp_sent_untrk, 0x1b),
954 CMN_EVENT_HNF(CMN_ANY, intv_dirty, 0x1c),
955 CMN_EVENT_HNF(CMN_ANY, stash_snp_sent, 0x1d),
956 CMN_EVENT_HNF(CMN_ANY, stash_data_pull, 0x1e),
957 CMN_EVENT_HNF(CMN_ANY, snp_fwded, 0x1f),
958 CMN_EVENT_HNF(NOT_CMN600, atomic_fwd, 0x20),
959 CMN_EVENT_HNF(NOT_CMN600, mpam_hardlim, 0x21),
960 CMN_EVENT_HNF(NOT_CMN600, mpam_softlim, 0x22),
961 CMN_EVENT_HNF(CMN_650ON, snp_sent_cluster, 0x23),
962 CMN_EVENT_HNF(CMN_650ON, sf_imprecise_evict, 0x24),
963 CMN_EVENT_HNF(CMN_650ON, sf_evict_shared_line, 0x25),
964 CMN_EVENT_HNF_CLS(CMN700, pocq_class_occup, 0x26),
965 CMN_EVENT_HNF_CLS(CMN700, pocq_class_retry, 0x27),
966 CMN_EVENT_HNF_CLS(CMN700, class_mc_reqs, 0x28),
967 CMN_EVENT_HNF_CLS(CMN700, class_cgnt_cmin, 0x29),
968 CMN_EVENT_HNF_SNT(CMN700, sn_throttle, 0x2a),
969 CMN_EVENT_HNF_SNT(CMN700, sn_throttle_min, 0x2b),
970 CMN_EVENT_HNF(CMN700, sf_precise_to_imprecise, 0x2c),
971 CMN_EVENT_HNF(CMN700, snp_intv_cln, 0x2d),
972 CMN_EVENT_HNF(CMN700, nc_excl, 0x2e),
973 CMN_EVENT_HNF(CMN700, excl_mon_ovfl, 0x2f),
974
975 CMN_EVENT_HNI(rrt_rd_occ_cnt_ovfl, 0x20),
976 CMN_EVENT_HNI(rrt_wr_occ_cnt_ovfl, 0x21),
977 CMN_EVENT_HNI(rdt_rd_occ_cnt_ovfl, 0x22),
978 CMN_EVENT_HNI(rdt_wr_occ_cnt_ovfl, 0x23),
979 CMN_EVENT_HNI(wdb_occ_cnt_ovfl, 0x24),
980 CMN_EVENT_HNI(rrt_rd_alloc, 0x25),
981 CMN_EVENT_HNI(rrt_wr_alloc, 0x26),
982 CMN_EVENT_HNI(rdt_rd_alloc, 0x27),
983 CMN_EVENT_HNI(rdt_wr_alloc, 0x28),
984 CMN_EVENT_HNI(wdb_alloc, 0x29),
985 CMN_EVENT_HNI(txrsp_retryack, 0x2a),
986 CMN_EVENT_HNI(arvalid_no_arready, 0x2b),
987 CMN_EVENT_HNI(arready_no_arvalid, 0x2c),
988 CMN_EVENT_HNI(awvalid_no_awready, 0x2d),
989 CMN_EVENT_HNI(awready_no_awvalid, 0x2e),
990 CMN_EVENT_HNI(wvalid_no_wready, 0x2f),
991 CMN_EVENT_HNI(txdat_stall, 0x30),
992 CMN_EVENT_HNI(nonpcie_serialization, 0x31),
993 CMN_EVENT_HNI(pcie_serialization, 0x32),
994
995 /*
996 * HN-P events squat on top of the HN-I similarly to DVM events, except
997 * for being crammed into the same physical node as well. And of course
998 * where would the fun be if the same events were in the same order...
999 */
1000 CMN_EVENT_HNP(rrt_wr_occ_cnt_ovfl, 0x01),
1001 CMN_EVENT_HNP(rdt_wr_occ_cnt_ovfl, 0x02),
1002 CMN_EVENT_HNP(wdb_occ_cnt_ovfl, 0x03),
1003 CMN_EVENT_HNP(rrt_wr_alloc, 0x04),
1004 CMN_EVENT_HNP(rdt_wr_alloc, 0x05),
1005 CMN_EVENT_HNP(wdb_alloc, 0x06),
1006 CMN_EVENT_HNP(awvalid_no_awready, 0x07),
1007 CMN_EVENT_HNP(awready_no_awvalid, 0x08),
1008 CMN_EVENT_HNP(wvalid_no_wready, 0x09),
1009 CMN_EVENT_HNP(rrt_rd_occ_cnt_ovfl, 0x11),
1010 CMN_EVENT_HNP(rdt_rd_occ_cnt_ovfl, 0x12),
1011 CMN_EVENT_HNP(rrt_rd_alloc, 0x13),
1012 CMN_EVENT_HNP(rdt_rd_alloc, 0x14),
1013 CMN_EVENT_HNP(arvalid_no_arready, 0x15),
1014 CMN_EVENT_HNP(arready_no_arvalid, 0x16),
1015
1016 CMN_EVENT_XP(txflit_valid, 0x01),
1017 CMN_EVENT_XP(txflit_stall, 0x02),
1018 CMN_EVENT_XP_DAT(partial_dat_flit, 0x03),
1019 /* We treat watchpoints as a special made-up class of XP events */
1020 CMN_EVENT_ATTR(CMN_ANY, watchpoint_up, CMN_TYPE_WP, CMN_WP_UP),
1021 CMN_EVENT_ATTR(CMN_ANY, watchpoint_down, CMN_TYPE_WP, CMN_WP_DOWN),
1022
1023 CMN_EVENT_SBSX(CMN_ANY, rd_req, 0x01),
1024 CMN_EVENT_SBSX(CMN_ANY, wr_req, 0x02),
1025 CMN_EVENT_SBSX(CMN_ANY, cmo_req, 0x03),
1026 CMN_EVENT_SBSX(CMN_ANY, txrsp_retryack, 0x04),
1027 CMN_EVENT_SBSX(CMN_ANY, txdat_flitv, 0x05),
1028 CMN_EVENT_SBSX(CMN_ANY, txrsp_flitv, 0x06),
1029 CMN_EVENT_SBSX(CMN_ANY, rd_req_trkr_occ_cnt_ovfl, 0x11),
1030 CMN_EVENT_SBSX(CMN_ANY, wr_req_trkr_occ_cnt_ovfl, 0x12),
1031 CMN_EVENT_SBSX(CMN_ANY, cmo_req_trkr_occ_cnt_ovfl, 0x13),
1032 CMN_EVENT_SBSX(CMN_ANY, wdb_occ_cnt_ovfl, 0x14),
1033 CMN_EVENT_SBSX(CMN_ANY, rd_axi_trkr_occ_cnt_ovfl, 0x15),
1034 CMN_EVENT_SBSX(CMN_ANY, cmo_axi_trkr_occ_cnt_ovfl, 0x16),
1035 CMN_EVENT_SBSX(NOT_CMN600, rdb_occ_cnt_ovfl, 0x17),
1036 CMN_EVENT_SBSX(CMN_ANY, arvalid_no_arready, 0x21),
1037 CMN_EVENT_SBSX(CMN_ANY, awvalid_no_awready, 0x22),
1038 CMN_EVENT_SBSX(CMN_ANY, wvalid_no_wready, 0x23),
1039 CMN_EVENT_SBSX(CMN_ANY, txdat_stall, 0x24),
1040 CMN_EVENT_SBSX(CMN_ANY, txrsp_stall, 0x25),
1041
1042 CMN_EVENT_RNID(CMN_ANY, s0_rdata_beats, 0x01),
1043 CMN_EVENT_RNID(CMN_ANY, s1_rdata_beats, 0x02),
1044 CMN_EVENT_RNID(CMN_ANY, s2_rdata_beats, 0x03),
1045 CMN_EVENT_RNID(CMN_ANY, rxdat_flits, 0x04),
1046 CMN_EVENT_RNID(CMN_ANY, txdat_flits, 0x05),
1047 CMN_EVENT_RNID(CMN_ANY, txreq_flits_total, 0x06),
1048 CMN_EVENT_RNID(CMN_ANY, txreq_flits_retried, 0x07),
1049 CMN_EVENT_RNID(CMN_ANY, rrt_occ_ovfl, 0x08),
1050 CMN_EVENT_RNID(CMN_ANY, wrt_occ_ovfl, 0x09),
1051 CMN_EVENT_RNID(CMN_ANY, txreq_flits_replayed, 0x0a),
1052 CMN_EVENT_RNID(CMN_ANY, wrcancel_sent, 0x0b),
1053 CMN_EVENT_RNID(CMN_ANY, s0_wdata_beats, 0x0c),
1054 CMN_EVENT_RNID(CMN_ANY, s1_wdata_beats, 0x0d),
1055 CMN_EVENT_RNID(CMN_ANY, s2_wdata_beats, 0x0e),
1056 CMN_EVENT_RNID(CMN_ANY, rrt_alloc, 0x0f),
1057 CMN_EVENT_RNID(CMN_ANY, wrt_alloc, 0x10),
1058 CMN_EVENT_RNID(CMN600, rdb_unord, 0x11),
1059 CMN_EVENT_RNID(CMN600, rdb_replay, 0x12),
1060 CMN_EVENT_RNID(CMN600, rdb_hybrid, 0x13),
1061 CMN_EVENT_RNID(CMN600, rdb_ord, 0x14),
1062 CMN_EVENT_RNID(NOT_CMN600, padb_occ_ovfl, 0x11),
1063 CMN_EVENT_RNID(NOT_CMN600, rpdb_occ_ovfl, 0x12),
1064 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice1, 0x13),
1065 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice2, 0x14),
1066 CMN_EVENT_RNID(NOT_CMN600, rrt_occup_ovfl_slice3, 0x15),
1067 CMN_EVENT_RNID(NOT_CMN600, wrt_throttled, 0x16),
1068 CMN_EVENT_RNID(CMN700, ldb_full, 0x17),
1069 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice0, 0x18),
1070 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice1, 0x19),
1071 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice2, 0x1a),
1072 CMN_EVENT_RNID(CMN700, rrt_rd_req_occup_ovfl_slice3, 0x1b),
1073 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice0, 0x1c),
1074 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice1, 0x1d),
1075 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice2, 0x1e),
1076 CMN_EVENT_RNID(CMN700, rrt_burst_occup_ovfl_slice3, 0x1f),
1077 CMN_EVENT_RNID(CMN700, rrt_burst_alloc, 0x20),
1078 CMN_EVENT_RNID(CMN700, awid_hash, 0x21),
1079 CMN_EVENT_RNID(CMN700, atomic_alloc, 0x22),
1080 CMN_EVENT_RNID(CMN700, atomic_occ_ovfl, 0x23),
1081
1082 CMN_EVENT_MTSX(tc_lookup, 0x01),
1083 CMN_EVENT_MTSX(tc_fill, 0x02),
1084 CMN_EVENT_MTSX(tc_miss, 0x03),
1085 CMN_EVENT_MTSX(tdb_forward, 0x04),
1086 CMN_EVENT_MTSX(tcq_hazard, 0x05),
1087 CMN_EVENT_MTSX(tcq_rd_alloc, 0x06),
1088 CMN_EVENT_MTSX(tcq_wr_alloc, 0x07),
1089 CMN_EVENT_MTSX(tcq_cmo_alloc, 0x08),
1090 CMN_EVENT_MTSX(axi_rd_req, 0x09),
1091 CMN_EVENT_MTSX(axi_wr_req, 0x0a),
1092 CMN_EVENT_MTSX(tcq_occ_cnt_ovfl, 0x0b),
1093 CMN_EVENT_MTSX(tdb_occ_cnt_ovfl, 0x0c),
1094
1095 CMN_EVENT_CXRA(CMN_ANY, rht_occ, 0x01),
1096 CMN_EVENT_CXRA(CMN_ANY, sht_occ, 0x02),
1097 CMN_EVENT_CXRA(CMN_ANY, rdb_occ, 0x03),
1098 CMN_EVENT_CXRA(CMN_ANY, wdb_occ, 0x04),
1099 CMN_EVENT_CXRA(CMN_ANY, ssb_occ, 0x05),
1100 CMN_EVENT_CXRA(CMN_ANY, snp_bcasts, 0x06),
1101 CMN_EVENT_CXRA(CMN_ANY, req_chains, 0x07),
1102 CMN_EVENT_CXRA(CMN_ANY, req_chain_avglen, 0x08),
1103 CMN_EVENT_CXRA(CMN_ANY, chirsp_stalls, 0x09),
1104 CMN_EVENT_CXRA(CMN_ANY, chidat_stalls, 0x0a),
1105 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link0, 0x0b),
1106 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link1, 0x0c),
1107 CMN_EVENT_CXRA(CMN_ANY, cxreq_pcrd_stalls_link2, 0x0d),
1108 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link0, 0x0e),
1109 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link1, 0x0f),
1110 CMN_EVENT_CXRA(CMN_ANY, cxdat_pcrd_stalls_link2, 0x10),
1111 CMN_EVENT_CXRA(CMN_ANY, external_chirsp_stalls, 0x11),
1112 CMN_EVENT_CXRA(CMN_ANY, external_chidat_stalls, 0x12),
1113 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link0, 0x13),
1114 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link1, 0x14),
1115 CMN_EVENT_CXRA(NOT_CMN600, cxmisc_pcrd_stalls_link2, 0x15),
1116
1117 CMN_EVENT_CXHA(rddatbyp, 0x21),
1118 CMN_EVENT_CXHA(chirsp_up_stall, 0x22),
1119 CMN_EVENT_CXHA(chidat_up_stall, 0x23),
1120 CMN_EVENT_CXHA(snppcrd_link0_stall, 0x24),
1121 CMN_EVENT_CXHA(snppcrd_link1_stall, 0x25),
1122 CMN_EVENT_CXHA(snppcrd_link2_stall, 0x26),
1123 CMN_EVENT_CXHA(reqtrk_occ, 0x27),
1124 CMN_EVENT_CXHA(rdb_occ, 0x28),
1125 CMN_EVENT_CXHA(rdbyp_occ, 0x29),
1126 CMN_EVENT_CXHA(wdb_occ, 0x2a),
1127 CMN_EVENT_CXHA(snptrk_occ, 0x2b),
1128 CMN_EVENT_CXHA(sdb_occ, 0x2c),
1129 CMN_EVENT_CXHA(snphaz_occ, 0x2d),
1130
1131 CMN_EVENT_CCRA(rht_occ, 0x41),
1132 CMN_EVENT_CCRA(sht_occ, 0x42),
1133 CMN_EVENT_CCRA(rdb_occ, 0x43),
1134 CMN_EVENT_CCRA(wdb_occ, 0x44),
1135 CMN_EVENT_CCRA(ssb_occ, 0x45),
1136 CMN_EVENT_CCRA(snp_bcasts, 0x46),
1137 CMN_EVENT_CCRA(req_chains, 0x47),
1138 CMN_EVENT_CCRA(req_chain_avglen, 0x48),
1139 CMN_EVENT_CCRA(chirsp_stalls, 0x49),
1140 CMN_EVENT_CCRA(chidat_stalls, 0x4a),
1141 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link0, 0x4b),
1142 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link1, 0x4c),
1143 CMN_EVENT_CCRA(cxreq_pcrd_stalls_link2, 0x4d),
1144 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link0, 0x4e),
1145 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link1, 0x4f),
1146 CMN_EVENT_CCRA(cxdat_pcrd_stalls_link2, 0x50),
1147 CMN_EVENT_CCRA(external_chirsp_stalls, 0x51),
1148 CMN_EVENT_CCRA(external_chidat_stalls, 0x52),
1149 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link0, 0x53),
1150 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link1, 0x54),
1151 CMN_EVENT_CCRA(cxmisc_pcrd_stalls_link2, 0x55),
1152 CMN_EVENT_CCRA(rht_alloc, 0x56),
1153 CMN_EVENT_CCRA(sht_alloc, 0x57),
1154 CMN_EVENT_CCRA(rdb_alloc, 0x58),
1155 CMN_EVENT_CCRA(wdb_alloc, 0x59),
1156 CMN_EVENT_CCRA(ssb_alloc, 0x5a),
1157
1158 CMN_EVENT_CCHA(CMN_ANY, rddatbyp, 0x61),
1159 CMN_EVENT_CCHA(CMN_ANY, chirsp_up_stall, 0x62),
1160 CMN_EVENT_CCHA(CMN_ANY, chidat_up_stall, 0x63),
1161 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link0_stall, 0x64),
1162 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link1_stall, 0x65),
1163 CMN_EVENT_CCHA(CMN_ANY, snppcrd_link2_stall, 0x66),
1164 CMN_EVENT_CCHA(CMN_ANY, reqtrk_occ, 0x67),
1165 CMN_EVENT_CCHA(CMN_ANY, rdb_occ, 0x68),
1166 CMN_EVENT_CCHA(CMN_ANY, rdbyp_occ, 0x69),
1167 CMN_EVENT_CCHA(CMN_ANY, wdb_occ, 0x6a),
1168 CMN_EVENT_CCHA(CMN_ANY, snptrk_occ, 0x6b),
1169 CMN_EVENT_CCHA(CMN_ANY, sdb_occ, 0x6c),
1170 CMN_EVENT_CCHA(CMN_ANY, snphaz_occ, 0x6d),
1171 CMN_EVENT_CCHA(CMN_ANY, reqtrk_alloc, 0x6e),
1172 CMN_EVENT_CCHA(CMN_ANY, rdb_alloc, 0x6f),
1173 CMN_EVENT_CCHA(CMN_ANY, rdbyp_alloc, 0x70),
1174 CMN_EVENT_CCHA(CMN_ANY, wdb_alloc, 0x71),
1175 CMN_EVENT_CCHA(CMN_ANY, snptrk_alloc, 0x72),
1176 CMN_EVENT_CCHA(CMN_ANY, db_alloc, 0x73),
1177 CMN_EVENT_CCHA(CMN_ANY, snphaz_alloc, 0x74),
1178 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_occ, 0x75),
1179 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_req_alloc, 0x76),
1180 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_occ, 0x77),
1181 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_req_alloc, 0x78),
1182 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_occ, 0x79),
1183 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_req_alloc, 0x7a),
1184 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_occ, 0x7b),
1185 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_reg_req_alloc, 0x7c),
1186 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_occ, 0x7d),
1187 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_rsvd_req_alloc, 0x7e),
1188 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_occ, 0x7f),
1189 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_dat_alloc, 0x80),
1190 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_occ, 0x81),
1191 CMN_EVENT_CCHA(CMN_ANY, pb_rhu_pcie_dat_alloc, 0x82),
1192 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_occ, 0x83),
1193 CMN_EVENT_CCHA(CMN_ANY, pb_pcie_wr_dat_alloc, 0x84),
1194 CMN_EVENT_CCHA(CMNS3, chirsp1_up_stall, 0x85),
1195
1196 CMN_EVENT_CCLA(rx_cxs, 0x21),
1197 CMN_EVENT_CCLA(tx_cxs, 0x22),
1198 CMN_EVENT_CCLA(rx_cxs_avg_size, 0x23),
1199 CMN_EVENT_CCLA(tx_cxs_avg_size, 0x24),
1200 CMN_EVENT_CCLA(tx_cxs_lcrd_backpressure, 0x25),
1201 CMN_EVENT_CCLA(link_crdbuf_occ, 0x26),
1202 CMN_EVENT_CCLA(link_crdbuf_alloc, 0x27),
1203 CMN_EVENT_CCLA(pfwd_rcvr_cxs, 0x28),
1204 CMN_EVENT_CCLA(pfwd_sndr_num_flits, 0x29),
1205 CMN_EVENT_CCLA(pfwd_sndr_stalls_static_crd, 0x2a),
1206 CMN_EVENT_CCLA(pfwd_sndr_stalls_dynmaic_crd, 0x2b),
1207
1208 CMN_EVENT_HNS_HBT(cache_miss, 0x01),
1209 CMN_EVENT_HNS_HBT(slc_sf_cache_access, 0x02),
1210 CMN_EVENT_HNS_HBT(cache_fill, 0x03),
1211 CMN_EVENT_HNS_HBT(pocq_retry, 0x04),
1212 CMN_EVENT_HNS_HBT(pocq_reqs_recvd, 0x05),
1213 CMN_EVENT_HNS_HBT(sf_hit, 0x06),
1214 CMN_EVENT_HNS_HBT(sf_evictions, 0x07),
1215 CMN_EVENT_HNS(dir_snoops_sent, 0x08),
1216 CMN_EVENT_HNS(brd_snoops_sent, 0x09),
1217 CMN_EVENT_HNS_HBT(slc_eviction, 0x0a),
1218 CMN_EVENT_HNS_HBT(slc_fill_invalid_way, 0x0b),
1219 CMN_EVENT_HNS(mc_retries_local, 0x0c),
1220 CMN_EVENT_HNS_SNH(mc_reqs_local, 0x0d),
1221 CMN_EVENT_HNS(qos_hh_retry, 0x0e),
1222 CMN_EVENT_HNS_OCC(qos_pocq_occupancy, 0x0f),
1223 CMN_EVENT_HNS(pocq_addrhaz, 0x10),
1224 CMN_EVENT_HNS(pocq_atomic_addrhaz, 0x11),
1225 CMN_EVENT_HNS(ld_st_swp_adq_full, 0x12),
1226 CMN_EVENT_HNS(cmp_adq_full, 0x13),
1227 CMN_EVENT_HNS(txdat_stall, 0x14),
1228 CMN_EVENT_HNS(txrsp_stall, 0x15),
1229 CMN_EVENT_HNS(seq_full, 0x16),
1230 CMN_EVENT_HNS(seq_hit, 0x17),
1231 CMN_EVENT_HNS(snp_sent, 0x18),
1232 CMN_EVENT_HNS(sfbi_dir_snp_sent, 0x19),
1233 CMN_EVENT_HNS(sfbi_brd_snp_sent, 0x1a),
1234 CMN_EVENT_HNS(intv_dirty, 0x1c),
1235 CMN_EVENT_HNS(stash_snp_sent, 0x1d),
1236 CMN_EVENT_HNS(stash_data_pull, 0x1e),
1237 CMN_EVENT_HNS(snp_fwded, 0x1f),
1238 CMN_EVENT_HNS(atomic_fwd, 0x20),
1239 CMN_EVENT_HNS(mpam_hardlim, 0x21),
1240 CMN_EVENT_HNS(mpam_softlim, 0x22),
1241 CMN_EVENT_HNS(snp_sent_cluster, 0x23),
1242 CMN_EVENT_HNS(sf_imprecise_evict, 0x24),
1243 CMN_EVENT_HNS(sf_evict_shared_line, 0x25),
1244 CMN_EVENT_HNS_CLS(pocq_class_occup, 0x26),
1245 CMN_EVENT_HNS_CLS(pocq_class_retry, 0x27),
1246 CMN_EVENT_HNS_CLS(class_mc_reqs_local, 0x28),
1247 CMN_EVENT_HNS_CLS(class_cgnt_cmin, 0x29),
1248 CMN_EVENT_HNS_SNT(sn_throttle, 0x2a),
1249 CMN_EVENT_HNS_SNT(sn_throttle_min, 0x2b),
1250 CMN_EVENT_HNS(sf_precise_to_imprecise, 0x2c),
1251 CMN_EVENT_HNS(snp_intv_cln, 0x2d),
1252 CMN_EVENT_HNS(nc_excl, 0x2e),
1253 CMN_EVENT_HNS(excl_mon_ovfl, 0x2f),
1254 CMN_EVENT_HNS(snp_req_recvd, 0x30),
1255 CMN_EVENT_HNS(snp_req_byp_pocq, 0x31),
1256 CMN_EVENT_HNS(dir_ccgha_snp_sent, 0x32),
1257 CMN_EVENT_HNS(brd_ccgha_snp_sent, 0x33),
1258 CMN_EVENT_HNS(ccgha_snp_stall, 0x34),
1259 CMN_EVENT_HNS(lbt_req_hardlim, 0x35),
1260 CMN_EVENT_HNS(hbt_req_hardlim, 0x36),
1261 CMN_EVENT_HNS(sf_reupdate, 0x37),
1262 CMN_EVENT_HNS(excl_sf_imprecise, 0x38),
1263 CMN_EVENT_HNS(snp_pocq_addrhaz, 0x39),
1264 CMN_EVENT_HNS(mc_retries_remote, 0x3a),
1265 CMN_EVENT_HNS_SNH(mc_reqs_remote, 0x3b),
1266 CMN_EVENT_HNS_CLS(class_mc_reqs_remote, 0x3c),
1267
1268 NULL
1269 };
1270
1271 static const struct attribute_group arm_cmn_event_attrs_group = {
1272 .name = "events",
1273 .attrs = arm_cmn_event_attrs,
1274 .is_visible = arm_cmn_event_attr_is_visible,
1275 };
1276
arm_cmn_format_show(struct device * dev,struct device_attribute * attr,char * buf)1277 static ssize_t arm_cmn_format_show(struct device *dev,
1278 struct device_attribute *attr, char *buf)
1279 {
1280 struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);
1281
1282 if (!fmt->config)
1283 return sysfs_emit(buf, "config:%*pbl\n", 64, &fmt->field);
1284
1285 return sysfs_emit(buf, "config%d:%*pbl\n", fmt->config, 64, &fmt->field);
1286 }
1287
1288 #define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \
1289 (&((struct arm_cmn_format_attr[]) {{ \
1290 .attr = __ATTR(_name, 0444, arm_cmn_format_show, NULL), \
1291 .config = _cfg, \
1292 .field = _fld, \
1293 }})[0].attr.attr)
1294 #define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0, _fld)
1295
1296 static struct attribute *arm_cmn_format_attrs[] = {
1297 CMN_FORMAT_ATTR(type, CMN_CONFIG_TYPE),
1298 CMN_FORMAT_ATTR(eventid, CMN_CONFIG_EVENTID),
1299 CMN_FORMAT_ATTR(occupid, CMN_CONFIG_OCCUPID),
1300 CMN_FORMAT_ATTR(bynodeid, CMN_CONFIG_BYNODEID),
1301 CMN_FORMAT_ATTR(nodeid, CMN_CONFIG_NODEID),
1302
1303 CMN_FORMAT_ATTR(wp_dev_sel, CMN_CONFIG_WP_DEV_SEL),
1304 CMN_FORMAT_ATTR(wp_chn_sel, CMN_CONFIG_WP_CHN_SEL),
1305 CMN_FORMAT_ATTR(wp_grp, CMN_CONFIG_WP_GRP),
1306 CMN_FORMAT_ATTR(wp_exclusive, CMN_CONFIG_WP_EXCLUSIVE),
1307 CMN_FORMAT_ATTR(wp_combine, CMN_CONFIG_WP_COMBINE),
1308
1309 _CMN_FORMAT_ATTR(wp_val, 1, CMN_CONFIG1_WP_VAL),
1310 _CMN_FORMAT_ATTR(wp_mask, 2, CMN_CONFIG2_WP_MASK),
1311
1312 NULL
1313 };
1314
1315 static const struct attribute_group arm_cmn_format_attrs_group = {
1316 .name = "format",
1317 .attrs = arm_cmn_format_attrs,
1318 };
1319
arm_cmn_cpumask_show(struct device * dev,struct device_attribute * attr,char * buf)1320 static ssize_t arm_cmn_cpumask_show(struct device *dev,
1321 struct device_attribute *attr, char *buf)
1322 {
1323 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1324
1325 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cmn->cpu));
1326 }
1327
1328 static struct device_attribute arm_cmn_cpumask_attr =
1329 __ATTR(cpumask, 0444, arm_cmn_cpumask_show, NULL);
1330
arm_cmn_identifier_show(struct device * dev,struct device_attribute * attr,char * buf)1331 static ssize_t arm_cmn_identifier_show(struct device *dev,
1332 struct device_attribute *attr, char *buf)
1333 {
1334 struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));
1335
1336 return sysfs_emit(buf, "%03x%02x\n", cmn->part, cmn->rev);
1337 }
1338
1339 static struct device_attribute arm_cmn_identifier_attr =
1340 __ATTR(identifier, 0444, arm_cmn_identifier_show, NULL);
1341
1342 static struct attribute *arm_cmn_other_attrs[] = {
1343 &arm_cmn_cpumask_attr.attr,
1344 &arm_cmn_identifier_attr.attr,
1345 NULL,
1346 };
1347
1348 static const struct attribute_group arm_cmn_other_attrs_group = {
1349 .attrs = arm_cmn_other_attrs,
1350 };
1351
1352 static const struct attribute_group *arm_cmn_attr_groups[] = {
1353 &arm_cmn_event_attrs_group,
1354 &arm_cmn_format_attrs_group,
1355 &arm_cmn_other_attrs_group,
1356 NULL
1357 };
1358
arm_cmn_find_free_wp_idx(struct arm_cmn_dtm * dtm,struct perf_event * event)1359 static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm,
1360 struct perf_event *event)
1361 {
1362 int wp_idx = CMN_EVENT_EVENTID(event);
1363
1364 if (dtm->wp_event[wp_idx] >= 0)
1365 if (dtm->wp_event[++wp_idx] >= 0)
1366 return -ENOSPC;
1367
1368 return wp_idx;
1369 }
1370
arm_cmn_get_assigned_wp_idx(struct perf_event * event,struct arm_cmn_hw_event * hw,unsigned int pos)1371 static int arm_cmn_get_assigned_wp_idx(struct perf_event *event,
1372 struct arm_cmn_hw_event *hw,
1373 unsigned int pos)
1374 {
1375 return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw->wp_idx, pos);
1376 }
1377
arm_cmn_claim_wp_idx(struct arm_cmn_dtm * dtm,struct perf_event * event,unsigned int dtc,int wp_idx,unsigned int pos)1378 static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm,
1379 struct perf_event *event,
1380 unsigned int dtc, int wp_idx,
1381 unsigned int pos)
1382 {
1383 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1384
1385 dtm->wp_event[wp_idx] = hw->dtc_idx[dtc];
1386 arm_cmn_set_wp_idx(hw->wp_idx, pos, wp_idx - CMN_EVENT_EVENTID(event));
1387 }
1388
arm_cmn_wp_config(struct perf_event * event,int wp_idx)1389 static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx)
1390 {
1391 u32 config;
1392 u32 dev = CMN_EVENT_WP_DEV_SEL(event);
1393 u32 chn = CMN_EVENT_WP_CHN_SEL(event);
1394 u32 grp = CMN_EVENT_WP_GRP(event);
1395 u32 exc = CMN_EVENT_WP_EXCLUSIVE(event);
1396 u32 combine = CMN_EVENT_WP_COMBINE(event);
1397 bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;
1398
1399 /* CMN-600 supports only primary and secondary matching groups */
1400 if (is_cmn600)
1401 grp &= 1;
1402
1403 config = FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL, dev) |
1404 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_CHN_SEL, chn) |
1405 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_GRP, grp) |
1406 FIELD_PREP(CMN_DTM_WPn_CONFIG_WP_DEV_SEL2, dev >> 1);
1407 if (exc)
1408 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_EXCLUSIVE :
1409 CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE;
1410
1411 /* wp_combine is available only on WP0 and WP2 */
1412 if (combine && !(wp_idx & 0x1))
1413 config |= is_cmn600 ? CMN600_WPn_CONFIG_WP_COMBINE :
1414 CMN_DTM_WPn_CONFIG_WP_COMBINE;
1415 return config;
1416 }
1417
arm_cmn_set_state(struct arm_cmn * cmn,u32 state)1418 static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)
1419 {
1420 if (!cmn->state)
1421 writel_relaxed(0, CMN_DT_PMCR(&cmn->dtc[0]));
1422 cmn->state |= state;
1423 }
1424
arm_cmn_clear_state(struct arm_cmn * cmn,u32 state)1425 static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)
1426 {
1427 cmn->state &= ~state;
1428 if (!cmn->state)
1429 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN,
1430 CMN_DT_PMCR(&cmn->dtc[0]));
1431 }
1432
arm_cmn_pmu_enable(struct pmu * pmu)1433 static void arm_cmn_pmu_enable(struct pmu *pmu)
1434 {
1435 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_DISABLED);
1436 }
1437
arm_cmn_pmu_disable(struct pmu * pmu)1438 static void arm_cmn_pmu_disable(struct pmu *pmu)
1439 {
1440 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_DISABLED);
1441 }
1442
arm_cmn_read_dtm(struct arm_cmn * cmn,struct arm_cmn_hw_event * hw,bool snapshot)1443 static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,
1444 bool snapshot)
1445 {
1446 struct arm_cmn_dtm *dtm = NULL;
1447 struct arm_cmn_node *dn;
1448 unsigned int i, offset, dtm_idx;
1449 u64 reg, count = 0;
1450
1451 offset = snapshot ? CMN_DTM_PMEVCNTSR : CMN_DTM_PMEVCNT;
1452 for_each_hw_dn(hw, dn, i) {
1453 if (dtm != &cmn->dtms[dn->dtm]) {
1454 dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1455 reg = readq_relaxed(dtm->base + offset);
1456 }
1457 dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1458 count += (u16)(reg >> (dtm_idx * 16));
1459 }
1460 return count;
1461 }
1462
arm_cmn_read_cc(struct arm_cmn_dtc * dtc)1463 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1464 {
1465 void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc);
1466 u64 val = readq_relaxed(pmccntr);
1467
1468 writeq_relaxed(CMN_CC_INIT, pmccntr);
1469 return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1) - 1);
1470 }
1471
arm_cmn_read_counter(struct arm_cmn_dtc * dtc,int idx)1472 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1473 {
1474 void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx);
1475 u32 val = readl_relaxed(pmevcnt);
1476
1477 writel_relaxed(CMN_COUNTER_INIT, pmevcnt);
1478 return val - CMN_COUNTER_INIT;
1479 }
1480
arm_cmn_init_counter(struct perf_event * event)1481 static void arm_cmn_init_counter(struct perf_event *event)
1482 {
1483 struct arm_cmn *cmn = to_cmn(event->pmu);
1484 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1485 u64 count;
1486
1487 for_each_hw_dtc_idx(hw, i, idx) {
1488 writel_relaxed(CMN_COUNTER_INIT, CMN_DT_PMEVCNT(&cmn->dtc[i], idx));
1489 cmn->dtc[i].counters[idx] = event;
1490 }
1491
1492 count = arm_cmn_read_dtm(cmn, hw, false);
1493 local64_set(&event->hw.prev_count, count);
1494 }
1495
arm_cmn_event_read(struct perf_event * event)1496 static void arm_cmn_event_read(struct perf_event *event)
1497 {
1498 struct arm_cmn *cmn = to_cmn(event->pmu);
1499 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1500 u64 delta, new, prev;
1501 unsigned long flags;
1502
1503 if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) {
1504 delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]);
1505 local64_add(delta, &event->count);
1506 return;
1507 }
1508 new = arm_cmn_read_dtm(cmn, hw, false);
1509 prev = local64_xchg(&event->hw.prev_count, new);
1510
1511 delta = new - prev;
1512
1513 local_irq_save(flags);
1514 for_each_hw_dtc_idx(hw, i, idx) {
1515 new = arm_cmn_read_counter(cmn->dtc + i, idx);
1516 delta += new << 16;
1517 }
1518 local_irq_restore(flags);
1519 local64_add(delta, &event->count);
1520 }
1521
arm_cmn_set_event_sel_hi(struct arm_cmn_node * dn,enum cmn_filter_select fsel,u8 occupid)1522 static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,
1523 enum cmn_filter_select fsel, u8 occupid)
1524 {
1525 u64 reg;
1526
1527 if (fsel == SEL_NONE)
1528 return 0;
1529
1530 if (!dn->occupid[fsel].count) {
1531 dn->occupid[fsel].val = occupid;
1532 reg = FIELD_PREP(CMN__PMU_CBUSY_SNTHROTTLE_SEL,
1533 dn->occupid[SEL_CBUSY_SNTHROTTLE_SEL].val) |
1534 FIELD_PREP(CMN__PMU_SN_HOME_SEL,
1535 dn->occupid[SEL_SN_HOME_SEL].val) |
1536 FIELD_PREP(CMN__PMU_HBT_LBT_SEL,
1537 dn->occupid[SEL_HBT_LBT_SEL].val) |
1538 FIELD_PREP(CMN__PMU_CLASS_OCCUP_ID,
1539 dn->occupid[SEL_CLASS_OCCUP_ID].val) |
1540 FIELD_PREP(CMN__PMU_OCCUP1_ID,
1541 dn->occupid[SEL_OCCUP1ID].val);
1542 writel_relaxed(reg >> 32, dn->pmu_base + CMN_PMU_EVENT_SEL + 4);
1543 } else if (dn->occupid[fsel].val != occupid) {
1544 return -EBUSY;
1545 }
1546 dn->occupid[fsel].count++;
1547 return 0;
1548 }
1549
arm_cmn_set_event_sel_lo(struct arm_cmn_node * dn,int dtm_idx,int eventid,bool wide_sel)1550 static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,
1551 int eventid, bool wide_sel)
1552 {
1553 if (wide_sel) {
1554 dn->event_w[dtm_idx] = eventid;
1555 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1556 } else {
1557 dn->event[dtm_idx] = eventid;
1558 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL);
1559 }
1560 }
1561
arm_cmn_event_start(struct perf_event * event,int flags)1562 static void arm_cmn_event_start(struct perf_event *event, int flags)
1563 {
1564 struct arm_cmn *cmn = to_cmn(event->pmu);
1565 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1566 struct arm_cmn_node *dn;
1567 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1568 int i;
1569
1570 if (type == CMN_TYPE_DTC) {
1571 struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];
1572
1573 writel_relaxed(CMN_DT_DTC_CTL_DT_EN | CMN_DT_DTC_CTL_CG_DISABLE,
1574 dtc->base + CMN_DT_DTC_CTL);
1575 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc));
1576 dtc->cc_active = true;
1577 } else if (type == CMN_TYPE_WP) {
1578 u64 val = CMN_EVENT_WP_VAL(event);
1579 u64 mask = CMN_EVENT_WP_MASK(event);
1580
1581 for_each_hw_dn(hw, dn, i) {
1582 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1583 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1584
1585 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1586 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1587 }
1588 } else for_each_hw_dn(hw, dn, i) {
1589 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1590
1591 arm_cmn_set_event_sel_lo(dn, dtm_idx, CMN_EVENT_EVENTID(event),
1592 hw->wide_sel);
1593 }
1594 }
1595
arm_cmn_event_stop(struct perf_event * event,int flags)1596 static void arm_cmn_event_stop(struct perf_event *event, int flags)
1597 {
1598 struct arm_cmn *cmn = to_cmn(event->pmu);
1599 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1600 struct arm_cmn_node *dn;
1601 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1602 int i;
1603
1604 if (type == CMN_TYPE_DTC) {
1605 struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0];
1606
1607 dtc->cc_active = false;
1608 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
1609 } else if (type == CMN_TYPE_WP) {
1610 for_each_hw_dn(hw, dn, i) {
1611 void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);
1612 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1613
1614 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1615 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1616 }
1617 } else for_each_hw_dn(hw, dn, i) {
1618 int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1619
1620 arm_cmn_set_event_sel_lo(dn, dtm_idx, 0, hw->wide_sel);
1621 }
1622
1623 arm_cmn_event_read(event);
1624 }
1625
1626 struct arm_cmn_val {
1627 u8 dtm_count[CMN_MAX_DTMS];
1628 u8 occupid[CMN_MAX_DTMS][SEL_MAX];
1629 u8 wp[CMN_MAX_DTMS][4];
1630 u8 wp_combine[CMN_MAX_DTMS][2];
1631 int dtc_count[CMN_MAX_DTCS];
1632 bool cycles;
1633 };
1634
arm_cmn_val_find_free_wp_config(struct perf_event * event,struct arm_cmn_val * val,int dtm)1635 static int arm_cmn_val_find_free_wp_config(struct perf_event *event,
1636 struct arm_cmn_val *val, int dtm)
1637 {
1638 int wp_idx = CMN_EVENT_EVENTID(event);
1639
1640 if (val->wp[dtm][wp_idx])
1641 if (val->wp[dtm][++wp_idx])
1642 return -ENOSPC;
1643
1644 return wp_idx;
1645 }
1646
arm_cmn_val_add_event(struct arm_cmn * cmn,struct arm_cmn_val * val,struct perf_event * event)1647 static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,
1648 struct perf_event *event)
1649 {
1650 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1651 struct arm_cmn_node *dn;
1652 enum cmn_node_type type;
1653 int i;
1654
1655 if (is_software_event(event))
1656 return;
1657
1658 type = CMN_EVENT_TYPE(event);
1659 if (type == CMN_TYPE_DTC) {
1660 val->cycles = true;
1661 return;
1662 }
1663
1664 for_each_hw_dtc_idx(hw, dtc, idx)
1665 val->dtc_count[dtc]++;
1666
1667 for_each_hw_dn(hw, dn, i) {
1668 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1669
1670 val->dtm_count[dtm]++;
1671
1672 if (sel > SEL_NONE)
1673 val->occupid[dtm][sel] = CMN_EVENT_OCCUPID(event) + 1;
1674
1675 if (type != CMN_TYPE_WP)
1676 continue;
1677
1678 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
1679 val->wp[dtm][wp_idx] = 1;
1680 val->wp_combine[dtm][wp_idx >> 1] += !!CMN_EVENT_WP_COMBINE(event);
1681 }
1682 }
1683
arm_cmn_validate_group(struct arm_cmn * cmn,struct perf_event * event)1684 static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)
1685 {
1686 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1687 struct arm_cmn_node *dn;
1688 struct perf_event *sibling, *leader = event->group_leader;
1689 enum cmn_node_type type;
1690 struct arm_cmn_val *val;
1691 int i, ret = -EINVAL;
1692
1693 if (leader == event)
1694 return 0;
1695
1696 if (event->pmu != leader->pmu && !is_software_event(leader))
1697 return -EINVAL;
1698
1699 val = kzalloc(sizeof(*val), GFP_KERNEL);
1700 if (!val)
1701 return -ENOMEM;
1702
1703 arm_cmn_val_add_event(cmn, val, leader);
1704
1705 for_each_sibling_event(sibling, leader)
1706 arm_cmn_val_add_event(cmn, val, sibling);
1707
1708 type = CMN_EVENT_TYPE(event);
1709 if (type == CMN_TYPE_DTC) {
1710 ret = val->cycles ? -EINVAL : 0;
1711 goto done;
1712 }
1713
1714 for_each_hw_dtc_idx(hw, dtc, idx)
1715 if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS)
1716 goto done;
1717
1718 for_each_hw_dn(hw, dn, i) {
1719 int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;
1720
1721 if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)
1722 goto done;
1723
1724 if (sel > SEL_NONE && val->occupid[dtm][sel] &&
1725 val->occupid[dtm][sel] != CMN_EVENT_OCCUPID(event) + 1)
1726 goto done;
1727
1728 if (type != CMN_TYPE_WP)
1729 continue;
1730
1731 wp_idx = arm_cmn_val_find_free_wp_config(event, val, dtm);
1732 if (wp_idx < 0)
1733 goto done;
1734
1735 if (wp_idx & 1 &&
1736 val->wp_combine[dtm][wp_idx >> 1] != !!CMN_EVENT_WP_COMBINE(event))
1737 goto done;
1738 }
1739
1740 ret = 0;
1741 done:
1742 kfree(val);
1743 return ret;
1744 }
1745
arm_cmn_filter_sel(const struct arm_cmn * cmn,enum cmn_node_type type,unsigned int eventid)1746 static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,
1747 enum cmn_node_type type,
1748 unsigned int eventid)
1749 {
1750 struct arm_cmn_event_attr *e;
1751 enum cmn_model model = arm_cmn_model(cmn);
1752
1753 for (int i = 0; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1; i++) {
1754 e = container_of(arm_cmn_event_attrs[i], typeof(*e), attr.attr);
1755 if (e->model & model && e->type == type && e->eventid == eventid)
1756 return e->fsel;
1757 }
1758 return SEL_NONE;
1759 }
1760
1761
arm_cmn_event_init(struct perf_event * event)1762 static int arm_cmn_event_init(struct perf_event *event)
1763 {
1764 struct arm_cmn *cmn = to_cmn(event->pmu);
1765 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1766 struct arm_cmn_node *dn;
1767 enum cmn_node_type type;
1768 bool bynodeid;
1769 u16 nodeid, eventid;
1770
1771 if (event->attr.type != event->pmu->type)
1772 return -ENOENT;
1773
1774 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
1775 return -EINVAL;
1776
1777 event->cpu = cmn->cpu;
1778 if (event->cpu < 0)
1779 return -EINVAL;
1780
1781 type = CMN_EVENT_TYPE(event);
1782 /* DTC events (i.e. cycles) already have everything they need */
1783 if (type == CMN_TYPE_DTC)
1784 return arm_cmn_validate_group(cmn, event);
1785
1786 eventid = CMN_EVENT_EVENTID(event);
1787 /* For watchpoints we need the actual XP node here */
1788 if (type == CMN_TYPE_WP) {
1789 type = CMN_TYPE_XP;
1790 /* ...and we need a "real" direction */
1791 if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)
1792 return -EINVAL;
1793 /* ...but the DTM may depend on which port we're watching */
1794 if (cmn->multi_dtm)
1795 hw->dtm_offset = CMN_EVENT_WP_DEV_SEL(event) / 2;
1796 } else if (type == CMN_TYPE_XP &&
1797 (cmn->part == PART_CMN700 || cmn->part == PART_CMN_S3)) {
1798 hw->wide_sel = true;
1799 } else if (type == CMN_TYPE_RND) {
1800 /* Secretly permit this as an alias for "rnid" events */
1801 type = CMN_TYPE_RNI;
1802 }
1803
1804 /* This is sufficiently annoying to recalculate, so cache it */
1805 hw->filter_sel = arm_cmn_filter_sel(cmn, type, eventid);
1806
1807 bynodeid = CMN_EVENT_BYNODEID(event);
1808 nodeid = CMN_EVENT_NODEID(event);
1809
1810 hw->dn = arm_cmn_node(cmn, type);
1811 if (!hw->dn)
1812 return -EINVAL;
1813
1814 memset(hw->dtc_idx, -1, sizeof(hw->dtc_idx));
1815 for (dn = hw->dn; dn->type == type; dn++) {
1816 if (bynodeid && dn->id != nodeid) {
1817 hw->dn++;
1818 continue;
1819 }
1820 hw->num_dns++;
1821 if (dn->dtc < 0)
1822 memset(hw->dtc_idx, 0, cmn->num_dtcs);
1823 else
1824 hw->dtc_idx[dn->dtc] = 0;
1825
1826 if (bynodeid)
1827 break;
1828 }
1829
1830 if (!hw->num_dns) {
1831 dev_dbg(cmn->dev, "invalid node 0x%x type 0x%x\n", nodeid, type);
1832 return -EINVAL;
1833 }
1834
1835 return arm_cmn_validate_group(cmn, event);
1836 }
1837
arm_cmn_event_clear(struct arm_cmn * cmn,struct perf_event * event,int i)1838 static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,
1839 int i)
1840 {
1841 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1842 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1843
1844 while (i--) {
1845 struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;
1846 unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);
1847
1848 if (type == CMN_TYPE_WP) {
1849 int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);
1850
1851 dtm->wp_event[wp_idx] = -1;
1852 }
1853
1854 if (hw->filter_sel > SEL_NONE)
1855 hw->dn[i].occupid[hw->filter_sel].count--;
1856
1857 dtm->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1858 writel_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
1859 }
1860 memset(hw->dtm_idx, 0, sizeof(hw->dtm_idx));
1861 memset(hw->wp_idx, 0, sizeof(hw->wp_idx));
1862
1863 for_each_hw_dtc_idx(hw, j, idx)
1864 cmn->dtc[j].counters[idx] = NULL;
1865 }
1866
arm_cmn_event_add(struct perf_event * event,int flags)1867 static int arm_cmn_event_add(struct perf_event *event, int flags)
1868 {
1869 struct arm_cmn *cmn = to_cmn(event->pmu);
1870 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1871 struct arm_cmn_node *dn;
1872 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1873 unsigned int input_sel, i = 0;
1874
1875 if (type == CMN_TYPE_DTC) {
1876 while (cmn->dtc[i].cycles)
1877 if (++i == cmn->num_dtcs)
1878 return -ENOSPC;
1879
1880 cmn->dtc[i].cycles = event;
1881 hw->dtc_idx[0] = i;
1882
1883 if (flags & PERF_EF_START)
1884 arm_cmn_event_start(event, 0);
1885 return 0;
1886 }
1887
1888 /* Grab the global counters first... */
1889 for_each_hw_dtc_idx(hw, j, idx) {
1890 if (cmn->part == PART_CMN600 && j > 0) {
1891 idx = hw->dtc_idx[0];
1892 } else {
1893 idx = 0;
1894 while (cmn->dtc[j].counters[idx])
1895 if (++idx == CMN_DT_NUM_COUNTERS)
1896 return -ENOSPC;
1897 }
1898 hw->dtc_idx[j] = idx;
1899 }
1900
1901 /* ...then the local counters to feed them */
1902 for_each_hw_dn(hw, dn, i) {
1903 struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;
1904 unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0);
1905 u64 reg;
1906
1907 dtm_idx = 0;
1908 while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1909 if (++dtm_idx == CMN_DTM_NUM_COUNTERS)
1910 goto free_dtms;
1911
1912 if (type == CMN_TYPE_XP) {
1913 input_sel = CMN__PMEVCNT0_INPUT_SEL_XP + dtm_idx;
1914 } else if (type == CMN_TYPE_WP) {
1915 int tmp, wp_idx;
1916 u32 cfg;
1917
1918 wp_idx = arm_cmn_find_free_wp_idx(dtm, event);
1919 if (wp_idx < 0)
1920 goto free_dtms;
1921
1922 cfg = arm_cmn_wp_config(event, wp_idx);
1923
1924 tmp = dtm->wp_event[wp_idx ^ 1];
1925 if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=
1926 CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp]))
1927 goto free_dtms;
1928
1929 input_sel = CMN__PMEVCNT0_INPUT_SEL_WP + wp_idx;
1930
1931 arm_cmn_claim_wp_idx(dtm, event, d, wp_idx, i);
1932 writel_relaxed(cfg, dtm->base + CMN_DTM_WPn_CONFIG(wp_idx));
1933 } else {
1934 struct arm_cmn_nodeid nid = arm_cmn_nid(dn);
1935
1936 if (cmn->multi_dtm)
1937 nid.port %= 2;
1938
1939 input_sel = CMN__PMEVCNT0_INPUT_SEL_DEV + dtm_idx +
1940 (nid.port << 4) + (nid.dev << 2);
1941
1942 if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))
1943 goto free_dtms;
1944 }
1945
1946 arm_cmn_set_index(hw->dtm_idx, i, dtm_idx);
1947
1948 dtm->input_sel[dtm_idx] = input_sel;
1949 shift = CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(dtm_idx);
1950 dtm->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1951 dtm->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, hw->dtc_idx[d]) << shift;
1952 dtm->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1953 reg = (u64)le32_to_cpu(dtm->pmu_config_high) << 32 | dtm->pmu_config_low;
1954 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
1955 }
1956
1957 /* Go go go! */
1958 arm_cmn_init_counter(event);
1959
1960 if (flags & PERF_EF_START)
1961 arm_cmn_event_start(event, 0);
1962
1963 return 0;
1964
1965 free_dtms:
1966 arm_cmn_event_clear(cmn, event, i);
1967 return -ENOSPC;
1968 }
1969
arm_cmn_event_del(struct perf_event * event,int flags)1970 static void arm_cmn_event_del(struct perf_event *event, int flags)
1971 {
1972 struct arm_cmn *cmn = to_cmn(event->pmu);
1973 struct arm_cmn_hw_event *hw = to_cmn_hw(event);
1974 enum cmn_node_type type = CMN_EVENT_TYPE(event);
1975
1976 arm_cmn_event_stop(event, PERF_EF_UPDATE);
1977
1978 if (type == CMN_TYPE_DTC)
1979 cmn->dtc[hw->dtc_idx[0]].cycles = NULL;
1980 else
1981 arm_cmn_event_clear(cmn, event, hw->num_dns);
1982 }
1983
1984 /*
1985 * We stop the PMU for both add and read, to avoid skew across DTM counters.
1986 * In theory we could use snapshots to read without stopping, but then it
1987 * becomes a lot trickier to deal with overlow and racing against interrupts,
1988 * plus it seems they don't work properly on some hardware anyway :(
1989 */
arm_cmn_start_txn(struct pmu * pmu,unsigned int flags)1990 static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)
1991 {
1992 arm_cmn_set_state(to_cmn(pmu), CMN_STATE_TXN);
1993 }
1994
arm_cmn_end_txn(struct pmu * pmu)1995 static void arm_cmn_end_txn(struct pmu *pmu)
1996 {
1997 arm_cmn_clear_state(to_cmn(pmu), CMN_STATE_TXN);
1998 }
1999
arm_cmn_commit_txn(struct pmu * pmu)2000 static int arm_cmn_commit_txn(struct pmu *pmu)
2001 {
2002 arm_cmn_end_txn(pmu);
2003 return 0;
2004 }
2005
arm_cmn_migrate(struct arm_cmn * cmn,unsigned int cpu)2006 static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)
2007 {
2008 unsigned int i;
2009
2010 perf_pmu_migrate_context(&cmn->pmu, cmn->cpu, cpu);
2011 for (i = 0; i < cmn->num_dtcs; i++)
2012 irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
2013 cmn->cpu = cpu;
2014 }
2015
arm_cmn_pmu_online_cpu(unsigned int cpu,struct hlist_node * cpuhp_node)2016 static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
2017 {
2018 struct arm_cmn *cmn;
2019 int node;
2020
2021 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
2022 node = dev_to_node(cmn->dev);
2023 if (cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)
2024 arm_cmn_migrate(cmn, cpu);
2025 return 0;
2026 }
2027
arm_cmn_pmu_offline_cpu(unsigned int cpu,struct hlist_node * cpuhp_node)2028 static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)
2029 {
2030 struct arm_cmn *cmn;
2031 unsigned int target;
2032 int node;
2033
2034 cmn = hlist_entry_safe(cpuhp_node, struct arm_cmn, cpuhp_node);
2035 if (cpu != cmn->cpu)
2036 return 0;
2037
2038 node = dev_to_node(cmn->dev);
2039
2040 target = cpumask_any_and_but(cpumask_of_node(node), cpu_online_mask, cpu);
2041 if (target >= nr_cpu_ids)
2042 target = cpumask_any_but(cpu_online_mask, cpu);
2043
2044 if (target < nr_cpu_ids)
2045 arm_cmn_migrate(cmn, target);
2046
2047 return 0;
2048 }
2049
arm_cmn_handle_irq(int irq,void * dev_id)2050 static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)
2051 {
2052 struct arm_cmn_dtc *dtc = dev_id;
2053 irqreturn_t ret = IRQ_NONE;
2054
2055 for (;;) {
2056 u32 status = readl_relaxed(CMN_DT_PMOVSR(dtc));
2057 u64 delta;
2058 int i;
2059
2060 for (i = 0; i < CMN_DT_NUM_COUNTERS; i++) {
2061 if (status & (1U << i)) {
2062 ret = IRQ_HANDLED;
2063 if (WARN_ON(!dtc->counters[i]))
2064 continue;
2065 delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
2066 local64_add(delta, &dtc->counters[i]->count);
2067 }
2068 }
2069
2070 if (status & (1U << CMN_DT_NUM_COUNTERS)) {
2071 ret = IRQ_HANDLED;
2072 if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
2073 delta = arm_cmn_read_cc(dtc);
2074 local64_add(delta, &dtc->cycles->count);
2075 }
2076 }
2077
2078 writel_relaxed(status, CMN_DT_PMOVSR_CLR(dtc));
2079
2080 if (!dtc->irq_friend)
2081 return ret;
2082 dtc += dtc->irq_friend;
2083 }
2084 }
2085
2086 /* We can reasonably accommodate DTCs of the same CMN sharing IRQs */
arm_cmn_init_irqs(struct arm_cmn * cmn)2087 static int arm_cmn_init_irqs(struct arm_cmn *cmn)
2088 {
2089 int i, j, irq, err;
2090
2091 for (i = 0; i < cmn->num_dtcs; i++) {
2092 irq = cmn->dtc[i].irq;
2093 for (j = i; j--; ) {
2094 if (cmn->dtc[j].irq == irq) {
2095 cmn->dtc[j].irq_friend = i - j;
2096 goto next;
2097 }
2098 }
2099 err = devm_request_irq(cmn->dev, irq, arm_cmn_handle_irq,
2100 IRQF_NOBALANCING | IRQF_NO_THREAD,
2101 dev_name(cmn->dev), &cmn->dtc[i]);
2102 if (err)
2103 return err;
2104
2105 err = irq_set_affinity(irq, cpumask_of(cmn->cpu));
2106 if (err)
2107 return err;
2108 next:
2109 ; /* isn't C great? */
2110 }
2111 return 0;
2112 }
2113
arm_cmn_init_dtm(struct arm_cmn_dtm * dtm,struct arm_cmn_node * xp,int idx)2114 static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)
2115 {
2116 int i;
2117
2118 dtm->base = xp->pmu_base + CMN_DTM_OFFSET(idx);
2119 dtm->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
2120 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2121 for (i = 0; i < 4; i++) {
2122 dtm->wp_event[i] = -1;
2123 writeq_relaxed(0, dtm->base + CMN_DTM_WPn_MASK(i));
2124 writeq_relaxed(~0ULL, dtm->base + CMN_DTM_WPn_VAL(i));
2125 }
2126 }
2127
arm_cmn_init_dtc(struct arm_cmn * cmn,struct arm_cmn_node * dn,int idx)2128 static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)
2129 {
2130 struct arm_cmn_dtc *dtc = cmn->dtc + idx;
2131
2132 dtc->pmu_base = dn->pmu_base;
2133 dtc->base = dtc->pmu_base - arm_cmn_pmu_offset(cmn, dn);
2134 dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
2135 if (dtc->irq < 0)
2136 return dtc->irq;
2137
2138 writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2139 writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, CMN_DT_PMCR(dtc));
2140 writeq_relaxed(0, CMN_DT_PMCCNTR(dtc));
2141 writel_relaxed(0x1ff, CMN_DT_PMOVSR_CLR(dtc));
2142
2143 return 0;
2144 }
2145
arm_cmn_node_cmp(const void * a,const void * b)2146 static int arm_cmn_node_cmp(const void *a, const void *b)
2147 {
2148 const struct arm_cmn_node *dna = a, *dnb = b;
2149 int cmp;
2150
2151 cmp = dna->type - dnb->type;
2152 if (!cmp)
2153 cmp = dna->logid - dnb->logid;
2154 return cmp;
2155 }
2156
arm_cmn_init_dtcs(struct arm_cmn * cmn)2157 static int arm_cmn_init_dtcs(struct arm_cmn *cmn)
2158 {
2159 struct arm_cmn_node *dn, *xp;
2160 int dtc_idx = 0;
2161
2162 cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
2163 if (!cmn->dtc)
2164 return -ENOMEM;
2165
2166 sort(cmn->dns, cmn->num_dns, sizeof(cmn->dns[0]), arm_cmn_node_cmp, NULL);
2167
2168 cmn->xps = arm_cmn_node(cmn, CMN_TYPE_XP);
2169
2170 if (cmn->part == PART_CMN600 && cmn->num_dtcs > 1) {
2171 /* We do at least know that a DTC's XP must be in that DTC's domain */
2172 dn = arm_cmn_node(cmn, CMN_TYPE_DTC);
2173 for (int i = 0; i < cmn->num_dtcs; i++)
2174 arm_cmn_node_to_xp(cmn, dn + i)->dtc = i;
2175 }
2176
2177 for (dn = cmn->dns; dn->type; dn++) {
2178 if (dn->type == CMN_TYPE_XP)
2179 continue;
2180
2181 xp = arm_cmn_node_to_xp(cmn, dn);
2182 dn->dtc = xp->dtc;
2183 dn->dtm = xp->dtm;
2184 if (cmn->multi_dtm)
2185 dn->dtm += arm_cmn_nid(dn).port / 2;
2186
2187 if (dn->type == CMN_TYPE_DTC) {
2188 int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);
2189
2190 if (err)
2191 return err;
2192 }
2193
2194 /* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */
2195 if (dn->type == CMN_TYPE_RND)
2196 dn->type = CMN_TYPE_RNI;
2197
2198 /* We split the RN-I off already, so let the CCLA part match CCLA events */
2199 if (dn->type == CMN_TYPE_CCLA_RNI)
2200 dn->type = CMN_TYPE_CCLA;
2201 }
2202
2203 arm_cmn_set_state(cmn, CMN_STATE_DISABLED);
2204
2205 return 0;
2206 }
2207
arm_cmn_dtc_domain(struct arm_cmn * cmn,void __iomem * xp_region)2208 static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region)
2209 {
2210 int offset = CMN_DTM_UNIT_INFO;
2211
2212 if (cmn->part == PART_CMN650 || cmn->part == PART_CI700)
2213 offset = CMN650_DTM_UNIT_INFO;
2214
2215 return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));
2216 }
2217
arm_cmn_init_node_info(struct arm_cmn * cmn,u32 offset,struct arm_cmn_node * node)2218 static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)
2219 {
2220 int level;
2221 u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
2222
2223 node->type = FIELD_GET(CMN_NI_NODE_TYPE, reg);
2224 node->id = FIELD_GET(CMN_NI_NODE_ID, reg);
2225 node->logid = FIELD_GET(CMN_NI_LOGICAL_ID, reg);
2226
2227 node->pmu_base = cmn->base + offset + arm_cmn_pmu_offset(cmn, node);
2228
2229 if (node->type == CMN_TYPE_CFG)
2230 level = 0;
2231 else if (node->type == CMN_TYPE_XP)
2232 level = 1;
2233 else
2234 level = 2;
2235
2236 dev_dbg(cmn->dev, "node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n",
2237 (level * 2) + 1, ' ', node->id, 5 - (level * 2), ' ',
2238 node->type, node->logid, offset);
2239 }
2240
arm_cmn_subtype(enum cmn_node_type type)2241 static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)
2242 {
2243 switch (type) {
2244 case CMN_TYPE_HNP:
2245 return CMN_TYPE_HNI;
2246 case CMN_TYPE_CCLA_RNI:
2247 return CMN_TYPE_RNI;
2248 default:
2249 return CMN_TYPE_INVALID;
2250 }
2251 }
2252
arm_cmn_discover(struct arm_cmn * cmn,unsigned int rgn_offset)2253 static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)
2254 {
2255 void __iomem *cfg_region;
2256 struct arm_cmn_node cfg, *dn;
2257 struct arm_cmn_dtm *dtm;
2258 enum cmn_part part;
2259 u16 child_count, child_poff;
2260 u32 xp_offset[CMN_MAX_XPS];
2261 u64 reg;
2262 int i, j;
2263 size_t sz;
2264
2265 arm_cmn_init_node_info(cmn, rgn_offset, &cfg);
2266 if (cfg.type != CMN_TYPE_CFG)
2267 return -ENODEV;
2268
2269 cfg_region = cmn->base + rgn_offset;
2270
2271 reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
2272 part = FIELD_GET(CMN_CFGM_PID0_PART_0, reg);
2273 part |= FIELD_GET(CMN_CFGM_PID1_PART_1, reg) << 8;
2274 if (cmn->part && cmn->part != part)
2275 dev_warn(cmn->dev,
2276 "Firmware binding mismatch: expected part number 0x%x, found 0x%x\n",
2277 cmn->part, part);
2278 cmn->part = part;
2279 if (!arm_cmn_model(cmn))
2280 dev_warn(cmn->dev, "Unknown part number: 0x%x\n", part);
2281
2282 reg = readl_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_23);
2283 cmn->rev = FIELD_GET(CMN_CFGM_PID2_REVISION, reg);
2284
2285 /*
2286 * With the device isolation feature, if firmware has neglected to enable
2287 * an XP port then we risk locking up if we try to access anything behind
2288 * it; however we also have no way to tell from Non-Secure whether any
2289 * given port is disabled or not, so the only way to win is not to play...
2290 */
2291 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
2292 if (reg & CMN_INFO_DEVICE_ISO_ENABLE) {
2293 dev_err(cmn->dev, "Device isolation enabled, not continuing due to risk of lockup\n");
2294 return -ENODEV;
2295 }
2296 cmn->multi_dtm = reg & CMN_INFO_MULTIPLE_DTM_EN;
2297 cmn->rsp_vc_num = FIELD_GET(CMN_INFO_RSP_VC_NUM, reg);
2298 cmn->dat_vc_num = FIELD_GET(CMN_INFO_DAT_VC_NUM, reg);
2299
2300 reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
2301 cmn->snp_vc_num = FIELD_GET(CMN_INFO_SNP_VC_NUM, reg);
2302 cmn->req_vc_num = FIELD_GET(CMN_INFO_REQ_VC_NUM, reg);
2303
2304 reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
2305 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2306 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2307
2308 cmn->num_xps = child_count;
2309 cmn->num_dns = cmn->num_xps;
2310
2311 /* Pass 1: visit the XPs, enumerate their children */
2312 for (i = 0; i < cmn->num_xps; i++) {
2313 reg = readq_relaxed(cfg_region + child_poff + i * 8);
2314 xp_offset[i] = reg & CMN_CHILD_NODE_ADDR;
2315
2316 reg = readq_relaxed(cmn->base + xp_offset[i] + CMN_CHILD_INFO);
2317 cmn->num_dns += FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2318 }
2319
2320 /*
2321 * Some nodes effectively have two separate types, which we'll handle
2322 * by creating one of each internally. For a (very) safe initial upper
2323 * bound, account for double the number of non-XP nodes.
2324 */
2325 dn = devm_kcalloc(cmn->dev, cmn->num_dns * 2 - cmn->num_xps,
2326 sizeof(*dn), GFP_KERNEL);
2327 if (!dn)
2328 return -ENOMEM;
2329
2330 /* Initial safe upper bound on DTMs for any possible mesh layout */
2331 i = cmn->num_xps;
2332 if (cmn->multi_dtm)
2333 i += cmn->num_xps + 1;
2334 dtm = devm_kcalloc(cmn->dev, i, sizeof(*dtm), GFP_KERNEL);
2335 if (!dtm)
2336 return -ENOMEM;
2337
2338 /* Pass 2: now we can actually populate the nodes */
2339 cmn->dns = dn;
2340 cmn->dtms = dtm;
2341 for (i = 0; i < cmn->num_xps; i++) {
2342 void __iomem *xp_region = cmn->base + xp_offset[i];
2343 struct arm_cmn_node *xp = dn++;
2344 unsigned int xp_ports = 0;
2345
2346 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
2347 /*
2348 * Thanks to the order in which XP logical IDs seem to be
2349 * assigned, we can handily infer the mesh X dimension by
2350 * looking out for the XP at (0,1) without needing to know
2351 * the exact node ID format, which we can later derive.
2352 */
2353 if (xp->id == (1 << 3))
2354 cmn->mesh_x = xp->logid;
2355
2356 if (cmn->part == PART_CMN600)
2357 xp->dtc = -1;
2358 else
2359 xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);
2360
2361 xp->dtm = dtm - cmn->dtms;
2362 arm_cmn_init_dtm(dtm++, xp, 0);
2363 /*
2364 * Keeping track of connected ports will let us filter out
2365 * unnecessary XP events easily, and also infer the per-XP
2366 * part of the node ID format.
2367 */
2368 for (int p = 0; p < CMN_MAX_PORTS; p++)
2369 if (arm_cmn_device_connect_info(cmn, xp, p))
2370 xp_ports |= BIT(p);
2371
2372 if (cmn->num_xps == 1) {
2373 xp->portid_bits = 3;
2374 xp->deviceid_bits = 2;
2375 } else if (xp_ports > 0x3) {
2376 xp->portid_bits = 2;
2377 xp->deviceid_bits = 1;
2378 } else {
2379 xp->portid_bits = 1;
2380 xp->deviceid_bits = 2;
2381 }
2382
2383 if (cmn->multi_dtm && (xp_ports > 0x3))
2384 arm_cmn_init_dtm(dtm++, xp, 1);
2385 if (cmn->multi_dtm && (xp_ports > 0xf))
2386 arm_cmn_init_dtm(dtm++, xp, 2);
2387
2388 cmn->ports_used |= xp_ports;
2389
2390 reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
2391 child_count = FIELD_GET(CMN_CI_CHILD_COUNT, reg);
2392 child_poff = FIELD_GET(CMN_CI_CHILD_PTR_OFFSET, reg);
2393
2394 for (j = 0; j < child_count; j++) {
2395 reg = readq_relaxed(xp_region + child_poff + j * 8);
2396 /*
2397 * Don't even try to touch anything external, since in general
2398 * we haven't a clue how to power up arbitrary CHI requesters.
2399 * As of CMN-600r1 these could only be RN-SAMs or CXLAs,
2400 * neither of which have any PMU events anyway.
2401 * (Actually, CXLAs do seem to have grown some events in r1p2,
2402 * but they don't go to regular XP DTMs, and they depend on
2403 * secure configuration which we can't easily deal with)
2404 */
2405 if (reg & CMN_CHILD_NODE_EXTERNAL) {
2406 dev_dbg(cmn->dev, "ignoring external node %llx\n", reg);
2407 continue;
2408 }
2409 /*
2410 * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus
2411 * child count larger than the number of valid child pointers.
2412 * A child offset of 0 can only occur on CMN-600; otherwise it
2413 * would imply the root node being its own grandchild, which
2414 * we can safely dismiss in general.
2415 */
2416 if (reg == 0 && cmn->part != PART_CMN600) {
2417 dev_dbg(cmn->dev, "bogus child pointer?\n");
2418 continue;
2419 }
2420
2421 arm_cmn_init_node_info(cmn, reg & CMN_CHILD_NODE_ADDR, dn);
2422 dn->portid_bits = xp->portid_bits;
2423 dn->deviceid_bits = xp->deviceid_bits;
2424
2425 switch (dn->type) {
2426 case CMN_TYPE_DTC:
2427 cmn->num_dtcs++;
2428 dn++;
2429 break;
2430 /* These guys have PMU events */
2431 case CMN_TYPE_DVM:
2432 case CMN_TYPE_HNI:
2433 case CMN_TYPE_HNF:
2434 case CMN_TYPE_SBSX:
2435 case CMN_TYPE_RNI:
2436 case CMN_TYPE_RND:
2437 case CMN_TYPE_MTSX:
2438 case CMN_TYPE_CXRA:
2439 case CMN_TYPE_CXHA:
2440 case CMN_TYPE_CCRA:
2441 case CMN_TYPE_CCHA:
2442 case CMN_TYPE_HNS:
2443 dn++;
2444 break;
2445 case CMN_TYPE_CCLA:
2446 dn->pmu_base += CMN_CCLA_PMU_EVENT_SEL;
2447 dn++;
2448 break;
2449 /* Nothing to see here */
2450 case CMN_TYPE_MPAM_S:
2451 case CMN_TYPE_MPAM_NS:
2452 case CMN_TYPE_RNSAM:
2453 case CMN_TYPE_CXLA:
2454 case CMN_TYPE_HNS_MPAM_S:
2455 case CMN_TYPE_HNS_MPAM_NS:
2456 case CMN_TYPE_APB:
2457 break;
2458 /*
2459 * Split "optimised" combination nodes into separate
2460 * types for the different event sets. Offsetting the
2461 * base address lets us handle the second pmu_event_sel
2462 * register via the normal mechanism later.
2463 */
2464 case CMN_TYPE_HNP:
2465 case CMN_TYPE_CCLA_RNI:
2466 dn[1] = dn[0];
2467 dn[0].pmu_base += CMN_CCLA_PMU_EVENT_SEL;
2468 dn[1].type = arm_cmn_subtype(dn->type);
2469 dn += 2;
2470 break;
2471 /* Something has gone horribly wrong */
2472 default:
2473 dev_err(cmn->dev, "invalid device node type: 0x%x\n", dn->type);
2474 return -ENODEV;
2475 }
2476 }
2477 }
2478
2479 /* Correct for any nodes we added or skipped */
2480 cmn->num_dns = dn - cmn->dns;
2481
2482 /* Cheeky +1 to help terminate pointer-based iteration later */
2483 sz = (void *)(dn + 1) - (void *)cmn->dns;
2484 dn = devm_krealloc(cmn->dev, cmn->dns, sz, GFP_KERNEL);
2485 if (dn)
2486 cmn->dns = dn;
2487
2488 sz = (void *)dtm - (void *)cmn->dtms;
2489 dtm = devm_krealloc(cmn->dev, cmn->dtms, sz, GFP_KERNEL);
2490 if (dtm)
2491 cmn->dtms = dtm;
2492
2493 /*
2494 * If mesh_x wasn't set during discovery then we never saw
2495 * an XP at (0,1), thus we must have an Nx1 configuration.
2496 */
2497 if (!cmn->mesh_x)
2498 cmn->mesh_x = cmn->num_xps;
2499 cmn->mesh_y = cmn->num_xps / cmn->mesh_x;
2500
2501 /* 1x1 config plays havoc with XP event encodings */
2502 if (cmn->num_xps == 1)
2503 dev_warn(cmn->dev, "1x1 config not fully supported, translate XP events manually\n");
2504
2505 dev_dbg(cmn->dev, "periph_id part 0x%03x revision %d\n", cmn->part, cmn->rev);
2506 reg = cmn->ports_used;
2507 dev_dbg(cmn->dev, "mesh %dx%d, ID width %d, ports %6pbl%s\n",
2508 cmn->mesh_x, cmn->mesh_y, arm_cmn_xyidbits(cmn), ®,
2509 cmn->multi_dtm ? ", multi-DTM" : "");
2510
2511 return 0;
2512 }
2513
arm_cmn600_acpi_probe(struct platform_device * pdev,struct arm_cmn * cmn)2514 static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)
2515 {
2516 struct resource *cfg, *root;
2517
2518 cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2519 if (!cfg)
2520 return -EINVAL;
2521
2522 root = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2523 if (!root)
2524 return -EINVAL;
2525
2526 if (!resource_contains(cfg, root))
2527 swap(cfg, root);
2528 /*
2529 * Note that devm_ioremap_resource() is dumb and won't let the platform
2530 * device claim cfg when the ACPI companion device has already claimed
2531 * root within it. But since they *are* already both claimed in the
2532 * appropriate name, we don't really need to do it again here anyway.
2533 */
2534 cmn->base = devm_ioremap(cmn->dev, cfg->start, resource_size(cfg));
2535 if (!cmn->base)
2536 return -ENOMEM;
2537
2538 return root->start - cfg->start;
2539 }
2540
arm_cmn600_of_probe(struct device_node * np)2541 static int arm_cmn600_of_probe(struct device_node *np)
2542 {
2543 u32 rootnode;
2544
2545 return of_property_read_u32(np, "arm,root-node", &rootnode) ?: rootnode;
2546 }
2547
arm_cmn_probe(struct platform_device * pdev)2548 static int arm_cmn_probe(struct platform_device *pdev)
2549 {
2550 struct arm_cmn *cmn;
2551 const char *name;
2552 static atomic_t id;
2553 int err, rootnode, this_id;
2554
2555 cmn = devm_kzalloc(&pdev->dev, sizeof(*cmn), GFP_KERNEL);
2556 if (!cmn)
2557 return -ENOMEM;
2558
2559 cmn->dev = &pdev->dev;
2560 cmn->part = (unsigned long)device_get_match_data(cmn->dev);
2561 platform_set_drvdata(pdev, cmn);
2562
2563 if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {
2564 rootnode = arm_cmn600_acpi_probe(pdev, cmn);
2565 } else {
2566 rootnode = 0;
2567 cmn->base = devm_platform_ioremap_resource(pdev, 0);
2568 if (IS_ERR(cmn->base))
2569 return PTR_ERR(cmn->base);
2570 if (cmn->part == PART_CMN600)
2571 rootnode = arm_cmn600_of_probe(pdev->dev.of_node);
2572 }
2573 if (rootnode < 0)
2574 return rootnode;
2575
2576 err = arm_cmn_discover(cmn, rootnode);
2577 if (err)
2578 return err;
2579
2580 err = arm_cmn_init_dtcs(cmn);
2581 if (err)
2582 return err;
2583
2584 err = arm_cmn_init_irqs(cmn);
2585 if (err)
2586 return err;
2587
2588 cmn->cpu = cpumask_local_spread(0, dev_to_node(cmn->dev));
2589 cmn->pmu = (struct pmu) {
2590 .module = THIS_MODULE,
2591 .parent = cmn->dev,
2592 .attr_groups = arm_cmn_attr_groups,
2593 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
2594 .task_ctx_nr = perf_invalid_context,
2595 .pmu_enable = arm_cmn_pmu_enable,
2596 .pmu_disable = arm_cmn_pmu_disable,
2597 .event_init = arm_cmn_event_init,
2598 .add = arm_cmn_event_add,
2599 .del = arm_cmn_event_del,
2600 .start = arm_cmn_event_start,
2601 .stop = arm_cmn_event_stop,
2602 .read = arm_cmn_event_read,
2603 .start_txn = arm_cmn_start_txn,
2604 .commit_txn = arm_cmn_commit_txn,
2605 .cancel_txn = arm_cmn_end_txn,
2606 };
2607
2608 this_id = atomic_fetch_inc(&id);
2609 name = devm_kasprintf(cmn->dev, GFP_KERNEL, "arm_cmn_%d", this_id);
2610 if (!name)
2611 return -ENOMEM;
2612
2613 err = cpuhp_state_add_instance(arm_cmn_hp_state, &cmn->cpuhp_node);
2614 if (err)
2615 return err;
2616
2617 err = perf_pmu_register(&cmn->pmu, name, -1);
2618 if (err)
2619 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2620 else
2621 arm_cmn_debugfs_init(cmn, this_id);
2622
2623 return err;
2624 }
2625
arm_cmn_remove(struct platform_device * pdev)2626 static void arm_cmn_remove(struct platform_device *pdev)
2627 {
2628 struct arm_cmn *cmn = platform_get_drvdata(pdev);
2629
2630 writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);
2631
2632 perf_pmu_unregister(&cmn->pmu);
2633 cpuhp_state_remove_instance_nocalls(arm_cmn_hp_state, &cmn->cpuhp_node);
2634 debugfs_remove(cmn->debug);
2635 }
2636
2637 #ifdef CONFIG_OF
2638 static const struct of_device_id arm_cmn_of_match[] = {
2639 { .compatible = "arm,cmn-600", .data = (void *)PART_CMN600 },
2640 { .compatible = "arm,cmn-650" },
2641 { .compatible = "arm,cmn-700" },
2642 { .compatible = "arm,cmn-s3" },
2643 { .compatible = "arm,ci-700" },
2644 {}
2645 };
2646 MODULE_DEVICE_TABLE(of, arm_cmn_of_match);
2647 #endif
2648
2649 #ifdef CONFIG_ACPI
2650 static const struct acpi_device_id arm_cmn_acpi_match[] = {
2651 { "ARMHC600", PART_CMN600 },
2652 { "ARMHC650" },
2653 { "ARMHC700" },
2654 {}
2655 };
2656 MODULE_DEVICE_TABLE(acpi, arm_cmn_acpi_match);
2657 #endif
2658
2659 static struct platform_driver arm_cmn_driver = {
2660 .driver = {
2661 .name = "arm-cmn",
2662 .of_match_table = of_match_ptr(arm_cmn_of_match),
2663 .acpi_match_table = ACPI_PTR(arm_cmn_acpi_match),
2664 },
2665 .probe = arm_cmn_probe,
2666 .remove = arm_cmn_remove,
2667 };
2668
arm_cmn_init(void)2669 static int __init arm_cmn_init(void)
2670 {
2671 int ret;
2672
2673 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
2674 "perf/arm/cmn:online",
2675 arm_cmn_pmu_online_cpu,
2676 arm_cmn_pmu_offline_cpu);
2677 if (ret < 0)
2678 return ret;
2679
2680 arm_cmn_hp_state = ret;
2681 arm_cmn_debugfs = debugfs_create_dir("arm-cmn", NULL);
2682
2683 ret = platform_driver_register(&arm_cmn_driver);
2684 if (ret) {
2685 cpuhp_remove_multi_state(arm_cmn_hp_state);
2686 debugfs_remove(arm_cmn_debugfs);
2687 }
2688 return ret;
2689 }
2690
arm_cmn_exit(void)2691 static void __exit arm_cmn_exit(void)
2692 {
2693 platform_driver_unregister(&arm_cmn_driver);
2694 cpuhp_remove_multi_state(arm_cmn_hp_state);
2695 debugfs_remove(arm_cmn_debugfs);
2696 }
2697
2698 module_init(arm_cmn_init);
2699 module_exit(arm_cmn_exit);
2700
2701 MODULE_AUTHOR("Robin Murphy <robin.murphy@arm.com>");
2702 MODULE_DESCRIPTION("Arm CMN-600 PMU driver");
2703 MODULE_LICENSE("GPL v2");
2704