1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCI Express PCI Hot Plug Driver
4  *
5  * Copyright (C) 1995,2001 Compaq Computer Corporation
6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7  * Copyright (C) 2001 IBM Corp.
8  * Copyright (C) 2003-2004 Intel Corporation
9  *
10  * All rights reserved.
11  *
12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13  */
14 
15 #define dev_fmt(fmt) "pciehp: " fmt
16 
17 #include <linux/bitfield.h>
18 #include <linux/dmi.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/jiffies.h>
22 #include <linux/kthread.h>
23 #include <linux/pci.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
26 #include <linux/slab.h>
27 
28 #include "../pci.h"
29 #include "pciehp.h"
30 
31 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
32 	/*
33 	 * Match all Dell systems, as some Dell systems have inband
34 	 * presence disabled on NVMe slots (but don't support the bit to
35 	 * report it). Setting inband presence disabled should have no
36 	 * negative effect, except on broken hotplug slots that never
37 	 * assert presence detect--and those will still work, they will
38 	 * just have a bit of extra delay before being probed.
39 	 */
40 	{
41 		.ident = "Dell System",
42 		.matches = {
43 			DMI_MATCH(DMI_OEM_STRING, "Dell System"),
44 		},
45 	},
46 	{}
47 };
48 
ctrl_dev(struct controller * ctrl)49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
50 {
51 	return ctrl->pcie->port;
52 }
53 
54 static irqreturn_t pciehp_isr(int irq, void *dev_id);
55 static irqreturn_t pciehp_ist(int irq, void *dev_id);
56 static int pciehp_poll(void *data);
57 
pciehp_request_irq(struct controller * ctrl)58 static inline int pciehp_request_irq(struct controller *ctrl)
59 {
60 	int retval, irq = ctrl->pcie->irq;
61 
62 	if (pciehp_poll_mode) {
63 		ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
64 						"pciehp_poll-%s",
65 						slot_name(ctrl));
66 		return PTR_ERR_OR_ZERO(ctrl->poll_thread);
67 	}
68 
69 	/* Installs the interrupt handler */
70 	retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
71 				      IRQF_SHARED, "pciehp", ctrl);
72 	if (retval)
73 		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
74 			 irq);
75 	return retval;
76 }
77 
pciehp_free_irq(struct controller * ctrl)78 static inline void pciehp_free_irq(struct controller *ctrl)
79 {
80 	if (pciehp_poll_mode)
81 		kthread_stop(ctrl->poll_thread);
82 	else
83 		free_irq(ctrl->pcie->irq, ctrl);
84 }
85 
pcie_poll_cmd(struct controller * ctrl,int timeout)86 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
87 {
88 	struct pci_dev *pdev = ctrl_dev(ctrl);
89 	u16 slot_status;
90 
91 	do {
92 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
93 		if (PCI_POSSIBLE_ERROR(slot_status)) {
94 			ctrl_info(ctrl, "%s: no response from device\n",
95 				  __func__);
96 			return 0;
97 		}
98 
99 		if (slot_status & PCI_EXP_SLTSTA_CC) {
100 			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
101 						   PCI_EXP_SLTSTA_CC);
102 			ctrl->cmd_busy = 0;
103 			smp_mb();
104 			return 1;
105 		}
106 		msleep(10);
107 		timeout -= 10;
108 	} while (timeout >= 0);
109 	return 0;	/* timeout */
110 }
111 
pcie_wait_cmd(struct controller * ctrl)112 static void pcie_wait_cmd(struct controller *ctrl)
113 {
114 	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
115 	unsigned long duration = msecs_to_jiffies(msecs);
116 	unsigned long cmd_timeout = ctrl->cmd_started + duration;
117 	unsigned long now, timeout;
118 	int rc;
119 
120 	/*
121 	 * If the controller does not generate notifications for command
122 	 * completions, we never need to wait between writes.
123 	 */
124 	if (NO_CMD_CMPL(ctrl))
125 		return;
126 
127 	if (!ctrl->cmd_busy)
128 		return;
129 
130 	/*
131 	 * Even if the command has already timed out, we want to call
132 	 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
133 	 */
134 	now = jiffies;
135 	if (time_before_eq(cmd_timeout, now))
136 		timeout = 1;
137 	else
138 		timeout = cmd_timeout - now;
139 
140 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
141 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
142 		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
143 	else
144 		rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
145 
146 	if (!rc)
147 		ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
148 			  ctrl->slot_ctrl,
149 			  jiffies_to_msecs(jiffies - ctrl->cmd_started));
150 }
151 
152 #define CC_ERRATUM_MASK		(PCI_EXP_SLTCTL_PCC |	\
153 				 PCI_EXP_SLTCTL_PIC |	\
154 				 PCI_EXP_SLTCTL_AIC |	\
155 				 PCI_EXP_SLTCTL_EIC)
156 
pcie_do_write_cmd(struct controller * ctrl,u16 cmd,u16 mask,bool wait)157 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
158 			      u16 mask, bool wait)
159 {
160 	struct pci_dev *pdev = ctrl_dev(ctrl);
161 	u16 slot_ctrl_orig, slot_ctrl;
162 
163 	mutex_lock(&ctrl->ctrl_lock);
164 
165 	/*
166 	 * Always wait for any previous command that might still be in progress
167 	 */
168 	pcie_wait_cmd(ctrl);
169 
170 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
171 	if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
172 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
173 		goto out;
174 	}
175 
176 	slot_ctrl_orig = slot_ctrl;
177 	slot_ctrl &= ~mask;
178 	slot_ctrl |= (cmd & mask);
179 	ctrl->cmd_busy = 1;
180 	smp_mb();
181 	ctrl->slot_ctrl = slot_ctrl;
182 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
183 	ctrl->cmd_started = jiffies;
184 
185 	/*
186 	 * Controllers with the Intel CF118 and similar errata advertise
187 	 * Command Completed support, but they only set Command Completed
188 	 * if we change the "Control" bits for power, power indicator,
189 	 * attention indicator, or interlock.  If we only change the
190 	 * "Enable" bits, they never set the Command Completed bit.
191 	 */
192 	if (pdev->broken_cmd_compl &&
193 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
194 		ctrl->cmd_busy = 0;
195 
196 	/*
197 	 * Optionally wait for the hardware to be ready for a new command,
198 	 * indicating completion of the above issued command.
199 	 */
200 	if (wait)
201 		pcie_wait_cmd(ctrl);
202 
203 out:
204 	mutex_unlock(&ctrl->ctrl_lock);
205 }
206 
207 /**
208  * pcie_write_cmd - Issue controller command
209  * @ctrl: controller to which the command is issued
210  * @cmd:  command value written to slot control register
211  * @mask: bitmask of slot control register to be modified
212  */
pcie_write_cmd(struct controller * ctrl,u16 cmd,u16 mask)213 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
214 {
215 	pcie_do_write_cmd(ctrl, cmd, mask, true);
216 }
217 
218 /* Same as above without waiting for the hardware to latch */
pcie_write_cmd_nowait(struct controller * ctrl,u16 cmd,u16 mask)219 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
220 {
221 	pcie_do_write_cmd(ctrl, cmd, mask, false);
222 }
223 
224 /**
225  * pciehp_check_link_active() - Is the link active
226  * @ctrl: PCIe hotplug controller
227  *
228  * Check whether the downstream link is currently active. Note it is
229  * possible that the card is removed immediately after this so the
230  * caller may need to take it into account.
231  *
232  * If the hotplug controller itself is not available anymore returns
233  * %-ENODEV.
234  */
pciehp_check_link_active(struct controller * ctrl)235 int pciehp_check_link_active(struct controller *ctrl)
236 {
237 	struct pci_dev *pdev = ctrl_dev(ctrl);
238 	u16 lnk_status;
239 	int ret;
240 
241 	ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
242 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status))
243 		return -ENODEV;
244 
245 	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
246 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
247 
248 	return ret;
249 }
250 
pci_bus_check_dev(struct pci_bus * bus,int devfn)251 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
252 {
253 	u32 l;
254 	int count = 0;
255 	int delay = 1000, step = 20;
256 	bool found = false;
257 
258 	do {
259 		found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
260 		count++;
261 
262 		if (found)
263 			break;
264 
265 		msleep(step);
266 		delay -= step;
267 	} while (delay > 0);
268 
269 	if (count > 1)
270 		pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
271 			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
272 			PCI_FUNC(devfn), count, step, l);
273 
274 	return found;
275 }
276 
pcie_wait_for_presence(struct pci_dev * pdev)277 static void pcie_wait_for_presence(struct pci_dev *pdev)
278 {
279 	int timeout = 1250;
280 	u16 slot_status;
281 
282 	do {
283 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
284 		if (slot_status & PCI_EXP_SLTSTA_PDS)
285 			return;
286 		msleep(10);
287 		timeout -= 10;
288 	} while (timeout > 0);
289 }
290 
pciehp_check_link_status(struct controller * ctrl)291 int pciehp_check_link_status(struct controller *ctrl)
292 {
293 	struct pci_dev *pdev = ctrl_dev(ctrl);
294 	bool found;
295 	u16 lnk_status, linksta2;
296 
297 	if (!pcie_wait_for_link(pdev, true)) {
298 		ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
299 		return -1;
300 	}
301 
302 	if (ctrl->inband_presence_disabled)
303 		pcie_wait_for_presence(pdev);
304 
305 	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
306 					PCI_DEVFN(0, 0));
307 
308 	/* ignore link or presence changes up to this point */
309 	if (found)
310 		atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
311 			   &ctrl->pending_events);
312 
313 	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
314 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
315 	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
316 	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
317 		ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
318 			  slot_name(ctrl), lnk_status);
319 		return -1;
320 	}
321 
322 	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &linksta2);
323 	__pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status, linksta2);
324 
325 	if (!found) {
326 		ctrl_info(ctrl, "Slot(%s): No device found\n",
327 			  slot_name(ctrl));
328 		return -1;
329 	}
330 
331 	return 0;
332 }
333 
__pciehp_link_set(struct controller * ctrl,bool enable)334 static int __pciehp_link_set(struct controller *ctrl, bool enable)
335 {
336 	struct pci_dev *pdev = ctrl_dev(ctrl);
337 
338 	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
339 					   PCI_EXP_LNKCTL_LD,
340 					   enable ? 0 : PCI_EXP_LNKCTL_LD);
341 
342 	return 0;
343 }
344 
pciehp_link_enable(struct controller * ctrl)345 static int pciehp_link_enable(struct controller *ctrl)
346 {
347 	return __pciehp_link_set(ctrl, true);
348 }
349 
pciehp_get_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 * status)350 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
351 				    u8 *status)
352 {
353 	struct controller *ctrl = to_ctrl(hotplug_slot);
354 	struct pci_dev *pdev = ctrl_dev(ctrl);
355 	u16 slot_ctrl;
356 
357 	pci_config_pm_runtime_get(pdev);
358 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
359 	pci_config_pm_runtime_put(pdev);
360 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
361 	return 0;
362 }
363 
pciehp_get_attention_status(struct hotplug_slot * hotplug_slot,u8 * status)364 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
365 {
366 	struct controller *ctrl = to_ctrl(hotplug_slot);
367 	struct pci_dev *pdev = ctrl_dev(ctrl);
368 	u16 slot_ctrl;
369 
370 	pci_config_pm_runtime_get(pdev);
371 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
372 	pci_config_pm_runtime_put(pdev);
373 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
374 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
375 
376 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
377 	case PCI_EXP_SLTCTL_ATTN_IND_ON:
378 		*status = 1;	/* On */
379 		break;
380 	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
381 		*status = 2;	/* Blink */
382 		break;
383 	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
384 		*status = 0;	/* Off */
385 		break;
386 	default:
387 		*status = 0xFF;
388 		break;
389 	}
390 
391 	return 0;
392 }
393 
pciehp_get_power_status(struct controller * ctrl,u8 * status)394 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
395 {
396 	struct pci_dev *pdev = ctrl_dev(ctrl);
397 	u16 slot_ctrl;
398 
399 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
400 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
401 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
402 
403 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
404 	case PCI_EXP_SLTCTL_PWR_ON:
405 		*status = 1;	/* On */
406 		break;
407 	case PCI_EXP_SLTCTL_PWR_OFF:
408 		*status = 0;	/* Off */
409 		break;
410 	default:
411 		*status = 0xFF;
412 		break;
413 	}
414 }
415 
pciehp_get_latch_status(struct controller * ctrl,u8 * status)416 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
417 {
418 	struct pci_dev *pdev = ctrl_dev(ctrl);
419 	u16 slot_status;
420 
421 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
422 	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
423 }
424 
425 /**
426  * pciehp_card_present() - Is the card present
427  * @ctrl: PCIe hotplug controller
428  *
429  * Function checks whether the card is currently present in the slot and
430  * in that case returns true. Note it is possible that the card is
431  * removed immediately after the check so the caller may need to take
432  * this into account.
433  *
434  * If the hotplug controller itself is not available anymore returns
435  * %-ENODEV.
436  */
pciehp_card_present(struct controller * ctrl)437 int pciehp_card_present(struct controller *ctrl)
438 {
439 	struct pci_dev *pdev = ctrl_dev(ctrl);
440 	u16 slot_status;
441 	int ret;
442 
443 	ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
444 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status))
445 		return -ENODEV;
446 
447 	return !!(slot_status & PCI_EXP_SLTSTA_PDS);
448 }
449 
450 /**
451  * pciehp_card_present_or_link_active() - whether given slot is occupied
452  * @ctrl: PCIe hotplug controller
453  *
454  * Unlike pciehp_card_present(), which determines presence solely from the
455  * Presence Detect State bit, this helper also returns true if the Link Active
456  * bit is set.  This is a concession to broken hotplug ports which hardwire
457  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
458  *
459  * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
460  *	    port is not present anymore returns %-ENODEV.
461  */
pciehp_card_present_or_link_active(struct controller * ctrl)462 int pciehp_card_present_or_link_active(struct controller *ctrl)
463 {
464 	int ret;
465 
466 	ret = pciehp_card_present(ctrl);
467 	if (ret)
468 		return ret;
469 
470 	return pciehp_check_link_active(ctrl);
471 }
472 
pciehp_query_power_fault(struct controller * ctrl)473 int pciehp_query_power_fault(struct controller *ctrl)
474 {
475 	struct pci_dev *pdev = ctrl_dev(ctrl);
476 	u16 slot_status;
477 
478 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
479 	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
480 }
481 
pciehp_set_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 status)482 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
483 				    u8 status)
484 {
485 	struct controller *ctrl = to_ctrl(hotplug_slot);
486 	struct pci_dev *pdev = ctrl_dev(ctrl);
487 
488 	pci_config_pm_runtime_get(pdev);
489 
490 	/* Attention and Power Indicator Control bits are supported */
491 	pcie_write_cmd_nowait(ctrl, FIELD_PREP(PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC, status),
492 			      PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
493 	pci_config_pm_runtime_put(pdev);
494 	return 0;
495 }
496 
497 /**
498  * pciehp_set_indicators() - set attention indicator, power indicator, or both
499  * @ctrl: PCIe hotplug controller
500  * @pwr: one of:
501  *	PCI_EXP_SLTCTL_PWR_IND_ON
502  *	PCI_EXP_SLTCTL_PWR_IND_BLINK
503  *	PCI_EXP_SLTCTL_PWR_IND_OFF
504  * @attn: one of:
505  *	PCI_EXP_SLTCTL_ATTN_IND_ON
506  *	PCI_EXP_SLTCTL_ATTN_IND_BLINK
507  *	PCI_EXP_SLTCTL_ATTN_IND_OFF
508  *
509  * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
510  * unchanged.
511  */
pciehp_set_indicators(struct controller * ctrl,int pwr,int attn)512 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
513 {
514 	u16 cmd = 0, mask = 0;
515 
516 	if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
517 		cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
518 		mask |= PCI_EXP_SLTCTL_PIC;
519 	}
520 
521 	if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
522 		cmd |= (attn & PCI_EXP_SLTCTL_AIC);
523 		mask |= PCI_EXP_SLTCTL_AIC;
524 	}
525 
526 	if (cmd) {
527 		pcie_write_cmd_nowait(ctrl, cmd, mask);
528 		ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 			 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
530 	}
531 }
532 
pciehp_power_on_slot(struct controller * ctrl)533 int pciehp_power_on_slot(struct controller *ctrl)
534 {
535 	struct pci_dev *pdev = ctrl_dev(ctrl);
536 	u16 slot_status;
537 	int retval;
538 
539 	/* Clear power-fault bit from previous power failures */
540 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
541 	if (slot_status & PCI_EXP_SLTSTA_PFD)
542 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
543 					   PCI_EXP_SLTSTA_PFD);
544 	ctrl->power_fault_detected = 0;
545 
546 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
547 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
548 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
549 		 PCI_EXP_SLTCTL_PWR_ON);
550 
551 	retval = pciehp_link_enable(ctrl);
552 	if (retval)
553 		ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
554 
555 	return retval;
556 }
557 
pciehp_power_off_slot(struct controller * ctrl)558 void pciehp_power_off_slot(struct controller *ctrl)
559 {
560 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
561 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
562 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
563 		 PCI_EXP_SLTCTL_PWR_OFF);
564 }
565 
pciehp_ignore_dpc_link_change(struct controller * ctrl,struct pci_dev * pdev,int irq)566 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
567 					  struct pci_dev *pdev, int irq)
568 {
569 	/*
570 	 * Ignore link changes which occurred while waiting for DPC recovery.
571 	 * Could be several if DPC triggered multiple times consecutively.
572 	 */
573 	synchronize_hardirq(irq);
574 	atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
575 	if (pciehp_poll_mode)
576 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
577 					   PCI_EXP_SLTSTA_DLLSC);
578 	ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
579 		  slot_name(ctrl));
580 
581 	/*
582 	 * If the link is unexpectedly down after successful recovery,
583 	 * the corresponding link change may have been ignored above.
584 	 * Synthesize it to ensure that it is acted on.
585 	 */
586 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
587 	if (!pciehp_check_link_active(ctrl))
588 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
589 	up_read(&ctrl->reset_lock);
590 }
591 
pciehp_isr(int irq,void * dev_id)592 static irqreturn_t pciehp_isr(int irq, void *dev_id)
593 {
594 	struct controller *ctrl = (struct controller *)dev_id;
595 	struct pci_dev *pdev = ctrl_dev(ctrl);
596 	struct device *parent = pdev->dev.parent;
597 	u16 status, events = 0;
598 
599 	/*
600 	 * Interrupts only occur in D3hot or shallower and only if enabled
601 	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
602 	 */
603 	if (pdev->current_state == PCI_D3cold ||
604 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
605 		return IRQ_NONE;
606 
607 	/*
608 	 * Keep the port accessible by holding a runtime PM ref on its parent.
609 	 * Defer resume of the parent to the IRQ thread if it's suspended.
610 	 * Mask the interrupt until then.
611 	 */
612 	if (parent) {
613 		pm_runtime_get_noresume(parent);
614 		if (!pm_runtime_active(parent)) {
615 			pm_runtime_put(parent);
616 			disable_irq_nosync(irq);
617 			atomic_or(RERUN_ISR, &ctrl->pending_events);
618 			return IRQ_WAKE_THREAD;
619 		}
620 	}
621 
622 read_status:
623 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
624 	if (PCI_POSSIBLE_ERROR(status)) {
625 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
626 		if (parent)
627 			pm_runtime_put(parent);
628 		return IRQ_NONE;
629 	}
630 
631 	/*
632 	 * Slot Status contains plain status bits as well as event
633 	 * notification bits; right now we only want the event bits.
634 	 */
635 	status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
636 		  PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
637 		  PCI_EXP_SLTSTA_DLLSC;
638 
639 	/*
640 	 * If we've already reported a power fault, don't report it again
641 	 * until we've done something to handle it.
642 	 */
643 	if (ctrl->power_fault_detected)
644 		status &= ~PCI_EXP_SLTSTA_PFD;
645 	else if (status & PCI_EXP_SLTSTA_PFD)
646 		ctrl->power_fault_detected = true;
647 
648 	events |= status;
649 	if (!events) {
650 		if (parent)
651 			pm_runtime_put(parent);
652 		return IRQ_NONE;
653 	}
654 
655 	if (status) {
656 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
657 
658 		/*
659 		 * In MSI mode, all event bits must be zero before the port
660 		 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
661 		 * So re-read the Slot Status register in case a bit was set
662 		 * between read and write.
663 		 */
664 		if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
665 			goto read_status;
666 	}
667 
668 	ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
669 	if (parent)
670 		pm_runtime_put(parent);
671 
672 	/*
673 	 * Command Completed notifications are not deferred to the
674 	 * IRQ thread because it may be waiting for their arrival.
675 	 */
676 	if (events & PCI_EXP_SLTSTA_CC) {
677 		ctrl->cmd_busy = 0;
678 		smp_mb();
679 		wake_up(&ctrl->queue);
680 
681 		if (events == PCI_EXP_SLTSTA_CC)
682 			return IRQ_HANDLED;
683 
684 		events &= ~PCI_EXP_SLTSTA_CC;
685 	}
686 
687 	if (pdev->ignore_hotplug) {
688 		ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
689 		return IRQ_HANDLED;
690 	}
691 
692 	/* Save pending events for consumption by IRQ thread. */
693 	atomic_or(events, &ctrl->pending_events);
694 	return IRQ_WAKE_THREAD;
695 }
696 
pciehp_ist(int irq,void * dev_id)697 static irqreturn_t pciehp_ist(int irq, void *dev_id)
698 {
699 	struct controller *ctrl = (struct controller *)dev_id;
700 	struct pci_dev *pdev = ctrl_dev(ctrl);
701 	irqreturn_t ret;
702 	u32 events;
703 
704 	ctrl->ist_running = true;
705 	pci_config_pm_runtime_get(pdev);
706 
707 	/* rerun pciehp_isr() if the port was inaccessible on interrupt */
708 	if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
709 		ret = pciehp_isr(irq, dev_id);
710 		enable_irq(irq);
711 		if (ret != IRQ_WAKE_THREAD)
712 			goto out;
713 	}
714 
715 	synchronize_hardirq(irq);
716 	events = atomic_xchg(&ctrl->pending_events, 0);
717 	if (!events) {
718 		ret = IRQ_NONE;
719 		goto out;
720 	}
721 
722 	/* Check Attention Button Pressed */
723 	if (events & PCI_EXP_SLTSTA_ABP)
724 		pciehp_handle_button_press(ctrl);
725 
726 	/* Check Power Fault Detected */
727 	if (events & PCI_EXP_SLTSTA_PFD) {
728 		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
729 		pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
730 				      PCI_EXP_SLTCTL_ATTN_IND_ON);
731 	}
732 
733 	/*
734 	 * Ignore Link Down/Up events caused by Downstream Port Containment
735 	 * if recovery from the error succeeded.
736 	 */
737 	if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
738 	    ctrl->state == ON_STATE) {
739 		events &= ~PCI_EXP_SLTSTA_DLLSC;
740 		pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
741 	}
742 
743 	/*
744 	 * Disable requests have higher priority than Presence Detect Changed
745 	 * or Data Link Layer State Changed events.
746 	 */
747 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
748 	if (events & DISABLE_SLOT)
749 		pciehp_handle_disable_request(ctrl);
750 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
751 		pciehp_handle_presence_or_link_change(ctrl, events);
752 	up_read(&ctrl->reset_lock);
753 
754 	ret = IRQ_HANDLED;
755 out:
756 	pci_config_pm_runtime_put(pdev);
757 	ctrl->ist_running = false;
758 	wake_up(&ctrl->requester);
759 	return ret;
760 }
761 
pciehp_poll(void * data)762 static int pciehp_poll(void *data)
763 {
764 	struct controller *ctrl = data;
765 
766 	schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
767 
768 	while (!kthread_should_stop()) {
769 		/* poll for interrupt events or user requests */
770 		while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
771 		       atomic_read(&ctrl->pending_events))
772 			pciehp_ist(IRQ_NOTCONNECTED, ctrl);
773 
774 		if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
775 			pciehp_poll_time = 2; /* clamp to sane value */
776 
777 		schedule_timeout_idle(pciehp_poll_time * HZ);
778 	}
779 
780 	return 0;
781 }
782 
pcie_enable_notification(struct controller * ctrl)783 static void pcie_enable_notification(struct controller *ctrl)
784 {
785 	u16 cmd, mask;
786 
787 	/*
788 	 * TBD: Power fault detected software notification support.
789 	 *
790 	 * Power fault detected software notification is not enabled
791 	 * now, because it caused power fault detected interrupt storm
792 	 * on some machines. On those machines, power fault detected
793 	 * bit in the slot status register was set again immediately
794 	 * when it is cleared in the interrupt service routine, and
795 	 * next power fault detected interrupt was notified again.
796 	 */
797 
798 	/*
799 	 * Always enable link events: thus link-up and link-down shall
800 	 * always be treated as hotplug and unplug respectively. Enable
801 	 * presence detect only if Attention Button is not present.
802 	 */
803 	cmd = PCI_EXP_SLTCTL_DLLSCE;
804 	if (ATTN_BUTTN(ctrl))
805 		cmd |= PCI_EXP_SLTCTL_ABPE;
806 	else
807 		cmd |= PCI_EXP_SLTCTL_PDCE;
808 	if (!pciehp_poll_mode)
809 		cmd |= PCI_EXP_SLTCTL_HPIE;
810 	if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl))
811 		cmd |= PCI_EXP_SLTCTL_CCIE;
812 
813 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
814 		PCI_EXP_SLTCTL_PFDE |
815 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
816 		PCI_EXP_SLTCTL_DLLSCE);
817 
818 	pcie_write_cmd_nowait(ctrl, cmd, mask);
819 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
820 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
821 }
822 
pcie_disable_notification(struct controller * ctrl)823 static void pcie_disable_notification(struct controller *ctrl)
824 {
825 	u16 mask;
826 
827 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
828 		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
829 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
830 		PCI_EXP_SLTCTL_DLLSCE);
831 	pcie_write_cmd(ctrl, 0, mask);
832 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
833 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
834 }
835 
pcie_clear_hotplug_events(struct controller * ctrl)836 void pcie_clear_hotplug_events(struct controller *ctrl)
837 {
838 	pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
839 				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
840 }
841 
pcie_enable_interrupt(struct controller * ctrl)842 void pcie_enable_interrupt(struct controller *ctrl)
843 {
844 	u16 mask;
845 
846 	mask = PCI_EXP_SLTCTL_DLLSCE;
847 	if (!pciehp_poll_mode)
848 		mask |= PCI_EXP_SLTCTL_HPIE;
849 	pcie_write_cmd(ctrl, mask, mask);
850 }
851 
pcie_disable_interrupt(struct controller * ctrl)852 void pcie_disable_interrupt(struct controller *ctrl)
853 {
854 	u16 mask;
855 
856 	/*
857 	 * Mask hot-plug interrupt to prevent it triggering immediately
858 	 * when the link goes inactive (we still get PME when any of the
859 	 * enabled events is detected). Same goes with Link Layer State
860 	 * changed event which generates PME immediately when the link goes
861 	 * inactive so mask it as well.
862 	 */
863 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
864 	pcie_write_cmd(ctrl, 0, mask);
865 }
866 
867 /**
868  * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
869  * @dev: PCI Express port service device
870  *
871  * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
872  * further up in the hierarchy to recover from an error.  The reset was
873  * propagated down to this hotplug port.  Ignore the resulting link flap.
874  * If the link failed to retrain successfully, synthesize the ignored event.
875  * Surprise removal during reset is detected through Presence Detect Changed.
876  */
pciehp_slot_reset(struct pcie_device * dev)877 int pciehp_slot_reset(struct pcie_device *dev)
878 {
879 	struct controller *ctrl = get_service_data(dev);
880 
881 	if (ctrl->state != ON_STATE)
882 		return 0;
883 
884 	pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
885 				   PCI_EXP_SLTSTA_DLLSC);
886 
887 	if (!pciehp_check_link_active(ctrl))
888 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
889 
890 	return 0;
891 }
892 
893 /*
894  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
895  * bus reset of the bridge, but at the same time we want to ensure that it is
896  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
897  * disable link state notification and presence detection change notification
898  * momentarily, if we see that they could interfere. Also, clear any spurious
899  * events after.
900  */
pciehp_reset_slot(struct hotplug_slot * hotplug_slot,bool probe)901 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
902 {
903 	struct controller *ctrl = to_ctrl(hotplug_slot);
904 	struct pci_dev *pdev = ctrl_dev(ctrl);
905 	u16 stat_mask = 0, ctrl_mask = 0;
906 	int rc;
907 
908 	if (probe)
909 		return 0;
910 
911 	down_write_nested(&ctrl->reset_lock, ctrl->depth);
912 
913 	if (!ATTN_BUTTN(ctrl)) {
914 		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
915 		stat_mask |= PCI_EXP_SLTSTA_PDC;
916 	}
917 	ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
918 	stat_mask |= PCI_EXP_SLTSTA_DLLSC;
919 
920 	pcie_write_cmd(ctrl, 0, ctrl_mask);
921 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
922 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
923 
924 	rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
925 
926 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
927 	pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
928 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
929 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
930 
931 	up_write(&ctrl->reset_lock);
932 	return rc;
933 }
934 
pcie_init_notification(struct controller * ctrl)935 int pcie_init_notification(struct controller *ctrl)
936 {
937 	if (pciehp_request_irq(ctrl))
938 		return -1;
939 	pcie_enable_notification(ctrl);
940 	ctrl->notification_enabled = 1;
941 	return 0;
942 }
943 
pcie_shutdown_notification(struct controller * ctrl)944 void pcie_shutdown_notification(struct controller *ctrl)
945 {
946 	if (ctrl->notification_enabled) {
947 		pcie_disable_notification(ctrl);
948 		pciehp_free_irq(ctrl);
949 		ctrl->notification_enabled = 0;
950 	}
951 }
952 
dbg_ctrl(struct controller * ctrl)953 static inline void dbg_ctrl(struct controller *ctrl)
954 {
955 	struct pci_dev *pdev = ctrl->pcie->port;
956 	u16 reg16;
957 
958 	ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
959 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
960 	ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
961 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
962 	ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
963 }
964 
965 #define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
966 
pcie_hotplug_depth(struct pci_dev * dev)967 static inline int pcie_hotplug_depth(struct pci_dev *dev)
968 {
969 	struct pci_bus *bus = dev->bus;
970 	int depth = 0;
971 
972 	while (bus->parent) {
973 		bus = bus->parent;
974 		if (bus->self && bus->self->is_hotplug_bridge)
975 			depth++;
976 	}
977 
978 	return depth;
979 }
980 
pcie_init(struct pcie_device * dev)981 struct controller *pcie_init(struct pcie_device *dev)
982 {
983 	struct controller *ctrl;
984 	u32 slot_cap, slot_cap2;
985 	u8 poweron;
986 	struct pci_dev *pdev = dev->port;
987 	struct pci_bus *subordinate = pdev->subordinate;
988 
989 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
990 	if (!ctrl)
991 		return NULL;
992 
993 	ctrl->pcie = dev;
994 	ctrl->depth = pcie_hotplug_depth(dev->port);
995 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
996 
997 	if (pdev->hotplug_user_indicators)
998 		slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
999 
1000 	/*
1001 	 * We assume no Thunderbolt controllers support Command Complete events,
1002 	 * but some controllers falsely claim they do.
1003 	 */
1004 	if (pdev->is_thunderbolt)
1005 		slot_cap |= PCI_EXP_SLTCAP_NCCS;
1006 
1007 	ctrl->slot_cap = slot_cap;
1008 	mutex_init(&ctrl->ctrl_lock);
1009 	mutex_init(&ctrl->state_lock);
1010 	init_rwsem(&ctrl->reset_lock);
1011 	init_waitqueue_head(&ctrl->requester);
1012 	init_waitqueue_head(&ctrl->queue);
1013 	INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1014 	dbg_ctrl(ctrl);
1015 
1016 	down_read(&pci_bus_sem);
1017 	ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1018 	up_read(&pci_bus_sem);
1019 
1020 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1021 	if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1022 		pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1023 				      PCI_EXP_SLTCTL_IBPD_DISABLE);
1024 		ctrl->inband_presence_disabled = 1;
1025 	}
1026 
1027 	if (dmi_first_match(inband_presence_disabled_dmi_table))
1028 		ctrl->inband_presence_disabled = 1;
1029 
1030 	/* Clear all remaining event bits in Slot Status register. */
1031 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1032 		PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1033 		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1034 		PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1035 
1036 	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1037 		FIELD_GET(PCI_EXP_SLTCAP_PSN, slot_cap),
1038 		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1039 		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1040 		FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1041 		FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1042 		FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1043 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1044 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1045 		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1046 		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1047 		FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1048 		FLAG(pdev->link_active_reporting, true),
1049 		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1050 
1051 	/*
1052 	 * If empty slot's power status is on, turn power off.  The IRQ isn't
1053 	 * requested yet, so avoid triggering a notification with this command.
1054 	 */
1055 	if (POWER_CTRL(ctrl)) {
1056 		pciehp_get_power_status(ctrl, &poweron);
1057 		if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1058 			pcie_disable_notification(ctrl);
1059 			pciehp_power_off_slot(ctrl);
1060 		}
1061 	}
1062 
1063 	pdev = pci_get_slot(subordinate, PCI_DEVFN(0, 0));
1064 	if (pdev)
1065 		ctrl->dsn = pci_get_dsn(pdev);
1066 	pci_dev_put(pdev);
1067 
1068 	return ctrl;
1069 }
1070 
pciehp_release_ctrl(struct controller * ctrl)1071 void pciehp_release_ctrl(struct controller *ctrl)
1072 {
1073 	cancel_delayed_work_sync(&ctrl->button_work);
1074 	kfree(ctrl);
1075 }
1076 
quirk_cmd_compl(struct pci_dev * pdev)1077 static void quirk_cmd_compl(struct pci_dev *pdev)
1078 {
1079 	u32 slot_cap;
1080 
1081 	if (pci_is_pcie(pdev)) {
1082 		pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1083 		if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1084 		    !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1085 			pdev->broken_cmd_compl = 1;
1086 	}
1087 }
1088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1089 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x010e,
1091 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1093 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1094 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1095 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1097 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1098 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1099 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1100