1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Rockchip SoCs.
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
7 *
8 * Author: Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #include "pcie-designware.h"
25
26 /*
27 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write
28 * mask for the lower 16 bits.
29 */
30 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
31 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
33
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
35
36 #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
37 #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
38 #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
39 #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
40 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10
41 #define PCIE_CLIENT_INTR_MASK_MISC 0x24
42 #define PCIE_SMLH_LINKUP BIT(16)
43 #define PCIE_RDLH_LINKUP BIT(17)
44 #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
45 #define PCIE_RDLH_LINK_UP_CHGED BIT(1)
46 #define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
47 #define PCIE_L0S_ENTRY 0x11
48 #define PCIE_CLIENT_GENERAL_CONTROL 0x0
49 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
50 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
51 #define PCIE_CLIENT_GENERAL_DEBUG 0x104
52 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
53 #define PCIE_CLIENT_LTSSM_STATUS 0x300
54 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
55 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
56
57 struct rockchip_pcie {
58 struct dw_pcie pci;
59 void __iomem *apb_base;
60 struct phy *phy;
61 struct clk_bulk_data *clks;
62 unsigned int clk_cnt;
63 struct reset_control *rst;
64 struct gpio_desc *rst_gpio;
65 struct regulator *vpcie3v3;
66 struct irq_domain *irq_domain;
67 const struct rockchip_pcie_of_data *data;
68 };
69
70 struct rockchip_pcie_of_data {
71 enum dw_pcie_device_mode mode;
72 const struct pci_epc_features *epc_features;
73 };
74
rockchip_pcie_readl_apb(struct rockchip_pcie * rockchip,u32 reg)75 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
76 {
77 return readl_relaxed(rockchip->apb_base + reg);
78 }
79
rockchip_pcie_writel_apb(struct rockchip_pcie * rockchip,u32 val,u32 reg)80 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,
81 u32 reg)
82 {
83 writel_relaxed(val, rockchip->apb_base + reg);
84 }
85
rockchip_pcie_intx_handler(struct irq_desc * desc)86 static void rockchip_pcie_intx_handler(struct irq_desc *desc)
87 {
88 struct irq_chip *chip = irq_desc_get_chip(desc);
89 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
90 unsigned long reg, hwirq;
91
92 chained_irq_enter(chip, desc);
93
94 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
95
96 for_each_set_bit(hwirq, ®, 4)
97 generic_handle_domain_irq(rockchip->irq_domain, hwirq);
98
99 chained_irq_exit(chip, desc);
100 }
101
rockchip_intx_mask(struct irq_data * data)102 static void rockchip_intx_mask(struct irq_data *data)
103 {
104 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
105 HIWORD_UPDATE_BIT(BIT(data->hwirq)),
106 PCIE_CLIENT_INTR_MASK_LEGACY);
107 };
108
rockchip_intx_unmask(struct irq_data * data)109 static void rockchip_intx_unmask(struct irq_data *data)
110 {
111 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
112 HIWORD_DISABLE_BIT(BIT(data->hwirq)),
113 PCIE_CLIENT_INTR_MASK_LEGACY);
114 };
115
116 static struct irq_chip rockchip_intx_irq_chip = {
117 .name = "INTx",
118 .irq_mask = rockchip_intx_mask,
119 .irq_unmask = rockchip_intx_unmask,
120 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
121 };
122
rockchip_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)123 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
124 irq_hw_number_t hwirq)
125 {
126 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
127 irq_set_chip_data(irq, domain->host_data);
128
129 return 0;
130 }
131
132 static const struct irq_domain_ops intx_domain_ops = {
133 .map = rockchip_pcie_intx_map,
134 };
135
rockchip_pcie_init_irq_domain(struct rockchip_pcie * rockchip)136 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
137 {
138 struct device *dev = rockchip->pci.dev;
139 struct device_node *intc;
140
141 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
142 if (!intc) {
143 dev_err(dev, "missing child interrupt-controller node\n");
144 return -EINVAL;
145 }
146
147 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
148 &intx_domain_ops, rockchip);
149 of_node_put(intc);
150 if (!rockchip->irq_domain) {
151 dev_err(dev, "failed to get a INTx IRQ domain\n");
152 return -EINVAL;
153 }
154
155 return 0;
156 }
157
rockchip_pcie_get_ltssm(struct rockchip_pcie * rockchip)158 static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
159 {
160 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
161 }
162
rockchip_pcie_enable_ltssm(struct rockchip_pcie * rockchip)163 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
164 {
165 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
166 PCIE_CLIENT_GENERAL_CONTROL);
167 }
168
rockchip_pcie_disable_ltssm(struct rockchip_pcie * rockchip)169 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
170 {
171 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
172 PCIE_CLIENT_GENERAL_CONTROL);
173 }
174
rockchip_pcie_link_up(struct dw_pcie * pci)175 static int rockchip_pcie_link_up(struct dw_pcie *pci)
176 {
177 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
178 u32 val = rockchip_pcie_get_ltssm(rockchip);
179
180 if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
181 (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
182 return 1;
183
184 return 0;
185 }
186
rockchip_pcie_start_link(struct dw_pcie * pci)187 static int rockchip_pcie_start_link(struct dw_pcie *pci)
188 {
189 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
190
191 /* Reset device */
192 gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
193
194 rockchip_pcie_enable_ltssm(rockchip);
195
196 /*
197 * PCIe requires the refclk to be stable for 100µs prior to releasing
198 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
199 * Express Card Electromechanical Specification, 1.1. However, we don't
200 * know if the refclk is coming from RC's PHY or external OSC. If it's
201 * from RC, so enabling LTSSM is the just right place to release #PERST.
202 * We need more extra time as before, rather than setting just
203 * 100us as we don't know how long should the device need to reset.
204 */
205 msleep(100);
206 gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
207
208 return 0;
209 }
210
rockchip_pcie_stop_link(struct dw_pcie * pci)211 static void rockchip_pcie_stop_link(struct dw_pcie *pci)
212 {
213 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
214
215 rockchip_pcie_disable_ltssm(rockchip);
216 }
217
rockchip_pcie_host_init(struct dw_pcie_rp * pp)218 static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
219 {
220 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
221 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
222 struct device *dev = rockchip->pci.dev;
223 int irq, ret;
224
225 irq = of_irq_get_byname(dev->of_node, "legacy");
226 if (irq < 0)
227 return irq;
228
229 ret = rockchip_pcie_init_irq_domain(rockchip);
230 if (ret < 0)
231 dev_err(dev, "failed to init irq domain\n");
232
233 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
234 rockchip);
235
236 return 0;
237 }
238
239 static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
240 .init = rockchip_pcie_host_init,
241 };
242
243 /*
244 * ATS does not work on RK3588 when running in EP mode.
245 *
246 * After the host has enabled ATS on the EP side, it will send an IOTLB
247 * invalidation request to the EP side. However, the RK3588 will never send
248 * a completion back and eventually the host will print an IOTLB_INV_TIMEOUT
249 * error, and the EP will not be operational. If we hide the ATS capability,
250 * things work as expected.
251 */
rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep * ep)252 static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
253 {
254 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
255 struct device *dev = pci->dev;
256
257 /* Only hide the ATS capability for RK3588 running in EP mode. */
258 if (!of_device_is_compatible(dev->of_node, "rockchip,rk3588-pcie-ep"))
259 return;
260
261 if (dw_pcie_ep_hide_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI,
262 PCI_EXT_CAP_ID_ATS))
263 dev_err(dev, "failed to hide ATS capability\n");
264 }
265
rockchip_pcie_ep_pre_init(struct dw_pcie_ep * ep)266 static void rockchip_pcie_ep_pre_init(struct dw_pcie_ep *ep)
267 {
268 rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
269 }
270
rockchip_pcie_ep_init(struct dw_pcie_ep * ep)271 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
272 {
273 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
274 enum pci_barno bar;
275
276 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
277 dw_pcie_ep_reset_bar(pci, bar);
278 };
279
rockchip_pcie_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)280 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
281 unsigned int type, u16 interrupt_num)
282 {
283 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
284
285 switch (type) {
286 case PCI_IRQ_INTX:
287 return dw_pcie_ep_raise_intx_irq(ep, func_no);
288 case PCI_IRQ_MSI:
289 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
290 case PCI_IRQ_MSIX:
291 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
292 default:
293 dev_err(pci->dev, "UNKNOWN IRQ type\n");
294 }
295
296 return 0;
297 }
298
299 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
300 .linkup_notifier = true,
301 .msi_capable = true,
302 .msix_capable = true,
303 .intx_capable = false,
304 .align = SZ_64K,
305 .bar[BAR_0] = { .type = BAR_RESIZABLE, },
306 .bar[BAR_1] = { .type = BAR_RESIZABLE, },
307 .bar[BAR_2] = { .type = BAR_RESIZABLE, },
308 .bar[BAR_3] = { .type = BAR_RESIZABLE, },
309 .bar[BAR_4] = { .type = BAR_RESIZABLE, },
310 .bar[BAR_5] = { .type = BAR_RESIZABLE, },
311 };
312
313 /*
314 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
315 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
316 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by
317 * default.) If the host could write to BAR4, the iATU settings (for all other
318 * BARs) would be overwritten, resulting in (all other BARs) no longer working.
319 */
320 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
321 .linkup_notifier = true,
322 .msi_capable = true,
323 .msix_capable = true,
324 .intx_capable = false,
325 .align = SZ_64K,
326 .bar[BAR_0] = { .type = BAR_RESIZABLE, },
327 .bar[BAR_1] = { .type = BAR_RESIZABLE, },
328 .bar[BAR_2] = { .type = BAR_RESIZABLE, },
329 .bar[BAR_3] = { .type = BAR_RESIZABLE, },
330 .bar[BAR_4] = { .type = BAR_RESERVED, },
331 .bar[BAR_5] = { .type = BAR_RESIZABLE, },
332 };
333
334 static const struct pci_epc_features *
rockchip_pcie_get_features(struct dw_pcie_ep * ep)335 rockchip_pcie_get_features(struct dw_pcie_ep *ep)
336 {
337 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
338 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
339
340 return rockchip->data->epc_features;
341 }
342
343 static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
344 .init = rockchip_pcie_ep_init,
345 .pre_init = rockchip_pcie_ep_pre_init,
346 .raise_irq = rockchip_pcie_raise_irq,
347 .get_features = rockchip_pcie_get_features,
348 };
349
rockchip_pcie_clk_init(struct rockchip_pcie * rockchip)350 static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
351 {
352 struct device *dev = rockchip->pci.dev;
353 int ret;
354
355 ret = devm_clk_bulk_get_all(dev, &rockchip->clks);
356 if (ret < 0)
357 return dev_err_probe(dev, ret, "failed to get clocks\n");
358
359 rockchip->clk_cnt = ret;
360
361 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
362 if (ret)
363 return dev_err_probe(dev, ret, "failed to enable clocks\n");
364
365 return 0;
366 }
367
rockchip_pcie_resource_get(struct platform_device * pdev,struct rockchip_pcie * rockchip)368 static int rockchip_pcie_resource_get(struct platform_device *pdev,
369 struct rockchip_pcie *rockchip)
370 {
371 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
372 if (IS_ERR(rockchip->apb_base))
373 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),
374 "failed to map apb registers\n");
375
376 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
377 GPIOD_OUT_LOW);
378 if (IS_ERR(rockchip->rst_gpio))
379 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),
380 "failed to get reset gpio\n");
381
382 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
383 if (IS_ERR(rockchip->rst))
384 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
385 "failed to get reset lines\n");
386
387 return 0;
388 }
389
rockchip_pcie_phy_init(struct rockchip_pcie * rockchip)390 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
391 {
392 struct device *dev = rockchip->pci.dev;
393 int ret;
394
395 rockchip->phy = devm_phy_get(dev, "pcie-phy");
396 if (IS_ERR(rockchip->phy))
397 return dev_err_probe(dev, PTR_ERR(rockchip->phy),
398 "missing PHY\n");
399
400 ret = phy_init(rockchip->phy);
401 if (ret < 0)
402 return ret;
403
404 ret = phy_power_on(rockchip->phy);
405 if (ret)
406 phy_exit(rockchip->phy);
407
408 return ret;
409 }
410
rockchip_pcie_phy_deinit(struct rockchip_pcie * rockchip)411 static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
412 {
413 phy_exit(rockchip->phy);
414 phy_power_off(rockchip->phy);
415 }
416
417 static const struct dw_pcie_ops dw_pcie_ops = {
418 .link_up = rockchip_pcie_link_up,
419 .start_link = rockchip_pcie_start_link,
420 .stop_link = rockchip_pcie_stop_link,
421 };
422
rockchip_pcie_rc_sys_irq_thread(int irq,void * arg)423 static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
424 {
425 struct rockchip_pcie *rockchip = arg;
426 struct dw_pcie *pci = &rockchip->pci;
427 struct dw_pcie_rp *pp = &pci->pp;
428 struct device *dev = pci->dev;
429 u32 reg, val;
430
431 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
432 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
433
434 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
435 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
436
437 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
438 val = rockchip_pcie_get_ltssm(rockchip);
439 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
440 dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
441 /* Rescan the bus to enumerate endpoint devices */
442 pci_lock_rescan_remove();
443 pci_rescan_bus(pp->bridge->bus);
444 pci_unlock_rescan_remove();
445 }
446 }
447
448 return IRQ_HANDLED;
449 }
450
rockchip_pcie_ep_sys_irq_thread(int irq,void * arg)451 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
452 {
453 struct rockchip_pcie *rockchip = arg;
454 struct dw_pcie *pci = &rockchip->pci;
455 struct device *dev = pci->dev;
456 u32 reg, val;
457
458 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
459 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
460
461 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
462 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
463
464 if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
465 dev_dbg(dev, "hot reset or link-down reset\n");
466 dw_pcie_ep_linkdown(&pci->ep);
467 }
468
469 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
470 val = rockchip_pcie_get_ltssm(rockchip);
471 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {
472 dev_dbg(dev, "link up\n");
473 dw_pcie_ep_linkup(&pci->ep);
474 }
475 }
476
477 return IRQ_HANDLED;
478 }
479
rockchip_pcie_configure_rc(struct platform_device * pdev,struct rockchip_pcie * rockchip)480 static int rockchip_pcie_configure_rc(struct platform_device *pdev,
481 struct rockchip_pcie *rockchip)
482 {
483 struct device *dev = &pdev->dev;
484 struct dw_pcie_rp *pp;
485 int irq, ret;
486 u32 val;
487
488 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
489 return -ENODEV;
490
491 irq = platform_get_irq_byname(pdev, "sys");
492 if (irq < 0)
493 return irq;
494
495 ret = devm_request_threaded_irq(dev, irq, NULL,
496 rockchip_pcie_rc_sys_irq_thread,
497 IRQF_ONESHOT, "pcie-sys-rc", rockchip);
498 if (ret) {
499 dev_err(dev, "failed to request PCIe sys IRQ\n");
500 return ret;
501 }
502
503 /* LTSSM enable control mode */
504 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
505 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
506
507 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
508 PCIE_CLIENT_GENERAL_CONTROL);
509
510 pp = &rockchip->pci.pp;
511 pp->ops = &rockchip_pcie_host_ops;
512 pp->use_linkup_irq = true;
513
514 ret = dw_pcie_host_init(pp);
515 if (ret) {
516 dev_err(dev, "failed to initialize host\n");
517 return ret;
518 }
519
520 /* unmask DLL up/down indicator */
521 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED, 0);
522 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
523
524 return ret;
525 }
526
rockchip_pcie_configure_ep(struct platform_device * pdev,struct rockchip_pcie * rockchip)527 static int rockchip_pcie_configure_ep(struct platform_device *pdev,
528 struct rockchip_pcie *rockchip)
529 {
530 struct device *dev = &pdev->dev;
531 int irq, ret;
532 u32 val;
533
534 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
535 return -ENODEV;
536
537 irq = platform_get_irq_byname(pdev, "sys");
538 if (irq < 0)
539 return irq;
540
541 ret = devm_request_threaded_irq(dev, irq, NULL,
542 rockchip_pcie_ep_sys_irq_thread,
543 IRQF_ONESHOT, "pcie-sys-ep", rockchip);
544 if (ret) {
545 dev_err(dev, "failed to request PCIe sys IRQ\n");
546 return ret;
547 }
548
549 /* LTSSM enable control mode */
550 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
551 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
552
553 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
554 PCIE_CLIENT_GENERAL_CONTROL);
555
556 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
557 rockchip->pci.ep.page_size = SZ_64K;
558
559 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
560
561 ret = dw_pcie_ep_init(&rockchip->pci.ep);
562 if (ret) {
563 dev_err(dev, "failed to initialize endpoint\n");
564 return ret;
565 }
566
567 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
568 if (ret) {
569 dev_err(dev, "failed to initialize DWC endpoint registers\n");
570 dw_pcie_ep_deinit(&rockchip->pci.ep);
571 return ret;
572 }
573
574 pci_epc_init_notify(rockchip->pci.ep.epc);
575
576 /* unmask DLL up/down indicator and hot reset/link-down reset */
577 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED | PCIE_LINK_REQ_RST_NOT_INT, 0);
578 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
579
580 return ret;
581 }
582
rockchip_pcie_probe(struct platform_device * pdev)583 static int rockchip_pcie_probe(struct platform_device *pdev)
584 {
585 struct device *dev = &pdev->dev;
586 struct rockchip_pcie *rockchip;
587 const struct rockchip_pcie_of_data *data;
588 int ret;
589
590 data = of_device_get_match_data(dev);
591 if (!data)
592 return -EINVAL;
593
594 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
595 if (!rockchip)
596 return -ENOMEM;
597
598 platform_set_drvdata(pdev, rockchip);
599
600 rockchip->pci.dev = dev;
601 rockchip->pci.ops = &dw_pcie_ops;
602 rockchip->data = data;
603
604 ret = rockchip_pcie_resource_get(pdev, rockchip);
605 if (ret)
606 return ret;
607
608 ret = reset_control_assert(rockchip->rst);
609 if (ret)
610 return ret;
611
612 /* DON'T MOVE ME: must be enable before PHY init */
613 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
614 if (IS_ERR(rockchip->vpcie3v3)) {
615 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
616 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
617 "failed to get vpcie3v3 regulator\n");
618 rockchip->vpcie3v3 = NULL;
619 } else {
620 ret = regulator_enable(rockchip->vpcie3v3);
621 if (ret)
622 return dev_err_probe(dev, ret,
623 "failed to enable vpcie3v3 regulator\n");
624 }
625
626 ret = rockchip_pcie_phy_init(rockchip);
627 if (ret)
628 goto disable_regulator;
629
630 ret = reset_control_deassert(rockchip->rst);
631 if (ret)
632 goto deinit_phy;
633
634 ret = rockchip_pcie_clk_init(rockchip);
635 if (ret)
636 goto deinit_phy;
637
638 switch (data->mode) {
639 case DW_PCIE_RC_TYPE:
640 ret = rockchip_pcie_configure_rc(pdev, rockchip);
641 if (ret)
642 goto deinit_clk;
643 break;
644 case DW_PCIE_EP_TYPE:
645 ret = rockchip_pcie_configure_ep(pdev, rockchip);
646 if (ret)
647 goto deinit_clk;
648 break;
649 default:
650 dev_err(dev, "INVALID device type %d\n", data->mode);
651 ret = -EINVAL;
652 goto deinit_clk;
653 }
654
655 return 0;
656
657 deinit_clk:
658 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
659 deinit_phy:
660 rockchip_pcie_phy_deinit(rockchip);
661 disable_regulator:
662 if (rockchip->vpcie3v3)
663 regulator_disable(rockchip->vpcie3v3);
664
665 return ret;
666 }
667
668 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
669 .mode = DW_PCIE_RC_TYPE,
670 };
671
672 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {
673 .mode = DW_PCIE_EP_TYPE,
674 .epc_features = &rockchip_pcie_epc_features_rk3568,
675 };
676
677 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {
678 .mode = DW_PCIE_EP_TYPE,
679 .epc_features = &rockchip_pcie_epc_features_rk3588,
680 };
681
682 static const struct of_device_id rockchip_pcie_of_match[] = {
683 {
684 .compatible = "rockchip,rk3568-pcie",
685 .data = &rockchip_pcie_rc_of_data_rk3568,
686 },
687 {
688 .compatible = "rockchip,rk3568-pcie-ep",
689 .data = &rockchip_pcie_ep_of_data_rk3568,
690 },
691 {
692 .compatible = "rockchip,rk3588-pcie-ep",
693 .data = &rockchip_pcie_ep_of_data_rk3588,
694 },
695 {},
696 };
697
698 static struct platform_driver rockchip_pcie_driver = {
699 .driver = {
700 .name = "rockchip-dw-pcie",
701 .of_match_table = rockchip_pcie_of_match,
702 .suppress_bind_attrs = true,
703 },
704 .probe = rockchip_pcie_probe,
705 };
706 builtin_platform_driver(rockchip_pcie_driver);
707