1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NVM Express device driver
4  * Copyright (c) 2011-2014, Intel Corporation.
5  */
6 
7 #include <linux/acpi.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-integrity.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kstrtox.h>
17 #include <linux/memremap.h>
18 #include <linux/mm.h>
19 #include <linux/module.h>
20 #include <linux/mutex.h>
21 #include <linux/once.h>
22 #include <linux/pci.h>
23 #include <linux/suspend.h>
24 #include <linux/t10-pi.h>
25 #include <linux/types.h>
26 #include <linux/io-64-nonatomic-lo-hi.h>
27 #include <linux/io-64-nonatomic-hi-lo.h>
28 #include <linux/sed-opal.h>
29 #include <linux/pci-p2pdma.h>
30 
31 #include "trace.h"
32 #include "nvme.h"
33 
34 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
35 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
36 
37 #define SGES_PER_PAGE	(NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
38 
39 /*
40  * These can be higher, but we need to ensure that any command doesn't
41  * require an sg allocation that needs more than a page of data.
42  */
43 #define NVME_MAX_KB_SZ	8192
44 #define NVME_MAX_SEGS	128
45 #define NVME_MAX_META_SEGS 15
46 #define NVME_MAX_NR_ALLOCATIONS	5
47 
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
50 
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54 
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59 
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 		"Use SGLs when average request segment size is larger or equal to "
64 		"this size. Use 0 to disable SGLs.");
65 
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 	.set = io_queue_depth_set,
71 	.get = param_get_uint,
72 };
73 
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77 
io_queue_count_set(const char * val,const struct kernel_param * kp)78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79 {
80 	unsigned int n;
81 	int ret;
82 
83 	ret = kstrtouint(val, 10, &n);
84 	if (ret != 0 || n > num_possible_cpus())
85 		return -EINVAL;
86 	return param_set_uint(val, kp);
87 }
88 
89 static const struct kernel_param_ops io_queue_count_ops = {
90 	.set = io_queue_count_set,
91 	.get = param_get_uint,
92 };
93 
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 	"Number of queues to use for writes. If not set, reads and writes "
98 	"will share a queue set.");
99 
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103 
104 static bool noacpi;
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107 
108 struct nvme_dev;
109 struct nvme_queue;
110 
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
113 static void nvme_update_attrs(struct nvme_dev *dev);
114 
115 /*
116  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
117  */
118 struct nvme_dev {
119 	struct nvme_queue *queues;
120 	struct blk_mq_tag_set tagset;
121 	struct blk_mq_tag_set admin_tagset;
122 	u32 __iomem *dbs;
123 	struct device *dev;
124 	struct dma_pool *prp_page_pool;
125 	struct dma_pool *prp_small_pool;
126 	unsigned online_queues;
127 	unsigned max_qid;
128 	unsigned io_queues[HCTX_MAX_TYPES];
129 	unsigned int num_vecs;
130 	u32 q_depth;
131 	int io_sqes;
132 	u32 db_stride;
133 	void __iomem *bar;
134 	unsigned long bar_mapped_size;
135 	struct mutex shutdown_lock;
136 	bool subsystem;
137 	u64 cmb_size;
138 	bool cmb_use_sqes;
139 	u32 cmbsz;
140 	u32 cmbloc;
141 	struct nvme_ctrl ctrl;
142 	u32 last_ps;
143 	bool hmb;
144 	struct sg_table *hmb_sgt;
145 
146 	mempool_t *iod_mempool;
147 	mempool_t *iod_meta_mempool;
148 
149 	/* shadow doorbell buffer support: */
150 	__le32 *dbbuf_dbs;
151 	dma_addr_t dbbuf_dbs_dma_addr;
152 	__le32 *dbbuf_eis;
153 	dma_addr_t dbbuf_eis_dma_addr;
154 
155 	/* host memory buffer support: */
156 	u64 host_mem_size;
157 	u32 nr_host_mem_descs;
158 	u32 host_mem_descs_size;
159 	dma_addr_t host_mem_descs_dma;
160 	struct nvme_host_mem_buf_desc *host_mem_descs;
161 	void **host_mem_desc_bufs;
162 	unsigned int nr_allocated_queues;
163 	unsigned int nr_write_queues;
164 	unsigned int nr_poll_queues;
165 };
166 
io_queue_depth_set(const char * val,const struct kernel_param * kp)167 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
168 {
169 	return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
170 			NVME_PCI_MAX_QUEUE_SIZE);
171 }
172 
sq_idx(unsigned int qid,u32 stride)173 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
174 {
175 	return qid * 2 * stride;
176 }
177 
cq_idx(unsigned int qid,u32 stride)178 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
179 {
180 	return (qid * 2 + 1) * stride;
181 }
182 
to_nvme_dev(struct nvme_ctrl * ctrl)183 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
184 {
185 	return container_of(ctrl, struct nvme_dev, ctrl);
186 }
187 
188 /*
189  * An NVM Express queue.  Each device has at least two (one for admin
190  * commands and one for I/O commands).
191  */
192 struct nvme_queue {
193 	struct nvme_dev *dev;
194 	spinlock_t sq_lock;
195 	void *sq_cmds;
196 	 /* only used for poll queues: */
197 	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
198 	struct nvme_completion *cqes;
199 	dma_addr_t sq_dma_addr;
200 	dma_addr_t cq_dma_addr;
201 	u32 __iomem *q_db;
202 	u32 q_depth;
203 	u16 cq_vector;
204 	u16 sq_tail;
205 	u16 last_sq_tail;
206 	u16 cq_head;
207 	u16 qid;
208 	u8 cq_phase;
209 	u8 sqes;
210 	unsigned long flags;
211 #define NVMEQ_ENABLED		0
212 #define NVMEQ_SQ_CMB		1
213 #define NVMEQ_DELETE_ERROR	2
214 #define NVMEQ_POLLED		3
215 	__le32 *dbbuf_sq_db;
216 	__le32 *dbbuf_cq_db;
217 	__le32 *dbbuf_sq_ei;
218 	__le32 *dbbuf_cq_ei;
219 	struct completion delete_done;
220 };
221 
222 union nvme_descriptor {
223 	struct nvme_sgl_desc	*sg_list;
224 	__le64			*prp_list;
225 };
226 
227 /*
228  * The nvme_iod describes the data in an I/O.
229  *
230  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
231  * to the actual struct scatterlist.
232  */
233 struct nvme_iod {
234 	struct nvme_request req;
235 	struct nvme_command cmd;
236 	bool aborted;
237 	s8 nr_allocations;	/* PRP list pool allocations. 0 means small
238 				   pool in use */
239 	unsigned int dma_len;	/* length of single DMA segment mapping */
240 	dma_addr_t first_dma;
241 	dma_addr_t meta_dma;
242 	struct sg_table sgt;
243 	struct sg_table meta_sgt;
244 	union nvme_descriptor meta_list;
245 	union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
246 };
247 
nvme_dbbuf_size(struct nvme_dev * dev)248 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
249 {
250 	return dev->nr_allocated_queues * 8 * dev->db_stride;
251 }
252 
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)253 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
254 {
255 	unsigned int mem_size = nvme_dbbuf_size(dev);
256 
257 	if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
258 		return;
259 
260 	if (dev->dbbuf_dbs) {
261 		/*
262 		 * Clear the dbbuf memory so the driver doesn't observe stale
263 		 * values from the previous instantiation.
264 		 */
265 		memset(dev->dbbuf_dbs, 0, mem_size);
266 		memset(dev->dbbuf_eis, 0, mem_size);
267 		return;
268 	}
269 
270 	dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
271 					    &dev->dbbuf_dbs_dma_addr,
272 					    GFP_KERNEL);
273 	if (!dev->dbbuf_dbs)
274 		goto fail;
275 	dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
276 					    &dev->dbbuf_eis_dma_addr,
277 					    GFP_KERNEL);
278 	if (!dev->dbbuf_eis)
279 		goto fail_free_dbbuf_dbs;
280 	return;
281 
282 fail_free_dbbuf_dbs:
283 	dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
284 			  dev->dbbuf_dbs_dma_addr);
285 	dev->dbbuf_dbs = NULL;
286 fail:
287 	dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
288 }
289 
nvme_dbbuf_dma_free(struct nvme_dev * dev)290 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
291 {
292 	unsigned int mem_size = nvme_dbbuf_size(dev);
293 
294 	if (dev->dbbuf_dbs) {
295 		dma_free_coherent(dev->dev, mem_size,
296 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
297 		dev->dbbuf_dbs = NULL;
298 	}
299 	if (dev->dbbuf_eis) {
300 		dma_free_coherent(dev->dev, mem_size,
301 				  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
302 		dev->dbbuf_eis = NULL;
303 	}
304 }
305 
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)306 static void nvme_dbbuf_init(struct nvme_dev *dev,
307 			    struct nvme_queue *nvmeq, int qid)
308 {
309 	if (!dev->dbbuf_dbs || !qid)
310 		return;
311 
312 	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
313 	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
314 	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
315 	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
316 }
317 
nvme_dbbuf_free(struct nvme_queue * nvmeq)318 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
319 {
320 	if (!nvmeq->qid)
321 		return;
322 
323 	nvmeq->dbbuf_sq_db = NULL;
324 	nvmeq->dbbuf_cq_db = NULL;
325 	nvmeq->dbbuf_sq_ei = NULL;
326 	nvmeq->dbbuf_cq_ei = NULL;
327 }
328 
nvme_dbbuf_set(struct nvme_dev * dev)329 static void nvme_dbbuf_set(struct nvme_dev *dev)
330 {
331 	struct nvme_command c = { };
332 	unsigned int i;
333 
334 	if (!dev->dbbuf_dbs)
335 		return;
336 
337 	c.dbbuf.opcode = nvme_admin_dbbuf;
338 	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
339 	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
340 
341 	if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
342 		dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
343 		/* Free memory and continue on */
344 		nvme_dbbuf_dma_free(dev);
345 
346 		for (i = 1; i <= dev->online_queues; i++)
347 			nvme_dbbuf_free(&dev->queues[i]);
348 	}
349 }
350 
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)351 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
352 {
353 	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
354 }
355 
356 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,__le32 * dbbuf_db,volatile __le32 * dbbuf_ei)357 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
358 					      volatile __le32 *dbbuf_ei)
359 {
360 	if (dbbuf_db) {
361 		u16 old_value, event_idx;
362 
363 		/*
364 		 * Ensure that the queue is written before updating
365 		 * the doorbell in memory
366 		 */
367 		wmb();
368 
369 		old_value = le32_to_cpu(*dbbuf_db);
370 		*dbbuf_db = cpu_to_le32(value);
371 
372 		/*
373 		 * Ensure that the doorbell is updated before reading the event
374 		 * index from memory.  The controller needs to provide similar
375 		 * ordering to ensure the event index is updated before reading
376 		 * the doorbell.
377 		 */
378 		mb();
379 
380 		event_idx = le32_to_cpu(*dbbuf_ei);
381 		if (!nvme_dbbuf_need_event(event_idx, value, old_value))
382 			return false;
383 	}
384 
385 	return true;
386 }
387 
388 /*
389  * Will slightly overestimate the number of pages needed.  This is OK
390  * as it only leads to a small amount of wasted memory for the lifetime of
391  * the I/O.
392  */
nvme_pci_npages_prp(void)393 static __always_inline int nvme_pci_npages_prp(void)
394 {
395 	unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
396 	unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
397 	return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
398 }
399 
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)400 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
401 				unsigned int hctx_idx)
402 {
403 	struct nvme_dev *dev = to_nvme_dev(data);
404 	struct nvme_queue *nvmeq = &dev->queues[0];
405 
406 	WARN_ON(hctx_idx != 0);
407 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
408 
409 	hctx->driver_data = nvmeq;
410 	return 0;
411 }
412 
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)413 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
414 			  unsigned int hctx_idx)
415 {
416 	struct nvme_dev *dev = to_nvme_dev(data);
417 	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
418 
419 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
420 	hctx->driver_data = nvmeq;
421 	return 0;
422 }
423 
nvme_pci_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)424 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
425 		struct request *req, unsigned int hctx_idx,
426 		unsigned int numa_node)
427 {
428 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
429 
430 	nvme_req(req)->ctrl = set->driver_data;
431 	nvme_req(req)->cmd = &iod->cmd;
432 	return 0;
433 }
434 
queue_irq_offset(struct nvme_dev * dev)435 static int queue_irq_offset(struct nvme_dev *dev)
436 {
437 	/* if we have more than 1 vec, admin queue offsets us by 1 */
438 	if (dev->num_vecs > 1)
439 		return 1;
440 
441 	return 0;
442 }
443 
nvme_pci_map_queues(struct blk_mq_tag_set * set)444 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
445 {
446 	struct nvme_dev *dev = to_nvme_dev(set->driver_data);
447 	int i, qoff, offset;
448 
449 	offset = queue_irq_offset(dev);
450 	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 		struct blk_mq_queue_map *map = &set->map[i];
452 
453 		map->nr_queues = dev->io_queues[i];
454 		if (!map->nr_queues) {
455 			BUG_ON(i == HCTX_TYPE_DEFAULT);
456 			continue;
457 		}
458 
459 		/*
460 		 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 		 * affinity), so use the regular blk-mq cpu mapping
462 		 */
463 		map->queue_offset = qoff;
464 		if (i != HCTX_TYPE_POLL && offset)
465 			blk_mq_map_hw_queues(map, dev->dev, offset);
466 		else
467 			blk_mq_map_queues(map);
468 		qoff += map->nr_queues;
469 		offset += map->nr_queues;
470 	}
471 }
472 
473 /*
474  * Write sq tail if we are asked to, or if the next command would wrap.
475  */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)476 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
477 {
478 	if (!write_sq) {
479 		u16 next_tail = nvmeq->sq_tail + 1;
480 
481 		if (next_tail == nvmeq->q_depth)
482 			next_tail = 0;
483 		if (next_tail != nvmeq->last_sq_tail)
484 			return;
485 	}
486 
487 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
488 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
489 		writel(nvmeq->sq_tail, nvmeq->q_db);
490 	nvmeq->last_sq_tail = nvmeq->sq_tail;
491 }
492 
nvme_sq_copy_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd)493 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
494 				    struct nvme_command *cmd)
495 {
496 	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
497 		absolute_pointer(cmd), sizeof(*cmd));
498 	if (++nvmeq->sq_tail == nvmeq->q_depth)
499 		nvmeq->sq_tail = 0;
500 }
501 
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)502 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
503 {
504 	struct nvme_queue *nvmeq = hctx->driver_data;
505 
506 	spin_lock(&nvmeq->sq_lock);
507 	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
508 		nvme_write_sq_db(nvmeq, true);
509 	spin_unlock(&nvmeq->sq_lock);
510 }
511 
nvme_pci_metadata_use_sgls(struct nvme_dev * dev,struct request * req)512 static inline bool nvme_pci_metadata_use_sgls(struct nvme_dev *dev,
513 					      struct request *req)
514 {
515 	if (!nvme_ctrl_meta_sgl_supported(&dev->ctrl))
516 		return false;
517 	return req->nr_integrity_segments > 1 ||
518 		nvme_req(req)->flags & NVME_REQ_USERCMD;
519 }
520 
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req,int nseg)521 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
522 				     int nseg)
523 {
524 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
525 	unsigned int avg_seg_size;
526 
527 	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
528 
529 	if (!nvme_ctrl_sgl_supported(&dev->ctrl))
530 		return false;
531 	if (!nvmeq->qid)
532 		return false;
533 	if (nvme_pci_metadata_use_sgls(dev, req))
534 		return true;
535 	if (!sgl_threshold || avg_seg_size < sgl_threshold)
536 		return nvme_req(req)->flags & NVME_REQ_USERCMD;
537 	return true;
538 }
539 
nvme_free_prps(struct nvme_dev * dev,struct request * req)540 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
541 {
542 	const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
543 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
544 	dma_addr_t dma_addr = iod->first_dma;
545 	int i;
546 
547 	for (i = 0; i < iod->nr_allocations; i++) {
548 		__le64 *prp_list = iod->list[i].prp_list;
549 		dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
550 
551 		dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
552 		dma_addr = next_dma_addr;
553 	}
554 }
555 
nvme_unmap_data(struct nvme_dev * dev,struct request * req)556 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
557 {
558 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
559 
560 	if (iod->dma_len) {
561 		dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
562 			       rq_dma_dir(req));
563 		return;
564 	}
565 
566 	WARN_ON_ONCE(!iod->sgt.nents);
567 
568 	dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
569 
570 	if (iod->nr_allocations == 0)
571 		dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
572 			      iod->first_dma);
573 	else if (iod->nr_allocations == 1)
574 		dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
575 			      iod->first_dma);
576 	else
577 		nvme_free_prps(dev, req);
578 	mempool_free(iod->sgt.sgl, dev->iod_mempool);
579 }
580 
nvme_print_sgl(struct scatterlist * sgl,int nents)581 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
582 {
583 	int i;
584 	struct scatterlist *sg;
585 
586 	for_each_sg(sgl, sg, nents, i) {
587 		dma_addr_t phys = sg_phys(sg);
588 		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
589 			"dma_address:%pad dma_length:%d\n",
590 			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
591 			sg_dma_len(sg));
592 	}
593 }
594 
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)595 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
596 		struct request *req, struct nvme_rw_command *cmnd)
597 {
598 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
599 	struct dma_pool *pool;
600 	int length = blk_rq_payload_bytes(req);
601 	struct scatterlist *sg = iod->sgt.sgl;
602 	int dma_len = sg_dma_len(sg);
603 	u64 dma_addr = sg_dma_address(sg);
604 	int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
605 	__le64 *prp_list;
606 	dma_addr_t prp_dma;
607 	int nprps, i;
608 
609 	length -= (NVME_CTRL_PAGE_SIZE - offset);
610 	if (length <= 0) {
611 		iod->first_dma = 0;
612 		goto done;
613 	}
614 
615 	dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
616 	if (dma_len) {
617 		dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
618 	} else {
619 		sg = sg_next(sg);
620 		dma_addr = sg_dma_address(sg);
621 		dma_len = sg_dma_len(sg);
622 	}
623 
624 	if (length <= NVME_CTRL_PAGE_SIZE) {
625 		iod->first_dma = dma_addr;
626 		goto done;
627 	}
628 
629 	nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
630 	if (nprps <= (256 / 8)) {
631 		pool = dev->prp_small_pool;
632 		iod->nr_allocations = 0;
633 	} else {
634 		pool = dev->prp_page_pool;
635 		iod->nr_allocations = 1;
636 	}
637 
638 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
639 	if (!prp_list) {
640 		iod->nr_allocations = -1;
641 		return BLK_STS_RESOURCE;
642 	}
643 	iod->list[0].prp_list = prp_list;
644 	iod->first_dma = prp_dma;
645 	i = 0;
646 	for (;;) {
647 		if (i == NVME_CTRL_PAGE_SIZE >> 3) {
648 			__le64 *old_prp_list = prp_list;
649 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
650 			if (!prp_list)
651 				goto free_prps;
652 			iod->list[iod->nr_allocations++].prp_list = prp_list;
653 			prp_list[0] = old_prp_list[i - 1];
654 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
655 			i = 1;
656 		}
657 		prp_list[i++] = cpu_to_le64(dma_addr);
658 		dma_len -= NVME_CTRL_PAGE_SIZE;
659 		dma_addr += NVME_CTRL_PAGE_SIZE;
660 		length -= NVME_CTRL_PAGE_SIZE;
661 		if (length <= 0)
662 			break;
663 		if (dma_len > 0)
664 			continue;
665 		if (unlikely(dma_len < 0))
666 			goto bad_sgl;
667 		sg = sg_next(sg);
668 		dma_addr = sg_dma_address(sg);
669 		dma_len = sg_dma_len(sg);
670 	}
671 done:
672 	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
673 	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
674 	return BLK_STS_OK;
675 free_prps:
676 	nvme_free_prps(dev, req);
677 	return BLK_STS_RESOURCE;
678 bad_sgl:
679 	WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
680 			"Invalid SGL for payload:%d nents:%d\n",
681 			blk_rq_payload_bytes(req), iod->sgt.nents);
682 	return BLK_STS_IOERR;
683 }
684 
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)685 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
686 		struct scatterlist *sg)
687 {
688 	sge->addr = cpu_to_le64(sg_dma_address(sg));
689 	sge->length = cpu_to_le32(sg_dma_len(sg));
690 	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
691 }
692 
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)693 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
694 		dma_addr_t dma_addr, int entries)
695 {
696 	sge->addr = cpu_to_le64(dma_addr);
697 	sge->length = cpu_to_le32(entries * sizeof(*sge));
698 	sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
699 }
700 
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd)701 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
702 		struct request *req, struct nvme_rw_command *cmd)
703 {
704 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
705 	struct dma_pool *pool;
706 	struct nvme_sgl_desc *sg_list;
707 	struct scatterlist *sg = iod->sgt.sgl;
708 	unsigned int entries = iod->sgt.nents;
709 	dma_addr_t sgl_dma;
710 	int i = 0;
711 
712 	/* setting the transfer type as SGL */
713 	cmd->flags = NVME_CMD_SGL_METABUF;
714 
715 	if (entries == 1) {
716 		nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
717 		return BLK_STS_OK;
718 	}
719 
720 	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
721 		pool = dev->prp_small_pool;
722 		iod->nr_allocations = 0;
723 	} else {
724 		pool = dev->prp_page_pool;
725 		iod->nr_allocations = 1;
726 	}
727 
728 	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
729 	if (!sg_list) {
730 		iod->nr_allocations = -1;
731 		return BLK_STS_RESOURCE;
732 	}
733 
734 	iod->list[0].sg_list = sg_list;
735 	iod->first_dma = sgl_dma;
736 
737 	nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
738 	do {
739 		nvme_pci_sgl_set_data(&sg_list[i++], sg);
740 		sg = sg_next(sg);
741 	} while (--entries > 0);
742 
743 	return BLK_STS_OK;
744 }
745 
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)746 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
747 		struct request *req, struct nvme_rw_command *cmnd,
748 		struct bio_vec *bv)
749 {
750 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
751 	unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
752 	unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
753 
754 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
755 	if (dma_mapping_error(dev->dev, iod->first_dma))
756 		return BLK_STS_RESOURCE;
757 	iod->dma_len = bv->bv_len;
758 
759 	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
760 	if (bv->bv_len > first_prp_len)
761 		cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
762 	else
763 		cmnd->dptr.prp2 = 0;
764 	return BLK_STS_OK;
765 }
766 
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)767 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
768 		struct request *req, struct nvme_rw_command *cmnd,
769 		struct bio_vec *bv)
770 {
771 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
772 
773 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
774 	if (dma_mapping_error(dev->dev, iod->first_dma))
775 		return BLK_STS_RESOURCE;
776 	iod->dma_len = bv->bv_len;
777 
778 	cmnd->flags = NVME_CMD_SGL_METABUF;
779 	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
780 	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
781 	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
782 	return BLK_STS_OK;
783 }
784 
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)785 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
786 		struct nvme_command *cmnd)
787 {
788 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
789 	blk_status_t ret = BLK_STS_RESOURCE;
790 	int rc;
791 
792 	if (blk_rq_nr_phys_segments(req) == 1) {
793 		struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
794 		struct bio_vec bv = req_bvec(req);
795 
796 		if (!is_pci_p2pdma_page(bv.bv_page)) {
797 			if (!nvme_pci_metadata_use_sgls(dev, req) &&
798 			    (bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) +
799 			     bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
800 				return nvme_setup_prp_simple(dev, req,
801 							     &cmnd->rw, &bv);
802 
803 			if (nvmeq->qid && sgl_threshold &&
804 			    nvme_ctrl_sgl_supported(&dev->ctrl))
805 				return nvme_setup_sgl_simple(dev, req,
806 							     &cmnd->rw, &bv);
807 		}
808 	}
809 
810 	iod->dma_len = 0;
811 	iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
812 	if (!iod->sgt.sgl)
813 		return BLK_STS_RESOURCE;
814 	sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
815 	iod->sgt.orig_nents = blk_rq_map_sg(req, iod->sgt.sgl);
816 	if (!iod->sgt.orig_nents)
817 		goto out_free_sg;
818 
819 	rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
820 			     DMA_ATTR_NO_WARN);
821 	if (rc) {
822 		if (rc == -EREMOTEIO)
823 			ret = BLK_STS_TARGET;
824 		goto out_free_sg;
825 	}
826 
827 	if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
828 		ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
829 	else
830 		ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
831 	if (ret != BLK_STS_OK)
832 		goto out_unmap_sg;
833 	return BLK_STS_OK;
834 
835 out_unmap_sg:
836 	dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
837 out_free_sg:
838 	mempool_free(iod->sgt.sgl, dev->iod_mempool);
839 	return ret;
840 }
841 
nvme_pci_setup_meta_sgls(struct nvme_dev * dev,struct request * req)842 static blk_status_t nvme_pci_setup_meta_sgls(struct nvme_dev *dev,
843 					     struct request *req)
844 {
845 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
846 	struct nvme_rw_command *cmnd = &iod->cmd.rw;
847 	struct nvme_sgl_desc *sg_list;
848 	struct scatterlist *sgl, *sg;
849 	unsigned int entries;
850 	dma_addr_t sgl_dma;
851 	int rc, i;
852 
853 	iod->meta_sgt.sgl = mempool_alloc(dev->iod_meta_mempool, GFP_ATOMIC);
854 	if (!iod->meta_sgt.sgl)
855 		return BLK_STS_RESOURCE;
856 
857 	sg_init_table(iod->meta_sgt.sgl, req->nr_integrity_segments);
858 	iod->meta_sgt.orig_nents = blk_rq_map_integrity_sg(req,
859 							   iod->meta_sgt.sgl);
860 	if (!iod->meta_sgt.orig_nents)
861 		goto out_free_sg;
862 
863 	rc = dma_map_sgtable(dev->dev, &iod->meta_sgt, rq_dma_dir(req),
864 			     DMA_ATTR_NO_WARN);
865 	if (rc)
866 		goto out_free_sg;
867 
868 	sg_list = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC, &sgl_dma);
869 	if (!sg_list)
870 		goto out_unmap_sg;
871 
872 	entries = iod->meta_sgt.nents;
873 	iod->meta_list.sg_list = sg_list;
874 	iod->meta_dma = sgl_dma;
875 
876 	cmnd->flags = NVME_CMD_SGL_METASEG;
877 	cmnd->metadata = cpu_to_le64(sgl_dma);
878 
879 	sgl = iod->meta_sgt.sgl;
880 	if (entries == 1) {
881 		nvme_pci_sgl_set_data(sg_list, sgl);
882 		return BLK_STS_OK;
883 	}
884 
885 	sgl_dma += sizeof(*sg_list);
886 	nvme_pci_sgl_set_seg(sg_list, sgl_dma, entries);
887 	for_each_sg(sgl, sg, entries, i)
888 		nvme_pci_sgl_set_data(&sg_list[i + 1], sg);
889 
890 	return BLK_STS_OK;
891 
892 out_unmap_sg:
893 	dma_unmap_sgtable(dev->dev, &iod->meta_sgt, rq_dma_dir(req), 0);
894 out_free_sg:
895 	mempool_free(iod->meta_sgt.sgl, dev->iod_meta_mempool);
896 	return BLK_STS_RESOURCE;
897 }
898 
nvme_pci_setup_meta_mptr(struct nvme_dev * dev,struct request * req)899 static blk_status_t nvme_pci_setup_meta_mptr(struct nvme_dev *dev,
900 					     struct request *req)
901 {
902 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
903 	struct bio_vec bv = rq_integrity_vec(req);
904 	struct nvme_command *cmnd = &iod->cmd;
905 
906 	iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0);
907 	if (dma_mapping_error(dev->dev, iod->meta_dma))
908 		return BLK_STS_IOERR;
909 	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
910 	return BLK_STS_OK;
911 }
912 
nvme_map_metadata(struct nvme_dev * dev,struct request * req)913 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req)
914 {
915 	if (nvme_pci_metadata_use_sgls(dev, req))
916 		return nvme_pci_setup_meta_sgls(dev, req);
917 	return nvme_pci_setup_meta_mptr(dev, req);
918 }
919 
nvme_prep_rq(struct nvme_dev * dev,struct request * req)920 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
921 {
922 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
923 	blk_status_t ret;
924 
925 	iod->aborted = false;
926 	iod->nr_allocations = -1;
927 	iod->sgt.nents = 0;
928 	iod->meta_sgt.nents = 0;
929 
930 	ret = nvme_setup_cmd(req->q->queuedata, req);
931 	if (ret)
932 		return ret;
933 
934 	if (blk_rq_nr_phys_segments(req)) {
935 		ret = nvme_map_data(dev, req, &iod->cmd);
936 		if (ret)
937 			goto out_free_cmd;
938 	}
939 
940 	if (blk_integrity_rq(req)) {
941 		ret = nvme_map_metadata(dev, req);
942 		if (ret)
943 			goto out_unmap_data;
944 	}
945 
946 	nvme_start_request(req);
947 	return BLK_STS_OK;
948 out_unmap_data:
949 	if (blk_rq_nr_phys_segments(req))
950 		nvme_unmap_data(dev, req);
951 out_free_cmd:
952 	nvme_cleanup_cmd(req);
953 	return ret;
954 }
955 
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)956 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
957 			 const struct blk_mq_queue_data *bd)
958 {
959 	struct nvme_queue *nvmeq = hctx->driver_data;
960 	struct nvme_dev *dev = nvmeq->dev;
961 	struct request *req = bd->rq;
962 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
963 	blk_status_t ret;
964 
965 	/*
966 	 * We should not need to do this, but we're still using this to
967 	 * ensure we can drain requests on a dying queue.
968 	 */
969 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
970 		return BLK_STS_IOERR;
971 
972 	if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
973 		return nvme_fail_nonready_command(&dev->ctrl, req);
974 
975 	ret = nvme_prep_rq(dev, req);
976 	if (unlikely(ret))
977 		return ret;
978 	spin_lock(&nvmeq->sq_lock);
979 	nvme_sq_copy_cmd(nvmeq, &iod->cmd);
980 	nvme_write_sq_db(nvmeq, bd->last);
981 	spin_unlock(&nvmeq->sq_lock);
982 	return BLK_STS_OK;
983 }
984 
nvme_submit_cmds(struct nvme_queue * nvmeq,struct rq_list * rqlist)985 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct rq_list *rqlist)
986 {
987 	struct request *req;
988 
989 	if (rq_list_empty(rqlist))
990 		return;
991 
992 	spin_lock(&nvmeq->sq_lock);
993 	while ((req = rq_list_pop(rqlist))) {
994 		struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
995 
996 		nvme_sq_copy_cmd(nvmeq, &iod->cmd);
997 	}
998 	nvme_write_sq_db(nvmeq, true);
999 	spin_unlock(&nvmeq->sq_lock);
1000 }
1001 
nvme_prep_rq_batch(struct nvme_queue * nvmeq,struct request * req)1002 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
1003 {
1004 	/*
1005 	 * We should not need to do this, but we're still using this to
1006 	 * ensure we can drain requests on a dying queue.
1007 	 */
1008 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
1009 		return false;
1010 	if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
1011 		return false;
1012 
1013 	return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
1014 }
1015 
nvme_queue_rqs(struct rq_list * rqlist)1016 static void nvme_queue_rqs(struct rq_list *rqlist)
1017 {
1018 	struct rq_list submit_list = { };
1019 	struct rq_list requeue_list = { };
1020 	struct nvme_queue *nvmeq = NULL;
1021 	struct request *req;
1022 
1023 	while ((req = rq_list_pop(rqlist))) {
1024 		if (nvmeq && nvmeq != req->mq_hctx->driver_data)
1025 			nvme_submit_cmds(nvmeq, &submit_list);
1026 		nvmeq = req->mq_hctx->driver_data;
1027 
1028 		if (nvme_prep_rq_batch(nvmeq, req))
1029 			rq_list_add_tail(&submit_list, req);
1030 		else
1031 			rq_list_add_tail(&requeue_list, req);
1032 	}
1033 
1034 	if (nvmeq)
1035 		nvme_submit_cmds(nvmeq, &submit_list);
1036 	*rqlist = requeue_list;
1037 }
1038 
nvme_unmap_metadata(struct nvme_dev * dev,struct request * req)1039 static __always_inline void nvme_unmap_metadata(struct nvme_dev *dev,
1040 						struct request *req)
1041 {
1042 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1043 
1044 	if (!iod->meta_sgt.nents) {
1045 		dma_unmap_page(dev->dev, iod->meta_dma,
1046 			       rq_integrity_vec(req).bv_len,
1047 			       rq_dma_dir(req));
1048 		return;
1049 	}
1050 
1051 	dma_pool_free(dev->prp_small_pool, iod->meta_list.sg_list,
1052 		      iod->meta_dma);
1053 	dma_unmap_sgtable(dev->dev, &iod->meta_sgt, rq_dma_dir(req), 0);
1054 	mempool_free(iod->meta_sgt.sgl, dev->iod_meta_mempool);
1055 }
1056 
nvme_pci_unmap_rq(struct request * req)1057 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1058 {
1059 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1060 	struct nvme_dev *dev = nvmeq->dev;
1061 
1062 	if (blk_integrity_rq(req))
1063 		nvme_unmap_metadata(dev, req);
1064 
1065 	if (blk_rq_nr_phys_segments(req))
1066 		nvme_unmap_data(dev, req);
1067 }
1068 
nvme_pci_complete_rq(struct request * req)1069 static void nvme_pci_complete_rq(struct request *req)
1070 {
1071 	nvme_pci_unmap_rq(req);
1072 	nvme_complete_rq(req);
1073 }
1074 
nvme_pci_complete_batch(struct io_comp_batch * iob)1075 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1076 {
1077 	nvme_complete_batch(iob, nvme_pci_unmap_rq);
1078 }
1079 
1080 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)1081 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1082 {
1083 	struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1084 
1085 	return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1086 }
1087 
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)1088 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1089 {
1090 	u16 head = nvmeq->cq_head;
1091 
1092 	if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1093 					      nvmeq->dbbuf_cq_ei))
1094 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1095 }
1096 
nvme_queue_tagset(struct nvme_queue * nvmeq)1097 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1098 {
1099 	if (!nvmeq->qid)
1100 		return nvmeq->dev->admin_tagset.tags[0];
1101 	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1102 }
1103 
nvme_handle_cqe(struct nvme_queue * nvmeq,struct io_comp_batch * iob,u16 idx)1104 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1105 				   struct io_comp_batch *iob, u16 idx)
1106 {
1107 	struct nvme_completion *cqe = &nvmeq->cqes[idx];
1108 	__u16 command_id = READ_ONCE(cqe->command_id);
1109 	struct request *req;
1110 
1111 	/*
1112 	 * AEN requests are special as they don't time out and can
1113 	 * survive any kind of queue freeze and often don't respond to
1114 	 * aborts.  We don't even bother to allocate a struct request
1115 	 * for them but rather special case them here.
1116 	 */
1117 	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1118 		nvme_complete_async_event(&nvmeq->dev->ctrl,
1119 				cqe->status, &cqe->result);
1120 		return;
1121 	}
1122 
1123 	req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1124 	if (unlikely(!req)) {
1125 		dev_warn(nvmeq->dev->ctrl.device,
1126 			"invalid id %d completed on queue %d\n",
1127 			command_id, le16_to_cpu(cqe->sq_id));
1128 		return;
1129 	}
1130 
1131 	trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1132 	if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1133 	    !blk_mq_add_to_batch(req, iob,
1134 				 nvme_req(req)->status != NVME_SC_SUCCESS,
1135 				 nvme_pci_complete_batch))
1136 		nvme_pci_complete_rq(req);
1137 }
1138 
nvme_update_cq_head(struct nvme_queue * nvmeq)1139 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1140 {
1141 	u32 tmp = nvmeq->cq_head + 1;
1142 
1143 	if (tmp == nvmeq->q_depth) {
1144 		nvmeq->cq_head = 0;
1145 		nvmeq->cq_phase ^= 1;
1146 	} else {
1147 		nvmeq->cq_head = tmp;
1148 	}
1149 }
1150 
nvme_poll_cq(struct nvme_queue * nvmeq,struct io_comp_batch * iob)1151 static inline bool nvme_poll_cq(struct nvme_queue *nvmeq,
1152 			        struct io_comp_batch *iob)
1153 {
1154 	bool found = false;
1155 
1156 	while (nvme_cqe_pending(nvmeq)) {
1157 		found = true;
1158 		/*
1159 		 * load-load control dependency between phase and the rest of
1160 		 * the cqe requires a full read memory barrier
1161 		 */
1162 		dma_rmb();
1163 		nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1164 		nvme_update_cq_head(nvmeq);
1165 	}
1166 
1167 	if (found)
1168 		nvme_ring_cq_doorbell(nvmeq);
1169 	return found;
1170 }
1171 
nvme_irq(int irq,void * data)1172 static irqreturn_t nvme_irq(int irq, void *data)
1173 {
1174 	struct nvme_queue *nvmeq = data;
1175 	DEFINE_IO_COMP_BATCH(iob);
1176 
1177 	if (nvme_poll_cq(nvmeq, &iob)) {
1178 		if (!rq_list_empty(&iob.req_list))
1179 			nvme_pci_complete_batch(&iob);
1180 		return IRQ_HANDLED;
1181 	}
1182 	return IRQ_NONE;
1183 }
1184 
nvme_irq_check(int irq,void * data)1185 static irqreturn_t nvme_irq_check(int irq, void *data)
1186 {
1187 	struct nvme_queue *nvmeq = data;
1188 
1189 	if (nvme_cqe_pending(nvmeq))
1190 		return IRQ_WAKE_THREAD;
1191 	return IRQ_NONE;
1192 }
1193 
1194 /*
1195  * Poll for completions for any interrupt driven queue
1196  * Can be called from any context.
1197  */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1198 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1199 {
1200 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1201 
1202 	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1203 
1204 	disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1205 	spin_lock(&nvmeq->cq_poll_lock);
1206 	nvme_poll_cq(nvmeq, NULL);
1207 	spin_unlock(&nvmeq->cq_poll_lock);
1208 	enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1209 }
1210 
nvme_poll(struct blk_mq_hw_ctx * hctx,struct io_comp_batch * iob)1211 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1212 {
1213 	struct nvme_queue *nvmeq = hctx->driver_data;
1214 	bool found;
1215 
1216 	if (!nvme_cqe_pending(nvmeq))
1217 		return 0;
1218 
1219 	spin_lock(&nvmeq->cq_poll_lock);
1220 	found = nvme_poll_cq(nvmeq, iob);
1221 	spin_unlock(&nvmeq->cq_poll_lock);
1222 
1223 	return found;
1224 }
1225 
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1226 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1227 {
1228 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1229 	struct nvme_queue *nvmeq = &dev->queues[0];
1230 	struct nvme_command c = { };
1231 
1232 	c.common.opcode = nvme_admin_async_event;
1233 	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1234 
1235 	spin_lock(&nvmeq->sq_lock);
1236 	nvme_sq_copy_cmd(nvmeq, &c);
1237 	nvme_write_sq_db(nvmeq, true);
1238 	spin_unlock(&nvmeq->sq_lock);
1239 }
1240 
nvme_pci_subsystem_reset(struct nvme_ctrl * ctrl)1241 static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl)
1242 {
1243 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1244 	int ret = 0;
1245 
1246 	/*
1247 	 * Taking the shutdown_lock ensures the BAR mapping is not being
1248 	 * altered by reset_work. Holding this lock before the RESETTING state
1249 	 * change, if successful, also ensures nvme_remove won't be able to
1250 	 * proceed to iounmap until we're done.
1251 	 */
1252 	mutex_lock(&dev->shutdown_lock);
1253 	if (!dev->bar_mapped_size) {
1254 		ret = -ENODEV;
1255 		goto unlock;
1256 	}
1257 
1258 	if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
1259 		ret = -EBUSY;
1260 		goto unlock;
1261 	}
1262 
1263 	writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR);
1264 	nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE);
1265 
1266 	/*
1267 	 * Read controller status to flush the previous write and trigger a
1268 	 * pcie read error.
1269 	 */
1270 	readl(dev->bar + NVME_REG_CSTS);
1271 unlock:
1272 	mutex_unlock(&dev->shutdown_lock);
1273 	return ret;
1274 }
1275 
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1276 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1277 {
1278 	struct nvme_command c = { };
1279 
1280 	c.delete_queue.opcode = opcode;
1281 	c.delete_queue.qid = cpu_to_le16(id);
1282 
1283 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1284 }
1285 
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1286 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1287 		struct nvme_queue *nvmeq, s16 vector)
1288 {
1289 	struct nvme_command c = { };
1290 	int flags = NVME_QUEUE_PHYS_CONTIG;
1291 
1292 	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1293 		flags |= NVME_CQ_IRQ_ENABLED;
1294 
1295 	/*
1296 	 * Note: we (ab)use the fact that the prp fields survive if no data
1297 	 * is attached to the request.
1298 	 */
1299 	c.create_cq.opcode = nvme_admin_create_cq;
1300 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1301 	c.create_cq.cqid = cpu_to_le16(qid);
1302 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1303 	c.create_cq.cq_flags = cpu_to_le16(flags);
1304 	c.create_cq.irq_vector = cpu_to_le16(vector);
1305 
1306 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1307 }
1308 
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1309 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1310 						struct nvme_queue *nvmeq)
1311 {
1312 	struct nvme_ctrl *ctrl = &dev->ctrl;
1313 	struct nvme_command c = { };
1314 	int flags = NVME_QUEUE_PHYS_CONTIG;
1315 
1316 	/*
1317 	 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1318 	 * set. Since URGENT priority is zeroes, it makes all queues
1319 	 * URGENT.
1320 	 */
1321 	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1322 		flags |= NVME_SQ_PRIO_MEDIUM;
1323 
1324 	/*
1325 	 * Note: we (ab)use the fact that the prp fields survive if no data
1326 	 * is attached to the request.
1327 	 */
1328 	c.create_sq.opcode = nvme_admin_create_sq;
1329 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1330 	c.create_sq.sqid = cpu_to_le16(qid);
1331 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1332 	c.create_sq.sq_flags = cpu_to_le16(flags);
1333 	c.create_sq.cqid = cpu_to_le16(qid);
1334 
1335 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1336 }
1337 
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1338 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1339 {
1340 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1341 }
1342 
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1343 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1344 {
1345 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1346 }
1347 
abort_endio(struct request * req,blk_status_t error)1348 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1349 {
1350 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1351 
1352 	dev_warn(nvmeq->dev->ctrl.device,
1353 		 "Abort status: 0x%x", nvme_req(req)->status);
1354 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1355 	blk_mq_free_request(req);
1356 	return RQ_END_IO_NONE;
1357 }
1358 
nvme_should_reset(struct nvme_dev * dev,u32 csts)1359 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1360 {
1361 	/* If true, indicates loss of adapter communication, possibly by a
1362 	 * NVMe Subsystem reset.
1363 	 */
1364 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1365 
1366 	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1367 	switch (nvme_ctrl_state(&dev->ctrl)) {
1368 	case NVME_CTRL_RESETTING:
1369 	case NVME_CTRL_CONNECTING:
1370 		return false;
1371 	default:
1372 		break;
1373 	}
1374 
1375 	/* We shouldn't reset unless the controller is on fatal error state
1376 	 * _or_ if we lost the communication with it.
1377 	 */
1378 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1379 		return false;
1380 
1381 	return true;
1382 }
1383 
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1384 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1385 {
1386 	/* Read a config register to help see what died. */
1387 	u16 pci_status;
1388 	int result;
1389 
1390 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1391 				      &pci_status);
1392 	if (result == PCIBIOS_SUCCESSFUL)
1393 		dev_warn(dev->ctrl.device,
1394 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1395 			 csts, pci_status);
1396 	else
1397 		dev_warn(dev->ctrl.device,
1398 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1399 			 csts, result);
1400 
1401 	if (csts != ~0)
1402 		return;
1403 
1404 	dev_warn(dev->ctrl.device,
1405 		 "Does your device have a faulty power saving mode enabled?\n");
1406 	dev_warn(dev->ctrl.device,
1407 		 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n");
1408 }
1409 
nvme_timeout(struct request * req)1410 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1411 {
1412 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1413 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1414 	struct nvme_dev *dev = nvmeq->dev;
1415 	struct request *abort_req;
1416 	struct nvme_command cmd = { };
1417 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1418 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1419 	u8 opcode;
1420 
1421 	/*
1422 	 * Shutdown the device immediately if we see it is disconnected. This
1423 	 * unblocks PCIe error handling if the nvme driver is waiting in
1424 	 * error_resume for a device that has been removed. We can't unbind the
1425 	 * driver while the driver's error callback is waiting to complete, so
1426 	 * we're relying on a timeout to break that deadlock if a removal
1427 	 * occurs while reset work is running.
1428 	 */
1429 	if (pci_dev_is_disconnected(pdev))
1430 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1431 	if (nvme_state_terminal(&dev->ctrl))
1432 		goto disable;
1433 
1434 	/* If PCI error recovery process is happening, we cannot reset or
1435 	 * the recovery mechanism will surely fail.
1436 	 */
1437 	mb();
1438 	if (pci_channel_offline(pdev))
1439 		return BLK_EH_RESET_TIMER;
1440 
1441 	/*
1442 	 * Reset immediately if the controller is failed
1443 	 */
1444 	if (nvme_should_reset(dev, csts)) {
1445 		nvme_warn_reset(dev, csts);
1446 		goto disable;
1447 	}
1448 
1449 	/*
1450 	 * Did we miss an interrupt?
1451 	 */
1452 	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1453 		nvme_poll(req->mq_hctx, NULL);
1454 	else
1455 		nvme_poll_irqdisable(nvmeq);
1456 
1457 	if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1458 		dev_warn(dev->ctrl.device,
1459 			 "I/O tag %d (%04x) QID %d timeout, completion polled\n",
1460 			 req->tag, nvme_cid(req), nvmeq->qid);
1461 		return BLK_EH_DONE;
1462 	}
1463 
1464 	/*
1465 	 * Shutdown immediately if controller times out while starting. The
1466 	 * reset work will see the pci device disabled when it gets the forced
1467 	 * cancellation error. All outstanding requests are completed on
1468 	 * shutdown, so we return BLK_EH_DONE.
1469 	 */
1470 	switch (nvme_ctrl_state(&dev->ctrl)) {
1471 	case NVME_CTRL_CONNECTING:
1472 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1473 		fallthrough;
1474 	case NVME_CTRL_DELETING:
1475 		dev_warn_ratelimited(dev->ctrl.device,
1476 			 "I/O tag %d (%04x) QID %d timeout, disable controller\n",
1477 			 req->tag, nvme_cid(req), nvmeq->qid);
1478 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1479 		nvme_dev_disable(dev, true);
1480 		return BLK_EH_DONE;
1481 	case NVME_CTRL_RESETTING:
1482 		return BLK_EH_RESET_TIMER;
1483 	default:
1484 		break;
1485 	}
1486 
1487 	/*
1488 	 * Shutdown the controller immediately and schedule a reset if the
1489 	 * command was already aborted once before and still hasn't been
1490 	 * returned to the driver, or if this is the admin queue.
1491 	 */
1492 	opcode = nvme_req(req)->cmd->common.opcode;
1493 	if (!nvmeq->qid || iod->aborted) {
1494 		dev_warn(dev->ctrl.device,
1495 			 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1496 			 req->tag, nvme_cid(req), opcode,
1497 			 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
1498 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1499 		goto disable;
1500 	}
1501 
1502 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1503 		atomic_inc(&dev->ctrl.abort_limit);
1504 		return BLK_EH_RESET_TIMER;
1505 	}
1506 	iod->aborted = true;
1507 
1508 	cmd.abort.opcode = nvme_admin_abort_cmd;
1509 	cmd.abort.cid = nvme_cid(req);
1510 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1511 
1512 	dev_warn(nvmeq->dev->ctrl.device,
1513 		 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1514 		 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1515 		 nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1516 		 blk_rq_bytes(req));
1517 
1518 	abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1519 					 BLK_MQ_REQ_NOWAIT);
1520 	if (IS_ERR(abort_req)) {
1521 		atomic_inc(&dev->ctrl.abort_limit);
1522 		return BLK_EH_RESET_TIMER;
1523 	}
1524 	nvme_init_request(abort_req, &cmd);
1525 
1526 	abort_req->end_io = abort_endio;
1527 	abort_req->end_io_data = NULL;
1528 	blk_execute_rq_nowait(abort_req, false);
1529 
1530 	/*
1531 	 * The aborted req will be completed on receiving the abort req.
1532 	 * We enable the timer again. If hit twice, it'll cause a device reset,
1533 	 * as the device then is in a faulty state.
1534 	 */
1535 	return BLK_EH_RESET_TIMER;
1536 
1537 disable:
1538 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1539 		if (nvme_state_terminal(&dev->ctrl))
1540 			nvme_dev_disable(dev, true);
1541 		return BLK_EH_DONE;
1542 	}
1543 
1544 	nvme_dev_disable(dev, false);
1545 	if (nvme_try_sched_reset(&dev->ctrl))
1546 		nvme_unquiesce_io_queues(&dev->ctrl);
1547 	return BLK_EH_DONE;
1548 }
1549 
nvme_free_queue(struct nvme_queue * nvmeq)1550 static void nvme_free_queue(struct nvme_queue *nvmeq)
1551 {
1552 	dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1553 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1554 	if (!nvmeq->sq_cmds)
1555 		return;
1556 
1557 	if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1558 		pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1559 				nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1560 	} else {
1561 		dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1562 				nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1563 	}
1564 }
1565 
nvme_free_queues(struct nvme_dev * dev,int lowest)1566 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1567 {
1568 	int i;
1569 
1570 	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1571 		dev->ctrl.queue_count--;
1572 		nvme_free_queue(&dev->queues[i]);
1573 	}
1574 }
1575 
nvme_suspend_queue(struct nvme_dev * dev,unsigned int qid)1576 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1577 {
1578 	struct nvme_queue *nvmeq = &dev->queues[qid];
1579 
1580 	if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1581 		return;
1582 
1583 	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1584 	mb();
1585 
1586 	nvmeq->dev->online_queues--;
1587 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1588 		nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1589 	if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1590 		pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1591 }
1592 
nvme_suspend_io_queues(struct nvme_dev * dev)1593 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1594 {
1595 	int i;
1596 
1597 	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1598 		nvme_suspend_queue(dev, i);
1599 }
1600 
1601 /*
1602  * Called only on a device that has been disabled and after all other threads
1603  * that can check this device's completion queues have synced, except
1604  * nvme_poll(). This is the last chance for the driver to see a natural
1605  * completion before nvme_cancel_request() terminates all incomplete requests.
1606  */
nvme_reap_pending_cqes(struct nvme_dev * dev)1607 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1608 {
1609 	int i;
1610 
1611 	for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1612 		spin_lock(&dev->queues[i].cq_poll_lock);
1613 		nvme_poll_cq(&dev->queues[i], NULL);
1614 		spin_unlock(&dev->queues[i].cq_poll_lock);
1615 	}
1616 }
1617 
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1618 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1619 				int entry_size)
1620 {
1621 	int q_depth = dev->q_depth;
1622 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1623 					  NVME_CTRL_PAGE_SIZE);
1624 
1625 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1626 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1627 
1628 		mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1629 		q_depth = div_u64(mem_per_q, entry_size);
1630 
1631 		/*
1632 		 * Ensure the reduced q_depth is above some threshold where it
1633 		 * would be better to map queues in system memory with the
1634 		 * original depth
1635 		 */
1636 		if (q_depth < 64)
1637 			return -ENOMEM;
1638 	}
1639 
1640 	return q_depth;
1641 }
1642 
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1643 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1644 				int qid)
1645 {
1646 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1647 
1648 	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1649 		nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1650 		if (nvmeq->sq_cmds) {
1651 			nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1652 							nvmeq->sq_cmds);
1653 			if (nvmeq->sq_dma_addr) {
1654 				set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1655 				return 0;
1656 			}
1657 
1658 			pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1659 		}
1660 	}
1661 
1662 	nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1663 				&nvmeq->sq_dma_addr, GFP_KERNEL);
1664 	if (!nvmeq->sq_cmds)
1665 		return -ENOMEM;
1666 	return 0;
1667 }
1668 
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1669 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1670 {
1671 	struct nvme_queue *nvmeq = &dev->queues[qid];
1672 
1673 	if (dev->ctrl.queue_count > qid)
1674 		return 0;
1675 
1676 	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1677 	nvmeq->q_depth = depth;
1678 	nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1679 					 &nvmeq->cq_dma_addr, GFP_KERNEL);
1680 	if (!nvmeq->cqes)
1681 		goto free_nvmeq;
1682 
1683 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1684 		goto free_cqdma;
1685 
1686 	nvmeq->dev = dev;
1687 	spin_lock_init(&nvmeq->sq_lock);
1688 	spin_lock_init(&nvmeq->cq_poll_lock);
1689 	nvmeq->cq_head = 0;
1690 	nvmeq->cq_phase = 1;
1691 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1692 	nvmeq->qid = qid;
1693 	dev->ctrl.queue_count++;
1694 
1695 	return 0;
1696 
1697  free_cqdma:
1698 	dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1699 			  nvmeq->cq_dma_addr);
1700  free_nvmeq:
1701 	return -ENOMEM;
1702 }
1703 
queue_request_irq(struct nvme_queue * nvmeq)1704 static int queue_request_irq(struct nvme_queue *nvmeq)
1705 {
1706 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1707 	int nr = nvmeq->dev->ctrl.instance;
1708 
1709 	if (use_threaded_interrupts) {
1710 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1711 				nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1712 	} else {
1713 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1714 				NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1715 	}
1716 }
1717 
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1718 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1719 {
1720 	struct nvme_dev *dev = nvmeq->dev;
1721 
1722 	nvmeq->sq_tail = 0;
1723 	nvmeq->last_sq_tail = 0;
1724 	nvmeq->cq_head = 0;
1725 	nvmeq->cq_phase = 1;
1726 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1727 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1728 	nvme_dbbuf_init(dev, nvmeq, qid);
1729 	dev->online_queues++;
1730 	wmb(); /* ensure the first interrupt sees the initialization */
1731 }
1732 
1733 /*
1734  * Try getting shutdown_lock while setting up IO queues.
1735  */
nvme_setup_io_queues_trylock(struct nvme_dev * dev)1736 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1737 {
1738 	/*
1739 	 * Give up if the lock is being held by nvme_dev_disable.
1740 	 */
1741 	if (!mutex_trylock(&dev->shutdown_lock))
1742 		return -ENODEV;
1743 
1744 	/*
1745 	 * Controller is in wrong state, fail early.
1746 	 */
1747 	if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
1748 		mutex_unlock(&dev->shutdown_lock);
1749 		return -ENODEV;
1750 	}
1751 
1752 	return 0;
1753 }
1754 
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1755 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1756 {
1757 	struct nvme_dev *dev = nvmeq->dev;
1758 	int result;
1759 	u16 vector = 0;
1760 
1761 	clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1762 
1763 	/*
1764 	 * A queue's vector matches the queue identifier unless the controller
1765 	 * has only one vector available.
1766 	 */
1767 	if (!polled)
1768 		vector = dev->num_vecs == 1 ? 0 : qid;
1769 	else
1770 		set_bit(NVMEQ_POLLED, &nvmeq->flags);
1771 
1772 	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1773 	if (result)
1774 		return result;
1775 
1776 	result = adapter_alloc_sq(dev, qid, nvmeq);
1777 	if (result < 0)
1778 		return result;
1779 	if (result)
1780 		goto release_cq;
1781 
1782 	nvmeq->cq_vector = vector;
1783 
1784 	result = nvme_setup_io_queues_trylock(dev);
1785 	if (result)
1786 		return result;
1787 	nvme_init_queue(nvmeq, qid);
1788 	if (!polled) {
1789 		result = queue_request_irq(nvmeq);
1790 		if (result < 0)
1791 			goto release_sq;
1792 	}
1793 
1794 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1795 	mutex_unlock(&dev->shutdown_lock);
1796 	return result;
1797 
1798 release_sq:
1799 	dev->online_queues--;
1800 	mutex_unlock(&dev->shutdown_lock);
1801 	adapter_delete_sq(dev, qid);
1802 release_cq:
1803 	adapter_delete_cq(dev, qid);
1804 	return result;
1805 }
1806 
1807 static const struct blk_mq_ops nvme_mq_admin_ops = {
1808 	.queue_rq	= nvme_queue_rq,
1809 	.complete	= nvme_pci_complete_rq,
1810 	.init_hctx	= nvme_admin_init_hctx,
1811 	.init_request	= nvme_pci_init_request,
1812 	.timeout	= nvme_timeout,
1813 };
1814 
1815 static const struct blk_mq_ops nvme_mq_ops = {
1816 	.queue_rq	= nvme_queue_rq,
1817 	.queue_rqs	= nvme_queue_rqs,
1818 	.complete	= nvme_pci_complete_rq,
1819 	.commit_rqs	= nvme_commit_rqs,
1820 	.init_hctx	= nvme_init_hctx,
1821 	.init_request	= nvme_pci_init_request,
1822 	.map_queues	= nvme_pci_map_queues,
1823 	.timeout	= nvme_timeout,
1824 	.poll		= nvme_poll,
1825 };
1826 
nvme_dev_remove_admin(struct nvme_dev * dev)1827 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1828 {
1829 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1830 		/*
1831 		 * If the controller was reset during removal, it's possible
1832 		 * user requests may be waiting on a stopped queue. Start the
1833 		 * queue to flush these to completion.
1834 		 */
1835 		nvme_unquiesce_admin_queue(&dev->ctrl);
1836 		nvme_remove_admin_tag_set(&dev->ctrl);
1837 	}
1838 }
1839 
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1840 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1841 {
1842 	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1843 }
1844 
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1845 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1846 {
1847 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1848 
1849 	if (size <= dev->bar_mapped_size)
1850 		return 0;
1851 	if (size > pci_resource_len(pdev, 0))
1852 		return -ENOMEM;
1853 	if (dev->bar)
1854 		iounmap(dev->bar);
1855 	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1856 	if (!dev->bar) {
1857 		dev->bar_mapped_size = 0;
1858 		return -ENOMEM;
1859 	}
1860 	dev->bar_mapped_size = size;
1861 	dev->dbs = dev->bar + NVME_REG_DBS;
1862 
1863 	return 0;
1864 }
1865 
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1866 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1867 {
1868 	int result;
1869 	u32 aqa;
1870 	struct nvme_queue *nvmeq;
1871 
1872 	result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1873 	if (result < 0)
1874 		return result;
1875 
1876 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1877 				NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1878 
1879 	if (dev->subsystem &&
1880 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1881 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1882 
1883 	/*
1884 	 * If the device has been passed off to us in an enabled state, just
1885 	 * clear the enabled bit.  The spec says we should set the 'shutdown
1886 	 * notification bits', but doing so may cause the device to complete
1887 	 * commands to the admin queue ... and we don't know what memory that
1888 	 * might be pointing at!
1889 	 */
1890 	result = nvme_disable_ctrl(&dev->ctrl, false);
1891 	if (result < 0)
1892 		return result;
1893 
1894 	result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1895 	if (result)
1896 		return result;
1897 
1898 	dev->ctrl.numa_node = dev_to_node(dev->dev);
1899 
1900 	nvmeq = &dev->queues[0];
1901 	aqa = nvmeq->q_depth - 1;
1902 	aqa |= aqa << 16;
1903 
1904 	writel(aqa, dev->bar + NVME_REG_AQA);
1905 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1906 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1907 
1908 	result = nvme_enable_ctrl(&dev->ctrl);
1909 	if (result)
1910 		return result;
1911 
1912 	nvmeq->cq_vector = 0;
1913 	nvme_init_queue(nvmeq, 0);
1914 	result = queue_request_irq(nvmeq);
1915 	if (result) {
1916 		dev->online_queues--;
1917 		return result;
1918 	}
1919 
1920 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1921 	return result;
1922 }
1923 
nvme_create_io_queues(struct nvme_dev * dev)1924 static int nvme_create_io_queues(struct nvme_dev *dev)
1925 {
1926 	unsigned i, max, rw_queues;
1927 	int ret = 0;
1928 
1929 	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1930 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1931 			ret = -ENOMEM;
1932 			break;
1933 		}
1934 	}
1935 
1936 	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1937 	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1938 		rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1939 				dev->io_queues[HCTX_TYPE_READ];
1940 	} else {
1941 		rw_queues = max;
1942 	}
1943 
1944 	for (i = dev->online_queues; i <= max; i++) {
1945 		bool polled = i > rw_queues;
1946 
1947 		ret = nvme_create_queue(&dev->queues[i], i, polled);
1948 		if (ret)
1949 			break;
1950 	}
1951 
1952 	/*
1953 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1954 	 * than the desired amount of queues, and even a controller without
1955 	 * I/O queues can still be used to issue admin commands.  This might
1956 	 * be useful to upgrade a buggy firmware for example.
1957 	 */
1958 	return ret >= 0 ? 0 : ret;
1959 }
1960 
nvme_cmb_size_unit(struct nvme_dev * dev)1961 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1962 {
1963 	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1964 
1965 	return 1ULL << (12 + 4 * szu);
1966 }
1967 
nvme_cmb_size(struct nvme_dev * dev)1968 static u32 nvme_cmb_size(struct nvme_dev *dev)
1969 {
1970 	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1971 }
1972 
nvme_map_cmb(struct nvme_dev * dev)1973 static void nvme_map_cmb(struct nvme_dev *dev)
1974 {
1975 	u64 size, offset;
1976 	resource_size_t bar_size;
1977 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1978 	int bar;
1979 
1980 	if (dev->cmb_size)
1981 		return;
1982 
1983 	if (NVME_CAP_CMBS(dev->ctrl.cap))
1984 		writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1985 
1986 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1987 	if (!dev->cmbsz)
1988 		return;
1989 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1990 
1991 	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1992 	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1993 	bar = NVME_CMB_BIR(dev->cmbloc);
1994 	bar_size = pci_resource_len(pdev, bar);
1995 
1996 	if (offset > bar_size)
1997 		return;
1998 
1999 	/*
2000 	 * Controllers may support a CMB size larger than their BAR, for
2001 	 * example, due to being behind a bridge. Reduce the CMB to the
2002 	 * reported size of the BAR
2003 	 */
2004 	size = min(size, bar_size - offset);
2005 
2006 	if (!IS_ALIGNED(size, memremap_compat_align()) ||
2007 	    !IS_ALIGNED(pci_resource_start(pdev, bar),
2008 			memremap_compat_align()))
2009 		return;
2010 
2011 	/*
2012 	 * Tell the controller about the host side address mapping the CMB,
2013 	 * and enable CMB decoding for the NVMe 1.4+ scheme:
2014 	 */
2015 	if (NVME_CAP_CMBS(dev->ctrl.cap)) {
2016 		hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
2017 			     (pci_bus_address(pdev, bar) + offset),
2018 			     dev->bar + NVME_REG_CMBMSC);
2019 	}
2020 
2021 	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
2022 		dev_warn(dev->ctrl.device,
2023 			 "failed to register the CMB\n");
2024 		hi_lo_writeq(0, dev->bar + NVME_REG_CMBMSC);
2025 		return;
2026 	}
2027 
2028 	dev->cmb_size = size;
2029 	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
2030 
2031 	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
2032 			(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
2033 		pci_p2pmem_publish(pdev, true);
2034 
2035 	nvme_update_attrs(dev);
2036 }
2037 
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)2038 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
2039 {
2040 	u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
2041 	u64 dma_addr = dev->host_mem_descs_dma;
2042 	struct nvme_command c = { };
2043 	int ret;
2044 
2045 	c.features.opcode	= nvme_admin_set_features;
2046 	c.features.fid		= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
2047 	c.features.dword11	= cpu_to_le32(bits);
2048 	c.features.dword12	= cpu_to_le32(host_mem_size);
2049 	c.features.dword13	= cpu_to_le32(lower_32_bits(dma_addr));
2050 	c.features.dword14	= cpu_to_le32(upper_32_bits(dma_addr));
2051 	c.features.dword15	= cpu_to_le32(dev->nr_host_mem_descs);
2052 
2053 	ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
2054 	if (ret) {
2055 		dev_warn(dev->ctrl.device,
2056 			 "failed to set host mem (err %d, flags %#x).\n",
2057 			 ret, bits);
2058 	} else
2059 		dev->hmb = bits & NVME_HOST_MEM_ENABLE;
2060 
2061 	return ret;
2062 }
2063 
nvme_free_host_mem_multi(struct nvme_dev * dev)2064 static void nvme_free_host_mem_multi(struct nvme_dev *dev)
2065 {
2066 	int i;
2067 
2068 	for (i = 0; i < dev->nr_host_mem_descs; i++) {
2069 		struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2070 		size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2071 
2072 		dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2073 			       le64_to_cpu(desc->addr),
2074 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2075 	}
2076 
2077 	kfree(dev->host_mem_desc_bufs);
2078 	dev->host_mem_desc_bufs = NULL;
2079 }
2080 
nvme_free_host_mem(struct nvme_dev * dev)2081 static void nvme_free_host_mem(struct nvme_dev *dev)
2082 {
2083 	if (dev->hmb_sgt)
2084 		dma_free_noncontiguous(dev->dev, dev->host_mem_size,
2085 				dev->hmb_sgt, DMA_BIDIRECTIONAL);
2086 	else
2087 		nvme_free_host_mem_multi(dev);
2088 
2089 	dma_free_coherent(dev->dev, dev->host_mem_descs_size,
2090 			dev->host_mem_descs, dev->host_mem_descs_dma);
2091 	dev->host_mem_descs = NULL;
2092 	dev->host_mem_descs_size = 0;
2093 	dev->nr_host_mem_descs = 0;
2094 }
2095 
nvme_alloc_host_mem_single(struct nvme_dev * dev,u64 size)2096 static int nvme_alloc_host_mem_single(struct nvme_dev *dev, u64 size)
2097 {
2098 	dev->hmb_sgt = dma_alloc_noncontiguous(dev->dev, size,
2099 				DMA_BIDIRECTIONAL, GFP_KERNEL, 0);
2100 	if (!dev->hmb_sgt)
2101 		return -ENOMEM;
2102 
2103 	dev->host_mem_descs = dma_alloc_coherent(dev->dev,
2104 			sizeof(*dev->host_mem_descs), &dev->host_mem_descs_dma,
2105 			GFP_KERNEL);
2106 	if (!dev->host_mem_descs) {
2107 		dma_free_noncontiguous(dev->dev, size, dev->hmb_sgt,
2108 				DMA_BIDIRECTIONAL);
2109 		dev->hmb_sgt = NULL;
2110 		return -ENOMEM;
2111 	}
2112 	dev->host_mem_size = size;
2113 	dev->host_mem_descs_size = sizeof(*dev->host_mem_descs);
2114 	dev->nr_host_mem_descs = 1;
2115 
2116 	dev->host_mem_descs[0].addr =
2117 		cpu_to_le64(dev->hmb_sgt->sgl->dma_address);
2118 	dev->host_mem_descs[0].size = cpu_to_le32(size / NVME_CTRL_PAGE_SIZE);
2119 	return 0;
2120 }
2121 
nvme_alloc_host_mem_multi(struct nvme_dev * dev,u64 preferred,u32 chunk_size)2122 static int nvme_alloc_host_mem_multi(struct nvme_dev *dev, u64 preferred,
2123 		u32 chunk_size)
2124 {
2125 	struct nvme_host_mem_buf_desc *descs;
2126 	u32 max_entries, len, descs_size;
2127 	dma_addr_t descs_dma;
2128 	int i = 0;
2129 	void **bufs;
2130 	u64 size, tmp;
2131 
2132 	tmp = (preferred + chunk_size - 1);
2133 	do_div(tmp, chunk_size);
2134 	max_entries = tmp;
2135 
2136 	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2137 		max_entries = dev->ctrl.hmmaxd;
2138 
2139 	descs_size = max_entries * sizeof(*descs);
2140 	descs = dma_alloc_coherent(dev->dev, descs_size, &descs_dma,
2141 			GFP_KERNEL);
2142 	if (!descs)
2143 		goto out;
2144 
2145 	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2146 	if (!bufs)
2147 		goto out_free_descs;
2148 
2149 	for (size = 0; size < preferred && i < max_entries; size += len) {
2150 		dma_addr_t dma_addr;
2151 
2152 		len = min_t(u64, chunk_size, preferred - size);
2153 		bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2154 				DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2155 		if (!bufs[i])
2156 			break;
2157 
2158 		descs[i].addr = cpu_to_le64(dma_addr);
2159 		descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2160 		i++;
2161 	}
2162 
2163 	if (!size)
2164 		goto out_free_bufs;
2165 
2166 	dev->nr_host_mem_descs = i;
2167 	dev->host_mem_size = size;
2168 	dev->host_mem_descs = descs;
2169 	dev->host_mem_descs_dma = descs_dma;
2170 	dev->host_mem_descs_size = descs_size;
2171 	dev->host_mem_desc_bufs = bufs;
2172 	return 0;
2173 
2174 out_free_bufs:
2175 	kfree(bufs);
2176 out_free_descs:
2177 	dma_free_coherent(dev->dev, descs_size, descs, descs_dma);
2178 out:
2179 	dev->host_mem_descs = NULL;
2180 	return -ENOMEM;
2181 }
2182 
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2183 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2184 {
2185 	unsigned long dma_merge_boundary = dma_get_merge_boundary(dev->dev);
2186 	u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2187 	u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2188 	u64 chunk_size;
2189 
2190 	/*
2191 	 * If there is an IOMMU that can merge pages, try a virtually
2192 	 * non-contiguous allocation for a single segment first.
2193 	 */
2194 	if (dma_merge_boundary && (PAGE_SIZE & dma_merge_boundary) == 0) {
2195 		if (!nvme_alloc_host_mem_single(dev, preferred))
2196 			return 0;
2197 	}
2198 
2199 	/* start big and work our way down */
2200 	for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2201 		if (!nvme_alloc_host_mem_multi(dev, preferred, chunk_size)) {
2202 			if (!min || dev->host_mem_size >= min)
2203 				return 0;
2204 			nvme_free_host_mem(dev);
2205 		}
2206 	}
2207 
2208 	return -ENOMEM;
2209 }
2210 
nvme_setup_host_mem(struct nvme_dev * dev)2211 static int nvme_setup_host_mem(struct nvme_dev *dev)
2212 {
2213 	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2214 	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2215 	u64 min = (u64)dev->ctrl.hmmin * 4096;
2216 	u32 enable_bits = NVME_HOST_MEM_ENABLE;
2217 	int ret;
2218 
2219 	if (!dev->ctrl.hmpre)
2220 		return 0;
2221 
2222 	preferred = min(preferred, max);
2223 	if (min > max) {
2224 		dev_warn(dev->ctrl.device,
2225 			"min host memory (%lld MiB) above limit (%d MiB).\n",
2226 			min >> ilog2(SZ_1M), max_host_mem_size_mb);
2227 		nvme_free_host_mem(dev);
2228 		return 0;
2229 	}
2230 
2231 	/*
2232 	 * If we already have a buffer allocated check if we can reuse it.
2233 	 */
2234 	if (dev->host_mem_descs) {
2235 		if (dev->host_mem_size >= min)
2236 			enable_bits |= NVME_HOST_MEM_RETURN;
2237 		else
2238 			nvme_free_host_mem(dev);
2239 	}
2240 
2241 	if (!dev->host_mem_descs) {
2242 		if (nvme_alloc_host_mem(dev, min, preferred)) {
2243 			dev_warn(dev->ctrl.device,
2244 				"failed to allocate host memory buffer.\n");
2245 			return 0; /* controller must work without HMB */
2246 		}
2247 
2248 		dev_info(dev->ctrl.device,
2249 			"allocated %lld MiB host memory buffer (%u segment%s).\n",
2250 			dev->host_mem_size >> ilog2(SZ_1M),
2251 			dev->nr_host_mem_descs,
2252 			str_plural(dev->nr_host_mem_descs));
2253 	}
2254 
2255 	ret = nvme_set_host_mem(dev, enable_bits);
2256 	if (ret)
2257 		nvme_free_host_mem(dev);
2258 	return ret;
2259 }
2260 
cmb_show(struct device * dev,struct device_attribute * attr,char * buf)2261 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2262 		char *buf)
2263 {
2264 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2265 
2266 	return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2267 		       ndev->cmbloc, ndev->cmbsz);
2268 }
2269 static DEVICE_ATTR_RO(cmb);
2270 
cmbloc_show(struct device * dev,struct device_attribute * attr,char * buf)2271 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2272 		char *buf)
2273 {
2274 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2275 
2276 	return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2277 }
2278 static DEVICE_ATTR_RO(cmbloc);
2279 
cmbsz_show(struct device * dev,struct device_attribute * attr,char * buf)2280 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2281 		char *buf)
2282 {
2283 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2284 
2285 	return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2286 }
2287 static DEVICE_ATTR_RO(cmbsz);
2288 
hmb_show(struct device * dev,struct device_attribute * attr,char * buf)2289 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2290 			char *buf)
2291 {
2292 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2293 
2294 	return sysfs_emit(buf, "%d\n", ndev->hmb);
2295 }
2296 
hmb_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2297 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2298 			 const char *buf, size_t count)
2299 {
2300 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2301 	bool new;
2302 	int ret;
2303 
2304 	if (kstrtobool(buf, &new) < 0)
2305 		return -EINVAL;
2306 
2307 	if (new == ndev->hmb)
2308 		return count;
2309 
2310 	if (new) {
2311 		ret = nvme_setup_host_mem(ndev);
2312 	} else {
2313 		ret = nvme_set_host_mem(ndev, 0);
2314 		if (!ret)
2315 			nvme_free_host_mem(ndev);
2316 	}
2317 
2318 	if (ret < 0)
2319 		return ret;
2320 
2321 	return count;
2322 }
2323 static DEVICE_ATTR_RW(hmb);
2324 
nvme_pci_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)2325 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2326 		struct attribute *a, int n)
2327 {
2328 	struct nvme_ctrl *ctrl =
2329 		dev_get_drvdata(container_of(kobj, struct device, kobj));
2330 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2331 
2332 	if (a == &dev_attr_cmb.attr ||
2333 	    a == &dev_attr_cmbloc.attr ||
2334 	    a == &dev_attr_cmbsz.attr) {
2335 	    	if (!dev->cmbsz)
2336 			return 0;
2337 	}
2338 	if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2339 		return 0;
2340 
2341 	return a->mode;
2342 }
2343 
2344 static struct attribute *nvme_pci_attrs[] = {
2345 	&dev_attr_cmb.attr,
2346 	&dev_attr_cmbloc.attr,
2347 	&dev_attr_cmbsz.attr,
2348 	&dev_attr_hmb.attr,
2349 	NULL,
2350 };
2351 
2352 static const struct attribute_group nvme_pci_dev_attrs_group = {
2353 	.attrs		= nvme_pci_attrs,
2354 	.is_visible	= nvme_pci_attrs_are_visible,
2355 };
2356 
2357 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2358 	&nvme_dev_attrs_group,
2359 	&nvme_pci_dev_attrs_group,
2360 	NULL,
2361 };
2362 
nvme_update_attrs(struct nvme_dev * dev)2363 static void nvme_update_attrs(struct nvme_dev *dev)
2364 {
2365 	sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2366 }
2367 
2368 /*
2369  * nirqs is the number of interrupts available for write and read
2370  * queues. The core already reserved an interrupt for the admin queue.
2371  */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2372 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2373 {
2374 	struct nvme_dev *dev = affd->priv;
2375 	unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2376 
2377 	/*
2378 	 * If there is no interrupt available for queues, ensure that
2379 	 * the default queue is set to 1. The affinity set size is
2380 	 * also set to one, but the irq core ignores it for this case.
2381 	 *
2382 	 * If only one interrupt is available or 'write_queue' == 0, combine
2383 	 * write and read queues.
2384 	 *
2385 	 * If 'write_queues' > 0, ensure it leaves room for at least one read
2386 	 * queue.
2387 	 */
2388 	if (!nrirqs) {
2389 		nrirqs = 1;
2390 		nr_read_queues = 0;
2391 	} else if (nrirqs == 1 || !nr_write_queues) {
2392 		nr_read_queues = 0;
2393 	} else if (nr_write_queues >= nrirqs) {
2394 		nr_read_queues = 1;
2395 	} else {
2396 		nr_read_queues = nrirqs - nr_write_queues;
2397 	}
2398 
2399 	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2400 	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2401 	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2402 	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2403 	affd->nr_sets = nr_read_queues ? 2 : 1;
2404 }
2405 
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2406 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2407 {
2408 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2409 	struct irq_affinity affd = {
2410 		.pre_vectors	= 1,
2411 		.calc_sets	= nvme_calc_irq_sets,
2412 		.priv		= dev,
2413 	};
2414 	unsigned int irq_queues, poll_queues;
2415 	unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2416 
2417 	/*
2418 	 * Poll queues don't need interrupts, but we need at least one I/O queue
2419 	 * left over for non-polled I/O.
2420 	 */
2421 	poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2422 	dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2423 
2424 	/*
2425 	 * Initialize for the single interrupt case, will be updated in
2426 	 * nvme_calc_irq_sets().
2427 	 */
2428 	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2429 	dev->io_queues[HCTX_TYPE_READ] = 0;
2430 
2431 	/*
2432 	 * We need interrupts for the admin queue and each non-polled I/O queue,
2433 	 * but some Apple controllers require all queues to use the first
2434 	 * vector.
2435 	 */
2436 	irq_queues = 1;
2437 	if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2438 		irq_queues += (nr_io_queues - poll_queues);
2439 	if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2440 		flags &= ~PCI_IRQ_MSI;
2441 	return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2442 					      &affd);
2443 }
2444 
nvme_max_io_queues(struct nvme_dev * dev)2445 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2446 {
2447 	/*
2448 	 * If tags are shared with admin queue (Apple bug), then
2449 	 * make sure we only use one IO queue.
2450 	 */
2451 	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2452 		return 1;
2453 	return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2454 }
2455 
nvme_setup_io_queues(struct nvme_dev * dev)2456 static int nvme_setup_io_queues(struct nvme_dev *dev)
2457 {
2458 	struct nvme_queue *adminq = &dev->queues[0];
2459 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2460 	unsigned int nr_io_queues;
2461 	unsigned long size;
2462 	int result;
2463 
2464 	/*
2465 	 * Sample the module parameters once at reset time so that we have
2466 	 * stable values to work with.
2467 	 */
2468 	dev->nr_write_queues = write_queues;
2469 	dev->nr_poll_queues = poll_queues;
2470 
2471 	nr_io_queues = dev->nr_allocated_queues - 1;
2472 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2473 	if (result < 0)
2474 		return result;
2475 
2476 	if (nr_io_queues == 0)
2477 		return 0;
2478 
2479 	/*
2480 	 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2481 	 * from set to unset. If there is a window to it is truely freed,
2482 	 * pci_free_irq_vectors() jumping into this window will crash.
2483 	 * And take lock to avoid racing with pci_free_irq_vectors() in
2484 	 * nvme_dev_disable() path.
2485 	 */
2486 	result = nvme_setup_io_queues_trylock(dev);
2487 	if (result)
2488 		return result;
2489 	if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2490 		pci_free_irq(pdev, 0, adminq);
2491 
2492 	if (dev->cmb_use_sqes) {
2493 		result = nvme_cmb_qdepth(dev, nr_io_queues,
2494 				sizeof(struct nvme_command));
2495 		if (result > 0) {
2496 			dev->q_depth = result;
2497 			dev->ctrl.sqsize = result - 1;
2498 		} else {
2499 			dev->cmb_use_sqes = false;
2500 		}
2501 	}
2502 
2503 	do {
2504 		size = db_bar_size(dev, nr_io_queues);
2505 		result = nvme_remap_bar(dev, size);
2506 		if (!result)
2507 			break;
2508 		if (!--nr_io_queues) {
2509 			result = -ENOMEM;
2510 			goto out_unlock;
2511 		}
2512 	} while (1);
2513 	adminq->q_db = dev->dbs;
2514 
2515  retry:
2516 	/* Deregister the admin queue's interrupt */
2517 	if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2518 		pci_free_irq(pdev, 0, adminq);
2519 
2520 	/*
2521 	 * If we enable msix early due to not intx, disable it again before
2522 	 * setting up the full range we need.
2523 	 */
2524 	pci_free_irq_vectors(pdev);
2525 
2526 	result = nvme_setup_irqs(dev, nr_io_queues);
2527 	if (result <= 0) {
2528 		result = -EIO;
2529 		goto out_unlock;
2530 	}
2531 
2532 	dev->num_vecs = result;
2533 	result = max(result - 1, 1);
2534 	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2535 
2536 	/*
2537 	 * Should investigate if there's a performance win from allocating
2538 	 * more queues than interrupt vectors; it might allow the submission
2539 	 * path to scale better, even if the receive path is limited by the
2540 	 * number of interrupts.
2541 	 */
2542 	result = queue_request_irq(adminq);
2543 	if (result)
2544 		goto out_unlock;
2545 	set_bit(NVMEQ_ENABLED, &adminq->flags);
2546 	mutex_unlock(&dev->shutdown_lock);
2547 
2548 	result = nvme_create_io_queues(dev);
2549 	if (result || dev->online_queues < 2)
2550 		return result;
2551 
2552 	if (dev->online_queues - 1 < dev->max_qid) {
2553 		nr_io_queues = dev->online_queues - 1;
2554 		nvme_delete_io_queues(dev);
2555 		result = nvme_setup_io_queues_trylock(dev);
2556 		if (result)
2557 			return result;
2558 		nvme_suspend_io_queues(dev);
2559 		goto retry;
2560 	}
2561 	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2562 					dev->io_queues[HCTX_TYPE_DEFAULT],
2563 					dev->io_queues[HCTX_TYPE_READ],
2564 					dev->io_queues[HCTX_TYPE_POLL]);
2565 	return 0;
2566 out_unlock:
2567 	mutex_unlock(&dev->shutdown_lock);
2568 	return result;
2569 }
2570 
nvme_del_queue_end(struct request * req,blk_status_t error)2571 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2572 					     blk_status_t error)
2573 {
2574 	struct nvme_queue *nvmeq = req->end_io_data;
2575 
2576 	blk_mq_free_request(req);
2577 	complete(&nvmeq->delete_done);
2578 	return RQ_END_IO_NONE;
2579 }
2580 
nvme_del_cq_end(struct request * req,blk_status_t error)2581 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2582 					  blk_status_t error)
2583 {
2584 	struct nvme_queue *nvmeq = req->end_io_data;
2585 
2586 	if (error)
2587 		set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2588 
2589 	return nvme_del_queue_end(req, error);
2590 }
2591 
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2592 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2593 {
2594 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2595 	struct request *req;
2596 	struct nvme_command cmd = { };
2597 
2598 	cmd.delete_queue.opcode = opcode;
2599 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2600 
2601 	req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2602 	if (IS_ERR(req))
2603 		return PTR_ERR(req);
2604 	nvme_init_request(req, &cmd);
2605 
2606 	if (opcode == nvme_admin_delete_cq)
2607 		req->end_io = nvme_del_cq_end;
2608 	else
2609 		req->end_io = nvme_del_queue_end;
2610 	req->end_io_data = nvmeq;
2611 
2612 	init_completion(&nvmeq->delete_done);
2613 	blk_execute_rq_nowait(req, false);
2614 	return 0;
2615 }
2616 
__nvme_delete_io_queues(struct nvme_dev * dev,u8 opcode)2617 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2618 {
2619 	int nr_queues = dev->online_queues - 1, sent = 0;
2620 	unsigned long timeout;
2621 
2622  retry:
2623 	timeout = NVME_ADMIN_TIMEOUT;
2624 	while (nr_queues > 0) {
2625 		if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2626 			break;
2627 		nr_queues--;
2628 		sent++;
2629 	}
2630 	while (sent) {
2631 		struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2632 
2633 		timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2634 				timeout);
2635 		if (timeout == 0)
2636 			return false;
2637 
2638 		sent--;
2639 		if (nr_queues)
2640 			goto retry;
2641 	}
2642 	return true;
2643 }
2644 
nvme_delete_io_queues(struct nvme_dev * dev)2645 static void nvme_delete_io_queues(struct nvme_dev *dev)
2646 {
2647 	if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2648 		__nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2649 }
2650 
nvme_pci_nr_maps(struct nvme_dev * dev)2651 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2652 {
2653 	if (dev->io_queues[HCTX_TYPE_POLL])
2654 		return 3;
2655 	if (dev->io_queues[HCTX_TYPE_READ])
2656 		return 2;
2657 	return 1;
2658 }
2659 
nvme_pci_update_nr_queues(struct nvme_dev * dev)2660 static bool nvme_pci_update_nr_queues(struct nvme_dev *dev)
2661 {
2662 	if (!dev->ctrl.tagset) {
2663 		nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
2664 				nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
2665 		return true;
2666 	}
2667 
2668 	/* Give up if we are racing with nvme_dev_disable() */
2669 	if (!mutex_trylock(&dev->shutdown_lock))
2670 		return false;
2671 
2672 	/* Check if nvme_dev_disable() has been executed already */
2673 	if (!dev->online_queues) {
2674 		mutex_unlock(&dev->shutdown_lock);
2675 		return false;
2676 	}
2677 
2678 	blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2679 	/* free previously allocated queues that are no longer usable */
2680 	nvme_free_queues(dev, dev->online_queues);
2681 	mutex_unlock(&dev->shutdown_lock);
2682 	return true;
2683 }
2684 
nvme_pci_enable(struct nvme_dev * dev)2685 static int nvme_pci_enable(struct nvme_dev *dev)
2686 {
2687 	int result = -ENOMEM;
2688 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2689 	unsigned int flags = PCI_IRQ_ALL_TYPES;
2690 
2691 	if (pci_enable_device_mem(pdev))
2692 		return result;
2693 
2694 	pci_set_master(pdev);
2695 
2696 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2697 		result = -ENODEV;
2698 		goto disable;
2699 	}
2700 
2701 	/*
2702 	 * Some devices and/or platforms don't advertise or work with INTx
2703 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2704 	 * adjust this later.
2705 	 */
2706 	if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2707 		flags &= ~PCI_IRQ_MSI;
2708 	result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
2709 	if (result < 0)
2710 		goto disable;
2711 
2712 	dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2713 
2714 	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2715 				io_queue_depth);
2716 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2717 	dev->dbs = dev->bar + 4096;
2718 
2719 	/*
2720 	 * Some Apple controllers require a non-standard SQE size.
2721 	 * Interestingly they also seem to ignore the CC:IOSQES register
2722 	 * so we don't bother updating it here.
2723 	 */
2724 	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2725 		dev->io_sqes = 7;
2726 	else
2727 		dev->io_sqes = NVME_NVM_IOSQES;
2728 
2729 	if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) {
2730 		dev->q_depth = 2;
2731 	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2732 		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2733 		   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2734 		dev->q_depth = 64;
2735 		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2736                         "set queue depth=%u\n", dev->q_depth);
2737 	}
2738 
2739 	/*
2740 	 * Controllers with the shared tags quirk need the IO queue to be
2741 	 * big enough so that we get 32 tags for the admin queue
2742 	 */
2743 	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2744 	    (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2745 		dev->q_depth = NVME_AQ_DEPTH + 2;
2746 		dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2747 			 dev->q_depth);
2748 	}
2749 	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2750 
2751 	nvme_map_cmb(dev);
2752 
2753 	pci_save_state(pdev);
2754 
2755 	result = nvme_pci_configure_admin_queue(dev);
2756 	if (result)
2757 		goto free_irq;
2758 	return result;
2759 
2760  free_irq:
2761 	pci_free_irq_vectors(pdev);
2762  disable:
2763 	pci_disable_device(pdev);
2764 	return result;
2765 }
2766 
nvme_dev_unmap(struct nvme_dev * dev)2767 static void nvme_dev_unmap(struct nvme_dev *dev)
2768 {
2769 	if (dev->bar)
2770 		iounmap(dev->bar);
2771 	pci_release_mem_regions(to_pci_dev(dev->dev));
2772 }
2773 
nvme_pci_ctrl_is_dead(struct nvme_dev * dev)2774 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2775 {
2776 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2777 	u32 csts;
2778 
2779 	if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2780 		return true;
2781 	if (pdev->error_state != pci_channel_io_normal)
2782 		return true;
2783 
2784 	csts = readl(dev->bar + NVME_REG_CSTS);
2785 	return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2786 }
2787 
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2788 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2789 {
2790 	enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
2791 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2792 	bool dead;
2793 
2794 	mutex_lock(&dev->shutdown_lock);
2795 	dead = nvme_pci_ctrl_is_dead(dev);
2796 	if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2797 		if (pci_is_enabled(pdev))
2798 			nvme_start_freeze(&dev->ctrl);
2799 		/*
2800 		 * Give the controller a chance to complete all entered requests
2801 		 * if doing a safe shutdown.
2802 		 */
2803 		if (!dead && shutdown)
2804 			nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2805 	}
2806 
2807 	nvme_quiesce_io_queues(&dev->ctrl);
2808 
2809 	if (!dead && dev->ctrl.queue_count > 0) {
2810 		nvme_delete_io_queues(dev);
2811 		nvme_disable_ctrl(&dev->ctrl, shutdown);
2812 		nvme_poll_irqdisable(&dev->queues[0]);
2813 	}
2814 	nvme_suspend_io_queues(dev);
2815 	nvme_suspend_queue(dev, 0);
2816 	pci_free_irq_vectors(pdev);
2817 	if (pci_is_enabled(pdev))
2818 		pci_disable_device(pdev);
2819 	nvme_reap_pending_cqes(dev);
2820 
2821 	nvme_cancel_tagset(&dev->ctrl);
2822 	nvme_cancel_admin_tagset(&dev->ctrl);
2823 
2824 	/*
2825 	 * The driver will not be starting up queues again if shutting down so
2826 	 * must flush all entered requests to their failed completion to avoid
2827 	 * deadlocking blk-mq hot-cpu notifier.
2828 	 */
2829 	if (shutdown) {
2830 		nvme_unquiesce_io_queues(&dev->ctrl);
2831 		if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2832 			nvme_unquiesce_admin_queue(&dev->ctrl);
2833 	}
2834 	mutex_unlock(&dev->shutdown_lock);
2835 }
2836 
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2837 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2838 {
2839 	if (!nvme_wait_reset(&dev->ctrl))
2840 		return -EBUSY;
2841 	nvme_dev_disable(dev, shutdown);
2842 	return 0;
2843 }
2844 
nvme_setup_prp_pools(struct nvme_dev * dev)2845 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2846 {
2847 	size_t small_align = 256;
2848 
2849 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2850 						NVME_CTRL_PAGE_SIZE,
2851 						NVME_CTRL_PAGE_SIZE, 0);
2852 	if (!dev->prp_page_pool)
2853 		return -ENOMEM;
2854 
2855 	if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512)
2856 		small_align = 512;
2857 
2858 	/* Optimisation for I/Os between 4k and 128k */
2859 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2860 						256, small_align, 0);
2861 	if (!dev->prp_small_pool) {
2862 		dma_pool_destroy(dev->prp_page_pool);
2863 		return -ENOMEM;
2864 	}
2865 	return 0;
2866 }
2867 
nvme_release_prp_pools(struct nvme_dev * dev)2868 static void nvme_release_prp_pools(struct nvme_dev *dev)
2869 {
2870 	dma_pool_destroy(dev->prp_page_pool);
2871 	dma_pool_destroy(dev->prp_small_pool);
2872 }
2873 
nvme_pci_alloc_iod_mempool(struct nvme_dev * dev)2874 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2875 {
2876 	size_t meta_size = sizeof(struct scatterlist) * (NVME_MAX_META_SEGS + 1);
2877 	size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2878 
2879 	dev->iod_mempool = mempool_create_node(1,
2880 			mempool_kmalloc, mempool_kfree,
2881 			(void *)alloc_size, GFP_KERNEL,
2882 			dev_to_node(dev->dev));
2883 	if (!dev->iod_mempool)
2884 		return -ENOMEM;
2885 
2886 	dev->iod_meta_mempool = mempool_create_node(1,
2887 			mempool_kmalloc, mempool_kfree,
2888 			(void *)meta_size, GFP_KERNEL,
2889 			dev_to_node(dev->dev));
2890 	if (!dev->iod_meta_mempool)
2891 		goto free;
2892 
2893 	return 0;
2894 free:
2895 	mempool_destroy(dev->iod_mempool);
2896 	return -ENOMEM;
2897 }
2898 
nvme_free_tagset(struct nvme_dev * dev)2899 static void nvme_free_tagset(struct nvme_dev *dev)
2900 {
2901 	if (dev->tagset.tags)
2902 		nvme_remove_io_tag_set(&dev->ctrl);
2903 	dev->ctrl.tagset = NULL;
2904 }
2905 
2906 /* pairs with nvme_pci_alloc_dev */
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2907 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2908 {
2909 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2910 
2911 	nvme_free_tagset(dev);
2912 	put_device(dev->dev);
2913 	kfree(dev->queues);
2914 	kfree(dev);
2915 }
2916 
nvme_reset_work(struct work_struct * work)2917 static void nvme_reset_work(struct work_struct *work)
2918 {
2919 	struct nvme_dev *dev =
2920 		container_of(work, struct nvme_dev, ctrl.reset_work);
2921 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2922 	int result;
2923 
2924 	if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
2925 		dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2926 			 dev->ctrl.state);
2927 		result = -ENODEV;
2928 		goto out;
2929 	}
2930 
2931 	/*
2932 	 * If we're called to reset a live controller first shut it down before
2933 	 * moving on.
2934 	 */
2935 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2936 		nvme_dev_disable(dev, false);
2937 	nvme_sync_queues(&dev->ctrl);
2938 
2939 	mutex_lock(&dev->shutdown_lock);
2940 	result = nvme_pci_enable(dev);
2941 	if (result)
2942 		goto out_unlock;
2943 	nvme_unquiesce_admin_queue(&dev->ctrl);
2944 	mutex_unlock(&dev->shutdown_lock);
2945 
2946 	/*
2947 	 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2948 	 * initializing procedure here.
2949 	 */
2950 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2951 		dev_warn(dev->ctrl.device,
2952 			"failed to mark controller CONNECTING\n");
2953 		result = -EBUSY;
2954 		goto out;
2955 	}
2956 
2957 	result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2958 	if (result)
2959 		goto out;
2960 
2961 	if (nvme_ctrl_meta_sgl_supported(&dev->ctrl))
2962 		dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
2963 	else
2964 		dev->ctrl.max_integrity_segments = 1;
2965 
2966 	nvme_dbbuf_dma_alloc(dev);
2967 
2968 	result = nvme_setup_host_mem(dev);
2969 	if (result < 0)
2970 		goto out;
2971 
2972 	result = nvme_setup_io_queues(dev);
2973 	if (result)
2974 		goto out;
2975 
2976 	/*
2977 	 * Freeze and update the number of I/O queues as thos might have
2978 	 * changed.  If there are no I/O queues left after this reset, keep the
2979 	 * controller around but remove all namespaces.
2980 	 */
2981 	if (dev->online_queues > 1) {
2982 		nvme_dbbuf_set(dev);
2983 		nvme_unquiesce_io_queues(&dev->ctrl);
2984 		nvme_wait_freeze(&dev->ctrl);
2985 		if (!nvme_pci_update_nr_queues(dev))
2986 			goto out;
2987 		nvme_unfreeze(&dev->ctrl);
2988 	} else {
2989 		dev_warn(dev->ctrl.device, "IO queues lost\n");
2990 		nvme_mark_namespaces_dead(&dev->ctrl);
2991 		nvme_unquiesce_io_queues(&dev->ctrl);
2992 		nvme_remove_namespaces(&dev->ctrl);
2993 		nvme_free_tagset(dev);
2994 	}
2995 
2996 	/*
2997 	 * If only admin queue live, keep it to do further investigation or
2998 	 * recovery.
2999 	 */
3000 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3001 		dev_warn(dev->ctrl.device,
3002 			"failed to mark controller live state\n");
3003 		result = -ENODEV;
3004 		goto out;
3005 	}
3006 
3007 	nvme_start_ctrl(&dev->ctrl);
3008 	return;
3009 
3010  out_unlock:
3011 	mutex_unlock(&dev->shutdown_lock);
3012  out:
3013 	/*
3014 	 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
3015 	 * may be holding this pci_dev's device lock.
3016 	 */
3017 	dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
3018 		 result);
3019 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3020 	nvme_dev_disable(dev, true);
3021 	nvme_sync_queues(&dev->ctrl);
3022 	nvme_mark_namespaces_dead(&dev->ctrl);
3023 	nvme_unquiesce_io_queues(&dev->ctrl);
3024 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3025 }
3026 
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)3027 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
3028 {
3029 	*val = readl(to_nvme_dev(ctrl)->bar + off);
3030 	return 0;
3031 }
3032 
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)3033 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
3034 {
3035 	writel(val, to_nvme_dev(ctrl)->bar + off);
3036 	return 0;
3037 }
3038 
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)3039 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
3040 {
3041 	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
3042 	return 0;
3043 }
3044 
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)3045 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
3046 {
3047 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3048 
3049 	return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
3050 }
3051 
nvme_pci_print_device_info(struct nvme_ctrl * ctrl)3052 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
3053 {
3054 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3055 	struct nvme_subsystem *subsys = ctrl->subsys;
3056 
3057 	dev_err(ctrl->device,
3058 		"VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
3059 		pdev->vendor, pdev->device,
3060 		nvme_strlen(subsys->model, sizeof(subsys->model)),
3061 		subsys->model, nvme_strlen(subsys->firmware_rev,
3062 					   sizeof(subsys->firmware_rev)),
3063 		subsys->firmware_rev);
3064 }
3065 
nvme_pci_supports_pci_p2pdma(struct nvme_ctrl * ctrl)3066 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
3067 {
3068 	struct nvme_dev *dev = to_nvme_dev(ctrl);
3069 
3070 	return dma_pci_p2pdma_supported(dev->dev);
3071 }
3072 
3073 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
3074 	.name			= "pcie",
3075 	.module			= THIS_MODULE,
3076 	.flags			= NVME_F_METADATA_SUPPORTED,
3077 	.dev_attr_groups	= nvme_pci_dev_attr_groups,
3078 	.reg_read32		= nvme_pci_reg_read32,
3079 	.reg_write32		= nvme_pci_reg_write32,
3080 	.reg_read64		= nvme_pci_reg_read64,
3081 	.free_ctrl		= nvme_pci_free_ctrl,
3082 	.submit_async_event	= nvme_pci_submit_async_event,
3083 	.subsystem_reset	= nvme_pci_subsystem_reset,
3084 	.get_address		= nvme_pci_get_address,
3085 	.print_device_info	= nvme_pci_print_device_info,
3086 	.supports_pci_p2pdma	= nvme_pci_supports_pci_p2pdma,
3087 };
3088 
nvme_dev_map(struct nvme_dev * dev)3089 static int nvme_dev_map(struct nvme_dev *dev)
3090 {
3091 	struct pci_dev *pdev = to_pci_dev(dev->dev);
3092 
3093 	if (pci_request_mem_regions(pdev, "nvme"))
3094 		return -ENODEV;
3095 
3096 	if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
3097 		goto release;
3098 
3099 	return 0;
3100   release:
3101 	pci_release_mem_regions(pdev);
3102 	return -ENODEV;
3103 }
3104 
check_vendor_combination_bug(struct pci_dev * pdev)3105 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3106 {
3107 	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3108 		/*
3109 		 * Several Samsung devices seem to drop off the PCIe bus
3110 		 * randomly when APST is on and uses the deepest sleep state.
3111 		 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3112 		 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3113 		 * 950 PRO 256GB", but it seems to be restricted to two Dell
3114 		 * laptops.
3115 		 */
3116 		if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3117 		    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3118 		     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3119 			return NVME_QUIRK_NO_DEEPEST_PS;
3120 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3121 		/*
3122 		 * Samsung SSD 960 EVO drops off the PCIe bus after system
3123 		 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3124 		 * within few minutes after bootup on a Coffee Lake board -
3125 		 * ASUS PRIME Z370-A
3126 		 */
3127 		if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3128 		    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3129 		     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3130 			return NVME_QUIRK_NO_APST;
3131 	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3132 		    pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3133 		   (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3134 		/*
3135 		 * Forcing to use host managed nvme power settings for
3136 		 * lowest idle power with quick resume latency on
3137 		 * Samsung and Toshiba SSDs based on suspend behavior
3138 		 * on Coffee Lake board for LENOVO C640
3139 		 */
3140 		if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3141 		     dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3142 			return NVME_QUIRK_SIMPLE_SUSPEND;
3143 	} else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
3144 		   pdev->device == 0x500f)) {
3145 		/*
3146 		 * Exclude some Kingston NV1 and A2000 devices from
3147 		 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
3148 		 * lot fo energy with s2idle sleep on some TUXEDO platforms.
3149 		 */
3150 		if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
3151 		    dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
3152 		    dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
3153 		    dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
3154 			return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3155 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
3156 		/*
3157 		 * Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
3158 		 * because of high power consumption (> 2 Watt) in s2idle
3159 		 * sleep. Only some boards with Intel CPU are affected.
3160 		 */
3161 		if (dmi_match(DMI_BOARD_NAME, "DN50Z-140HC-YD") ||
3162 		    dmi_match(DMI_BOARD_NAME, "GMxPXxx") ||
3163 		    dmi_match(DMI_BOARD_NAME, "GXxMRXx") ||
3164 		    dmi_match(DMI_BOARD_NAME, "PH4PG31") ||
3165 		    dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") ||
3166 		    dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71"))
3167 			return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3168 	}
3169 
3170 	/*
3171 	 * NVMe SSD drops off the PCIe bus after system idle
3172 	 * for 10 hours on a Lenovo N60z board.
3173 	 */
3174 	if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6"))
3175 		return NVME_QUIRK_NO_APST;
3176 
3177 	return 0;
3178 }
3179 
nvme_pci_alloc_dev(struct pci_dev * pdev,const struct pci_device_id * id)3180 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
3181 		const struct pci_device_id *id)
3182 {
3183 	unsigned long quirks = id->driver_data;
3184 	int node = dev_to_node(&pdev->dev);
3185 	struct nvme_dev *dev;
3186 	int ret = -ENOMEM;
3187 
3188 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3189 	if (!dev)
3190 		return ERR_PTR(-ENOMEM);
3191 	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3192 	mutex_init(&dev->shutdown_lock);
3193 
3194 	dev->nr_write_queues = write_queues;
3195 	dev->nr_poll_queues = poll_queues;
3196 	dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3197 	dev->queues = kcalloc_node(dev->nr_allocated_queues,
3198 			sizeof(struct nvme_queue), GFP_KERNEL, node);
3199 	if (!dev->queues)
3200 		goto out_free_dev;
3201 
3202 	dev->dev = get_device(&pdev->dev);
3203 
3204 	quirks |= check_vendor_combination_bug(pdev);
3205 	if (!noacpi &&
3206 	    !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
3207 	    acpi_storage_d3(&pdev->dev)) {
3208 		/*
3209 		 * Some systems use a bios work around to ask for D3 on
3210 		 * platforms that support kernel managed suspend.
3211 		 */
3212 		dev_info(&pdev->dev,
3213 			 "platform quirk: setting simple suspend\n");
3214 		quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3215 	}
3216 	ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3217 			     quirks);
3218 	if (ret)
3219 		goto out_put_device;
3220 
3221 	if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
3222 		dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
3223 	else
3224 		dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3225 	dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3226 	dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3227 
3228 	/*
3229 	 * Limit the max command size to prevent iod->sg allocations going
3230 	 * over a single page.
3231 	 */
3232 	dev->ctrl.max_hw_sectors = min_t(u32,
3233 		NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
3234 	dev->ctrl.max_segments = NVME_MAX_SEGS;
3235 	dev->ctrl.max_integrity_segments = 1;
3236 	return dev;
3237 
3238 out_put_device:
3239 	put_device(dev->dev);
3240 	kfree(dev->queues);
3241 out_free_dev:
3242 	kfree(dev);
3243 	return ERR_PTR(ret);
3244 }
3245 
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)3246 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3247 {
3248 	struct nvme_dev *dev;
3249 	int result = -ENOMEM;
3250 
3251 	dev = nvme_pci_alloc_dev(pdev, id);
3252 	if (IS_ERR(dev))
3253 		return PTR_ERR(dev);
3254 
3255 	result = nvme_add_ctrl(&dev->ctrl);
3256 	if (result)
3257 		goto out_put_ctrl;
3258 
3259 	result = nvme_dev_map(dev);
3260 	if (result)
3261 		goto out_uninit_ctrl;
3262 
3263 	result = nvme_setup_prp_pools(dev);
3264 	if (result)
3265 		goto out_dev_unmap;
3266 
3267 	result = nvme_pci_alloc_iod_mempool(dev);
3268 	if (result)
3269 		goto out_release_prp_pools;
3270 
3271 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3272 
3273 	result = nvme_pci_enable(dev);
3274 	if (result)
3275 		goto out_release_iod_mempool;
3276 
3277 	result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3278 				&nvme_mq_admin_ops, sizeof(struct nvme_iod));
3279 	if (result)
3280 		goto out_disable;
3281 
3282 	/*
3283 	 * Mark the controller as connecting before sending admin commands to
3284 	 * allow the timeout handler to do the right thing.
3285 	 */
3286 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3287 		dev_warn(dev->ctrl.device,
3288 			"failed to mark controller CONNECTING\n");
3289 		result = -EBUSY;
3290 		goto out_disable;
3291 	}
3292 
3293 	result = nvme_init_ctrl_finish(&dev->ctrl, false);
3294 	if (result)
3295 		goto out_disable;
3296 
3297 	if (nvme_ctrl_meta_sgl_supported(&dev->ctrl))
3298 		dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
3299 	else
3300 		dev->ctrl.max_integrity_segments = 1;
3301 
3302 	nvme_dbbuf_dma_alloc(dev);
3303 
3304 	result = nvme_setup_host_mem(dev);
3305 	if (result < 0)
3306 		goto out_disable;
3307 
3308 	result = nvme_setup_io_queues(dev);
3309 	if (result)
3310 		goto out_disable;
3311 
3312 	if (dev->online_queues > 1) {
3313 		nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3314 				nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3315 		nvme_dbbuf_set(dev);
3316 	}
3317 
3318 	if (!dev->ctrl.tagset)
3319 		dev_warn(dev->ctrl.device, "IO queues not created\n");
3320 
3321 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3322 		dev_warn(dev->ctrl.device,
3323 			"failed to mark controller live state\n");
3324 		result = -ENODEV;
3325 		goto out_disable;
3326 	}
3327 
3328 	pci_set_drvdata(pdev, dev);
3329 
3330 	nvme_start_ctrl(&dev->ctrl);
3331 	nvme_put_ctrl(&dev->ctrl);
3332 	flush_work(&dev->ctrl.scan_work);
3333 	return 0;
3334 
3335 out_disable:
3336 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3337 	nvme_dev_disable(dev, true);
3338 	nvme_free_host_mem(dev);
3339 	nvme_dev_remove_admin(dev);
3340 	nvme_dbbuf_dma_free(dev);
3341 	nvme_free_queues(dev, 0);
3342 out_release_iod_mempool:
3343 	mempool_destroy(dev->iod_mempool);
3344 	mempool_destroy(dev->iod_meta_mempool);
3345 out_release_prp_pools:
3346 	nvme_release_prp_pools(dev);
3347 out_dev_unmap:
3348 	nvme_dev_unmap(dev);
3349 out_uninit_ctrl:
3350 	nvme_uninit_ctrl(&dev->ctrl);
3351 out_put_ctrl:
3352 	nvme_put_ctrl(&dev->ctrl);
3353 	return result;
3354 }
3355 
nvme_reset_prepare(struct pci_dev * pdev)3356 static void nvme_reset_prepare(struct pci_dev *pdev)
3357 {
3358 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3359 
3360 	/*
3361 	 * We don't need to check the return value from waiting for the reset
3362 	 * state as pci_dev device lock is held, making it impossible to race
3363 	 * with ->remove().
3364 	 */
3365 	nvme_disable_prepare_reset(dev, false);
3366 	nvme_sync_queues(&dev->ctrl);
3367 }
3368 
nvme_reset_done(struct pci_dev * pdev)3369 static void nvme_reset_done(struct pci_dev *pdev)
3370 {
3371 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3372 
3373 	if (!nvme_try_sched_reset(&dev->ctrl))
3374 		flush_work(&dev->ctrl.reset_work);
3375 }
3376 
nvme_shutdown(struct pci_dev * pdev)3377 static void nvme_shutdown(struct pci_dev *pdev)
3378 {
3379 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3380 
3381 	nvme_disable_prepare_reset(dev, true);
3382 }
3383 
3384 /*
3385  * The driver's remove may be called on a device in a partially initialized
3386  * state. This function must not have any dependencies on the device state in
3387  * order to proceed.
3388  */
nvme_remove(struct pci_dev * pdev)3389 static void nvme_remove(struct pci_dev *pdev)
3390 {
3391 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3392 
3393 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3394 	pci_set_drvdata(pdev, NULL);
3395 
3396 	if (!pci_device_is_present(pdev)) {
3397 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3398 		nvme_dev_disable(dev, true);
3399 	}
3400 
3401 	flush_work(&dev->ctrl.reset_work);
3402 	nvme_stop_ctrl(&dev->ctrl);
3403 	nvme_remove_namespaces(&dev->ctrl);
3404 	nvme_dev_disable(dev, true);
3405 	nvme_free_host_mem(dev);
3406 	nvme_dev_remove_admin(dev);
3407 	nvme_dbbuf_dma_free(dev);
3408 	nvme_free_queues(dev, 0);
3409 	mempool_destroy(dev->iod_mempool);
3410 	mempool_destroy(dev->iod_meta_mempool);
3411 	nvme_release_prp_pools(dev);
3412 	nvme_dev_unmap(dev);
3413 	nvme_uninit_ctrl(&dev->ctrl);
3414 }
3415 
3416 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3417 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3418 {
3419 	return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3420 }
3421 
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3422 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3423 {
3424 	return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3425 }
3426 
nvme_resume(struct device * dev)3427 static int nvme_resume(struct device *dev)
3428 {
3429 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3430 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3431 
3432 	if (ndev->last_ps == U32_MAX ||
3433 	    nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3434 		goto reset;
3435 	if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3436 		goto reset;
3437 
3438 	return 0;
3439 reset:
3440 	return nvme_try_sched_reset(ctrl);
3441 }
3442 
nvme_suspend(struct device * dev)3443 static int nvme_suspend(struct device *dev)
3444 {
3445 	struct pci_dev *pdev = to_pci_dev(dev);
3446 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3447 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3448 	int ret = -EBUSY;
3449 
3450 	ndev->last_ps = U32_MAX;
3451 
3452 	/*
3453 	 * The platform does not remove power for a kernel managed suspend so
3454 	 * use host managed nvme power settings for lowest idle power if
3455 	 * possible. This should have quicker resume latency than a full device
3456 	 * shutdown.  But if the firmware is involved after the suspend or the
3457 	 * device does not support any non-default power states, shut down the
3458 	 * device fully.
3459 	 *
3460 	 * If ASPM is not enabled for the device, shut down the device and allow
3461 	 * the PCI bus layer to put it into D3 in order to take the PCIe link
3462 	 * down, so as to allow the platform to achieve its minimum low-power
3463 	 * state (which may not be possible if the link is up).
3464 	 */
3465 	if (pm_suspend_via_firmware() || !ctrl->npss ||
3466 	    !pcie_aspm_enabled(pdev) ||
3467 	    (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3468 		return nvme_disable_prepare_reset(ndev, true);
3469 
3470 	nvme_start_freeze(ctrl);
3471 	nvme_wait_freeze(ctrl);
3472 	nvme_sync_queues(ctrl);
3473 
3474 	if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3475 		goto unfreeze;
3476 
3477 	/*
3478 	 * Host memory access may not be successful in a system suspend state,
3479 	 * but the specification allows the controller to access memory in a
3480 	 * non-operational power state.
3481 	 */
3482 	if (ndev->hmb) {
3483 		ret = nvme_set_host_mem(ndev, 0);
3484 		if (ret < 0)
3485 			goto unfreeze;
3486 	}
3487 
3488 	ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3489 	if (ret < 0)
3490 		goto unfreeze;
3491 
3492 	/*
3493 	 * A saved state prevents pci pm from generically controlling the
3494 	 * device's power. If we're using protocol specific settings, we don't
3495 	 * want pci interfering.
3496 	 */
3497 	pci_save_state(pdev);
3498 
3499 	ret = nvme_set_power_state(ctrl, ctrl->npss);
3500 	if (ret < 0)
3501 		goto unfreeze;
3502 
3503 	if (ret) {
3504 		/* discard the saved state */
3505 		pci_load_saved_state(pdev, NULL);
3506 
3507 		/*
3508 		 * Clearing npss forces a controller reset on resume. The
3509 		 * correct value will be rediscovered then.
3510 		 */
3511 		ret = nvme_disable_prepare_reset(ndev, true);
3512 		ctrl->npss = 0;
3513 	}
3514 unfreeze:
3515 	nvme_unfreeze(ctrl);
3516 	return ret;
3517 }
3518 
nvme_simple_suspend(struct device * dev)3519 static int nvme_simple_suspend(struct device *dev)
3520 {
3521 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3522 
3523 	return nvme_disable_prepare_reset(ndev, true);
3524 }
3525 
nvme_simple_resume(struct device * dev)3526 static int nvme_simple_resume(struct device *dev)
3527 {
3528 	struct pci_dev *pdev = to_pci_dev(dev);
3529 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3530 
3531 	return nvme_try_sched_reset(&ndev->ctrl);
3532 }
3533 
3534 static const struct dev_pm_ops nvme_dev_pm_ops = {
3535 	.suspend	= nvme_suspend,
3536 	.resume		= nvme_resume,
3537 	.freeze		= nvme_simple_suspend,
3538 	.thaw		= nvme_simple_resume,
3539 	.poweroff	= nvme_simple_suspend,
3540 	.restore	= nvme_simple_resume,
3541 };
3542 #endif /* CONFIG_PM_SLEEP */
3543 
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3544 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3545 						pci_channel_state_t state)
3546 {
3547 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3548 
3549 	/*
3550 	 * A frozen channel requires a reset. When detected, this method will
3551 	 * shutdown the controller to quiesce. The controller will be restarted
3552 	 * after the slot reset through driver's slot_reset callback.
3553 	 */
3554 	switch (state) {
3555 	case pci_channel_io_normal:
3556 		return PCI_ERS_RESULT_CAN_RECOVER;
3557 	case pci_channel_io_frozen:
3558 		dev_warn(dev->ctrl.device,
3559 			"frozen state error detected, reset controller\n");
3560 		if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3561 			nvme_dev_disable(dev, true);
3562 			return PCI_ERS_RESULT_DISCONNECT;
3563 		}
3564 		nvme_dev_disable(dev, false);
3565 		return PCI_ERS_RESULT_NEED_RESET;
3566 	case pci_channel_io_perm_failure:
3567 		dev_warn(dev->ctrl.device,
3568 			"failure state error detected, request disconnect\n");
3569 		return PCI_ERS_RESULT_DISCONNECT;
3570 	}
3571 	return PCI_ERS_RESULT_NEED_RESET;
3572 }
3573 
nvme_slot_reset(struct pci_dev * pdev)3574 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3575 {
3576 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3577 
3578 	dev_info(dev->ctrl.device, "restart after slot reset\n");
3579 	pci_restore_state(pdev);
3580 	if (nvme_try_sched_reset(&dev->ctrl))
3581 		nvme_unquiesce_io_queues(&dev->ctrl);
3582 	return PCI_ERS_RESULT_RECOVERED;
3583 }
3584 
nvme_error_resume(struct pci_dev * pdev)3585 static void nvme_error_resume(struct pci_dev *pdev)
3586 {
3587 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3588 
3589 	flush_work(&dev->ctrl.reset_work);
3590 }
3591 
3592 static const struct pci_error_handlers nvme_err_handler = {
3593 	.error_detected	= nvme_error_detected,
3594 	.slot_reset	= nvme_slot_reset,
3595 	.resume		= nvme_error_resume,
3596 	.reset_prepare	= nvme_reset_prepare,
3597 	.reset_done	= nvme_reset_done,
3598 };
3599 
3600 static const struct pci_device_id nvme_id_table[] = {
3601 	{ PCI_VDEVICE(INTEL, 0x0953),	/* Intel 750/P3500/P3600/P3700 */
3602 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3603 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3604 	{ PCI_VDEVICE(INTEL, 0x0a53),	/* Intel P3520 */
3605 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3606 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3607 	{ PCI_VDEVICE(INTEL, 0x0a54),	/* Intel P4500/P4600 */
3608 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3609 				NVME_QUIRK_IGNORE_DEV_SUBNQN |
3610 				NVME_QUIRK_BOGUS_NID, },
3611 	{ PCI_VDEVICE(INTEL, 0x0a55),	/* Dell Express Flash P4600 */
3612 		.driver_data = NVME_QUIRK_STRIPE_SIZE, },
3613 	{ PCI_VDEVICE(INTEL, 0xf1a5),	/* Intel 600P/P3100 */
3614 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3615 				NVME_QUIRK_MEDIUM_PRIO_SQ |
3616 				NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3617 				NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3618 	{ PCI_VDEVICE(INTEL, 0xf1a6),	/* Intel 760p/Pro 7600p */
3619 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3620 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
3621 		.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3622 				NVME_QUIRK_DISABLE_WRITE_ZEROES |
3623 				NVME_QUIRK_BOGUS_NID, },
3624 	{ PCI_VDEVICE(REDHAT, 0x0010),	/* Qemu emulated controller */
3625 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3626 	{ PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */
3627 		.driver_data = NVME_QUIRK_DMAPOOL_ALIGN_512, },
3628 	{ PCI_DEVICE(0x126f, 0x1001),	/* Silicon Motion generic */
3629 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3630 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3631 	{ PCI_DEVICE(0x126f, 0x2262),	/* Silicon Motion generic */
3632 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3633 				NVME_QUIRK_BOGUS_NID, },
3634 	{ PCI_DEVICE(0x126f, 0x2263),	/* Silicon Motion unidentified */
3635 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3636 				NVME_QUIRK_BOGUS_NID, },
3637 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3638 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3639 				NVME_QUIRK_NO_NS_DESC_LIST, },
3640 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
3641 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3642 	{ PCI_DEVICE(0x1c58, 0x0023),	/* WDC SN200 adapter */
3643 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3644 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
3645 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3646 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3647 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3648 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3649 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3650 				NVME_QUIRK_DISABLE_WRITE_ZEROES|
3651 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3652 	{ PCI_DEVICE(0x15b7, 0x5008),   /* Sandisk SN530 */
3653 		.driver_data = NVME_QUIRK_BROKEN_MSI },
3654 	{ PCI_DEVICE(0x15b7, 0x5009),   /* Sandisk SN550 */
3655 		.driver_data = NVME_QUIRK_BROKEN_MSI |
3656 				NVME_QUIRK_NO_DEEPEST_PS },
3657 	{ PCI_DEVICE(0x1987, 0x5012),	/* Phison E12 */
3658 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3659 	{ PCI_DEVICE(0x1987, 0x5016),	/* Phison E16 */
3660 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3661 				NVME_QUIRK_BOGUS_NID, },
3662 	{ PCI_DEVICE(0x1987, 0x5019),  /* phison E19 */
3663 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3664 	{ PCI_DEVICE(0x1987, 0x5021),   /* Phison E21 */
3665 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3666 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
3667 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3668 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3669 	{ PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3670 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3671 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3672 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3673 				NVME_QUIRK_BOGUS_NID, },
3674 	{ PCI_DEVICE(0x10ec, 0x5763),  /* ADATA SX6000PNP */
3675 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3676 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3677 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3678 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3679 	 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3680 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3681 	 { PCI_DEVICE(0x1344, 0x6001),   /* Micron Nitro NVMe */
3682 		 .driver_data = NVME_QUIRK_BOGUS_NID, },
3683 	{ PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3684 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3685 	{ PCI_DEVICE(0x1c5c, 0x174a),   /* SK Hynix P31 SSD */
3686 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3687 	{ PCI_DEVICE(0x1c5c, 0x1D59),   /* SK Hynix BC901 */
3688 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3689 	{ PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3690 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3691 	{ PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3692 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3693 	{ PCI_DEVICE(0x144d, 0xa80b),   /* Samsung PM9B1 256G and 512G */
3694 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3695 				NVME_QUIRK_BOGUS_NID, },
3696 	{ PCI_DEVICE(0x144d, 0xa809),   /* Samsung MZALQ256HBJD 256G */
3697 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3698 	{ PCI_DEVICE(0x144d, 0xa802),   /* Samsung SM953 */
3699 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3700 	{ PCI_DEVICE(0x1cc4, 0x6303),   /* UMIS RPJTJ512MGE1QDY 512G */
3701 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3702 	{ PCI_DEVICE(0x1cc4, 0x6302),   /* UMIS RPJTJ256MGE1QDY 256G */
3703 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3704 	{ PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3705 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3706 	{ PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3707 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3708 	{ PCI_DEVICE(0x2646, 0x5013),   /* Kingston KC3000, Kingston FURY Renegade */
3709 		.driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3710 	{ PCI_DEVICE(0x2646, 0x5018),   /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3711 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3712 	{ PCI_DEVICE(0x2646, 0x5016),   /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3713 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3714 	{ PCI_DEVICE(0x2646, 0x501A),   /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3715 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3716 	{ PCI_DEVICE(0x2646, 0x501B),   /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3717 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3718 	{ PCI_DEVICE(0x2646, 0x501E),   /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3719 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3720 	{ PCI_DEVICE(0x1f40, 0x1202),   /* Netac Technologies Co. NV3000 NVMe SSD */
3721 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3722 	{ PCI_DEVICE(0x1f40, 0x5236),   /* Netac Technologies Co. NV7000 NVMe SSD */
3723 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3724 	{ PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3725 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3726 	{ PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3727 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3728 	{ PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3729 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3730 	{ PCI_DEVICE(0x1e4B, 0x1602),   /* MAXIO MAP1602 */
3731 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3732 	{ PCI_DEVICE(0x1cc1, 0x5350),   /* ADATA XPG GAMMIX S50 */
3733 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3734 	{ PCI_DEVICE(0x1dbe, 0x5216),   /* Acer/INNOGRIT FA100/5216 NVMe SSD */
3735 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3736 	{ PCI_DEVICE(0x1dbe, 0x5236),   /* ADATA XPG GAMMIX S70 */
3737 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3738 	{ PCI_DEVICE(0x1e49, 0x0021),   /* ZHITAI TiPro5000 NVMe SSD */
3739 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3740 	{ PCI_DEVICE(0x1e49, 0x0041),   /* ZHITAI TiPro7000 NVMe SSD */
3741 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3742 	{ PCI_DEVICE(0x025e, 0xf1ac),   /* SOLIDIGM  P44 pro SSDPFKKW020X7  */
3743 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3744 	{ PCI_DEVICE(0xc0a9, 0x540a),   /* Crucial P2 */
3745 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3746 	{ PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3747 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3748 	{ PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3749 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3750 	{ PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3751 		.driver_data = NVME_QUIRK_BOGUS_NID |
3752 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3753 	{ PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3754 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3755 	{ PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G  */
3756 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3757 	{ PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3758 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3759 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3760 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3761 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3762 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3763 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3764 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3765 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3766 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3767 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3768 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3769 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3770 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3771 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3772 		/*
3773 		 * Fix for the Apple controller found in the MacBook8,1 and
3774 		 * some MacBook7,1 to avoid controller resets and data loss.
3775 		 */
3776 		.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3777 				NVME_QUIRK_QDEPTH_ONE },
3778 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3779 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3780 		.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3781 				NVME_QUIRK_128_BYTES_SQES |
3782 				NVME_QUIRK_SHARED_TAGS |
3783 				NVME_QUIRK_SKIP_CID_GEN |
3784 				NVME_QUIRK_IDENTIFY_CNS },
3785 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3786 	{ 0, }
3787 };
3788 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3789 
3790 static struct pci_driver nvme_driver = {
3791 	.name		= "nvme",
3792 	.id_table	= nvme_id_table,
3793 	.probe		= nvme_probe,
3794 	.remove		= nvme_remove,
3795 	.shutdown	= nvme_shutdown,
3796 	.driver		= {
3797 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
3798 #ifdef CONFIG_PM_SLEEP
3799 		.pm		= &nvme_dev_pm_ops,
3800 #endif
3801 	},
3802 	.sriov_configure = pci_sriov_configure_simple,
3803 	.err_handler	= &nvme_err_handler,
3804 };
3805 
nvme_init(void)3806 static int __init nvme_init(void)
3807 {
3808 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3809 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3810 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3811 	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3812 	BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3813 	BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3814 	BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3815 
3816 	return pci_register_driver(&nvme_driver);
3817 }
3818 
nvme_exit(void)3819 static void __exit nvme_exit(void)
3820 {
3821 	pci_unregister_driver(&nvme_driver);
3822 	flush_workqueue(nvme_wq);
3823 }
3824 
3825 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3826 MODULE_LICENSE("GPL");
3827 MODULE_VERSION("1.0");
3828 MODULE_DESCRIPTION("NVMe host PCIe transport driver");
3829 module_init(nvme_init);
3830 module_exit(nvme_exit);
3831