1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852b.h"
11 #include "rtw8852b_common.h"
12 #include "rtw8852b_rfk.h"
13 #include "rtw8852b_table.h"
14 #include "txrx.h"
15
16 #define RTW8852B_FW_FORMAT_MAX 1
17 #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw"
18 #define RTW8852B_MODULE_FIRMWARE \
19 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin"
20
21 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
22 {5, 341, grp_0}, /* ACH 0 */
23 {5, 341, grp_0}, /* ACH 1 */
24 {4, 342, grp_0}, /* ACH 2 */
25 {4, 342, grp_0}, /* ACH 3 */
26 {0, 0, grp_0}, /* ACH 4 */
27 {0, 0, grp_0}, /* ACH 5 */
28 {0, 0, grp_0}, /* ACH 6 */
29 {0, 0, grp_0}, /* ACH 7 */
30 {4, 342, grp_0}, /* B0MGQ */
31 {4, 342, grp_0}, /* B0HIQ */
32 {0, 0, grp_0}, /* B1MGQ */
33 {0, 0, grp_0}, /* B1HIQ */
34 {40, 0, 0} /* FWCMDQ */
35 };
36
37 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = {
38 446, /* Group 0 */
39 0, /* Group 1 */
40 446, /* Public Max */
41 0 /* WP threshold */
42 };
43
44 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
45 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie,
46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
48 RTW89_HCIFC_POH},
49 [RTW89_QTA_INVALID] = {NULL},
50 };
51
52 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7,
54 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7,
55 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18,
56 &rtw89_mac_size.ple_qt58},
57 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7,
58 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7,
59 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18,
60 &rtw89_mac_size.ple_qt_52b_wow},
61 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
62 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
63 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
64 &rtw89_mac_size.ple_qt13},
65 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
66 NULL},
67 };
68
69 static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = {
70 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
71 R_AX_H2CREG_DATA3
72 };
73
74 static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
75 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
76 R_AX_C2HREG_DATA3
77 };
78
79 static const u32 rtw8852b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
80 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
81 };
82
83 static const struct rtw89_page_regs rtw8852b_page_regs = {
84 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
85 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
86 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
87 .ach_page_info = R_AX_ACH0_PAGE_INFO,
88 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
89 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
90 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
91 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
92 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
93 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
94 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
95 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
96 };
97
98 static const struct rtw89_reg_def rtw8852b_dcfo_comp = {
99 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
100 };
101
102 static const struct rtw89_imr_info rtw8852b_imr_info = {
103 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
104 .wsec_imr_reg = R_AX_SEC_DEBUG,
105 .wsec_imr_set = B_AX_IMR_ERROR,
106 .mpdu_tx_imr_set = 0,
107 .mpdu_rx_imr_set = 0,
108 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
109 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
110 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
111 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
112 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
113 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
114 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
115 .wde_imr_clr = B_AX_WDE_IMR_CLR,
116 .wde_imr_set = B_AX_WDE_IMR_SET,
117 .ple_imr_clr = B_AX_PLE_IMR_CLR,
118 .ple_imr_set = B_AX_PLE_IMR_SET,
119 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
120 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
121 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
122 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
123 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
124 .other_disp_imr_set = 0,
125 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
126 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
127 .bbrpt_err_imr_set = 0,
128 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
129 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
130 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
131 .cdma_imr_0_reg = R_AX_DLE_CTRL,
132 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
133 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
134 .cdma_imr_1_reg = 0,
135 .cdma_imr_1_clr = 0,
136 .cdma_imr_1_set = 0,
137 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
138 .phy_intf_imr_clr = 0,
139 .phy_intf_imr_set = 0,
140 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
141 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
142 .rmac_imr_set = B_AX_RMAC_IMR_SET,
143 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
144 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
145 .tmac_imr_set = B_AX_TMAC_IMR_SET,
146 };
147
148 static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = {
149 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
150 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
151 };
152
153 static const struct rtw89_rfkill_regs rtw8852b_rfkill_regs = {
154 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
155 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
156 0xf},
157 .mode = {R_AX_GPIO_EXT_CTRL + 2,
158 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
159 0x0},
160 };
161
162 static const struct rtw89_dig_regs rtw8852b_dig_regs = {
163 .seg0_pd_reg = R_SEG0R_PD_V1,
164 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
165 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
166 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
167 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
168 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
169 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
170 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
171 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
172 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
173 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
174 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
175 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
176 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
177 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
178 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
179 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
180 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
181 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
182 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
183 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
184 };
185
186 static const struct rtw89_edcca_regs rtw8852b_edcca_regs = {
187 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
188 .edcca_mask = B_EDCCA_LVL_MSK0,
189 .edcca_p_mask = B_EDCCA_LVL_MSK1,
190 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
191 .ppdu_mask = B_EDCCA_LVL_MSK3,
192 .p = {{
193 .rpt_a = R_EDCCA_RPT_A,
194 .rpt_b = R_EDCCA_RPT_B,
195 .rpt_sel = R_EDCCA_RPT_SEL,
196 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
197 }, {
198 .rpt_a = R_EDCCA_RPT_P1_A,
199 .rpt_b = R_EDCCA_RPT_P1_B,
200 .rpt_sel = R_EDCCA_RPT_SEL,
201 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
202 }},
203 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
204 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
205 };
206
207 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
208 {255, 0, 0, 7}, /* 0 -> original */
209 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
210 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
211 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
212 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
213 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
214 {6, 1, 0, 7},
215 {13, 1, 0, 7},
216 {13, 1, 0, 7}
217 };
218
219 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = {
220 {255, 0, 0, 7}, /* 0 -> original */
221 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
222 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
223 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
224 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
225 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
226 {255, 1, 0, 7},
227 {255, 1, 0, 7},
228 {255, 1, 0, 7}
229 };
230
231 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = {
232 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
235 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
236 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
237 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
238 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
239 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
240 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
241 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
242 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
243 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
244 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
245 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
246 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
247 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
248 };
249
250 static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
251 static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
252
rtw8852b_pwr_sps_ana(struct rtw89_dev * rtwdev)253 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev)
254 {
255 struct rtw89_efuse *efuse = &rtwdev->efuse;
256
257 if (efuse->rfe_type == 0x5)
258 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA);
259 }
260
rtw8852b_pwr_on_func(struct rtw89_dev * rtwdev)261 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
262 {
263 u32 val32;
264 int ret;
265
266 rtw8852b_pwr_sps_ana(rtwdev);
267
268 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
269 B_AX_AFSM_PCIE_SUS_EN);
270 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
271 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
272 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
273 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
274
275 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
276 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
277 if (ret)
278 return ret;
279
280 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
281 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
282 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
283 if (ret)
284 return ret;
285
286 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
287 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
288 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
289 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
290
291 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
292 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
293 if (ret)
294 return ret;
295
296 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
297 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
298 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
299 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
300
301 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
302 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
303
304 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
305
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
307 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
308 if (ret)
309 return ret;
310
311 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
312
313 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
314 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
315 if (ret)
316 return ret;
317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
318 XTAL_SI_OFF_WEI);
319 if (ret)
320 return ret;
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
322 XTAL_SI_OFF_EI);
323 if (ret)
324 return ret;
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
326 if (ret)
327 return ret;
328 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
329 XTAL_SI_PON_WEI);
330 if (ret)
331 return ret;
332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
333 XTAL_SI_PON_EI);
334 if (ret)
335 return ret;
336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
337 if (ret)
338 return ret;
339 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
340 if (ret)
341 return ret;
342 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
343 if (ret)
344 return ret;
345 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
346 if (ret)
347 return ret;
348
349 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
350 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
351 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
352
353 fsleep(1000);
354
355 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
356 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
357
358 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
359 goto func_en;
360
361 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
362 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
363
364 if (rtwdev->hal.cv == CHIP_CBV) {
365 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
366 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
367 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
368 }
369
370 func_en:
371 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
372 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
373 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
374 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
375 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
376 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
377 B_AX_DMACREG_GCKEN);
378 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
379 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
380 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
381 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
382 B_AX_RMAC_EN);
383
384 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
385 PINMUX_EESK_FUNC_SEL_BT_LOG);
386
387 return 0;
388 }
389
rtw8852b_pwr_off_func(struct rtw89_dev * rtwdev)390 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
391 {
392 u32 val32;
393 int ret;
394
395 rtw8852b_pwr_sps_ana(rtwdev);
396
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
398 XTAL_SI_RFC2RF);
399 if (ret)
400 return ret;
401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
402 if (ret)
403 return ret;
404 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
405 if (ret)
406 return ret;
407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
408 if (ret)
409 return ret;
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
411 if (ret)
412 return ret;
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
414 XTAL_SI_SRAM2RFC);
415 if (ret)
416 return ret;
417 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
418 if (ret)
419 return ret;
420 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
421 if (ret)
422 return ret;
423
424 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
425 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
426 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
427 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
428
429 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
430 if (ret)
431 return ret;
432
433 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
434
435 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
436 if (ret)
437 return ret;
438
439 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
440
441 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
442 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
443 if (ret)
444 return ret;
445
446 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
447 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
448 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
449 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
450
451 return 0;
452 }
453
rtw8852b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)454 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
455 enum rtw89_phy_idx phy_idx, bool en)
456 {
457 if (en) {
458 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
459 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
460 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
461 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
462 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
463 if (band == RTW89_BAND_2G)
464 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
465 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
466 } else {
467 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
468 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
469 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
470 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
471 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
472 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
473 fsleep(1);
474 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
475 }
476 }
477
rtw8852b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)478 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
479 enum rtw89_phy_idx phy_idx)
480 {
481 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
482 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
483 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
484 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
485 rtw8852bx_bb_reset_all(rtwdev, phy_idx);
486 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
487 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
488 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
489 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
490 }
491
rtw8852b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)492 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
493 const struct rtw89_chan *chan,
494 enum rtw89_mac_idx mac_idx,
495 enum rtw89_phy_idx phy_idx)
496 {
497 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx);
498 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx);
499 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
500 }
501
rtw8852b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)502 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
503 enum rtw89_rf_path path)
504 {
505 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
506 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
507
508 if (en) {
509 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
510 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
511 } else {
512 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
513 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
514 }
515 }
516
rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)517 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
518 u8 phy_idx)
519 {
520 if (!rtwdev->dbcc_en) {
521 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
522 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
523 } else {
524 if (phy_idx == RTW89_PHY_0)
525 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
526 else
527 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
528 }
529 }
530
rtw8852b_adc_en(struct rtw89_dev * rtwdev,bool en)531 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
532 {
533 if (en)
534 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
535 else
536 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
537 }
538
rtw8852b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)539 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
540 struct rtw89_channel_help_params *p,
541 const struct rtw89_chan *chan,
542 enum rtw89_mac_idx mac_idx,
543 enum rtw89_phy_idx phy_idx)
544 {
545 if (enter) {
546 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
547 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
548 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
549 rtw8852b_adc_en(rtwdev, false);
550 fsleep(40);
551 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
552 } else {
553 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
554 rtw8852b_adc_en(rtwdev, true);
555 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
556 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
557 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
558 }
559 }
560
rtw8852b_rfk_init(struct rtw89_dev * rtwdev)561 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
562 {
563 rtwdev->is_tssi_mode[RF_PATH_A] = false;
564 rtwdev->is_tssi_mode[RF_PATH_B] = false;
565
566 rtw8852b_dpk_init(rtwdev);
567 rtw8852b_rck(rtwdev);
568 rtw8852b_dack(rtwdev, RTW89_CHANCTX_0);
569 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
570 }
571
rtw8852b_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)572 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev,
573 struct rtw89_vif_link *rtwvif_link)
574 {
575 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
576 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
577
578 rtw89_btc_ntfy_conn_rfk(rtwdev, true);
579
580 rtw8852b_rx_dck(rtwdev, phy_idx, chanctx_idx);
581 rtw8852b_iqk(rtwdev, phy_idx, chanctx_idx);
582 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
583 rtw8852b_tssi(rtwdev, phy_idx, true, chanctx_idx);
584 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
585 rtw8852b_dpk(rtwdev, phy_idx, chanctx_idx);
586
587 rtw89_btc_ntfy_conn_rfk(rtwdev, false);
588 }
589
rtw8852b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)590 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
591 enum rtw89_phy_idx phy_idx,
592 const struct rtw89_chan *chan)
593 {
594 rtw8852b_tssi_scan(rtwdev, phy_idx, chan);
595 }
596
rtw8852b_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)597 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev,
598 struct rtw89_vif_link *rtwvif_link,
599 bool start)
600 {
601 rtw8852b_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
602 rtwvif_link->chanctx_idx);
603 }
604
rtw8852b_rfk_track(struct rtw89_dev * rtwdev)605 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
606 {
607 rtw8852b_dpk_track(rtwdev);
608 }
609
rtw8852b_btc_set_rfe(struct rtw89_dev * rtwdev)610 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
611 {
612 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
613 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
614
615 if (ver->fcxinit == 7) {
616 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
617 md->md_v7.kt_ver = rtwdev->hal.cv;
618 md->md_v7.bt_solo = 0;
619 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
620
621 if (md->md_v7.rfe_type > 0)
622 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3);
623 else
624 md->md_v7.ant.num = 2;
625
626 md->md_v7.ant.diversity = 0;
627 md->md_v7.ant.isolation = 10;
628
629 if (md->md_v7.ant.num == 3) {
630 md->md_v7.ant.type = BTC_ANT_DEDICATED;
631 md->md_v7.bt_pos = BTC_BT_ALONE;
632 } else {
633 md->md_v7.ant.type = BTC_ANT_SHARED;
634 md->md_v7.bt_pos = BTC_BT_BTG;
635 }
636 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
637 rtwdev->btc.ant_type = md->md_v7.ant.type;
638 } else {
639 md->md.rfe_type = rtwdev->efuse.rfe_type;
640 md->md.cv = rtwdev->hal.cv;
641 md->md.bt_solo = 0;
642 md->md.switch_type = BTC_SWITCH_INTERNAL;
643
644 if (md->md.rfe_type > 0)
645 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3);
646 else
647 md->md.ant.num = 2;
648
649 md->md.ant.diversity = 0;
650 md->md.ant.isolation = 10;
651
652 if (md->md.ant.num == 3) {
653 md->md.ant.type = BTC_ANT_DEDICATED;
654 md->md.bt_pos = BTC_BT_ALONE;
655 } else {
656 md->md.ant.type = BTC_ANT_SHARED;
657 md->md.bt_pos = BTC_BT_BTG;
658 }
659 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
660 rtwdev->btc.ant_type = md->md.ant.type;
661 }
662 }
663
664 union rtw8852b_btc_wl_txpwr_ctrl {
665 u32 txpwr_val;
666 struct {
667 union {
668 u16 ctrl_all_time;
669 struct {
670 s16 data:9;
671 u16 rsvd:6;
672 u16 flag:1;
673 } all_time;
674 };
675 union {
676 u16 ctrl_gnt_bt;
677 struct {
678 s16 data:9;
679 u16 rsvd:7;
680 } gnt_bt;
681 };
682 };
683 } __packed;
684
685 static void
rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)686 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
687 {
688 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
689 s32 val;
690
691 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
692 do { \
693 u32 _wrt = FIELD_PREP(_msk, _val); \
694 BUILD_BUG_ON(!!(_msk & _en)); \
695 if (_cond) \
696 _wrt |= _en; \
697 else \
698 _wrt &= ~_en; \
699 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
700 _msk | _en, _wrt); \
701 } while (0)
702
703 switch (arg.ctrl_all_time) {
704 case 0xffff:
705 val = 0;
706 break;
707 default:
708 val = arg.all_time.data;
709 break;
710 }
711
712 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
713 val, B_AX_FORCE_PWR_BY_RATE_EN,
714 arg.ctrl_all_time != 0xffff);
715
716 switch (arg.ctrl_gnt_bt) {
717 case 0xffff:
718 val = 0;
719 break;
720 default:
721 val = arg.gnt_bt.data;
722 break;
723 }
724
725 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
726 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
727
728 #undef __write_ctrl
729 }
730
731 static const struct rtw89_chip_ops rtw8852b_chip_ops = {
732 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf,
733 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf,
734 .bb_preinit = NULL,
735 .bb_postinit = NULL,
736 .bb_reset = rtw8852b_bb_reset,
737 .bb_sethw = rtw8852bx_bb_sethw,
738 .read_rf = rtw89_phy_read_rf_v1,
739 .write_rf = rtw89_phy_write_rf_v1,
740 .set_channel = rtw8852b_set_channel,
741 .set_channel_help = rtw8852b_set_channel_help,
742 .read_efuse = rtw8852bx_read_efuse,
743 .read_phycap = rtw8852bx_read_phycap,
744 .fem_setup = NULL,
745 .rfe_gpio = NULL,
746 .rfk_hw_init = NULL,
747 .rfk_init = rtw8852b_rfk_init,
748 .rfk_init_late = NULL,
749 .rfk_channel = rtw8852b_rfk_channel,
750 .rfk_band_changed = rtw8852b_rfk_band_changed,
751 .rfk_scan = rtw8852b_rfk_scan,
752 .rfk_track = rtw8852b_rfk_track,
753 .power_trim = rtw8852bx_power_trim,
754 .set_txpwr = rtw8852bx_set_txpwr,
755 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl,
756 .init_txpwr_unit = rtw8852bx_init_txpwr_unit,
757 .get_thermal = rtw8852bx_get_thermal,
758 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx,
759 .query_ppdu = rtw8852bx_query_ppdu,
760 .convert_rpl_to_rssi = rtw8852bx_convert_rpl_to_rssi,
761 .phy_rpt_to_rssi = NULL,
762 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx,
763 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path,
764 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset,
765 .digital_pwr_comp = NULL,
766 .pwr_on_func = rtw8852b_pwr_on_func,
767 .pwr_off_func = rtw8852b_pwr_off_func,
768 .query_rxdesc = rtw89_core_query_rxdesc,
769 .fill_txdesc = rtw89_core_fill_txdesc,
770 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
771 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
772 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
773 .stop_sch_tx = rtw89_mac_stop_sch_tx,
774 .resume_sch_tx = rtw89_mac_resume_sch_tx,
775 .h2c_dctl_sec_cam = NULL,
776 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
777 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
778 .h2c_ampdu_cmac_tbl = NULL,
779 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
780 .h2c_default_dmac_tbl = NULL,
781 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
782 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
783
784 .btc_set_rfe = rtw8852b_btc_set_rfe,
785 .btc_init_cfg = rtw8852bx_btc_init_cfg,
786 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri,
787 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
788 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi,
789 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt,
790 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby,
791 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain,
792 .btc_set_policy = rtw89_btc_set_policy_v1,
793 };
794
795 #ifdef CONFIG_PM
796 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = {
797 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
798 .n_patterns = RTW89_MAX_PATTERN_NUM,
799 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
800 .pattern_min_len = 1,
801 };
802 #endif
803
804 const struct rtw89_chip_info rtw8852b_chip_info = {
805 .chip_id = RTL8852B,
806 .chip_gen = RTW89_CHIP_AX,
807 .ops = &rtw8852b_chip_ops,
808 .mac_def = &rtw89_mac_gen_ax,
809 .phy_def = &rtw89_phy_gen_ax,
810 .fw_basename = RTW8852B_FW_BASENAME,
811 .fw_format_max = RTW8852B_FW_FORMAT_MAX,
812 .try_ce_fw = true,
813 .bbmcu_nr = 0,
814 .needed_fw_elms = 0,
815 .fw_blacklist = &rtw89_fw_blacklist_default,
816 .fifo_size = 196608,
817 .small_fifo_size = true,
818 .dle_scc_rsvd_size = 98304,
819 .max_amsdu_limit = 5000,
820 .dis_2g_40m_ul_ofdma = true,
821 .rsvd_ple_ofst = 0x2f800,
822 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
823 .dle_mem = rtw8852b_dle_mem_pcie,
824 .wde_qempty_acq_grpnum = 4,
825 .wde_qempty_mgq_grpsel = 4,
826 .rf_base_addr = {0xe000, 0xf000},
827 .thermal_th = {0x32, 0x35},
828 .pwr_on_seq = NULL,
829 .pwr_off_seq = NULL,
830 .bb_table = &rtw89_8852b_phy_bb_table,
831 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table,
832 .rf_table = {&rtw89_8852b_phy_radioa_table,
833 &rtw89_8852b_phy_radiob_table,},
834 .nctl_table = &rtw89_8852b_phy_nctl_table,
835 .nctl_post_table = NULL,
836 .dflt_parms = &rtw89_8852b_dflt_parms,
837 .rfe_parms_conf = NULL,
838 .txpwr_factor_bb = 3,
839 .txpwr_factor_rf = 2,
840 .txpwr_factor_mac = 1,
841 .dig_table = NULL,
842 .dig_regs = &rtw8852b_dig_regs,
843 .tssi_dbw_table = NULL,
844 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
845 .support_link_num = 0,
846 .support_chanctx_num = 0,
847 .support_rnr = false,
848 .support_bands = BIT(NL80211_BAND_2GHZ) |
849 BIT(NL80211_BAND_5GHZ),
850 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
851 BIT(NL80211_CHAN_WIDTH_40) |
852 BIT(NL80211_CHAN_WIDTH_80),
853 .support_unii4 = true,
854 .support_ant_gain = true,
855 .support_tas = false,
856 .ul_tb_waveform_ctrl = true,
857 .ul_tb_pwr_diff = false,
858 .rx_freq_frome_ie = true,
859 .hw_sec_hdr = false,
860 .hw_mgmt_tx_encrypt = false,
861 .hw_tkip_crypto = false,
862 .rf_path_num = 2,
863 .tx_nss = 2,
864 .rx_nss = 2,
865 .acam_num = 128,
866 .bcam_num = 10,
867 .scam_num = 128,
868 .bacam_num = 2,
869 .bacam_dynamic_num = 4,
870 .bacam_ver = RTW89_BACAM_V0,
871 .ppdu_max_usr = 4,
872 .sec_ctrl_efuse_size = 4,
873 .physical_efuse_size = 1216,
874 .logical_efuse_size = 2048,
875 .limit_efuse_size = 1280,
876 .dav_phy_efuse_size = 96,
877 .dav_log_efuse_size = 16,
878 .efuse_blocks = NULL,
879 .phycap_addr = 0x580,
880 .phycap_size = 128,
881 .para_ver = 0,
882 .wlcx_desired = 0x05050000,
883 .btcx_desired = 0x5,
884 .scbd = 0x1,
885 .mailbox = 0x1,
886
887 .afh_guard_ch = 6,
888 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres,
889 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres,
890 .rssi_tol = 2,
891 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg),
892 .mon_reg = rtw89_btc_8852b_mon_reg,
893 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul),
894 .rf_para_ulink = rtw89_btc_8852b_rf_ul,
895 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
896 .rf_para_dlink = rtw89_btc_8852b_rf_dl,
897 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
898 BIT(RTW89_PS_MODE_CLK_GATED) |
899 BIT(RTW89_PS_MODE_PWR_GATED),
900 .low_power_hci_modes = 0,
901 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
902 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
903 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
904 .txwd_body_size = sizeof(struct rtw89_txwd_body),
905 .txwd_info_size = sizeof(struct rtw89_txwd_info),
906 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
907 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
908 .h2c_regs = rtw8852b_h2c_regs,
909 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
910 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
911 .c2h_regs = rtw8852b_c2h_regs,
912 .page_regs = &rtw8852b_page_regs,
913 .wow_reason_reg = rtw8852b_wow_wakeup_regs,
914 .cfo_src_fd = true,
915 .cfo_hw_comp = true,
916 .dcfo_comp = &rtw8852b_dcfo_comp,
917 .dcfo_comp_sft = 10,
918 .imr_info = &rtw8852b_imr_info,
919 .imr_dmac_table = NULL,
920 .imr_cmac_table = NULL,
921 .rrsr_cfgs = &rtw8852b_rrsr_cfgs,
922 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
923 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
924 .rfkill_init = &rtw8852b_rfkill_regs,
925 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
926 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
927 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
928 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
929 .edcca_regs = &rtw8852b_edcca_regs,
930 #ifdef CONFIG_PM
931 .wowlan_stub = &rtw_wowlan_stub_8852b,
932 #endif
933 .xtal_info = NULL,
934 };
935 EXPORT_SYMBOL(rtw8852b_chip_info);
936
937 MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE);
938 MODULE_AUTHOR("Realtek Corporation");
939 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver");
940 MODULE_LICENSE("Dual BSD/GPL");
941