1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #include <linux/types.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/etherdevice.h>
11 #include <linux/pci.h>
12 #include <linux/firmware.h>
13
14 #include "iwl-drv.h"
15 #include "iwl-modparams.h"
16 #include "iwl-nvm-parse.h"
17 #include "iwl-prph.h"
18 #include "iwl-io.h"
19 #include "iwl-csr.h"
20 #include "fw/acpi.h"
21 #include "fw/api/nvm-reg.h"
22 #include "fw/api/commands.h"
23 #include "fw/api/cmdhdr.h"
24 #include "fw/img.h"
25 #include "mei/iwl-mei.h"
26
27 /* NVM offsets (in words) definitions */
28 enum nvm_offsets {
29 /* NVM HW-Section offset (in words) definitions */
30 SUBSYSTEM_ID = 0x0A,
31 HW_ADDR = 0x15,
32
33 /* NVM SW-Section offset (in words) definitions */
34 NVM_SW_SECTION = 0x1C0,
35 NVM_VERSION = 0,
36 RADIO_CFG = 1,
37 SKU = 2,
38 N_HW_ADDRS = 3,
39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
40
41 /* NVM REGULATORY -Section offset (in words) definitions */
42 NVM_CHANNELS_SDP = 0,
43 };
44
45 enum ext_nvm_offsets {
46 /* NVM HW-Section offset (in words) definitions */
47
48 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
49
50 /* NVM SW-Section offset (in words) definitions */
51 NVM_VERSION_EXT_NVM = 0,
52 N_HW_ADDRS_FAMILY_8000 = 3,
53
54 /* NVM PHY_SKU-Section offset (in words) definitions */
55 RADIO_CFG_FAMILY_EXT_NVM = 0,
56 SKU_FAMILY_8000 = 2,
57
58 /* NVM REGULATORY -Section offset (in words) definitions */
59 NVM_CHANNELS_EXTENDED = 0,
60 NVM_LAR_OFFSET_OLD = 0x4C7,
61 NVM_LAR_OFFSET = 0x507,
62 NVM_LAR_ENABLED = 0x7,
63 };
64
65 /* SKU Capabilities (actual values from NVM definition) */
66 enum nvm_sku_bits {
67 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
68 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
69 NVM_SKU_CAP_11N_ENABLE = BIT(2),
70 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
71 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
72 };
73
74 /*
75 * These are the channel numbers in the order that they are stored in the NVM
76 */
77 static const u16 iwl_nvm_channels[] = {
78 /* 2.4 GHz */
79 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
80 /* 5 GHz */
81 36, 40, 44, 48, 52, 56, 60, 64,
82 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
83 149, 153, 157, 161, 165
84 };
85
86 static const u16 iwl_ext_nvm_channels[] = {
87 /* 2.4 GHz */
88 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
89 /* 5 GHz */
90 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
91 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
92 149, 153, 157, 161, 165, 169, 173, 177, 181
93 };
94
95 static const u16 iwl_uhb_nvm_channels[] = {
96 /* 2.4 GHz */
97 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
98 /* 5 GHz */
99 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
100 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
101 149, 153, 157, 161, 165, 169, 173, 177, 181,
102 /* 6-7 GHz */
103 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
104 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
105 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
106 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
107 };
108
109 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
110 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
111 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
112 #define NUM_2GHZ_CHANNELS 14
113 #define NUM_5GHZ_CHANNELS 37
114 #define FIRST_2GHZ_HT_MINUS 5
115 #define LAST_2GHZ_HT_PLUS 9
116 #define N_HW_ADDR_MASK 0xF
117
118 /* rate data (static) */
119 static struct ieee80211_rate iwl_cfg80211_rates[] = {
120 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
121 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
122 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
123 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
125 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
127 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
128 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
129 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
130 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
131 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
132 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
133 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
134 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
135 };
136 #define RATES_24_OFFS 0
137 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
138 #define RATES_52_OFFS 4
139 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
140
141 /**
142 * enum iwl_nvm_channel_flags - channel flags in NVM
143 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
144 * @NVM_CHANNEL_IBSS: usable as an IBSS channel and deprecated
145 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled.
146 * @NVM_CHANNEL_ACTIVE: active scanning allowed and allows IBSS
147 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled.
148 * @NVM_CHANNEL_RADAR: radar detection required
149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
151 * on same channel on 2.4 or same UNII band on 5.2
152 * @NVM_CHANNEL_UNIFORM: uniform spreading required
153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
158 * @NVM_CHANNEL_VLP: client support connection to UHB VLP AP
159 * @NVM_CHANNEL_AFC: client support connection to UHB AFC AP
160 */
161 enum iwl_nvm_channel_flags {
162 NVM_CHANNEL_VALID = BIT(0),
163 NVM_CHANNEL_IBSS = BIT(1),
164 NVM_CHANNEL_ACTIVE = BIT(3),
165 NVM_CHANNEL_RADAR = BIT(4),
166 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
167 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
168 NVM_CHANNEL_UNIFORM = BIT(7),
169 NVM_CHANNEL_20MHZ = BIT(8),
170 NVM_CHANNEL_40MHZ = BIT(9),
171 NVM_CHANNEL_80MHZ = BIT(10),
172 NVM_CHANNEL_160MHZ = BIT(11),
173 NVM_CHANNEL_DC_HIGH = BIT(12),
174 NVM_CHANNEL_VLP = BIT(13),
175 NVM_CHANNEL_AFC = BIT(14),
176 };
177
178 /**
179 * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory
180 * domain.
181 * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
182 * 2.4Ghz band is allowed.
183 * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
184 * 5Ghz band is allowed.
185 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
186 * for this regulatory domain (valid only in 5Ghz).
187 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
188 * for this regulatory domain (valid only in 5Ghz).
189 * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
190 * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
191 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
192 * for this regulatory domain (valid only in 5Ghz).
193 * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed.
194 * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
195 */
196 enum iwl_reg_capa_flags_v1 {
197 REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0),
198 REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1),
199 REG_CAPA_V1_160MHZ_ALLOWED = BIT(2),
200 REG_CAPA_V1_80MHZ_ALLOWED = BIT(3),
201 REG_CAPA_V1_MCS_8_ALLOWED = BIT(4),
202 REG_CAPA_V1_MCS_9_ALLOWED = BIT(5),
203 REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7),
204 REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9),
205 REG_CAPA_V1_11AX_DISABLED = BIT(10),
206 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */
207
208 /**
209 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
210 * domain (version 2).
211 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
212 * disabled.
213 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
214 * 2.4Ghz band is allowed.
215 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
216 * 5Ghz band is allowed.
217 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
218 * for this regulatory domain (valid only in 5Ghz).
219 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
220 * for this regulatory domain (valid only in 5Ghz).
221 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
222 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
223 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
224 * 126, 122) are disabled.
225 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
226 * for this regulatory domain (uvalid only in 5Ghz).
227 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
228 */
229 enum iwl_reg_capa_flags_v2 {
230 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
231 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
232 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
233 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
234 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
235 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
236 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
237 REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
238 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
239 REG_CAPA_V2_11AX_DISABLED = BIT(10),
240 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */
241
242 /**
243 * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory
244 * domain.
245 * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
246 * for this regulatory domain (valid only in 5Ghz).
247 * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
248 * for this regulatory domain (valid only in 5Ghz).
249 * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed.
250 * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed.
251 * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain.
252 * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
253 * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed
254 * for this regulatory domain (valid only in 5GHz).
255 */
256 enum iwl_reg_capa_flags_v4 {
257 REG_CAPA_V4_160MHZ_ALLOWED = BIT(3),
258 REG_CAPA_V4_80MHZ_ALLOWED = BIT(4),
259 REG_CAPA_V4_MCS_12_ALLOWED = BIT(5),
260 REG_CAPA_V4_MCS_13_ALLOWED = BIT(6),
261 REG_CAPA_V4_11BE_DISABLED = BIT(8),
262 REG_CAPA_V4_11AX_DISABLED = BIT(13),
263 REG_CAPA_V4_320MHZ_ALLOWED = BIT(16),
264 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */
265
266 /*
267 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the
268 * MCC update command response.
269 */
270 #define REG_CAPA_V2_RESP_VER 6
271
272 /* API v4 for reg_capa_flags is relevant from version 8 and onwards of the
273 * MCC update command response.
274 */
275 #define REG_CAPA_V4_RESP_VER 8
276
277 /**
278 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
279 * handling the different APIs of reg_capa_flags.
280 *
281 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
282 * for this regulatory domain.
283 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
284 * for this regulatory domain (valid only in 5 and 6 Ghz).
285 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
286 * for this regulatory domain (valid only in 5 and 6 Ghz).
287 * @allow_320mhz: 11be channel with a width of 320Mhz is allowed
288 * for this regulatory domain (valid only in 6 Ghz).
289 * @disable_11ax: 11ax is forbidden for this regulatory domain.
290 * @disable_11be: 11be is forbidden for this regulatory domain.
291 */
292 struct iwl_reg_capa {
293 bool allow_40mhz;
294 bool allow_80mhz;
295 bool allow_160mhz;
296 bool allow_320mhz;
297 bool disable_11ax;
298 bool disable_11be;
299 };
300
iwl_nvm_print_channel_flags(struct device * dev,u32 level,int chan,u32 flags)301 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
302 int chan, u32 flags)
303 {
304 #define CHECK_AND_PRINT_I(x) \
305 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
306
307 if (!(flags & NVM_CHANNEL_VALID)) {
308 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
309 chan, flags);
310 return;
311 }
312
313 /* Note: already can print up to 101 characters, 110 is the limit! */
314 IWL_DEBUG_DEV(dev, level,
315 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
316 chan, flags,
317 CHECK_AND_PRINT_I(VALID),
318 CHECK_AND_PRINT_I(IBSS),
319 CHECK_AND_PRINT_I(ACTIVE),
320 CHECK_AND_PRINT_I(RADAR),
321 CHECK_AND_PRINT_I(INDOOR_ONLY),
322 CHECK_AND_PRINT_I(GO_CONCURRENT),
323 CHECK_AND_PRINT_I(UNIFORM),
324 CHECK_AND_PRINT_I(20MHZ),
325 CHECK_AND_PRINT_I(40MHZ),
326 CHECK_AND_PRINT_I(80MHZ),
327 CHECK_AND_PRINT_I(160MHZ),
328 CHECK_AND_PRINT_I(DC_HIGH),
329 CHECK_AND_PRINT_I(VLP),
330 CHECK_AND_PRINT_I(AFC));
331 #undef CHECK_AND_PRINT_I
332 }
333
iwl_get_channel_flags(u8 ch_num,int ch_idx,enum nl80211_band band,u32 nvm_flags,const struct iwl_cfg * cfg)334 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
335 u32 nvm_flags, const struct iwl_cfg *cfg)
336 {
337 u32 flags = IEEE80211_CHAN_NO_HT40;
338
339 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
340 if (ch_num <= LAST_2GHZ_HT_PLUS)
341 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
342 if (ch_num >= FIRST_2GHZ_HT_MINUS)
343 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
344 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
345 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
346 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
347 else
348 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
349 }
350 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
351 flags |= IEEE80211_CHAN_NO_80MHZ;
352 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
353 flags |= IEEE80211_CHAN_NO_160MHZ;
354
355 if (!(nvm_flags & NVM_CHANNEL_IBSS))
356 flags |= IEEE80211_CHAN_NO_IR;
357
358 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
359 flags |= IEEE80211_CHAN_NO_IR;
360
361 if (nvm_flags & NVM_CHANNEL_RADAR)
362 flags |= IEEE80211_CHAN_RADAR;
363
364 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
365 flags |= IEEE80211_CHAN_INDOOR_ONLY;
366
367 /* Set the GO concurrent flag only in case that NO_IR is set.
368 * Otherwise it is meaningless
369 */
370 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
371 (flags & IEEE80211_CHAN_NO_IR))
372 flags |= IEEE80211_CHAN_IR_CONCURRENT;
373
374 /* Set the AP type for the UHB case. */
375 if (nvm_flags & NVM_CHANNEL_VLP)
376 flags |= IEEE80211_CHAN_ALLOW_6GHZ_VLP_AP;
377 else
378 flags |= IEEE80211_CHAN_NO_6GHZ_VLP_CLIENT;
379 if (!(nvm_flags & NVM_CHANNEL_AFC))
380 flags |= IEEE80211_CHAN_NO_6GHZ_AFC_CLIENT;
381
382 return flags;
383 }
384
iwl_nl80211_band_from_channel_idx(int ch_idx)385 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
386 {
387 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
388 return NL80211_BAND_6GHZ;
389 }
390
391 if (ch_idx >= NUM_2GHZ_CHANNELS)
392 return NL80211_BAND_5GHZ;
393 return NL80211_BAND_2GHZ;
394 }
395
iwl_init_channel_map(struct iwl_trans * trans,const struct iwl_fw * fw,struct iwl_nvm_data * data,const void * const nvm_ch_flags,u32 sbands_flags,bool v4)396 static int iwl_init_channel_map(struct iwl_trans *trans,
397 const struct iwl_fw *fw,
398 struct iwl_nvm_data *data,
399 const void * const nvm_ch_flags,
400 u32 sbands_flags, bool v4)
401 {
402 const struct iwl_cfg *cfg = trans->cfg;
403 struct device *dev = trans->dev;
404 int ch_idx;
405 int n_channels = 0;
406 struct ieee80211_channel *channel;
407 u32 ch_flags;
408 int num_of_ch;
409 const u16 *nvm_chan;
410
411 if (cfg->uhb_supported) {
412 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
413 nvm_chan = iwl_uhb_nvm_channels;
414 } else if (cfg->nvm_type == IWL_NVM_EXT) {
415 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
416 nvm_chan = iwl_ext_nvm_channels;
417 } else {
418 num_of_ch = IWL_NVM_NUM_CHANNELS;
419 nvm_chan = iwl_nvm_channels;
420 }
421
422 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
423 enum nl80211_band band =
424 iwl_nl80211_band_from_channel_idx(ch_idx);
425
426 if (v4)
427 ch_flags =
428 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx);
429 else
430 ch_flags =
431 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx);
432
433 if (band == NL80211_BAND_5GHZ &&
434 !data->sku_cap_band_52ghz_enable)
435 continue;
436
437 /* workaround to disable wide channels in 5GHz */
438 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
439 band == NL80211_BAND_5GHZ) {
440 ch_flags &= ~(NVM_CHANNEL_40MHZ |
441 NVM_CHANNEL_80MHZ |
442 NVM_CHANNEL_160MHZ);
443 }
444
445 if (ch_flags & NVM_CHANNEL_160MHZ)
446 data->vht160_supported = true;
447
448 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
449 !(ch_flags & NVM_CHANNEL_VALID)) {
450 /*
451 * Channels might become valid later if lar is
452 * supported, hence we still want to add them to
453 * the list of supported channels to cfg80211.
454 */
455 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
456 nvm_chan[ch_idx], ch_flags);
457 continue;
458 }
459
460 channel = &data->channels[n_channels];
461 n_channels++;
462
463 channel->hw_value = nvm_chan[ch_idx];
464 channel->band = band;
465 channel->center_freq =
466 ieee80211_channel_to_frequency(
467 channel->hw_value, channel->band);
468
469 /* Initialize regulatory-based run-time data */
470
471 /*
472 * Default value - highest tx power value. max_power
473 * is not used in mvm, and is used for backwards compatibility
474 */
475 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
476
477 /* don't put limitations in case we're using LAR */
478 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
479 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
480 ch_idx, band,
481 ch_flags, cfg);
482 else
483 channel->flags = 0;
484
485 if (fw_has_capa(&fw->ucode_capa,
486 IWL_UCODE_TLV_CAPA_MONITOR_PASSIVE_CHANS))
487 channel->flags |= IEEE80211_CHAN_CAN_MONITOR;
488
489 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
490 channel->hw_value, ch_flags);
491 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
492 channel->hw_value, channel->max_power);
493 }
494
495 return n_channels;
496 }
497
iwl_init_vht_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_sta_vht_cap * vht_cap,u8 tx_chains,u8 rx_chains)498 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
499 struct iwl_nvm_data *data,
500 struct ieee80211_sta_vht_cap *vht_cap,
501 u8 tx_chains, u8 rx_chains)
502 {
503 const struct iwl_cfg *cfg = trans->cfg;
504 int num_rx_ants = num_of_ant(rx_chains);
505 int num_tx_ants = num_of_ant(tx_chains);
506
507 vht_cap->vht_supported = true;
508
509 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
510 IEEE80211_VHT_CAP_RXSTBC_1 |
511 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
512 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
513 IEEE80211_VHT_MAX_AMPDU_1024K <<
514 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
515
516 if (!trans->cfg->ht_params->stbc)
517 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK;
518
519 if (data->vht160_supported)
520 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
521 IEEE80211_VHT_CAP_SHORT_GI_160;
522
523 if (cfg->vht_mu_mimo_supported)
524 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
525
526 if (cfg->ht_params->ldpc)
527 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
528
529 if (data->sku_cap_mimo_disabled) {
530 num_rx_ants = 1;
531 num_tx_ants = 1;
532 }
533
534 if (trans->cfg->ht_params->stbc && num_tx_ants > 1)
535 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
536 else
537 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
538
539 switch (iwlwifi_mod_params.amsdu_size) {
540 case IWL_AMSDU_DEF:
541 if (trans->trans_cfg->mq_rx_supported)
542 vht_cap->cap |=
543 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
544 else
545 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
546 break;
547 case IWL_AMSDU_2K:
548 if (trans->trans_cfg->mq_rx_supported)
549 vht_cap->cap |=
550 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
551 else
552 WARN(1, "RB size of 2K is not supported by this device\n");
553 break;
554 case IWL_AMSDU_4K:
555 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
556 break;
557 case IWL_AMSDU_8K:
558 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
559 break;
560 case IWL_AMSDU_12K:
561 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
562 break;
563 default:
564 break;
565 }
566
567 vht_cap->vht_mcs.rx_mcs_map =
568 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
569 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
570 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
571 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
572 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
573 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
574 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
575 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
576
577 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
578 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
579 /* this works because NOT_SUPPORTED == 3 */
580 vht_cap->vht_mcs.rx_mcs_map |=
581 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
582 }
583
584 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
585
586 vht_cap->vht_mcs.tx_highest |=
587 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
588 }
589
590 static const u8 iwl_vendor_caps[] = {
591 0xdd, /* vendor element */
592 0x06, /* length */
593 0x00, 0x17, 0x35, /* Intel OUI */
594 0x08, /* type (Intel Capabilities) */
595 /* followed by 16 bits of capabilities */
596 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0)
597 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE,
598 0x00
599 };
600
601 static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = {
602 {
603 .types_mask = BIT(NL80211_IFTYPE_STATION) |
604 BIT(NL80211_IFTYPE_P2P_CLIENT),
605 .he_cap = {
606 .has_he = true,
607 .he_cap_elem = {
608 .mac_cap_info[0] =
609 IEEE80211_HE_MAC_CAP0_HTC_HE,
610 .mac_cap_info[1] =
611 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
612 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
613 .mac_cap_info[2] =
614 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
615 .mac_cap_info[3] =
616 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
617 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS,
618 .mac_cap_info[4] =
619 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
620 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
621 .mac_cap_info[5] =
622 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
623 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
624 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
625 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
626 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
627 .phy_cap_info[1] =
628 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
629 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
630 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
631 .phy_cap_info[2] =
632 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
633 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
634 .phy_cap_info[3] =
635 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
636 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
637 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
638 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
639 .phy_cap_info[4] =
640 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
641 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
642 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
643 .phy_cap_info[6] =
644 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
645 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
646 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
647 .phy_cap_info[7] =
648 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
649 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
650 .phy_cap_info[8] =
651 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
652 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
653 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
654 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
655 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
656 .phy_cap_info[9] =
657 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
658 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
659 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED <<
660 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS),
661 .phy_cap_info[10] =
662 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF,
663 },
664 /*
665 * Set default Tx/Rx HE MCS NSS Support field.
666 * Indicate support for up to 2 spatial streams and all
667 * MCS, without any special cases
668 */
669 .he_mcs_nss_supp = {
670 .rx_mcs_80 = cpu_to_le16(0xfffa),
671 .tx_mcs_80 = cpu_to_le16(0xfffa),
672 .rx_mcs_160 = cpu_to_le16(0xfffa),
673 .tx_mcs_160 = cpu_to_le16(0xfffa),
674 .rx_mcs_80p80 = cpu_to_le16(0xffff),
675 .tx_mcs_80p80 = cpu_to_le16(0xffff),
676 },
677 /*
678 * Set default PPE thresholds, with PPET16 set to 0,
679 * PPET8 set to 7
680 */
681 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
682 },
683 .eht_cap = {
684 .has_eht = true,
685 .eht_cap_elem = {
686 .mac_cap_info[0] =
687 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS |
688 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
689 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
690 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2 |
691 IEEE80211_EHT_MAC_CAP0_SCS_TRAFFIC_DESC,
692 .mac_cap_info[1] =
693 IEEE80211_EHT_MAC_CAP1_UNSOL_EPCS_PRIO_ACCESS,
694 .phy_cap_info[0] =
695 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
696 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
697 IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
698 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE |
699 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK,
700 .phy_cap_info[1] =
701 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK |
702 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK,
703 .phy_cap_info[3] =
704 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
705 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
706 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
707 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
708 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
709 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
710 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK,
711
712 .phy_cap_info[4] =
713 IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
714 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
715 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI,
716 .phy_cap_info[5] =
717 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
718 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US) |
719 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK |
720 IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP |
721 IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP,
722 .phy_cap_info[6] =
723 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
724 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP,
725 .phy_cap_info[8] =
726 IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA |
727 IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA,
728 },
729
730 /* For all MCS and bandwidth, set 2 NSS for both Tx and
731 * Rx - note we don't set the only_20mhz, but due to this
732 * being a union, it gets set correctly anyway.
733 */
734 .eht_mcs_nss_supp = {
735 .bw._80 = {
736 .rx_tx_mcs9_max_nss = 0x22,
737 .rx_tx_mcs11_max_nss = 0x22,
738 .rx_tx_mcs13_max_nss = 0x22,
739 },
740 .bw._160 = {
741 .rx_tx_mcs9_max_nss = 0x22,
742 .rx_tx_mcs11_max_nss = 0x22,
743 .rx_tx_mcs13_max_nss = 0x22,
744 },
745 .bw._320 = {
746 .rx_tx_mcs9_max_nss = 0x22,
747 .rx_tx_mcs11_max_nss = 0x22,
748 .rx_tx_mcs13_max_nss = 0x22,
749 },
750 },
751
752 /*
753 * PPE thresholds for NSS = 2, and RU index bitmap set
754 * to 0xc.
755 * Note: just for stating what we want, not present in
756 * the transmitted data due to not including
757 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
758 */
759 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
760 },
761 },
762 {
763 .types_mask = BIT(NL80211_IFTYPE_AP) |
764 BIT(NL80211_IFTYPE_P2P_GO),
765 .he_cap = {
766 .has_he = true,
767 .he_cap_elem = {
768 .mac_cap_info[0] =
769 IEEE80211_HE_MAC_CAP0_HTC_HE,
770 .mac_cap_info[1] =
771 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
772 .mac_cap_info[3] =
773 IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
774 .phy_cap_info[1] =
775 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
776 .phy_cap_info[2] =
777 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
778 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
779 .phy_cap_info[3] =
780 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
781 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
782 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
783 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
784 .phy_cap_info[6] =
785 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
786 .phy_cap_info[7] =
787 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
788 .phy_cap_info[8] =
789 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
790 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
791 .phy_cap_info[9] =
792 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED
793 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS,
794 },
795 /*
796 * Set default Tx/Rx HE MCS NSS Support field.
797 * Indicate support for up to 2 spatial streams and all
798 * MCS, without any special cases
799 */
800 .he_mcs_nss_supp = {
801 .rx_mcs_80 = cpu_to_le16(0xfffa),
802 .tx_mcs_80 = cpu_to_le16(0xfffa),
803 .rx_mcs_160 = cpu_to_le16(0xfffa),
804 .tx_mcs_160 = cpu_to_le16(0xfffa),
805 .rx_mcs_80p80 = cpu_to_le16(0xffff),
806 .tx_mcs_80p80 = cpu_to_le16(0xffff),
807 },
808 /*
809 * Set default PPE thresholds, with PPET16 set to 0,
810 * PPET8 set to 7
811 */
812 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
813 },
814 .eht_cap = {
815 .has_eht = true,
816 .eht_cap_elem = {
817 .mac_cap_info[0] =
818 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
819 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
820 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2,
821 .phy_cap_info[0] =
822 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
823 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI,
824 .phy_cap_info[5] =
825 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
826 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US),
827 },
828
829 /* For all MCS and bandwidth, set 2 NSS for both Tx and
830 * Rx - note we don't set the only_20mhz, but due to this
831 * being a union, it gets set correctly anyway.
832 */
833 .eht_mcs_nss_supp = {
834 .bw._80 = {
835 .rx_tx_mcs9_max_nss = 0x22,
836 .rx_tx_mcs11_max_nss = 0x22,
837 .rx_tx_mcs13_max_nss = 0x22,
838 },
839 .bw._160 = {
840 .rx_tx_mcs9_max_nss = 0x22,
841 .rx_tx_mcs11_max_nss = 0x22,
842 .rx_tx_mcs13_max_nss = 0x22,
843 },
844 .bw._320 = {
845 .rx_tx_mcs9_max_nss = 0x22,
846 .rx_tx_mcs11_max_nss = 0x22,
847 .rx_tx_mcs13_max_nss = 0x22,
848 },
849 },
850
851 /*
852 * PPE thresholds for NSS = 2, and RU index bitmap set
853 * to 0xc.
854 * Note: just for stating what we want, not present in
855 * the transmitted data due to not including
856 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
857 */
858 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
859 },
860 },
861 };
862
iwl_init_he_6ghz_capa(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains)863 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
864 struct iwl_nvm_data *data,
865 struct ieee80211_supported_band *sband,
866 u8 tx_chains, u8 rx_chains)
867 {
868 struct ieee80211_sta_ht_cap ht_cap;
869 struct ieee80211_sta_vht_cap vht_cap = {};
870 struct ieee80211_sband_iftype_data *iftype_data;
871 u16 he_6ghz_capa = 0;
872 u32 exp;
873 int i;
874
875 if (sband->band != NL80211_BAND_6GHZ)
876 return;
877
878 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
879 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
880 tx_chains, rx_chains);
881 WARN_ON(!ht_cap.ht_supported);
882 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
883 WARN_ON(!vht_cap.vht_supported);
884
885 he_6ghz_capa |=
886 u16_encode_bits(ht_cap.ampdu_density,
887 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
888 exp = u32_get_bits(vht_cap.cap,
889 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
890 he_6ghz_capa |=
891 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
892 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
893 he_6ghz_capa |=
894 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
895 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
896 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
897 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
898 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
899 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
900
901 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
902
903 /* we know it's writable - we set it before ourselves */
904 iftype_data = (void *)(uintptr_t)sband->iftype_data;
905 for (i = 0; i < sband->n_iftype_data; i++)
906 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
907 }
908
909 static void
iwl_nvm_fixup_sband_iftd(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,struct ieee80211_sband_iftype_data * iftype_data,u8 tx_chains,u8 rx_chains,const struct iwl_fw * fw)910 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
911 struct iwl_nvm_data *data,
912 struct ieee80211_supported_band *sband,
913 struct ieee80211_sband_iftype_data *iftype_data,
914 u8 tx_chains, u8 rx_chains,
915 const struct iwl_fw *fw)
916 {
917 bool is_ap = iftype_data->types_mask & (BIT(NL80211_IFTYPE_AP) |
918 BIT(NL80211_IFTYPE_P2P_GO));
919 bool slow_pcie = (!trans->trans_cfg->integrated &&
920 trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB);
921
922 if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be)
923 iftype_data->eht_cap.has_eht = false;
924
925 /* Advertise an A-MPDU exponent extension based on
926 * operating band
927 */
928 if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht)
929 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
930 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
931 else if (sband->band != NL80211_BAND_2GHZ)
932 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
933 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
934 else
935 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
936 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
937
938 switch (sband->band) {
939 case NL80211_BAND_2GHZ:
940 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
941 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
942 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |=
943 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
944 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
945 break;
946 case NL80211_BAND_6GHZ:
947 if (!trans->reduced_cap_sku) {
948 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
949 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
950 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |=
951 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK;
952 }
953 fallthrough;
954 case NL80211_BAND_5GHZ:
955 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
956 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
957 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
958 break;
959 default:
960 WARN_ON(1);
961 break;
962 }
963
964 if ((tx_chains & rx_chains) == ANT_AB) {
965 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
966 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ;
967 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
968 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
969 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
970 if (!is_ap) {
971 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
972 IEEE80211_HE_PHY_CAP7_MAX_NC_2;
973
974 if (iftype_data->eht_cap.has_eht) {
975 /*
976 * Set the number of sounding dimensions for each
977 * bandwidth to 1 to indicate the maximal supported
978 * value of TXVECTOR parameter NUM_STS of 2
979 */
980 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49;
981
982 /*
983 * Set the MAX NC to 1 to indicate sounding feedback of
984 * 2 supported by the beamfomee.
985 */
986 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10;
987 }
988 }
989
990 if (slow_pcie) {
991 struct ieee80211_eht_mcs_nss_supp *mcs_nss =
992 &iftype_data->eht_cap.eht_mcs_nss_supp;
993
994 mcs_nss->bw._320.rx_tx_mcs11_max_nss = 0;
995 mcs_nss->bw._320.rx_tx_mcs13_max_nss = 0;
996 }
997 } else {
998 struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp =
999 &iftype_data->he_cap.he_mcs_nss_supp;
1000
1001 if (iftype_data->eht_cap.has_eht) {
1002 struct ieee80211_eht_mcs_nss_supp *mcs_nss =
1003 &iftype_data->eht_cap.eht_mcs_nss_supp;
1004
1005 memset(mcs_nss, 0x11, sizeof(*mcs_nss));
1006 }
1007
1008 if (!is_ap) {
1009 /* If not 2x2, we need to indicate 1x1 in the
1010 * Midamble RX Max NSTS - but not for AP mode
1011 */
1012 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
1013 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
1014 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1015 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
1016 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
1017 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
1018 }
1019
1020 he_mcs_nss_supp->rx_mcs_80 |=
1021 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1022 he_mcs_nss_supp->tx_mcs_80 |=
1023 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1024 he_mcs_nss_supp->rx_mcs_160 |=
1025 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1026 he_mcs_nss_supp->tx_mcs_160 |=
1027 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1028 he_mcs_nss_supp->rx_mcs_80p80 |=
1029 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1030 he_mcs_nss_supp->tx_mcs_80p80 |=
1031 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1032 }
1033
1034 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap)
1035 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
1036 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1037
1038 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
1039 case IWL_CFG_RF_TYPE_GF:
1040 case IWL_CFG_RF_TYPE_FM:
1041 case IWL_CFG_RF_TYPE_WH:
1042 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1043 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
1044 if (!is_ap)
1045 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1046 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1047 break;
1048 }
1049
1050 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
1051 iftype_data->eht_cap.has_eht) {
1052 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &=
1053 ~(IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
1054 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2);
1055 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &=
1056 ~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
1057 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1058 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1059 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1060 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
1061 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
1062 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK);
1063 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &=
1064 ~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
1065 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP);
1066 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &=
1067 ~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK;
1068 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &=
1069 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
1070 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP);
1071 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |=
1072 IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF;
1073 }
1074
1075 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
1076 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
1077 IEEE80211_HE_MAC_CAP2_BCAST_TWT;
1078
1079 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1080 !is_ap) {
1081 iftype_data->vendor_elems.data = iwl_vendor_caps;
1082 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps);
1083 }
1084
1085 if (!trans->cfg->ht_params->stbc) {
1086 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1087 ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1088 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &=
1089 ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1090 }
1091
1092 if (trans->step_urm) {
1093 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0;
1094 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0;
1095 }
1096
1097 if (trans->no_160)
1098 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &=
1099 ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1100
1101 if (trans->reduced_cap_sku) {
1102 memset(&iftype_data->eht_cap.eht_mcs_nss_supp.bw._320, 0,
1103 sizeof(iftype_data->eht_cap.eht_mcs_nss_supp.bw._320));
1104 iftype_data->eht_cap.eht_mcs_nss_supp.bw._80.rx_tx_mcs13_max_nss = 0;
1105 iftype_data->eht_cap.eht_mcs_nss_supp.bw._160.rx_tx_mcs13_max_nss = 0;
1106 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[8] &=
1107 ~IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA;
1108 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] &=
1109 ~IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK;
1110 }
1111 }
1112
iwl_init_he_hw_capab(struct iwl_trans * trans,struct iwl_nvm_data * data,struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains,const struct iwl_fw * fw)1113 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
1114 struct iwl_nvm_data *data,
1115 struct ieee80211_supported_band *sband,
1116 u8 tx_chains, u8 rx_chains,
1117 const struct iwl_fw *fw)
1118 {
1119 struct ieee80211_sband_iftype_data *iftype_data;
1120 int i;
1121
1122 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa));
1123 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa));
1124 BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa));
1125
1126 switch (sband->band) {
1127 case NL80211_BAND_2GHZ:
1128 iftype_data = data->iftd.low;
1129 break;
1130 case NL80211_BAND_5GHZ:
1131 iftype_data = data->iftd.high;
1132 break;
1133 case NL80211_BAND_6GHZ:
1134 iftype_data = data->iftd.uhb;
1135 break;
1136 default:
1137 WARN_ON(1);
1138 return;
1139 }
1140
1141 memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa));
1142
1143 _ieee80211_set_sband_iftype_data(sband, iftype_data,
1144 ARRAY_SIZE(iwl_he_eht_capa));
1145
1146 for (i = 0; i < sband->n_iftype_data; i++)
1147 iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i],
1148 tx_chains, rx_chains, fw);
1149
1150 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
1151 }
1152
iwl_reinit_cab(struct iwl_trans * trans,struct iwl_nvm_data * data,u8 tx_chains,u8 rx_chains,const struct iwl_fw * fw)1153 void iwl_reinit_cab(struct iwl_trans *trans, struct iwl_nvm_data *data,
1154 u8 tx_chains, u8 rx_chains, const struct iwl_fw *fw)
1155 {
1156 struct ieee80211_supported_band *sband;
1157
1158 sband = &data->bands[NL80211_BAND_2GHZ];
1159 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1160 tx_chains, rx_chains);
1161
1162 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1163 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1164 fw);
1165
1166 sband = &data->bands[NL80211_BAND_5GHZ];
1167 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1168 tx_chains, rx_chains);
1169 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1170 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1171 tx_chains, rx_chains);
1172
1173 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1174 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1175 fw);
1176
1177 sband = &data->bands[NL80211_BAND_6GHZ];
1178 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1179 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1180 fw);
1181 }
1182 IWL_EXPORT_SYMBOL(iwl_reinit_cab);
1183
iwl_init_sbands(struct iwl_trans * trans,struct iwl_nvm_data * data,const void * nvm_ch_flags,u8 tx_chains,u8 rx_chains,u32 sbands_flags,bool v4,const struct iwl_fw * fw)1184 static void iwl_init_sbands(struct iwl_trans *trans,
1185 struct iwl_nvm_data *data,
1186 const void *nvm_ch_flags, u8 tx_chains,
1187 u8 rx_chains, u32 sbands_flags, bool v4,
1188 const struct iwl_fw *fw)
1189 {
1190 struct device *dev = trans->dev;
1191 int n_channels;
1192 int n_used = 0;
1193 struct ieee80211_supported_band *sband;
1194
1195 n_channels = iwl_init_channel_map(trans, fw, data, nvm_ch_flags,
1196 sbands_flags, v4);
1197 sband = &data->bands[NL80211_BAND_2GHZ];
1198 sband->band = NL80211_BAND_2GHZ;
1199 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
1200 sband->n_bitrates = N_RATES_24;
1201 n_used += iwl_init_sband_channels(data, sband, n_channels,
1202 NL80211_BAND_2GHZ);
1203 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1204 tx_chains, rx_chains);
1205
1206 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1207 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1208 fw);
1209
1210 sband = &data->bands[NL80211_BAND_5GHZ];
1211 sband->band = NL80211_BAND_5GHZ;
1212 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1213 sband->n_bitrates = N_RATES_52;
1214 n_used += iwl_init_sband_channels(data, sband, n_channels,
1215 NL80211_BAND_5GHZ);
1216 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1217 tx_chains, rx_chains);
1218 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1219 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1220 tx_chains, rx_chains);
1221
1222 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1223 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1224 fw);
1225
1226 /* 6GHz band. */
1227 sband = &data->bands[NL80211_BAND_6GHZ];
1228 sband->band = NL80211_BAND_6GHZ;
1229 /* use the same rates as 5GHz band */
1230 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1231 sband->n_bitrates = N_RATES_52;
1232 n_used += iwl_init_sband_channels(data, sband, n_channels,
1233 NL80211_BAND_6GHZ);
1234
1235 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1236 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1237 fw);
1238 else
1239 sband->n_channels = 0;
1240 if (n_channels != n_used)
1241 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
1242 n_used, n_channels);
1243 }
1244
iwl_get_sku(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)1245 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1246 const __le16 *phy_sku)
1247 {
1248 if (cfg->nvm_type != IWL_NVM_EXT)
1249 return le16_to_cpup(nvm_sw + SKU);
1250
1251 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000));
1252 }
1253
iwl_get_nvm_version(const struct iwl_cfg * cfg,const __le16 * nvm_sw)1254 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1255 {
1256 if (cfg->nvm_type != IWL_NVM_EXT)
1257 return le16_to_cpup(nvm_sw + NVM_VERSION);
1258 else
1259 return le32_to_cpup((const __le32 *)(nvm_sw +
1260 NVM_VERSION_EXT_NVM));
1261 }
1262
iwl_get_radio_cfg(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)1263 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1264 const __le16 *phy_sku)
1265 {
1266 if (cfg->nvm_type != IWL_NVM_EXT)
1267 return le16_to_cpup(nvm_sw + RADIO_CFG);
1268
1269 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
1270
1271 }
1272
iwl_get_n_hw_addrs(const struct iwl_cfg * cfg,const __le16 * nvm_sw)1273 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1274 {
1275 int n_hw_addr;
1276
1277 if (cfg->nvm_type != IWL_NVM_EXT)
1278 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
1279
1280 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
1281
1282 return n_hw_addr & N_HW_ADDR_MASK;
1283 }
1284
iwl_set_radio_cfg(const struct iwl_cfg * cfg,struct iwl_nvm_data * data,u32 radio_cfg)1285 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
1286 struct iwl_nvm_data *data,
1287 u32 radio_cfg)
1288 {
1289 if (cfg->nvm_type != IWL_NVM_EXT) {
1290 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
1291 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
1292 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
1293 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
1294 return;
1295 }
1296
1297 /* set the radio configuration for family 8000 */
1298 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
1299 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
1300 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
1301 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
1302 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
1303 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
1304 }
1305
iwl_flip_hw_address(__le32 mac_addr0,__le32 mac_addr1,u8 * dest)1306 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
1307 {
1308 const u8 *hw_addr;
1309
1310 hw_addr = (const u8 *)&mac_addr0;
1311 dest[0] = hw_addr[3];
1312 dest[1] = hw_addr[2];
1313 dest[2] = hw_addr[1];
1314 dest[3] = hw_addr[0];
1315
1316 hw_addr = (const u8 *)&mac_addr1;
1317 dest[4] = hw_addr[1];
1318 dest[5] = hw_addr[0];
1319 }
1320
iwl_set_hw_address_from_csr(struct iwl_trans * trans,struct iwl_nvm_data * data)1321 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
1322 struct iwl_nvm_data *data)
1323 {
1324 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
1325 CSR_MAC_ADDR0_STRAP(trans)));
1326 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
1327 CSR_MAC_ADDR1_STRAP(trans)));
1328
1329 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1330 /*
1331 * If the OEM fused a valid address, use it instead of the one in the
1332 * OTP
1333 */
1334 if (is_valid_ether_addr(data->hw_addr))
1335 return;
1336
1337 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
1338 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
1339
1340 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1341 }
1342
iwl_set_hw_address_family_8000(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * mac_override,const __be16 * nvm_hw)1343 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
1344 const struct iwl_cfg *cfg,
1345 struct iwl_nvm_data *data,
1346 const __le16 *mac_override,
1347 const __be16 *nvm_hw)
1348 {
1349 const u8 *hw_addr;
1350
1351 if (mac_override) {
1352 static const u8 reserved_mac[] = {
1353 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
1354 };
1355
1356 hw_addr = (const u8 *)(mac_override +
1357 MAC_ADDRESS_OVERRIDE_EXT_NVM);
1358
1359 /*
1360 * Store the MAC address from MAO section.
1361 * No byte swapping is required in MAO section
1362 */
1363 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
1364
1365 /*
1366 * Force the use of the OTP MAC address in case of reserved MAC
1367 * address in the NVM, or if address is given but invalid.
1368 */
1369 if (is_valid_ether_addr(data->hw_addr) &&
1370 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
1371 return;
1372
1373 IWL_ERR(trans,
1374 "mac address from nvm override section is not valid\n");
1375 }
1376
1377 if (nvm_hw) {
1378 /* read the mac address from WFMP registers */
1379 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1380 WFMP_MAC_ADDR_0));
1381 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1382 WFMP_MAC_ADDR_1));
1383
1384 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1385
1386 return;
1387 }
1388
1389 IWL_ERR(trans, "mac address is not found\n");
1390 }
1391
iwl_set_hw_address(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __be16 * nvm_hw,const __le16 * mac_override)1392 static int iwl_set_hw_address(struct iwl_trans *trans,
1393 const struct iwl_cfg *cfg,
1394 struct iwl_nvm_data *data, const __be16 *nvm_hw,
1395 const __le16 *mac_override)
1396 {
1397 if (cfg->mac_addr_from_csr) {
1398 iwl_set_hw_address_from_csr(trans, data);
1399 } else if (cfg->nvm_type != IWL_NVM_EXT) {
1400 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1401
1402 /* The byte order is little endian 16 bit, meaning 214365 */
1403 data->hw_addr[0] = hw_addr[1];
1404 data->hw_addr[1] = hw_addr[0];
1405 data->hw_addr[2] = hw_addr[3];
1406 data->hw_addr[3] = hw_addr[2];
1407 data->hw_addr[4] = hw_addr[5];
1408 data->hw_addr[5] = hw_addr[4];
1409 } else {
1410 iwl_set_hw_address_family_8000(trans, cfg, data,
1411 mac_override, nvm_hw);
1412 }
1413
1414 if (!is_valid_ether_addr(data->hw_addr)) {
1415 IWL_ERR(trans, "no valid mac address was found\n");
1416 return -EINVAL;
1417 }
1418
1419 if (!trans->csme_own)
1420 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n",
1421 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
1422
1423 return 0;
1424 }
1425
1426 static bool
iwl_nvm_no_wide_in_5ghz(struct iwl_trans * trans,const struct iwl_cfg * cfg,const __be16 * nvm_hw)1427 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1428 const __be16 *nvm_hw)
1429 {
1430 /*
1431 * Workaround a bug in Indonesia SKUs where the regulatory in
1432 * some 7000-family OTPs erroneously allow wide channels in
1433 * 5GHz. To check for Indonesia, we take the SKU value from
1434 * bits 1-4 in the subsystem ID and check if it is either 5 or
1435 * 9. In those cases, we need to force-disable wide channels
1436 * in 5GHz otherwise the FW will throw a sysassert when we try
1437 * to use them.
1438 */
1439 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1440 /*
1441 * Unlike the other sections in the NVM, the hw
1442 * section uses big-endian.
1443 */
1444 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1445 u8 sku = (subsystem_id & 0x1e) >> 1;
1446
1447 if (sku == 5 || sku == 9) {
1448 IWL_DEBUG_EEPROM(trans->dev,
1449 "disabling wide channels in 5GHz (0x%0x %d)\n",
1450 subsystem_id, sku);
1451 return true;
1452 }
1453 }
1454
1455 return false;
1456 }
1457
1458 struct iwl_nvm_data *
iwl_parse_mei_nvm_data(struct iwl_trans * trans,const struct iwl_cfg * cfg,const struct iwl_mei_nvm * mei_nvm,const struct iwl_fw * fw,u8 tx_ant,u8 rx_ant)1459 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1460 const struct iwl_mei_nvm *mei_nvm,
1461 const struct iwl_fw *fw, u8 tx_ant, u8 rx_ant)
1462 {
1463 struct iwl_nvm_data *data;
1464 u32 sbands_flags = 0;
1465 u8 rx_chains = fw->valid_rx_ant;
1466 u8 tx_chains = fw->valid_rx_ant;
1467
1468 if (cfg->uhb_supported)
1469 data = kzalloc(struct_size(data, channels,
1470 IWL_NVM_NUM_CHANNELS_UHB),
1471 GFP_KERNEL);
1472 else
1473 data = kzalloc(struct_size(data, channels,
1474 IWL_NVM_NUM_CHANNELS_EXT),
1475 GFP_KERNEL);
1476 if (!data)
1477 return NULL;
1478
1479 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) !=
1480 IWL_NVM_NUM_CHANNELS_UHB);
1481 data->nvm_version = mei_nvm->nvm_version;
1482
1483 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg);
1484 if (data->valid_tx_ant)
1485 tx_chains &= data->valid_tx_ant;
1486 if (data->valid_rx_ant)
1487 rx_chains &= data->valid_rx_ant;
1488 if (tx_ant)
1489 tx_chains &= tx_ant;
1490 if (rx_ant)
1491 rx_chains &= rx_ant;
1492
1493 data->sku_cap_mimo_disabled = false;
1494 data->sku_cap_band_24ghz_enable = true;
1495 data->sku_cap_band_52ghz_enable = true;
1496 data->sku_cap_11n_enable =
1497 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL);
1498 data->sku_cap_11ac_enable = true;
1499 data->sku_cap_11ax_enable =
1500 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT;
1501
1502 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT;
1503
1504 data->n_hw_addrs = mei_nvm->n_hw_addrs;
1505 /* If no valid mac address was found - bail out */
1506 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) {
1507 kfree(data);
1508 return NULL;
1509 }
1510
1511 if (data->lar_enabled &&
1512 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1513 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1514
1515 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains,
1516 sbands_flags, true, fw);
1517
1518 return data;
1519 }
1520 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data);
1521
1522 struct iwl_nvm_data *
iwl_parse_nvm_data(struct iwl_trans * trans,const struct iwl_cfg * cfg,const struct iwl_fw * fw,const __be16 * nvm_hw,const __le16 * nvm_sw,const __le16 * nvm_calib,const __le16 * regulatory,const __le16 * mac_override,const __le16 * phy_sku,u8 tx_chains,u8 rx_chains)1523 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1524 const struct iwl_fw *fw,
1525 const __be16 *nvm_hw, const __le16 *nvm_sw,
1526 const __le16 *nvm_calib, const __le16 *regulatory,
1527 const __le16 *mac_override, const __le16 *phy_sku,
1528 u8 tx_chains, u8 rx_chains)
1529 {
1530 struct iwl_nvm_data *data;
1531 bool lar_enabled;
1532 u32 sku, radio_cfg;
1533 u32 sbands_flags = 0;
1534 u16 lar_config;
1535 const __le16 *ch_section;
1536
1537 if (cfg->uhb_supported)
1538 data = kzalloc(struct_size(data, channels,
1539 IWL_NVM_NUM_CHANNELS_UHB),
1540 GFP_KERNEL);
1541 else if (cfg->nvm_type != IWL_NVM_EXT)
1542 data = kzalloc(struct_size(data, channels,
1543 IWL_NVM_NUM_CHANNELS),
1544 GFP_KERNEL);
1545 else
1546 data = kzalloc(struct_size(data, channels,
1547 IWL_NVM_NUM_CHANNELS_EXT),
1548 GFP_KERNEL);
1549 if (!data)
1550 return NULL;
1551
1552 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1553
1554 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1555 iwl_set_radio_cfg(cfg, data, radio_cfg);
1556 if (data->valid_tx_ant)
1557 tx_chains &= data->valid_tx_ant;
1558 if (data->valid_rx_ant)
1559 rx_chains &= data->valid_rx_ant;
1560
1561 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1562 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1563 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1564 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1565 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1566 data->sku_cap_11n_enable = false;
1567 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1568 (sku & NVM_SKU_CAP_11AC_ENABLE);
1569 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1570
1571 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1572
1573 if (cfg->nvm_type != IWL_NVM_EXT) {
1574 /* Checking for required sections */
1575 if (!nvm_calib) {
1576 IWL_ERR(trans,
1577 "Can't parse empty Calib NVM sections\n");
1578 kfree(data);
1579 return NULL;
1580 }
1581
1582 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1583 ®ulatory[NVM_CHANNELS_SDP] :
1584 &nvm_sw[NVM_CHANNELS];
1585
1586 lar_enabled = true;
1587 } else {
1588 u16 lar_offset = data->nvm_version < 0xE39 ?
1589 NVM_LAR_OFFSET_OLD :
1590 NVM_LAR_OFFSET;
1591
1592 lar_config = le16_to_cpup(regulatory + lar_offset);
1593 data->lar_enabled = !!(lar_config &
1594 NVM_LAR_ENABLED);
1595 lar_enabled = data->lar_enabled;
1596 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
1597 }
1598
1599 /* If no valid mac address was found - bail out */
1600 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1601 kfree(data);
1602 return NULL;
1603 }
1604
1605 if (lar_enabled &&
1606 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1607 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1608
1609 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1610 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1611
1612 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1613 sbands_flags, false, fw);
1614 data->calib_version = 255;
1615
1616 return data;
1617 }
1618 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1619
iwl_nvm_get_regdom_bw_flags(const u16 * nvm_chan,int ch_idx,u16 nvm_flags,struct iwl_reg_capa reg_capa,const struct iwl_cfg * cfg)1620 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1621 int ch_idx, u16 nvm_flags,
1622 struct iwl_reg_capa reg_capa,
1623 const struct iwl_cfg *cfg)
1624 {
1625 u32 flags = NL80211_RRF_NO_HT40;
1626
1627 if (ch_idx < NUM_2GHZ_CHANNELS &&
1628 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1629 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1630 flags &= ~NL80211_RRF_NO_HT40PLUS;
1631 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1632 flags &= ~NL80211_RRF_NO_HT40MINUS;
1633 } else if (ch_idx < NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS &&
1634 nvm_flags & NVM_CHANNEL_40MHZ) {
1635 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1636 flags &= ~NL80211_RRF_NO_HT40PLUS;
1637 else
1638 flags &= ~NL80211_RRF_NO_HT40MINUS;
1639 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1640 flags &= ~NL80211_RRF_NO_HT40PLUS;
1641 flags &= ~NL80211_RRF_NO_HT40MINUS;
1642 }
1643
1644 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1645 flags |= NL80211_RRF_NO_80MHZ;
1646 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1647 flags |= NL80211_RRF_NO_160MHZ;
1648
1649 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1650 flags |= NL80211_RRF_NO_IR;
1651
1652 if (nvm_flags & NVM_CHANNEL_RADAR)
1653 flags |= NL80211_RRF_DFS;
1654
1655 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1656 flags |= NL80211_RRF_NO_OUTDOOR;
1657
1658 /* Set the GO concurrent flag only in case that NO_IR is set.
1659 * Otherwise it is meaningless
1660 */
1661 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT)) {
1662 if (flags & NL80211_RRF_NO_IR)
1663 flags |= NL80211_RRF_GO_CONCURRENT;
1664 if (flags & NL80211_RRF_DFS) {
1665 flags |= NL80211_RRF_DFS_CONCURRENT;
1666 /* Our device doesn't set active bit for DFS channels
1667 * however, once marked as DFS no-ir is not needed.
1668 */
1669 flags &= ~NL80211_RRF_NO_IR;
1670 }
1671 }
1672
1673 /* Set the AP type for the UHB case. */
1674 if (nvm_flags & NVM_CHANNEL_VLP)
1675 flags |= NL80211_RRF_ALLOW_6GHZ_VLP_AP;
1676 else
1677 flags |= NL80211_RRF_NO_6GHZ_VLP_CLIENT;
1678
1679 if (!(nvm_flags & NVM_CHANNEL_AFC))
1680 flags |= NL80211_RRF_NO_6GHZ_AFC_CLIENT;
1681
1682 /*
1683 * reg_capa is per regulatory domain so apply it for every channel
1684 */
1685 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1686 if (!reg_capa.allow_40mhz)
1687 flags |= NL80211_RRF_NO_HT40;
1688
1689 if (!reg_capa.allow_80mhz)
1690 flags |= NL80211_RRF_NO_80MHZ;
1691
1692 if (!reg_capa.allow_160mhz)
1693 flags |= NL80211_RRF_NO_160MHZ;
1694
1695 if (!reg_capa.allow_320mhz)
1696 flags |= NL80211_RRF_NO_320MHZ;
1697 }
1698
1699 if (reg_capa.disable_11ax)
1700 flags |= NL80211_RRF_NO_HE;
1701
1702 if (reg_capa.disable_11be)
1703 flags |= NL80211_RRF_NO_EHT;
1704
1705 return flags;
1706 }
1707
iwl_get_reg_capa(u32 flags,u8 resp_ver)1708 static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver)
1709 {
1710 struct iwl_reg_capa reg_capa = {};
1711
1712 if (resp_ver >= REG_CAPA_V4_RESP_VER) {
1713 reg_capa.allow_40mhz = true;
1714 reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED;
1715 reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED;
1716 reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED;
1717 reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED;
1718 reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED;
1719 } else if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1720 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1721 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1722 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1723 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1724 } else {
1725 reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN);
1726 reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED;
1727 reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED;
1728 reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED;
1729 }
1730 return reg_capa;
1731 }
1732
1733 struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device * dev,const struct iwl_cfg * cfg,int num_of_ch,__le32 * channels,u16 fw_mcc,u16 geo_info,u32 cap,u8 resp_ver)1734 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1735 int num_of_ch, __le32 *channels, u16 fw_mcc,
1736 u16 geo_info, u32 cap, u8 resp_ver)
1737 {
1738 int ch_idx;
1739 u16 ch_flags;
1740 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1741 const u16 *nvm_chan;
1742 struct ieee80211_regdomain *regd, *copy_rd;
1743 struct ieee80211_reg_rule *rule;
1744 int center_freq, prev_center_freq = 0;
1745 int valid_rules = 0;
1746 bool new_rule;
1747 int max_num_ch;
1748 struct iwl_reg_capa reg_capa;
1749
1750 if (cfg->uhb_supported) {
1751 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1752 nvm_chan = iwl_uhb_nvm_channels;
1753 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1754 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1755 nvm_chan = iwl_ext_nvm_channels;
1756 } else {
1757 max_num_ch = IWL_NVM_NUM_CHANNELS;
1758 nvm_chan = iwl_nvm_channels;
1759 }
1760
1761 if (num_of_ch > max_num_ch) {
1762 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
1763 "Num of channels (%d) is greater than expected. Truncating to %d\n",
1764 num_of_ch, max_num_ch);
1765 num_of_ch = max_num_ch;
1766 }
1767
1768 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1769 return ERR_PTR(-EINVAL);
1770
1771 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1772 num_of_ch);
1773
1774 /* build a regdomain rule for every valid channel */
1775 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1776 if (!regd)
1777 return ERR_PTR(-ENOMEM);
1778
1779 /* set alpha2 from FW. */
1780 regd->alpha2[0] = fw_mcc >> 8;
1781 regd->alpha2[1] = fw_mcc & 0xff;
1782
1783 /* parse regulatory capability flags */
1784 reg_capa = iwl_get_reg_capa(cap, resp_ver);
1785
1786 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1787 enum nl80211_band band =
1788 iwl_nl80211_band_from_channel_idx(ch_idx);
1789
1790 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1791 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1792 band);
1793 new_rule = false;
1794
1795 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1796 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1797 nvm_chan[ch_idx], ch_flags);
1798 continue;
1799 }
1800
1801 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1802 ch_flags, reg_capa,
1803 cfg);
1804
1805 /* we can't continue the same rule */
1806 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1807 center_freq - prev_center_freq > 20) {
1808 valid_rules++;
1809 new_rule = true;
1810 }
1811
1812 rule = ®d->reg_rules[valid_rules - 1];
1813
1814 if (new_rule)
1815 rule->freq_range.start_freq_khz =
1816 MHZ_TO_KHZ(center_freq - 10);
1817
1818 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1819
1820 /* this doesn't matter - not used by FW */
1821 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1822 rule->power_rule.max_eirp =
1823 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1824
1825 rule->flags = reg_rule_flags;
1826
1827 /* rely on auto-calculation to merge BW of contiguous chans */
1828 rule->flags |= NL80211_RRF_AUTO_BW;
1829 rule->freq_range.max_bandwidth_khz = 0;
1830
1831 prev_center_freq = center_freq;
1832 prev_reg_rule_flags = reg_rule_flags;
1833
1834 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1835 nvm_chan[ch_idx], ch_flags);
1836
1837 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1838 band == NL80211_BAND_2GHZ)
1839 continue;
1840
1841 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1842 }
1843
1844 /*
1845 * Certain firmware versions might report no valid channels
1846 * if booted in RF-kill, i.e. not all calibrations etc. are
1847 * running. We'll get out of this situation later when the
1848 * rfkill is removed and we update the regdomain again, but
1849 * since cfg80211 doesn't accept an empty regdomain, add a
1850 * dummy (unusable) rule here in this case so we can init.
1851 */
1852 if (!valid_rules) {
1853 valid_rules = 1;
1854 rule = ®d->reg_rules[valid_rules - 1];
1855 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412);
1856 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413);
1857 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1);
1858 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1859 rule->power_rule.max_eirp =
1860 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1861 }
1862
1863 regd->n_reg_rules = valid_rules;
1864
1865 /*
1866 * Narrow down regdom for unused regulatory rules to prevent hole
1867 * between reg rules to wmm rules.
1868 */
1869 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1870 GFP_KERNEL);
1871 if (!copy_rd)
1872 copy_rd = ERR_PTR(-ENOMEM);
1873
1874 kfree(regd);
1875 return copy_rd;
1876 }
1877 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1878
1879 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1880 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1881 #define MAX_NVM_FILE_LEN 16384
1882
iwl_nvm_fixups(u32 hw_id,unsigned int section,u8 * data,unsigned int len)1883 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1884 unsigned int len)
1885 {
1886 #define IWL_4165_DEVICE_ID 0x5501
1887 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1888
1889 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1890 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1891 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1892 /* OTP 0x52 bug work around: it's a 1x1 device */
1893 data[3] = ANT_B | (ANT_B << 4);
1894 }
1895 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1896
1897 /*
1898 * Reads external NVM from a file into mvm->nvm_sections
1899 *
1900 * HOW TO CREATE THE NVM FILE FORMAT:
1901 * ------------------------------
1902 * 1. create hex file, format:
1903 * 3800 -> header
1904 * 0000 -> header
1905 * 5a40 -> data
1906 *
1907 * rev - 6 bit (word1)
1908 * len - 10 bit (word1)
1909 * id - 4 bit (word2)
1910 * rsv - 12 bit (word2)
1911 *
1912 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1913 *
1914 * 3. create binary file from the hex file
1915 *
1916 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1917 */
iwl_read_external_nvm(struct iwl_trans * trans,const char * nvm_file_name,struct iwl_nvm_section * nvm_sections)1918 int iwl_read_external_nvm(struct iwl_trans *trans,
1919 const char *nvm_file_name,
1920 struct iwl_nvm_section *nvm_sections)
1921 {
1922 int ret, section_size;
1923 u16 section_id;
1924 const struct firmware *fw_entry;
1925 const struct {
1926 __le16 word1;
1927 __le16 word2;
1928 u8 data[];
1929 } *file_sec;
1930 const u8 *eof;
1931 u8 *temp;
1932 int max_section_size;
1933 const __le32 *dword_buff;
1934
1935 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1936 #define NVM_WORD2_ID(x) (x >> 12)
1937 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1938 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1939 #define NVM_HEADER_0 (0x2A504C54)
1940 #define NVM_HEADER_1 (0x4E564D2A)
1941 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1942
1943 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1944
1945 /* Maximal size depends on NVM version */
1946 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1947 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1948 else
1949 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1950
1951 /*
1952 * Obtain NVM image via request_firmware. Since we already used
1953 * request_firmware_nowait() for the firmware binary load and only
1954 * get here after that we assume the NVM request can be satisfied
1955 * synchronously.
1956 */
1957 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1958 if (ret) {
1959 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1960 nvm_file_name, ret);
1961 return ret;
1962 }
1963
1964 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1965 nvm_file_name, fw_entry->size);
1966
1967 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1968 IWL_ERR(trans, "NVM file too large\n");
1969 ret = -EINVAL;
1970 goto out;
1971 }
1972
1973 eof = fw_entry->data + fw_entry->size;
1974 dword_buff = (const __le32 *)fw_entry->data;
1975
1976 /* some NVM file will contain a header.
1977 * The header is identified by 2 dwords header as follow:
1978 * dword[0] = 0x2A504C54
1979 * dword[1] = 0x4E564D2A
1980 *
1981 * This header must be skipped when providing the NVM data to the FW.
1982 */
1983 if (fw_entry->size > NVM_HEADER_SIZE &&
1984 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1985 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1986 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE);
1987 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1988 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1989 le32_to_cpu(dword_buff[3]));
1990
1991 /* nvm file validation, dword_buff[2] holds the file version */
1992 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1993 trans->hw_rev_step == SILICON_C_STEP &&
1994 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1995 ret = -EFAULT;
1996 goto out;
1997 }
1998 } else {
1999 file_sec = (const void *)fw_entry->data;
2000 }
2001
2002 while (true) {
2003 if (file_sec->data > eof) {
2004 IWL_ERR(trans,
2005 "ERROR - NVM file too short for section header\n");
2006 ret = -EINVAL;
2007 break;
2008 }
2009
2010 /* check for EOF marker */
2011 if (!file_sec->word1 && !file_sec->word2) {
2012 ret = 0;
2013 break;
2014 }
2015
2016 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
2017 section_size =
2018 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
2019 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
2020 } else {
2021 section_size = 2 * EXT_NVM_WORD2_LEN(
2022 le16_to_cpu(file_sec->word2));
2023 section_id = EXT_NVM_WORD1_ID(
2024 le16_to_cpu(file_sec->word1));
2025 }
2026
2027 if (section_size > max_section_size) {
2028 IWL_ERR(trans, "ERROR - section too large (%d)\n",
2029 section_size);
2030 ret = -EINVAL;
2031 break;
2032 }
2033
2034 if (!section_size) {
2035 IWL_ERR(trans, "ERROR - section empty\n");
2036 ret = -EINVAL;
2037 break;
2038 }
2039
2040 if (file_sec->data + section_size > eof) {
2041 IWL_ERR(trans,
2042 "ERROR - NVM file too short for section (%d bytes)\n",
2043 section_size);
2044 ret = -EINVAL;
2045 break;
2046 }
2047
2048 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
2049 "Invalid NVM section ID %d\n", section_id)) {
2050 ret = -EINVAL;
2051 break;
2052 }
2053
2054 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
2055 if (!temp) {
2056 ret = -ENOMEM;
2057 break;
2058 }
2059
2060 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
2061
2062 kfree(nvm_sections[section_id].data);
2063 nvm_sections[section_id].data = temp;
2064 nvm_sections[section_id].length = section_size;
2065
2066 /* advance to the next section */
2067 file_sec = (const void *)(file_sec->data + section_size);
2068 }
2069 out:
2070 release_firmware(fw_entry);
2071 return ret;
2072 }
2073 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
2074
iwl_get_nvm(struct iwl_trans * trans,const struct iwl_fw * fw,u8 set_tx_ant,u8 set_rx_ant)2075 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
2076 const struct iwl_fw *fw,
2077 u8 set_tx_ant, u8 set_rx_ant)
2078 {
2079 struct iwl_nvm_get_info cmd = {};
2080 struct iwl_nvm_data *nvm;
2081 struct iwl_host_cmd hcmd = {
2082 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
2083 .data = { &cmd, },
2084 .len = { sizeof(cmd) },
2085 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
2086 };
2087 int ret;
2088 bool empty_otp;
2089 u32 mac_flags;
2090 u32 sbands_flags = 0;
2091 u8 tx_ant;
2092 u8 rx_ant;
2093
2094 /*
2095 * All the values in iwl_nvm_get_info_rsp v4 are the same as
2096 * in v3, except for the channel profile part of the
2097 * regulatory. So we can just access the new struct, with the
2098 * exception of the latter.
2099 */
2100 struct iwl_nvm_get_info_rsp *rsp;
2101 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
2102 bool v4 = fw_has_api(&fw->ucode_capa,
2103 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
2104 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
2105 void *channel_profile;
2106
2107 ret = iwl_trans_send_cmd(trans, &hcmd);
2108 if (ret)
2109 return ERR_PTR(ret);
2110
2111 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
2112 "Invalid payload len in NVM response from FW %d",
2113 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
2114 ret = -EINVAL;
2115 goto out;
2116 }
2117
2118 rsp = (void *)hcmd.resp_pkt->data;
2119 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
2120 NVM_GENERAL_FLAGS_EMPTY_OTP);
2121 if (empty_otp)
2122 IWL_INFO(trans, "OTP is empty\n");
2123
2124 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
2125 if (!nvm) {
2126 ret = -ENOMEM;
2127 goto out;
2128 }
2129
2130 iwl_set_hw_address_from_csr(trans, nvm);
2131 /* TODO: if platform NVM has MAC address - override it here */
2132
2133 if (!is_valid_ether_addr(nvm->hw_addr)) {
2134 IWL_ERR(trans, "no valid mac address was found\n");
2135 ret = -EINVAL;
2136 goto err_free;
2137 }
2138
2139 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
2140
2141 /* Initialize general data */
2142 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
2143 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
2144 if (nvm->n_hw_addrs == 0)
2145 IWL_WARN(trans,
2146 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
2147 empty_otp);
2148
2149 /* Initialize MAC sku data */
2150 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
2151 nvm->sku_cap_11ac_enable =
2152 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
2153 nvm->sku_cap_11n_enable =
2154 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
2155 nvm->sku_cap_11ax_enable =
2156 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
2157 nvm->sku_cap_band_24ghz_enable =
2158 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
2159 nvm->sku_cap_band_52ghz_enable =
2160 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
2161 nvm->sku_cap_mimo_disabled =
2162 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
2163 if (CSR_HW_RFID_TYPE(trans->hw_rf_id) >= IWL_CFG_RF_TYPE_FM)
2164 nvm->sku_cap_11be_enable = true;
2165
2166 /* Initialize PHY sku data */
2167 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
2168 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
2169
2170 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
2171 fw_has_capa(&fw->ucode_capa,
2172 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
2173 nvm->lar_enabled = true;
2174 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
2175 }
2176
2177 rsp_v3 = (void *)rsp;
2178 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
2179 (void *)rsp_v3->regulatory.channel_profile;
2180
2181 tx_ant = nvm->valid_tx_ant & fw->valid_tx_ant;
2182 rx_ant = nvm->valid_rx_ant & fw->valid_rx_ant;
2183
2184 if (set_tx_ant)
2185 tx_ant &= set_tx_ant;
2186 if (set_rx_ant)
2187 rx_ant &= set_rx_ant;
2188
2189 iwl_init_sbands(trans, nvm, channel_profile, tx_ant, rx_ant,
2190 sbands_flags, v4, fw);
2191
2192 iwl_free_resp(&hcmd);
2193 return nvm;
2194
2195 err_free:
2196 kfree(nvm);
2197 out:
2198 iwl_free_resp(&hcmd);
2199 return ERR_PTR(ret);
2200 }
2201 IWL_EXPORT_SYMBOL(iwl_get_nvm);
2202