1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2015-2017 Intel Deutschland GmbH
4  * Copyright (C) 2018-2025 Intel Corporation
5  */
6 #include <linux/module.h>
7 #include <linux/stringify.h>
8 #include "iwl-config.h"
9 #include "iwl-prph.h"
10 #include "fw/api/txq.h"
11 
12 /* Highest firmware API version supported */
13 #define IWL_BZ_UCODE_API_MAX	98
14 
15 /* Lowest firmware API version supported */
16 #define IWL_BZ_UCODE_API_MIN	93
17 
18 /* NVM versions */
19 #define IWL_BZ_NVM_VERSION		0x0a1d
20 
21 /* Memory offsets and lengths */
22 #define IWL_BZ_DCCM_OFFSET		0x800000 /* LMAC1 */
23 #define IWL_BZ_DCCM_LEN			0x10000 /* LMAC1 */
24 #define IWL_BZ_DCCM2_OFFSET		0x880000
25 #define IWL_BZ_DCCM2_LEN		0x8000
26 #define IWL_BZ_SMEM_OFFSET		0x400000
27 #define IWL_BZ_SMEM_LEN			0xD0000
28 
29 #define IWL_BZ_A_HR_B_FW_PRE		"iwlwifi-bz-a0-hr-b0"
30 #define IWL_BZ_A_GF_A_FW_PRE		"iwlwifi-bz-a0-gf-a0"
31 #define IWL_BZ_A_GF4_A_FW_PRE		"iwlwifi-bz-a0-gf4-a0"
32 #define IWL_BZ_A_FM_B_FW_PRE		"iwlwifi-bz-a0-fm-b0"
33 #define IWL_BZ_A_FM_C_FW_PRE		"iwlwifi-bz-a0-fm-c0"
34 #define IWL_BZ_A_FM4_B_FW_PRE		"iwlwifi-bz-a0-fm4-b0"
35 #define IWL_GL_B_FM_B_FW_PRE		"iwlwifi-gl-b0-fm-b0"
36 #define IWL_GL_C_FM_C_FW_PRE		"iwlwifi-gl-c0-fm-c0"
37 
38 #define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
39 	IWL_BZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
40 
41 #if !IS_ENABLED(CONFIG_IWLMVM)
42 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
43 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
44 #endif
45 
46 static const struct iwl_base_params iwl_bz_base_params = {
47 	.eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
48 	.num_of_queues = 512,
49 	.max_tfd_queue_size = 65536,
50 	.shadow_ram_support = true,
51 	.led_compensation = 57,
52 	.wd_timeout = IWL_LONG_WD_TIMEOUT,
53 	.max_event_log_size = 512,
54 	.shadow_reg_enable = true,
55 	.pcie_l1_allowed = true,
56 };
57 
58 const struct iwl_ht_params iwl_bz_ht_params = {
59 	.stbc = true,
60 	.ldpc = true,
61 	.ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
62 		      BIT(NL80211_BAND_6GHZ),
63 };
64 
65 #define IWL_DEVICE_BZ_COMMON						\
66 	.ucode_api_max = IWL_BZ_UCODE_API_MAX,			\
67 	.ucode_api_min = IWL_BZ_UCODE_API_MIN,			\
68 	.led_mode = IWL_LED_RF_STATE,					\
69 	.nvm_hw_section_num = 10,					\
70 	.non_shared_ant = ANT_B,					\
71 	.dccm_offset = IWL_BZ_DCCM_OFFSET,				\
72 	.dccm_len = IWL_BZ_DCCM_LEN,					\
73 	.dccm2_offset = IWL_BZ_DCCM2_OFFSET,				\
74 	.dccm2_len = IWL_BZ_DCCM2_LEN,				\
75 	.smem_offset = IWL_BZ_SMEM_OFFSET,				\
76 	.smem_len = IWL_BZ_SMEM_LEN,					\
77 	.apmg_not_supported = true,					\
78 	.trans.mq_rx_supported = true,					\
79 	.vht_mu_mimo_supported = true,					\
80 	.mac_addr_from_csr = 0x30,					\
81 	.nvm_ver = IWL_BZ_NVM_VERSION,				\
82 	.trans.rf_id = true,						\
83 	.trans.gen2 = true,						\
84 	.nvm_type = IWL_NVM_EXT,					\
85 	.dbgc_supported = true,						\
86 	.min_umac_error_event_table = 0xD0000,				\
87 	.d3_debug_data_base_addr = 0x401000,				\
88 	.d3_debug_data_length = 60 * 1024,				\
89 	.mon_smem_regs = {						\
90 		.write_ptr = {						\
91 			.addr = LDBG_M2S_BUF_WPTR,			\
92 			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,		\
93 	},								\
94 		.cycle_cnt = {						\
95 			.addr = LDBG_M2S_BUF_WRAP_CNT,			\
96 			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,		\
97 		},							\
98 	},								\
99 	.trans.umac_prph_offset = 0x300000,				\
100 	.trans.device_family = IWL_DEVICE_FAMILY_BZ,			\
101 	.trans.base_params = &iwl_bz_base_params,			\
102 	.min_txq_size = 128,						\
103 	.gp2_reg_addr = 0xd02c68,					\
104 	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,			\
105 	.mon_dram_regs = {						\
106 		.write_ptr = {						\
107 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
108 			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,	\
109 		},							\
110 		.cycle_cnt = {						\
111 			.addr = DBGC_DBGBUF_WRAP_AROUND,		\
112 			.mask = 0xffffffff,				\
113 		},							\
114 		.cur_frag = {						\
115 			.addr = DBGC_CUR_DBGBUF_STATUS,			\
116 			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,		\
117 		},							\
118 	},								\
119 	.mon_dbgi_regs = {						\
120 		.write_ptr = {						\
121 			.addr = DBGI_SRAM_FIFO_POINTERS,		\
122 			.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,	\
123 		},							\
124 	}
125 
126 #define IWL_DEVICE_BZ							\
127 	IWL_DEVICE_BZ_COMMON,						\
128 	.ht_params = &iwl_bz_ht_params
129 
130 /*
131  * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an
132  * A-MPDU, with additional overhead to account for processing time.
133  */
134 #define IWL_NUM_RBDS_BZ_EHT		(512 * 16)
135 
136 const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
137 	.device_family = IWL_DEVICE_FAMILY_BZ,
138 	.base_params = &iwl_bz_base_params,
139 	.mq_rx_supported = true,
140 	.rf_id = true,
141 	.gen2 = true,
142 	.integrated = true,
143 	.umac_prph_offset = 0x300000,
144 	.xtal_latency = 12000,
145 	.low_latency_xtal = true,
146 	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
147 };
148 
149 const struct iwl_cfg_trans_params iwl_gl_trans_cfg = {
150 	.device_family = IWL_DEVICE_FAMILY_BZ,
151 	.base_params = &iwl_bz_base_params,
152 	.mq_rx_supported = true,
153 	.rf_id = true,
154 	.gen2 = true,
155 	.umac_prph_offset = 0x300000,
156 	.xtal_latency = 12000,
157 	.low_latency_xtal = true,
158 };
159 
160 const char iwl_fm_name[] = "Intel(R) Wi-Fi 7 BE201 320MHz";
161 const char iwl_wh_name[] = "Intel(R) Wi-Fi 7 BE211 320MHz";
162 const char iwl_gl_name[] = "Intel(R) Wi-Fi 7 BE200 320MHz";
163 const char iwl_mtp_name[] = "Intel(R) Wi-Fi 7 BE202 160MHz";
164 
165 const struct iwl_cfg iwl_cfg_bz = {
166 	.fw_name_mac = "bz",
167 	.uhb_supported = true,
168 	IWL_DEVICE_BZ,
169 	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
170 	.num_rbds = IWL_NUM_RBDS_BZ_EHT,
171 };
172 
173 const struct iwl_cfg iwl_cfg_gl = {
174 	.fw_name_mac = "gl",
175 	.uhb_supported = true,
176 	IWL_DEVICE_BZ,
177 	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
178 	.num_rbds = IWL_NUM_RBDS_BZ_EHT,
179 };
180 
181 MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_BZ_UCODE_API_MAX));
182 IWL_FW_AND_PNVM(IWL_BZ_A_GF_A_FW_PRE, IWL_BZ_UCODE_API_MAX);
183 IWL_FW_AND_PNVM(IWL_BZ_A_GF4_A_FW_PRE, IWL_BZ_UCODE_API_MAX);
184 IWL_FW_AND_PNVM(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
185 IWL_FW_AND_PNVM(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX);
186 IWL_FW_AND_PNVM(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
187 IWL_FW_AND_PNVM(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_API_MAX);
188 IWL_FW_AND_PNVM(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_API_MAX);
189