1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef ATH12K_REG_H
8 #define ATH12K_REG_H
9 
10 #include <linux/kernel.h>
11 #include <net/regulatory.h>
12 
13 struct ath12k_base;
14 struct ath12k;
15 
16 #define ATH12K_2GHZ_MAX_FREQUENCY	2495
17 #define ATH12K_5GHZ_MAX_FREQUENCY	5920
18 
19 /* DFS regdomains supported by Firmware */
20 enum ath12k_dfs_region {
21 	ATH12K_DFS_REG_UNSET,
22 	ATH12K_DFS_REG_FCC,
23 	ATH12K_DFS_REG_ETSI,
24 	ATH12K_DFS_REG_MKK,
25 	ATH12K_DFS_REG_CN,
26 	ATH12K_DFS_REG_KR,
27 	ATH12K_DFS_REG_MKK_N,
28 	ATH12K_DFS_REG_UNDEF,
29 };
30 
31 enum ath12k_reg_cc_code {
32 	REG_SET_CC_STATUS_PASS = 0,
33 	REG_CURRENT_ALPHA2_NOT_FOUND = 1,
34 	REG_INIT_ALPHA2_NOT_FOUND = 2,
35 	REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
36 	REG_SET_CC_STATUS_NO_MEMORY = 4,
37 	REG_SET_CC_STATUS_FAIL = 5,
38 };
39 
40 struct ath12k_reg_rule {
41 	u16 start_freq;
42 	u16 end_freq;
43 	u16 max_bw;
44 	u8 reg_power;
45 	u8 ant_gain;
46 	u16 flags;
47 	bool psd_flag;
48 	u16 psd_eirp;
49 };
50 
51 struct ath12k_reg_info {
52 	enum ath12k_reg_cc_code status_code;
53 	u8 num_phy;
54 	u8 phy_id;
55 	u16 reg_dmn_pair;
56 	u16 ctry_code;
57 	u8 alpha2[REG_ALPHA2_LEN + 1];
58 	u32 dfs_region;
59 	u32 phybitmap;
60 	bool is_ext_reg_event;
61 	u32 min_bw_2g;
62 	u32 max_bw_2g;
63 	u32 min_bw_5g;
64 	u32 max_bw_5g;
65 	u32 num_2g_reg_rules;
66 	u32 num_5g_reg_rules;
67 	struct ath12k_reg_rule *reg_rules_2g_ptr;
68 	struct ath12k_reg_rule *reg_rules_5g_ptr;
69 	enum wmi_reg_6g_client_type client_type;
70 	bool rnr_tpe_usable;
71 	bool unspecified_ap_usable;
72 	/* TODO: All 6G related info can be stored only for required
73 	 * combination instead of all types, to optimize memory usage.
74 	 */
75 	u8 domain_code_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
76 	u8 domain_code_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
77 	u32 domain_code_6g_super_id;
78 	u32 min_bw_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
79 	u32 max_bw_6g_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
80 	u32 min_bw_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
81 	u32 max_bw_6g_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
82 	u32 num_6g_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
83 	u32 num_6g_reg_rules_cl[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
84 	struct ath12k_reg_rule *reg_rules_6g_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE];
85 	struct ath12k_reg_rule *reg_rules_6g_client_ptr
86 		[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
87 };
88 
89 /* Phy bitmaps */
90 enum ath12k_reg_phy_bitmap {
91 	ATH12K_REG_PHY_BITMAP_NO11AX	= BIT(5),
92 	ATH12K_REG_PHY_BITMAP_NO11BE	= BIT(6),
93 };
94 
95 void ath12k_reg_init(struct ieee80211_hw *hw);
96 void ath12k_reg_free(struct ath12k_base *ab);
97 void ath12k_regd_update_work(struct work_struct *work);
98 struct ieee80211_regdomain *ath12k_reg_build_regd(struct ath12k_base *ab,
99 						  struct ath12k_reg_info *reg_info,
100 						  bool intersect);
101 int ath12k_regd_update(struct ath12k *ar, bool init);
102 int ath12k_reg_update_chan_list(struct ath12k *ar);
103 
104 #endif
105