1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477, lan8804
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/ethtool_netlink.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/phy.h>
27 #include <linux/micrel_phy.h>
28 #include <linux/of.h>
29 #include <linux/clk.h>
30 #include <linux/delay.h>
31 #include <linux/ptp_clock_kernel.h>
32 #include <linux/ptp_clock.h>
33 #include <linux/ptp_classify.h>
34 #include <linux/net_tstamp.h>
35 #include <linux/gpio/consumer.h>
36
37 #include "phylib.h"
38
39 /* Operation Mode Strap Override */
40 #define MII_KSZPHY_OMSO 0x16
41 #define KSZPHY_OMSO_FACTORY_TEST BIT(15)
42 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
43 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
44 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
45 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
46
47 /* general Interrupt control/status reg in vendor specific block. */
48 #define MII_KSZPHY_INTCS 0x1B
49 #define KSZPHY_INTCS_JABBER BIT(15)
50 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
51 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
52 #define KSZPHY_INTCS_PARELLEL BIT(12)
53 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
54 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
55 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
56 #define KSZPHY_INTCS_LINK_UP BIT(8)
57 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
58 KSZPHY_INTCS_LINK_DOWN)
59 #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
60 #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
61 #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
62 KSZPHY_INTCS_LINK_UP_STATUS)
63
64 /* LinkMD Control/Status */
65 #define KSZ8081_LMD 0x1d
66 #define KSZ8081_LMD_ENABLE_TEST BIT(15)
67 #define KSZ8081_LMD_STAT_NORMAL 0
68 #define KSZ8081_LMD_STAT_OPEN 1
69 #define KSZ8081_LMD_STAT_SHORT 2
70 #define KSZ8081_LMD_STAT_FAIL 3
71 #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
72 /* Short cable (<10 meter) has been detected by LinkMD */
73 #define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
74 #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
75
76 #define KSZ9x31_LMD 0x12
77 #define KSZ9x31_LMD_VCT_EN BIT(15)
78 #define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
79 #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
80 #define KSZ9x31_LMD_VCT_SEL_RESULT 0
81 #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
82 #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
83 #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
84 #define KSZ9x31_LMD_VCT_ST_NORMAL 0
85 #define KSZ9x31_LMD_VCT_ST_OPEN 1
86 #define KSZ9x31_LMD_VCT_ST_SHORT 2
87 #define KSZ9x31_LMD_VCT_ST_FAIL 3
88 #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
89 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
90 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
91 #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
92 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
93 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
94 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
95 #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
96
97 #define KSZPHY_WIRE_PAIR_MASK 0x3
98
99 #define LAN8814_CABLE_DIAG 0x12
100 #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
101 #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
102 #define LAN8814_PAIR_BIT_SHIFT 12
103
104 #define LAN8814_WIRE_PAIR_MASK 0xF
105
106 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
107 #define LAN8814_INTC 0x18
108 #define LAN8814_INTS 0x1B
109
110 #define LAN8814_INT_LINK_DOWN BIT(2)
111 #define LAN8814_INT_LINK_UP BIT(0)
112 #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
113 LAN8814_INT_LINK_DOWN)
114
115 #define LAN8814_INTR_CTRL_REG 0x34
116 #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
117 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
118
119 #define LAN8814_EEE_STATE 0x38
120 #define LAN8814_EEE_STATE_MASK2P5P BIT(10)
121
122 #define LAN8814_PD_CONTROLS 0x9d
123 #define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)
124 #define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb
125
126 /* Represents 1ppm adjustment in 2^32 format with
127 * each nsec contains 4 clock cycles.
128 * The value is calculated as following: (1/1000000)/((2^-32)/4)
129 */
130 #define LAN8814_1PPM_FORMAT 17179
131
132 /* Represents 1ppm adjustment in 2^32 format with
133 * each nsec contains 8 clock cycles.
134 * The value is calculated as following: (1/1000000)/((2^-32)/8)
135 */
136 #define LAN8841_1PPM_FORMAT 34360
137
138 #define PTP_RX_VERSION 0x0248
139 #define PTP_TX_VERSION 0x0288
140 #define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
141 #define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
142
143 #define PTP_RX_MOD 0x024F
144 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
145 #define PTP_RX_TIMESTAMP_EN 0x024D
146 #define PTP_TX_TIMESTAMP_EN 0x028D
147
148 #define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
149 #define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
150 #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
151 #define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
152
153 #define PTP_TX_PARSE_L2_ADDR_EN 0x0284
154 #define PTP_RX_PARSE_L2_ADDR_EN 0x0244
155
156 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285
157 #define PTP_RX_PARSE_IP_ADDR_EN 0x0245
158 #define LTC_HARD_RESET 0x023F
159 #define LTC_HARD_RESET_ BIT(0)
160
161 #define TSU_HARD_RESET 0x02C1
162 #define TSU_HARD_RESET_ BIT(0)
163
164 #define PTP_CMD_CTL 0x0200
165 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
166 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
167 #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
168 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
169 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
170 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
171
172 #define PTP_COMMON_INT_ENA 0x0204
173 #define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2)
174
175 #define PTP_CLOCK_SET_SEC_HI 0x0205
176 #define PTP_CLOCK_SET_SEC_MID 0x0206
177 #define PTP_CLOCK_SET_SEC_LO 0x0207
178 #define PTP_CLOCK_SET_NS_HI 0x0208
179 #define PTP_CLOCK_SET_NS_LO 0x0209
180
181 #define PTP_CLOCK_READ_SEC_HI 0x0229
182 #define PTP_CLOCK_READ_SEC_MID 0x022A
183 #define PTP_CLOCK_READ_SEC_LO 0x022B
184 #define PTP_CLOCK_READ_NS_HI 0x022C
185 #define PTP_CLOCK_READ_NS_LO 0x022D
186
187 #define PTP_GPIO_SEL 0x0230
188 #define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8)
189 #define PTP_GPIO_CAP_MAP_LO 0x0232
190
191 #define PTP_GPIO_CAP_EN 0x0233
192 #define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio)
193 #define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
194
195 #define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235
196 #define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236
197 #define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237
198 #define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238
199 #define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239
200 #define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A
201 #define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B
202 #define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C
203
204 #define PTP_GPIO_CAP_STS 0x023D
205 #define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio)
206 #define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8)
207
208 #define PTP_OPERATING_MODE 0x0241
209 #define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
210
211 #define PTP_TX_MOD 0x028F
212 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
213 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
214
215 #define PTP_RX_PARSE_CONFIG 0x0242
216 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
217 #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
218 #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
219
220 #define PTP_TX_PARSE_CONFIG 0x0282
221 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
222 #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
223 #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
224
225 #define PTP_CLOCK_RATE_ADJ_HI 0x020C
226 #define PTP_CLOCK_RATE_ADJ_LO 0x020D
227 #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
228
229 #define PTP_LTC_STEP_ADJ_HI 0x0212
230 #define PTP_LTC_STEP_ADJ_LO 0x0213
231 #define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
232
233 #define LAN8814_INTR_STS_REG 0x0033
234 #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
235 #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
236 #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
237 #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
238
239 #define PTP_CAP_INFO 0x022A
240 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
241 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
242
243 #define PTP_TX_EGRESS_SEC_HI 0x0296
244 #define PTP_TX_EGRESS_SEC_LO 0x0297
245 #define PTP_TX_EGRESS_NS_HI 0x0294
246 #define PTP_TX_EGRESS_NS_LO 0x0295
247 #define PTP_TX_MSG_HEADER2 0x0299
248
249 #define PTP_RX_INGRESS_SEC_HI 0x0256
250 #define PTP_RX_INGRESS_SEC_LO 0x0257
251 #define PTP_RX_INGRESS_NS_HI 0x0254
252 #define PTP_RX_INGRESS_NS_LO 0x0255
253 #define PTP_RX_MSG_HEADER2 0x0259
254
255 #define PTP_TSU_INT_EN 0x0200
256 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
257 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
258 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
259 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
260
261 #define PTP_TSU_INT_STS 0x0201
262 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
263 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
264 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
265 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
266
267 #define LAN8814_LED_CTRL_1 0x0
268 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
269
270 /* PHY Control 1 */
271 #define MII_KSZPHY_CTRL_1 0x1e
272 #define KSZ8081_CTRL1_MDIX_STAT BIT(4)
273
274 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
275 #define MII_KSZPHY_CTRL_2 0x1f
276 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
277 /* bitmap of PHY register to set interrupt mode */
278 #define KSZ8081_CTRL2_HP_MDIX BIT(15)
279 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
280 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
281 #define KSZ8081_CTRL2_FORCE_LINK BIT(11)
282 #define KSZ8081_CTRL2_POWER_SAVING BIT(10)
283 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
284 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
285
286 /* Write/read to/from extended registers */
287 #define MII_KSZPHY_EXTREG 0x0b
288 #define KSZPHY_EXTREG_WRITE 0x8000
289
290 #define MII_KSZPHY_EXTREG_WRITE 0x0c
291 #define MII_KSZPHY_EXTREG_READ 0x0d
292
293 /* Extended registers */
294 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
295 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
296 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
297
298 #define PS_TO_REG 200
299 #define FIFO_SIZE 8
300
301 #define LAN8814_PTP_GPIO_NUM 24
302 #define LAN8814_PTP_PEROUT_NUM 2
303 #define LAN8814_PTP_EXTTS_NUM 3
304
305 #define LAN8814_BUFFER_TIME 2
306
307 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
308 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
309 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
310 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
311 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
312 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
313 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
314 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
315 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
316 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
317 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
318 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
319 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
320 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
321
322 #define LAN8814_GPIO_EN1 0x20
323 #define LAN8814_GPIO_EN2 0x21
324 #define LAN8814_GPIO_DIR1 0x22
325 #define LAN8814_GPIO_DIR2 0x23
326 #define LAN8814_GPIO_BUF1 0x24
327 #define LAN8814_GPIO_BUF2 0x25
328
329 #define LAN8814_GPIO_EN_ADDR(pin) \
330 ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
331 #define LAN8814_GPIO_EN_BIT(pin) BIT(pin)
332 #define LAN8814_GPIO_DIR_ADDR(pin) \
333 ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
334 #define LAN8814_GPIO_DIR_BIT(pin) BIT(pin)
335 #define LAN8814_GPIO_BUF_ADDR(pin) \
336 ((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)
337 #define LAN8814_GPIO_BUF_BIT(pin) BIT(pin)
338
339 #define LAN8814_EVENT_A 0
340 #define LAN8814_EVENT_B 1
341
342 #define LAN8814_PTP_GENERAL_CONFIG 0x0201
343 #define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \
344 ((event) ? GENMASK(11, 8) : GENMASK(7, 4))
345 #define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \
346 (((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))
347 #define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \
348 ((event) ? BIT(2) : BIT(0))
349 #define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \
350 ((event) ? BIT(3) : BIT(1))
351
352 #define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215)
353 #define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216)
354 #define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217)
355 #define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218)
356
357 #define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219)
358 #define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A)
359 #define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B)
360 #define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C)
361
362 /* Delay used to get the second part from the LTC */
363 #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
364
365 struct kszphy_hw_stat {
366 const char *string;
367 u8 reg;
368 u8 bits;
369 };
370
371 static struct kszphy_hw_stat kszphy_hw_stats[] = {
372 { "phy_receive_errors", 21, 16},
373 { "phy_idle_errors", 10, 8 },
374 };
375
376 struct kszphy_type {
377 u32 led_mode_reg;
378 u16 interrupt_level_mask;
379 u16 cable_diag_reg;
380 unsigned long pair_mask;
381 u16 disable_dll_tx_bit;
382 u16 disable_dll_rx_bit;
383 u16 disable_dll_mask;
384 bool has_broadcast_disable;
385 bool has_nand_tree_disable;
386 bool has_rmii_ref_clk_sel;
387 };
388
389 /* Shared structure between the PHYs of the same package. */
390 struct lan8814_shared_priv {
391 struct phy_device *phydev;
392 struct ptp_clock *ptp_clock;
393 struct ptp_clock_info ptp_clock_info;
394 struct ptp_pin_desc *pin_config;
395
396 /* Lock for ptp_clock */
397 struct mutex shared_lock;
398 };
399
400 struct lan8814_ptp_rx_ts {
401 struct list_head list;
402 u32 seconds;
403 u32 nsec;
404 u16 seq_id;
405 };
406
407 struct kszphy_ptp_priv {
408 struct mii_timestamper mii_ts;
409 struct phy_device *phydev;
410
411 struct sk_buff_head tx_queue;
412 struct sk_buff_head rx_queue;
413
414 struct list_head rx_ts_list;
415 /* Lock for Rx ts fifo */
416 spinlock_t rx_ts_lock;
417
418 int hwts_tx_type;
419 enum hwtstamp_rx_filters rx_filter;
420 int layer;
421 int version;
422
423 struct ptp_clock *ptp_clock;
424 struct ptp_clock_info ptp_clock_info;
425 /* Lock for ptp_clock */
426 struct mutex ptp_lock;
427 struct ptp_pin_desc *pin_config;
428
429 s64 seconds;
430 /* Lock for accessing seconds */
431 spinlock_t seconds_lock;
432 };
433
434 struct kszphy_priv {
435 struct kszphy_ptp_priv ptp_priv;
436 const struct kszphy_type *type;
437 struct clk *clk;
438 int led_mode;
439 u16 vct_ctrl1000;
440 bool rmii_ref_clk_sel;
441 bool rmii_ref_clk_sel_val;
442 bool clk_enable;
443 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
444 };
445
446 static const struct kszphy_type lan8814_type = {
447 .led_mode_reg = ~LAN8814_LED_CTRL_1,
448 .cable_diag_reg = LAN8814_CABLE_DIAG,
449 .pair_mask = LAN8814_WIRE_PAIR_MASK,
450 };
451
452 static const struct kszphy_type ksz886x_type = {
453 .cable_diag_reg = KSZ8081_LMD,
454 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
455 };
456
457 static const struct kszphy_type ksz8021_type = {
458 .led_mode_reg = MII_KSZPHY_CTRL_2,
459 .has_broadcast_disable = true,
460 .has_nand_tree_disable = true,
461 .has_rmii_ref_clk_sel = true,
462 };
463
464 static const struct kszphy_type ksz8041_type = {
465 .led_mode_reg = MII_KSZPHY_CTRL_1,
466 };
467
468 static const struct kszphy_type ksz8051_type = {
469 .led_mode_reg = MII_KSZPHY_CTRL_2,
470 .has_nand_tree_disable = true,
471 };
472
473 static const struct kszphy_type ksz8081_type = {
474 .led_mode_reg = MII_KSZPHY_CTRL_2,
475 .has_broadcast_disable = true,
476 .has_nand_tree_disable = true,
477 .has_rmii_ref_clk_sel = true,
478 };
479
480 static const struct kszphy_type ks8737_type = {
481 .interrupt_level_mask = BIT(14),
482 };
483
484 static const struct kszphy_type ksz9021_type = {
485 .interrupt_level_mask = BIT(14),
486 };
487
488 static const struct kszphy_type ksz9131_type = {
489 .interrupt_level_mask = BIT(14),
490 .disable_dll_tx_bit = BIT(12),
491 .disable_dll_rx_bit = BIT(12),
492 .disable_dll_mask = BIT_MASK(12),
493 };
494
495 static const struct kszphy_type lan8841_type = {
496 .disable_dll_tx_bit = BIT(14),
497 .disable_dll_rx_bit = BIT(14),
498 .disable_dll_mask = BIT_MASK(14),
499 .cable_diag_reg = LAN8814_CABLE_DIAG,
500 .pair_mask = LAN8814_WIRE_PAIR_MASK,
501 };
502
kszphy_extended_write(struct phy_device * phydev,u32 regnum,u16 val)503 static int kszphy_extended_write(struct phy_device *phydev,
504 u32 regnum, u16 val)
505 {
506 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
507 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
508 }
509
kszphy_extended_read(struct phy_device * phydev,u32 regnum)510 static int kszphy_extended_read(struct phy_device *phydev,
511 u32 regnum)
512 {
513 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
514 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
515 }
516
kszphy_ack_interrupt(struct phy_device * phydev)517 static int kszphy_ack_interrupt(struct phy_device *phydev)
518 {
519 /* bit[7..0] int status, which is a read and clear register. */
520 int rc;
521
522 rc = phy_read(phydev, MII_KSZPHY_INTCS);
523
524 return (rc < 0) ? rc : 0;
525 }
526
kszphy_config_intr(struct phy_device * phydev)527 static int kszphy_config_intr(struct phy_device *phydev)
528 {
529 const struct kszphy_type *type = phydev->drv->driver_data;
530 int temp, err;
531 u16 mask;
532
533 if (type && type->interrupt_level_mask)
534 mask = type->interrupt_level_mask;
535 else
536 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
537
538 /* set the interrupt pin active low */
539 temp = phy_read(phydev, MII_KSZPHY_CTRL);
540 if (temp < 0)
541 return temp;
542 temp &= ~mask;
543 phy_write(phydev, MII_KSZPHY_CTRL, temp);
544
545 /* enable / disable interrupts */
546 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
547 err = kszphy_ack_interrupt(phydev);
548 if (err)
549 return err;
550
551 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
552 } else {
553 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
554 if (err)
555 return err;
556
557 err = kszphy_ack_interrupt(phydev);
558 }
559
560 return err;
561 }
562
kszphy_handle_interrupt(struct phy_device * phydev)563 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
564 {
565 int irq_status;
566
567 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
568 if (irq_status < 0) {
569 phy_error(phydev);
570 return IRQ_NONE;
571 }
572
573 if (!(irq_status & KSZPHY_INTCS_STATUS))
574 return IRQ_NONE;
575
576 phy_trigger_machine(phydev);
577
578 return IRQ_HANDLED;
579 }
580
kszphy_rmii_clk_sel(struct phy_device * phydev,bool val)581 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
582 {
583 int ctrl;
584
585 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
586 if (ctrl < 0)
587 return ctrl;
588
589 if (val)
590 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
591 else
592 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
593
594 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
595 }
596
kszphy_setup_led(struct phy_device * phydev,u32 reg,int val)597 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
598 {
599 int rc, temp, shift;
600
601 switch (reg) {
602 case MII_KSZPHY_CTRL_1:
603 shift = 14;
604 break;
605 case MII_KSZPHY_CTRL_2:
606 shift = 4;
607 break;
608 default:
609 return -EINVAL;
610 }
611
612 temp = phy_read(phydev, reg);
613 if (temp < 0) {
614 rc = temp;
615 goto out;
616 }
617
618 temp &= ~(3 << shift);
619 temp |= val << shift;
620 rc = phy_write(phydev, reg, temp);
621 out:
622 if (rc < 0)
623 phydev_err(phydev, "failed to set led mode\n");
624
625 return rc;
626 }
627
628 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
629 * unique (non-broadcast) address on a shared bus.
630 */
kszphy_broadcast_disable(struct phy_device * phydev)631 static int kszphy_broadcast_disable(struct phy_device *phydev)
632 {
633 int ret;
634
635 ret = phy_read(phydev, MII_KSZPHY_OMSO);
636 if (ret < 0)
637 goto out;
638
639 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
640 out:
641 if (ret)
642 phydev_err(phydev, "failed to disable broadcast address\n");
643
644 return ret;
645 }
646
kszphy_nand_tree_disable(struct phy_device * phydev)647 static int kszphy_nand_tree_disable(struct phy_device *phydev)
648 {
649 int ret;
650
651 ret = phy_read(phydev, MII_KSZPHY_OMSO);
652 if (ret < 0)
653 goto out;
654
655 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
656 return 0;
657
658 ret = phy_write(phydev, MII_KSZPHY_OMSO,
659 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
660 out:
661 if (ret)
662 phydev_err(phydev, "failed to disable NAND tree mode\n");
663
664 return ret;
665 }
666
667 /* Some config bits need to be set again on resume, handle them here. */
kszphy_config_reset(struct phy_device * phydev)668 static int kszphy_config_reset(struct phy_device *phydev)
669 {
670 struct kszphy_priv *priv = phydev->priv;
671 int ret;
672
673 if (priv->rmii_ref_clk_sel) {
674 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
675 if (ret) {
676 phydev_err(phydev,
677 "failed to set rmii reference clock\n");
678 return ret;
679 }
680 }
681
682 if (priv->type && priv->led_mode >= 0)
683 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
684
685 return 0;
686 }
687
kszphy_config_init(struct phy_device * phydev)688 static int kszphy_config_init(struct phy_device *phydev)
689 {
690 struct kszphy_priv *priv = phydev->priv;
691 const struct kszphy_type *type;
692
693 if (!priv)
694 return 0;
695
696 type = priv->type;
697
698 if (type && type->has_broadcast_disable)
699 kszphy_broadcast_disable(phydev);
700
701 if (type && type->has_nand_tree_disable)
702 kszphy_nand_tree_disable(phydev);
703
704 return kszphy_config_reset(phydev);
705 }
706
ksz8041_fiber_mode(struct phy_device * phydev)707 static int ksz8041_fiber_mode(struct phy_device *phydev)
708 {
709 struct device_node *of_node = phydev->mdio.dev.of_node;
710
711 return of_property_read_bool(of_node, "micrel,fiber-mode");
712 }
713
ksz8041_config_init(struct phy_device * phydev)714 static int ksz8041_config_init(struct phy_device *phydev)
715 {
716 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
717
718 /* Limit supported and advertised modes in fiber mode */
719 if (ksz8041_fiber_mode(phydev)) {
720 phydev->dev_flags |= MICREL_PHY_FXEN;
721 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
722 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
723
724 linkmode_and(phydev->supported, phydev->supported, mask);
725 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
726 phydev->supported);
727 linkmode_and(phydev->advertising, phydev->advertising, mask);
728 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
729 phydev->advertising);
730 phydev->autoneg = AUTONEG_DISABLE;
731 }
732
733 return kszphy_config_init(phydev);
734 }
735
ksz8041_config_aneg(struct phy_device * phydev)736 static int ksz8041_config_aneg(struct phy_device *phydev)
737 {
738 /* Skip auto-negotiation in fiber mode */
739 if (phydev->dev_flags & MICREL_PHY_FXEN) {
740 phydev->speed = SPEED_100;
741 return 0;
742 }
743
744 return genphy_config_aneg(phydev);
745 }
746
ksz8051_ksz8795_match_phy_device(struct phy_device * phydev,const bool ksz_8051)747 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
748 const bool ksz_8051)
749 {
750 int ret;
751
752 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
753 return 0;
754
755 ret = phy_read(phydev, MII_BMSR);
756 if (ret < 0)
757 return ret;
758
759 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
760 * exact PHY ID. However, they can be told apart by the extended
761 * capability registers presence. The KSZ8051 PHY has them while
762 * the switch does not.
763 */
764 ret &= BMSR_ERCAP;
765 if (ksz_8051)
766 return ret;
767 else
768 return !ret;
769 }
770
ksz8051_match_phy_device(struct phy_device * phydev)771 static int ksz8051_match_phy_device(struct phy_device *phydev)
772 {
773 return ksz8051_ksz8795_match_phy_device(phydev, true);
774 }
775
ksz8081_config_init(struct phy_device * phydev)776 static int ksz8081_config_init(struct phy_device *phydev)
777 {
778 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
779 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
780 * pull-down is missing, the factory test mode should be cleared by
781 * manually writing a 0.
782 */
783 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
784
785 return kszphy_config_init(phydev);
786 }
787
ksz8081_config_mdix(struct phy_device * phydev,u8 ctrl)788 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
789 {
790 u16 val;
791
792 switch (ctrl) {
793 case ETH_TP_MDI:
794 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
795 break;
796 case ETH_TP_MDI_X:
797 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
798 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
799 break;
800 case ETH_TP_MDI_AUTO:
801 val = 0;
802 break;
803 default:
804 return 0;
805 }
806
807 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
808 KSZ8081_CTRL2_HP_MDIX |
809 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
810 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
811 KSZ8081_CTRL2_HP_MDIX | val);
812 }
813
ksz8081_config_aneg(struct phy_device * phydev)814 static int ksz8081_config_aneg(struct phy_device *phydev)
815 {
816 int ret;
817
818 ret = genphy_config_aneg(phydev);
819 if (ret)
820 return ret;
821
822 /* The MDI-X configuration is automatically changed by the PHY after
823 * switching from autoneg off to on. So, take MDI-X configuration under
824 * own control and set it after autoneg configuration was done.
825 */
826 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
827 }
828
ksz8081_mdix_update(struct phy_device * phydev)829 static int ksz8081_mdix_update(struct phy_device *phydev)
830 {
831 int ret;
832
833 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
834 if (ret < 0)
835 return ret;
836
837 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
838 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
839 phydev->mdix_ctrl = ETH_TP_MDI_X;
840 else
841 phydev->mdix_ctrl = ETH_TP_MDI;
842 } else {
843 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
844 }
845
846 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
847 if (ret < 0)
848 return ret;
849
850 if (ret & KSZ8081_CTRL1_MDIX_STAT)
851 phydev->mdix = ETH_TP_MDI;
852 else
853 phydev->mdix = ETH_TP_MDI_X;
854
855 return 0;
856 }
857
ksz8081_read_status(struct phy_device * phydev)858 static int ksz8081_read_status(struct phy_device *phydev)
859 {
860 int ret;
861
862 ret = ksz8081_mdix_update(phydev);
863 if (ret < 0)
864 return ret;
865
866 return genphy_read_status(phydev);
867 }
868
ksz8061_config_init(struct phy_device * phydev)869 static int ksz8061_config_init(struct phy_device *phydev)
870 {
871 int ret;
872
873 /* Chip can be powered down by the bootstrap code. */
874 ret = phy_read(phydev, MII_BMCR);
875 if (ret < 0)
876 return ret;
877 if (ret & BMCR_PDOWN) {
878 ret = phy_write(phydev, MII_BMCR, ret & ~BMCR_PDOWN);
879 if (ret < 0)
880 return ret;
881 usleep_range(1000, 2000);
882 }
883
884 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
885 if (ret)
886 return ret;
887
888 return kszphy_config_init(phydev);
889 }
890
ksz8795_match_phy_device(struct phy_device * phydev)891 static int ksz8795_match_phy_device(struct phy_device *phydev)
892 {
893 return ksz8051_ksz8795_match_phy_device(phydev, false);
894 }
895
ksz9021_load_values_from_of(struct phy_device * phydev,const struct device_node * of_node,u16 reg,const char * field1,const char * field2,const char * field3,const char * field4)896 static int ksz9021_load_values_from_of(struct phy_device *phydev,
897 const struct device_node *of_node,
898 u16 reg,
899 const char *field1, const char *field2,
900 const char *field3, const char *field4)
901 {
902 int val1 = -1;
903 int val2 = -2;
904 int val3 = -3;
905 int val4 = -4;
906 int newval;
907 int matches = 0;
908
909 if (!of_property_read_u32(of_node, field1, &val1))
910 matches++;
911
912 if (!of_property_read_u32(of_node, field2, &val2))
913 matches++;
914
915 if (!of_property_read_u32(of_node, field3, &val3))
916 matches++;
917
918 if (!of_property_read_u32(of_node, field4, &val4))
919 matches++;
920
921 if (!matches)
922 return 0;
923
924 if (matches < 4)
925 newval = kszphy_extended_read(phydev, reg);
926 else
927 newval = 0;
928
929 if (val1 != -1)
930 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
931
932 if (val2 != -2)
933 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
934
935 if (val3 != -3)
936 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
937
938 if (val4 != -4)
939 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
940
941 return kszphy_extended_write(phydev, reg, newval);
942 }
943
ksz9021_config_init(struct phy_device * phydev)944 static int ksz9021_config_init(struct phy_device *phydev)
945 {
946 const struct device_node *of_node;
947 const struct device *dev_walker;
948
949 /* The Micrel driver has a deprecated option to place phy OF
950 * properties in the MAC node. Walk up the tree of devices to
951 * find a device with an OF node.
952 */
953 dev_walker = &phydev->mdio.dev;
954 do {
955 of_node = dev_walker->of_node;
956 dev_walker = dev_walker->parent;
957
958 } while (!of_node && dev_walker);
959
960 if (of_node) {
961 ksz9021_load_values_from_of(phydev, of_node,
962 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
963 "txen-skew-ps", "txc-skew-ps",
964 "rxdv-skew-ps", "rxc-skew-ps");
965 ksz9021_load_values_from_of(phydev, of_node,
966 MII_KSZPHY_RX_DATA_PAD_SKEW,
967 "rxd0-skew-ps", "rxd1-skew-ps",
968 "rxd2-skew-ps", "rxd3-skew-ps");
969 ksz9021_load_values_from_of(phydev, of_node,
970 MII_KSZPHY_TX_DATA_PAD_SKEW,
971 "txd0-skew-ps", "txd1-skew-ps",
972 "txd2-skew-ps", "txd3-skew-ps");
973 }
974 return 0;
975 }
976
977 #define KSZ9031_PS_TO_REG 60
978
979 /* Extended registers */
980 /* MMD Address 0x0 */
981 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
982 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
983
984 /* MMD Address 0x2 */
985 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
986 #define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
987 #define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
988
989 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
990 #define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
991 #define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
992 #define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
993 #define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
994
995 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
996 #define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
997 #define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
998 #define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
999 #define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
1000
1001 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
1002 #define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
1003 #define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
1004
1005 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
1006 * provide different RGMII options we need to configure delay offset
1007 * for each pad relative to build in delay.
1008 */
1009 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
1010 * 1.80ns
1011 */
1012 #define RX_ID 0x7
1013 #define RX_CLK_ID 0x19
1014
1015 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
1016 * internal 1.2ns delay.
1017 */
1018 #define RX_ND 0xc
1019 #define RX_CLK_ND 0x0
1020
1021 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
1022 #define TX_ID 0x0
1023 #define TX_CLK_ID 0x1f
1024
1025 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
1026 * dealy
1027 */
1028 #define TX_ND 0x7
1029 #define TX_CLK_ND 0xf
1030
1031 /* MMD Address 0x1C */
1032 #define MII_KSZ9031RN_EDPD 0x23
1033 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
1034
ksz9031_set_loopback(struct phy_device * phydev,bool enable,int speed)1035 static int ksz9031_set_loopback(struct phy_device *phydev, bool enable,
1036 int speed)
1037 {
1038 u16 ctl = BMCR_LOOPBACK;
1039 int val;
1040
1041 if (!enable)
1042 return genphy_loopback(phydev, enable, 0);
1043
1044 if (speed == SPEED_10 || speed == SPEED_100 || speed == SPEED_1000)
1045 phydev->speed = speed;
1046 else if (speed)
1047 return -EINVAL;
1048 phydev->duplex = DUPLEX_FULL;
1049
1050 ctl |= mii_bmcr_encode_fixed(phydev->speed, phydev->duplex);
1051
1052 phy_write(phydev, MII_BMCR, ctl);
1053
1054 return phy_read_poll_timeout(phydev, MII_BMSR, val, val & BMSR_LSTATUS,
1055 5000, 500000, true);
1056 }
1057
ksz9031_of_load_skew_values(struct phy_device * phydev,const struct device_node * of_node,u16 reg,size_t field_sz,const char * field[],u8 numfields,bool * update)1058 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
1059 const struct device_node *of_node,
1060 u16 reg, size_t field_sz,
1061 const char *field[], u8 numfields,
1062 bool *update)
1063 {
1064 int val[4] = {-1, -2, -3, -4};
1065 int matches = 0;
1066 u16 mask;
1067 u16 maxval;
1068 u16 newval;
1069 int i;
1070
1071 for (i = 0; i < numfields; i++)
1072 if (!of_property_read_u32(of_node, field[i], val + i))
1073 matches++;
1074
1075 if (!matches)
1076 return 0;
1077
1078 *update |= true;
1079
1080 if (matches < numfields)
1081 newval = phy_read_mmd(phydev, 2, reg);
1082 else
1083 newval = 0;
1084
1085 maxval = (field_sz == 4) ? 0xf : 0x1f;
1086 for (i = 0; i < numfields; i++)
1087 if (val[i] != -(i + 1)) {
1088 mask = 0xffff;
1089 mask ^= maxval << (field_sz * i);
1090 newval = (newval & mask) |
1091 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
1092 << (field_sz * i));
1093 }
1094
1095 return phy_write_mmd(phydev, 2, reg, newval);
1096 }
1097
1098 /* Center KSZ9031RNX FLP timing at 16ms. */
ksz9031_center_flp_timing(struct phy_device * phydev)1099 static int ksz9031_center_flp_timing(struct phy_device *phydev)
1100 {
1101 int result;
1102
1103 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
1104 0x0006);
1105 if (result)
1106 return result;
1107
1108 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
1109 0x1A80);
1110 if (result)
1111 return result;
1112
1113 return genphy_restart_aneg(phydev);
1114 }
1115
1116 /* Enable energy-detect power-down mode */
ksz9031_enable_edpd(struct phy_device * phydev)1117 static int ksz9031_enable_edpd(struct phy_device *phydev)
1118 {
1119 int reg;
1120
1121 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
1122 if (reg < 0)
1123 return reg;
1124 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
1125 reg | MII_KSZ9031RN_EDPD_ENABLE);
1126 }
1127
ksz9031_config_rgmii_delay(struct phy_device * phydev)1128 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1129 {
1130 u16 rx, tx, rx_clk, tx_clk;
1131 int ret;
1132
1133 switch (phydev->interface) {
1134 case PHY_INTERFACE_MODE_RGMII:
1135 tx = TX_ND;
1136 tx_clk = TX_CLK_ND;
1137 rx = RX_ND;
1138 rx_clk = RX_CLK_ND;
1139 break;
1140 case PHY_INTERFACE_MODE_RGMII_ID:
1141 tx = TX_ID;
1142 tx_clk = TX_CLK_ID;
1143 rx = RX_ID;
1144 rx_clk = RX_CLK_ID;
1145 break;
1146 case PHY_INTERFACE_MODE_RGMII_RXID:
1147 tx = TX_ND;
1148 tx_clk = TX_CLK_ND;
1149 rx = RX_ID;
1150 rx_clk = RX_CLK_ID;
1151 break;
1152 case PHY_INTERFACE_MODE_RGMII_TXID:
1153 tx = TX_ID;
1154 tx_clk = TX_CLK_ID;
1155 rx = RX_ND;
1156 rx_clk = RX_CLK_ND;
1157 break;
1158 default:
1159 return 0;
1160 }
1161
1162 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1163 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1164 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1165 if (ret < 0)
1166 return ret;
1167
1168 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1169 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1170 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1171 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1172 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1173 if (ret < 0)
1174 return ret;
1175
1176 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1177 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1178 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1179 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1180 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1181 if (ret < 0)
1182 return ret;
1183
1184 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1185 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1186 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1187 }
1188
ksz9031_config_init(struct phy_device * phydev)1189 static int ksz9031_config_init(struct phy_device *phydev)
1190 {
1191 const struct device_node *of_node;
1192 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1193 static const char *rx_data_skews[4] = {
1194 "rxd0-skew-ps", "rxd1-skew-ps",
1195 "rxd2-skew-ps", "rxd3-skew-ps"
1196 };
1197 static const char *tx_data_skews[4] = {
1198 "txd0-skew-ps", "txd1-skew-ps",
1199 "txd2-skew-ps", "txd3-skew-ps"
1200 };
1201 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1202 const struct device *dev_walker;
1203 int result;
1204
1205 result = ksz9031_enable_edpd(phydev);
1206 if (result < 0)
1207 return result;
1208
1209 /* The Micrel driver has a deprecated option to place phy OF
1210 * properties in the MAC node. Walk up the tree of devices to
1211 * find a device with an OF node.
1212 */
1213 dev_walker = &phydev->mdio.dev;
1214 do {
1215 of_node = dev_walker->of_node;
1216 dev_walker = dev_walker->parent;
1217 } while (!of_node && dev_walker);
1218
1219 if (of_node) {
1220 bool update = false;
1221
1222 if (phy_interface_is_rgmii(phydev)) {
1223 result = ksz9031_config_rgmii_delay(phydev);
1224 if (result < 0)
1225 return result;
1226 }
1227
1228 ksz9031_of_load_skew_values(phydev, of_node,
1229 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1230 clk_skews, 2, &update);
1231
1232 ksz9031_of_load_skew_values(phydev, of_node,
1233 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1234 control_skews, 2, &update);
1235
1236 ksz9031_of_load_skew_values(phydev, of_node,
1237 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1238 rx_data_skews, 4, &update);
1239
1240 ksz9031_of_load_skew_values(phydev, of_node,
1241 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1242 tx_data_skews, 4, &update);
1243
1244 if (update && !phy_interface_is_rgmii(phydev))
1245 phydev_warn(phydev,
1246 "*-skew-ps values should be used only with RGMII PHY modes\n");
1247
1248 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1249 * When the device links in the 1000BASE-T slave mode only,
1250 * the optional 125MHz reference output clock (CLK125_NDO)
1251 * has wide duty cycle variation.
1252 *
1253 * The optional CLK125_NDO clock does not meet the RGMII
1254 * 45/55 percent (min/max) duty cycle requirement and therefore
1255 * cannot be used directly by the MAC side for clocking
1256 * applications that have setup/hold time requirements on
1257 * rising and falling clock edges.
1258 *
1259 * Workaround:
1260 * Force the phy to be the master to receive a stable clock
1261 * which meets the duty cycle requirement.
1262 */
1263 if (of_property_read_bool(of_node, "micrel,force-master")) {
1264 result = phy_read(phydev, MII_CTRL1000);
1265 if (result < 0)
1266 goto err_force_master;
1267
1268 /* enable master mode, config & prefer master */
1269 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1270 result = phy_write(phydev, MII_CTRL1000, result);
1271 if (result < 0)
1272 goto err_force_master;
1273 }
1274 }
1275
1276 return ksz9031_center_flp_timing(phydev);
1277
1278 err_force_master:
1279 phydev_err(phydev, "failed to force the phy to master mode\n");
1280 return result;
1281 }
1282
1283 #define KSZ9131_SKEW_5BIT_MAX 2400
1284 #define KSZ9131_SKEW_4BIT_MAX 800
1285 #define KSZ9131_OFFSET 700
1286 #define KSZ9131_STEP 100
1287
ksz9131_of_load_skew_values(struct phy_device * phydev,struct device_node * of_node,u16 reg,size_t field_sz,char * field[],u8 numfields)1288 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1289 struct device_node *of_node,
1290 u16 reg, size_t field_sz,
1291 char *field[], u8 numfields)
1292 {
1293 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1294 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1295 int skewval, skewmax = 0;
1296 int matches = 0;
1297 u16 maxval;
1298 u16 newval;
1299 u16 mask;
1300 int i;
1301
1302 /* psec properties in dts should mean x pico seconds */
1303 if (field_sz == 5)
1304 skewmax = KSZ9131_SKEW_5BIT_MAX;
1305 else
1306 skewmax = KSZ9131_SKEW_4BIT_MAX;
1307
1308 for (i = 0; i < numfields; i++)
1309 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1310 if (skewval < -KSZ9131_OFFSET)
1311 skewval = -KSZ9131_OFFSET;
1312 else if (skewval > skewmax)
1313 skewval = skewmax;
1314
1315 val[i] = skewval + KSZ9131_OFFSET;
1316 matches++;
1317 }
1318
1319 if (!matches)
1320 return 0;
1321
1322 if (matches < numfields)
1323 newval = phy_read_mmd(phydev, 2, reg);
1324 else
1325 newval = 0;
1326
1327 maxval = (field_sz == 4) ? 0xf : 0x1f;
1328 for (i = 0; i < numfields; i++)
1329 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1330 mask = 0xffff;
1331 mask ^= maxval << (field_sz * i);
1332 newval = (newval & mask) |
1333 (((val[i] / KSZ9131_STEP) & maxval)
1334 << (field_sz * i));
1335 }
1336
1337 return phy_write_mmd(phydev, 2, reg, newval);
1338 }
1339
1340 #define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1341 #define KSZ9131RN_RXC_DLL_CTRL 76
1342 #define KSZ9131RN_TXC_DLL_CTRL 77
1343 #define KSZ9131RN_DLL_ENABLE_DELAY 0
1344
ksz9131_config_rgmii_delay(struct phy_device * phydev)1345 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1346 {
1347 const struct kszphy_type *type = phydev->drv->driver_data;
1348 u16 rxcdll_val, txcdll_val;
1349 int ret;
1350
1351 switch (phydev->interface) {
1352 case PHY_INTERFACE_MODE_RGMII:
1353 rxcdll_val = type->disable_dll_rx_bit;
1354 txcdll_val = type->disable_dll_tx_bit;
1355 break;
1356 case PHY_INTERFACE_MODE_RGMII_ID:
1357 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1358 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1359 break;
1360 case PHY_INTERFACE_MODE_RGMII_RXID:
1361 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1362 txcdll_val = type->disable_dll_tx_bit;
1363 break;
1364 case PHY_INTERFACE_MODE_RGMII_TXID:
1365 rxcdll_val = type->disable_dll_rx_bit;
1366 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1367 break;
1368 default:
1369 return 0;
1370 }
1371
1372 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1373 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1374 rxcdll_val);
1375 if (ret < 0)
1376 return ret;
1377
1378 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1379 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1380 txcdll_val);
1381 }
1382
1383 /* Silicon Errata DS80000693B
1384 *
1385 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1386 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1387 * according to the datasheet (off if there is no link).
1388 */
ksz9131_led_errata(struct phy_device * phydev)1389 static int ksz9131_led_errata(struct phy_device *phydev)
1390 {
1391 int reg;
1392
1393 reg = phy_read_mmd(phydev, 2, 0);
1394 if (reg < 0)
1395 return reg;
1396
1397 if (!(reg & BIT(4)))
1398 return 0;
1399
1400 return phy_set_bits(phydev, 0x1e, BIT(9));
1401 }
1402
ksz9131_config_init(struct phy_device * phydev)1403 static int ksz9131_config_init(struct phy_device *phydev)
1404 {
1405 struct device_node *of_node;
1406 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1407 char *rx_data_skews[4] = {
1408 "rxd0-skew-psec", "rxd1-skew-psec",
1409 "rxd2-skew-psec", "rxd3-skew-psec"
1410 };
1411 char *tx_data_skews[4] = {
1412 "txd0-skew-psec", "txd1-skew-psec",
1413 "txd2-skew-psec", "txd3-skew-psec"
1414 };
1415 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1416 const struct device *dev_walker;
1417 int ret;
1418
1419 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1420
1421 dev_walker = &phydev->mdio.dev;
1422 do {
1423 of_node = dev_walker->of_node;
1424 dev_walker = dev_walker->parent;
1425 } while (!of_node && dev_walker);
1426
1427 if (!of_node)
1428 return 0;
1429
1430 if (phy_interface_is_rgmii(phydev)) {
1431 ret = ksz9131_config_rgmii_delay(phydev);
1432 if (ret < 0)
1433 return ret;
1434 }
1435
1436 ret = ksz9131_of_load_skew_values(phydev, of_node,
1437 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1438 clk_skews, 2);
1439 if (ret < 0)
1440 return ret;
1441
1442 ret = ksz9131_of_load_skew_values(phydev, of_node,
1443 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1444 control_skews, 2);
1445 if (ret < 0)
1446 return ret;
1447
1448 ret = ksz9131_of_load_skew_values(phydev, of_node,
1449 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1450 rx_data_skews, 4);
1451 if (ret < 0)
1452 return ret;
1453
1454 ret = ksz9131_of_load_skew_values(phydev, of_node,
1455 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1456 tx_data_skews, 4);
1457 if (ret < 0)
1458 return ret;
1459
1460 ret = ksz9131_led_errata(phydev);
1461 if (ret < 0)
1462 return ret;
1463
1464 return 0;
1465 }
1466
1467 #define MII_KSZ9131_AUTO_MDIX 0x1C
1468 #define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1469 #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1470 #define MII_KSZ9131_DIG_AXAN_STS 0x14
1471 #define MII_KSZ9131_DIG_AXAN_STS_LINK_DET BIT(14)
1472 #define MII_KSZ9131_DIG_AXAN_STS_A_SELECT BIT(12)
1473
ksz9131_mdix_update(struct phy_device * phydev)1474 static int ksz9131_mdix_update(struct phy_device *phydev)
1475 {
1476 int ret;
1477
1478 if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {
1479 phydev->mdix = phydev->mdix_ctrl;
1480 } else {
1481 ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);
1482 if (ret < 0)
1483 return ret;
1484
1485 if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {
1486 if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)
1487 phydev->mdix = ETH_TP_MDI;
1488 else
1489 phydev->mdix = ETH_TP_MDI_X;
1490 } else {
1491 phydev->mdix = ETH_TP_MDI_INVALID;
1492 }
1493 }
1494
1495 return 0;
1496 }
1497
ksz9131_config_mdix(struct phy_device * phydev,u8 ctrl)1498 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1499 {
1500 u16 val;
1501
1502 switch (ctrl) {
1503 case ETH_TP_MDI:
1504 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1505 MII_KSZ9131_AUTO_MDI_SET;
1506 break;
1507 case ETH_TP_MDI_X:
1508 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1509 break;
1510 case ETH_TP_MDI_AUTO:
1511 val = 0;
1512 break;
1513 default:
1514 return 0;
1515 }
1516
1517 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1518 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1519 MII_KSZ9131_AUTO_MDI_SET, val);
1520 }
1521
ksz9131_read_status(struct phy_device * phydev)1522 static int ksz9131_read_status(struct phy_device *phydev)
1523 {
1524 int ret;
1525
1526 ret = ksz9131_mdix_update(phydev);
1527 if (ret < 0)
1528 return ret;
1529
1530 return genphy_read_status(phydev);
1531 }
1532
ksz9131_config_aneg(struct phy_device * phydev)1533 static int ksz9131_config_aneg(struct phy_device *phydev)
1534 {
1535 int ret;
1536
1537 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1538 if (ret)
1539 return ret;
1540
1541 return genphy_config_aneg(phydev);
1542 }
1543
ksz9477_get_features(struct phy_device * phydev)1544 static int ksz9477_get_features(struct phy_device *phydev)
1545 {
1546 int ret;
1547
1548 ret = genphy_read_abilities(phydev);
1549 if (ret)
1550 return ret;
1551
1552 /* The "EEE control and capability 1" (Register 3.20) seems to be
1553 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1554 * on the 7.60 will affect 3.20. So, we need to construct our own list
1555 * of caps.
1556 * KSZ8563R should have 100BaseTX/Full only.
1557 */
1558 linkmode_and(phydev->supported_eee, phydev->supported,
1559 PHY_EEE_CAP1_FEATURES);
1560
1561 return 0;
1562 }
1563
1564 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1565 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1566 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
ksz8873mll_read_status(struct phy_device * phydev)1567 static int ksz8873mll_read_status(struct phy_device *phydev)
1568 {
1569 int regval;
1570
1571 /* dummy read */
1572 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1573
1574 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1575
1576 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1577 phydev->duplex = DUPLEX_HALF;
1578 else
1579 phydev->duplex = DUPLEX_FULL;
1580
1581 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1582 phydev->speed = SPEED_10;
1583 else
1584 phydev->speed = SPEED_100;
1585
1586 phydev->link = 1;
1587 phydev->pause = phydev->asym_pause = 0;
1588
1589 return 0;
1590 }
1591
ksz9031_get_features(struct phy_device * phydev)1592 static int ksz9031_get_features(struct phy_device *phydev)
1593 {
1594 int ret;
1595
1596 ret = genphy_read_abilities(phydev);
1597 if (ret < 0)
1598 return ret;
1599
1600 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1601 * Whenever the device's Asymmetric Pause capability is set to 1,
1602 * link-up may fail after a link-up to link-down transition.
1603 *
1604 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1605 *
1606 * Workaround:
1607 * Do not enable the Asymmetric Pause capability bit.
1608 */
1609 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1610
1611 /* We force setting the Pause capability as the core will force the
1612 * Asymmetric Pause capability to 1 otherwise.
1613 */
1614 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1615
1616 return 0;
1617 }
1618
ksz9031_read_status(struct phy_device * phydev)1619 static int ksz9031_read_status(struct phy_device *phydev)
1620 {
1621 int err;
1622 int regval;
1623
1624 err = genphy_read_status(phydev);
1625 if (err)
1626 return err;
1627
1628 /* Make sure the PHY is not broken. Read idle error count,
1629 * and reset the PHY if it is maxed out.
1630 */
1631 regval = phy_read(phydev, MII_STAT1000);
1632 if ((regval & 0xFF) == 0xFF) {
1633 phy_init_hw(phydev);
1634 phydev->link = 0;
1635 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1636 phydev->drv->config_intr(phydev);
1637 return genphy_config_aneg(phydev);
1638 }
1639
1640 return 0;
1641 }
1642
ksz9x31_cable_test_start(struct phy_device * phydev)1643 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1644 {
1645 struct kszphy_priv *priv = phydev->priv;
1646 int ret;
1647
1648 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1649 * Prior to running the cable diagnostics, Auto-negotiation should
1650 * be disabled, full duplex set and the link speed set to 1000Mbps
1651 * via the Basic Control Register.
1652 */
1653 ret = phy_modify(phydev, MII_BMCR,
1654 BMCR_SPEED1000 | BMCR_FULLDPLX |
1655 BMCR_ANENABLE | BMCR_SPEED100,
1656 BMCR_SPEED1000 | BMCR_FULLDPLX);
1657 if (ret)
1658 return ret;
1659
1660 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1661 * The Master-Slave configuration should be set to Slave by writing
1662 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1663 * Register.
1664 */
1665 ret = phy_read(phydev, MII_CTRL1000);
1666 if (ret < 0)
1667 return ret;
1668
1669 /* Cache these bits, they need to be restored once LinkMD finishes. */
1670 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1671 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1672 ret |= CTL1000_ENABLE_MASTER;
1673
1674 return phy_write(phydev, MII_CTRL1000, ret);
1675 }
1676
ksz9x31_cable_test_result_trans(u16 status)1677 static int ksz9x31_cable_test_result_trans(u16 status)
1678 {
1679 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1680 case KSZ9x31_LMD_VCT_ST_NORMAL:
1681 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1682 case KSZ9x31_LMD_VCT_ST_OPEN:
1683 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1684 case KSZ9x31_LMD_VCT_ST_SHORT:
1685 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1686 case KSZ9x31_LMD_VCT_ST_FAIL:
1687 fallthrough;
1688 default:
1689 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1690 }
1691 }
1692
ksz9x31_cable_test_failed(u16 status)1693 static bool ksz9x31_cable_test_failed(u16 status)
1694 {
1695 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1696
1697 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1698 }
1699
ksz9x31_cable_test_fault_length_valid(u16 status)1700 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1701 {
1702 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1703 case KSZ9x31_LMD_VCT_ST_OPEN:
1704 fallthrough;
1705 case KSZ9x31_LMD_VCT_ST_SHORT:
1706 return true;
1707 }
1708 return false;
1709 }
1710
ksz9x31_cable_test_fault_length(struct phy_device * phydev,u16 stat)1711 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1712 {
1713 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1714
1715 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1716 *
1717 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1718 */
1719 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1720 dt = clamp(dt - 22, 0, 255);
1721
1722 return (dt * 400) / 10;
1723 }
1724
ksz9x31_cable_test_wait_for_completion(struct phy_device * phydev)1725 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1726 {
1727 int val, ret;
1728
1729 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1730 !(val & KSZ9x31_LMD_VCT_EN),
1731 30000, 100000, true);
1732
1733 return ret < 0 ? ret : 0;
1734 }
1735
ksz9x31_cable_test_get_pair(int pair)1736 static int ksz9x31_cable_test_get_pair(int pair)
1737 {
1738 static const int ethtool_pair[] = {
1739 ETHTOOL_A_CABLE_PAIR_A,
1740 ETHTOOL_A_CABLE_PAIR_B,
1741 ETHTOOL_A_CABLE_PAIR_C,
1742 ETHTOOL_A_CABLE_PAIR_D,
1743 };
1744
1745 return ethtool_pair[pair];
1746 }
1747
ksz9x31_cable_test_one_pair(struct phy_device * phydev,int pair)1748 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1749 {
1750 int ret, val;
1751
1752 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1753 * To test each individual cable pair, set the cable pair in the Cable
1754 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1755 * Diagnostic Register, along with setting the Cable Diagnostics Test
1756 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1757 * will self clear when the test is concluded.
1758 */
1759 ret = phy_write(phydev, KSZ9x31_LMD,
1760 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1761 if (ret)
1762 return ret;
1763
1764 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1765 if (ret)
1766 return ret;
1767
1768 val = phy_read(phydev, KSZ9x31_LMD);
1769 if (val < 0)
1770 return val;
1771
1772 if (ksz9x31_cable_test_failed(val))
1773 return -EAGAIN;
1774
1775 ret = ethnl_cable_test_result(phydev,
1776 ksz9x31_cable_test_get_pair(pair),
1777 ksz9x31_cable_test_result_trans(val));
1778 if (ret)
1779 return ret;
1780
1781 if (!ksz9x31_cable_test_fault_length_valid(val))
1782 return 0;
1783
1784 return ethnl_cable_test_fault_length(phydev,
1785 ksz9x31_cable_test_get_pair(pair),
1786 ksz9x31_cable_test_fault_length(phydev, val));
1787 }
1788
ksz9x31_cable_test_get_status(struct phy_device * phydev,bool * finished)1789 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1790 bool *finished)
1791 {
1792 struct kszphy_priv *priv = phydev->priv;
1793 unsigned long pair_mask = 0xf;
1794 int retries = 20;
1795 int pair, ret, rv;
1796
1797 *finished = false;
1798
1799 /* Try harder if link partner is active */
1800 while (pair_mask && retries--) {
1801 for_each_set_bit(pair, &pair_mask, 4) {
1802 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1803 if (ret == -EAGAIN)
1804 continue;
1805 if (ret < 0)
1806 return ret;
1807 clear_bit(pair, &pair_mask);
1808 }
1809 /* If link partner is in autonegotiation mode it will send 2ms
1810 * of FLPs with at least 6ms of silence.
1811 * Add 2ms sleep to have better chances to hit this silence.
1812 */
1813 if (pair_mask)
1814 usleep_range(2000, 3000);
1815 }
1816
1817 /* Report remaining unfinished pair result as unknown. */
1818 for_each_set_bit(pair, &pair_mask, 4) {
1819 ret = ethnl_cable_test_result(phydev,
1820 ksz9x31_cable_test_get_pair(pair),
1821 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1822 }
1823
1824 *finished = true;
1825
1826 /* Restore cached bits from before LinkMD got started. */
1827 rv = phy_modify(phydev, MII_CTRL1000,
1828 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1829 priv->vct_ctrl1000);
1830 if (rv)
1831 return rv;
1832
1833 return ret;
1834 }
1835
ksz8873mll_config_aneg(struct phy_device * phydev)1836 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1837 {
1838 return 0;
1839 }
1840
ksz886x_config_mdix(struct phy_device * phydev,u8 ctrl)1841 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1842 {
1843 u16 val;
1844
1845 switch (ctrl) {
1846 case ETH_TP_MDI:
1847 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1848 break;
1849 case ETH_TP_MDI_X:
1850 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1851 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1852 * sheet seems to be missing:
1853 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1854 * 0 = Normal operation (transmit on TX+/TX- pins)
1855 */
1856 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1857 break;
1858 case ETH_TP_MDI_AUTO:
1859 val = 0;
1860 break;
1861 default:
1862 return 0;
1863 }
1864
1865 return phy_modify(phydev, MII_BMCR,
1866 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1867 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1868 KSZ886X_BMCR_HP_MDIX | val);
1869 }
1870
ksz886x_config_aneg(struct phy_device * phydev)1871 static int ksz886x_config_aneg(struct phy_device *phydev)
1872 {
1873 int ret;
1874
1875 ret = genphy_config_aneg(phydev);
1876 if (ret)
1877 return ret;
1878
1879 if (phydev->autoneg != AUTONEG_ENABLE) {
1880 /* When autonegotation is disabled, we need to manually force
1881 * the link state. If we don't do this, the PHY will keep
1882 * sending Fast Link Pulses (FLPs) which are part of the
1883 * autonegotiation process. This is not desired when
1884 * autonegotiation is off.
1885 */
1886 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1887 KSZ886X_CTRL_FORCE_LINK);
1888 if (ret)
1889 return ret;
1890 } else {
1891 /* If we had previously forced the link state, we need to
1892 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1893 * will not perform autonegotiation.
1894 */
1895 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1896 KSZ886X_CTRL_FORCE_LINK);
1897 if (ret)
1898 return ret;
1899 }
1900
1901 /* The MDI-X configuration is automatically changed by the PHY after
1902 * switching from autoneg off to on. So, take MDI-X configuration under
1903 * own control and set it after autoneg configuration was done.
1904 */
1905 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1906 }
1907
ksz886x_mdix_update(struct phy_device * phydev)1908 static int ksz886x_mdix_update(struct phy_device *phydev)
1909 {
1910 int ret;
1911
1912 ret = phy_read(phydev, MII_BMCR);
1913 if (ret < 0)
1914 return ret;
1915
1916 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1917 if (ret & KSZ886X_BMCR_FORCE_MDI)
1918 phydev->mdix_ctrl = ETH_TP_MDI_X;
1919 else
1920 phydev->mdix_ctrl = ETH_TP_MDI;
1921 } else {
1922 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1923 }
1924
1925 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1926 if (ret < 0)
1927 return ret;
1928
1929 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1930 if (ret & KSZ886X_CTRL_MDIX_STAT)
1931 phydev->mdix = ETH_TP_MDI_X;
1932 else
1933 phydev->mdix = ETH_TP_MDI;
1934
1935 return 0;
1936 }
1937
ksz886x_read_status(struct phy_device * phydev)1938 static int ksz886x_read_status(struct phy_device *phydev)
1939 {
1940 int ret;
1941
1942 ret = ksz886x_mdix_update(phydev);
1943 if (ret < 0)
1944 return ret;
1945
1946 return genphy_read_status(phydev);
1947 }
1948
1949 struct ksz9477_errata_write {
1950 u8 dev_addr;
1951 u8 reg_addr;
1952 u16 val;
1953 };
1954
1955 static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1956 /* Register settings are needed to improve PHY receive performance */
1957 {0x01, 0x6f, 0xdd0b},
1958 {0x01, 0x8f, 0x6032},
1959 {0x01, 0x9d, 0x248c},
1960 {0x01, 0x75, 0x0060},
1961 {0x01, 0xd3, 0x7777},
1962 {0x1c, 0x06, 0x3008},
1963 {0x1c, 0x08, 0x2000},
1964
1965 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1966 {0x1c, 0x04, 0x00d0},
1967
1968 /* Register settings are required to meet data sheet supply current specifications */
1969 {0x1c, 0x13, 0x6eff},
1970 {0x1c, 0x14, 0xe6ff},
1971 {0x1c, 0x15, 0x6eff},
1972 {0x1c, 0x16, 0xe6ff},
1973 {0x1c, 0x17, 0x00ff},
1974 {0x1c, 0x18, 0x43ff},
1975 {0x1c, 0x19, 0xc3ff},
1976 {0x1c, 0x1a, 0x6fff},
1977 {0x1c, 0x1b, 0x07ff},
1978 {0x1c, 0x1c, 0x0fff},
1979 {0x1c, 0x1d, 0xe7ff},
1980 {0x1c, 0x1e, 0xefff},
1981 {0x1c, 0x20, 0xeeee},
1982 };
1983
ksz9477_phy_errata(struct phy_device * phydev)1984 static int ksz9477_phy_errata(struct phy_device *phydev)
1985 {
1986 int err;
1987 int i;
1988
1989 /* Apply PHY settings to address errata listed in
1990 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1991 * Silicon Errata and Data Sheet Clarification documents.
1992 *
1993 * Document notes: Before configuring the PHY MMD registers, it is
1994 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1995 * disabled by writing to register 0xN100-0xN101. After writing the
1996 * MMD registers, and after all errata workarounds that involve PHY
1997 * register settings, write register 0xN100-0xN101 again to enable
1998 * and restart auto-negotiation.
1999 */
2000 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
2001 if (err)
2002 return err;
2003
2004 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
2005 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
2006
2007 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
2008 if (err)
2009 return err;
2010 }
2011
2012 err = genphy_restart_aneg(phydev);
2013 if (err)
2014 return err;
2015
2016 return err;
2017 }
2018
ksz9477_config_init(struct phy_device * phydev)2019 static int ksz9477_config_init(struct phy_device *phydev)
2020 {
2021 int err;
2022
2023 /* Only KSZ9897 family of switches needs this fix. */
2024 if ((phydev->phy_id & 0xf) == 1) {
2025 err = ksz9477_phy_errata(phydev);
2026 if (err)
2027 return err;
2028 }
2029
2030 return kszphy_config_init(phydev);
2031 }
2032
kszphy_get_sset_count(struct phy_device * phydev)2033 static int kszphy_get_sset_count(struct phy_device *phydev)
2034 {
2035 return ARRAY_SIZE(kszphy_hw_stats);
2036 }
2037
kszphy_get_strings(struct phy_device * phydev,u8 * data)2038 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
2039 {
2040 int i;
2041
2042 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2043 ethtool_puts(&data, kszphy_hw_stats[i].string);
2044 }
2045
kszphy_get_stat(struct phy_device * phydev,int i)2046 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
2047 {
2048 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
2049 struct kszphy_priv *priv = phydev->priv;
2050 int val;
2051 u64 ret;
2052
2053 val = phy_read(phydev, stat.reg);
2054 if (val < 0) {
2055 ret = U64_MAX;
2056 } else {
2057 val = val & ((1 << stat.bits) - 1);
2058 priv->stats[i] += val;
2059 ret = priv->stats[i];
2060 }
2061
2062 return ret;
2063 }
2064
kszphy_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)2065 static void kszphy_get_stats(struct phy_device *phydev,
2066 struct ethtool_stats *stats, u64 *data)
2067 {
2068 int i;
2069
2070 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2071 data[i] = kszphy_get_stat(phydev, i);
2072 }
2073
kszphy_enable_clk(struct phy_device * phydev)2074 static void kszphy_enable_clk(struct phy_device *phydev)
2075 {
2076 struct kszphy_priv *priv = phydev->priv;
2077
2078 if (!priv->clk_enable && priv->clk) {
2079 clk_prepare_enable(priv->clk);
2080 priv->clk_enable = true;
2081 }
2082 }
2083
kszphy_disable_clk(struct phy_device * phydev)2084 static void kszphy_disable_clk(struct phy_device *phydev)
2085 {
2086 struct kszphy_priv *priv = phydev->priv;
2087
2088 if (priv->clk_enable && priv->clk) {
2089 clk_disable_unprepare(priv->clk);
2090 priv->clk_enable = false;
2091 }
2092 }
2093
kszphy_generic_resume(struct phy_device * phydev)2094 static int kszphy_generic_resume(struct phy_device *phydev)
2095 {
2096 kszphy_enable_clk(phydev);
2097
2098 return genphy_resume(phydev);
2099 }
2100
kszphy_generic_suspend(struct phy_device * phydev)2101 static int kszphy_generic_suspend(struct phy_device *phydev)
2102 {
2103 int ret;
2104
2105 ret = genphy_suspend(phydev);
2106 if (ret)
2107 return ret;
2108
2109 kszphy_disable_clk(phydev);
2110
2111 return 0;
2112 }
2113
kszphy_suspend(struct phy_device * phydev)2114 static int kszphy_suspend(struct phy_device *phydev)
2115 {
2116 /* Disable PHY Interrupts */
2117 if (phy_interrupt_is_valid(phydev)) {
2118 phydev->interrupts = PHY_INTERRUPT_DISABLED;
2119 if (phydev->drv->config_intr)
2120 phydev->drv->config_intr(phydev);
2121 }
2122
2123 return kszphy_generic_suspend(phydev);
2124 }
2125
kszphy_parse_led_mode(struct phy_device * phydev)2126 static void kszphy_parse_led_mode(struct phy_device *phydev)
2127 {
2128 const struct kszphy_type *type = phydev->drv->driver_data;
2129 const struct device_node *np = phydev->mdio.dev.of_node;
2130 struct kszphy_priv *priv = phydev->priv;
2131 int ret;
2132
2133 if (type && type->led_mode_reg) {
2134 ret = of_property_read_u32(np, "micrel,led-mode",
2135 &priv->led_mode);
2136
2137 if (ret)
2138 priv->led_mode = -1;
2139
2140 if (priv->led_mode > 3) {
2141 phydev_err(phydev, "invalid led mode: 0x%02x\n",
2142 priv->led_mode);
2143 priv->led_mode = -1;
2144 }
2145 } else {
2146 priv->led_mode = -1;
2147 }
2148 }
2149
kszphy_resume(struct phy_device * phydev)2150 static int kszphy_resume(struct phy_device *phydev)
2151 {
2152 int ret;
2153
2154 ret = kszphy_generic_resume(phydev);
2155 if (ret)
2156 return ret;
2157
2158 /* After switching from power-down to normal mode, an internal global
2159 * reset is automatically generated. Wait a minimum of 1 ms before
2160 * read/write access to the PHY registers.
2161 */
2162 usleep_range(1000, 2000);
2163
2164 ret = kszphy_config_reset(phydev);
2165 if (ret)
2166 return ret;
2167
2168 /* Enable PHY Interrupts */
2169 if (phy_interrupt_is_valid(phydev)) {
2170 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2171 if (phydev->drv->config_intr)
2172 phydev->drv->config_intr(phydev);
2173 }
2174
2175 return 0;
2176 }
2177
2178 /* Because of errata DS80000700A, receiver error following software
2179 * power down. Suspend and resume callbacks only disable and enable
2180 * external rmii reference clock.
2181 */
ksz8041_resume(struct phy_device * phydev)2182 static int ksz8041_resume(struct phy_device *phydev)
2183 {
2184 kszphy_enable_clk(phydev);
2185
2186 return 0;
2187 }
2188
ksz8041_suspend(struct phy_device * phydev)2189 static int ksz8041_suspend(struct phy_device *phydev)
2190 {
2191 kszphy_disable_clk(phydev);
2192
2193 return 0;
2194 }
2195
ksz9477_resume(struct phy_device * phydev)2196 static int ksz9477_resume(struct phy_device *phydev)
2197 {
2198 int ret;
2199
2200 /* No need to initialize registers if not powered down. */
2201 ret = phy_read(phydev, MII_BMCR);
2202 if (ret < 0)
2203 return ret;
2204 if (!(ret & BMCR_PDOWN))
2205 return 0;
2206
2207 genphy_resume(phydev);
2208
2209 /* After switching from power-down to normal mode, an internal global
2210 * reset is automatically generated. Wait a minimum of 1 ms before
2211 * read/write access to the PHY registers.
2212 */
2213 usleep_range(1000, 2000);
2214
2215 /* Only KSZ9897 family of switches needs this fix. */
2216 if ((phydev->phy_id & 0xf) == 1) {
2217 ret = ksz9477_phy_errata(phydev);
2218 if (ret)
2219 return ret;
2220 }
2221
2222 /* Enable PHY Interrupts */
2223 if (phy_interrupt_is_valid(phydev)) {
2224 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2225 if (phydev->drv->config_intr)
2226 phydev->drv->config_intr(phydev);
2227 }
2228
2229 return 0;
2230 }
2231
ksz8061_resume(struct phy_device * phydev)2232 static int ksz8061_resume(struct phy_device *phydev)
2233 {
2234 int ret;
2235
2236 /* This function can be called twice when the Ethernet device is on. */
2237 ret = phy_read(phydev, MII_BMCR);
2238 if (ret < 0)
2239 return ret;
2240 if (!(ret & BMCR_PDOWN))
2241 return 0;
2242
2243 ret = kszphy_generic_resume(phydev);
2244 if (ret)
2245 return ret;
2246
2247 usleep_range(1000, 2000);
2248
2249 /* Re-program the value after chip is reset. */
2250 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
2251 if (ret)
2252 return ret;
2253
2254 /* Enable PHY Interrupts */
2255 if (phy_interrupt_is_valid(phydev)) {
2256 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2257 if (phydev->drv->config_intr)
2258 phydev->drv->config_intr(phydev);
2259 }
2260
2261 return 0;
2262 }
2263
ksz8061_suspend(struct phy_device * phydev)2264 static int ksz8061_suspend(struct phy_device *phydev)
2265 {
2266 return kszphy_suspend(phydev);
2267 }
2268
kszphy_probe(struct phy_device * phydev)2269 static int kszphy_probe(struct phy_device *phydev)
2270 {
2271 const struct kszphy_type *type = phydev->drv->driver_data;
2272 const struct device_node *np = phydev->mdio.dev.of_node;
2273 struct kszphy_priv *priv;
2274 struct clk *clk;
2275
2276 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2277 if (!priv)
2278 return -ENOMEM;
2279
2280 phydev->priv = priv;
2281
2282 priv->type = type;
2283
2284 kszphy_parse_led_mode(phydev);
2285
2286 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
2287 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2288 if (!IS_ERR_OR_NULL(clk)) {
2289 unsigned long rate = clk_get_rate(clk);
2290 bool rmii_ref_clk_sel_25_mhz;
2291
2292 if (type)
2293 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2294 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2295 "micrel,rmii-reference-clock-select-25-mhz");
2296
2297 if (rate > 24500000 && rate < 25500000) {
2298 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2299 } else if (rate > 49500000 && rate < 50500000) {
2300 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2301 } else {
2302 phydev_err(phydev, "Clock rate out of range: %ld\n",
2303 rate);
2304 return -EINVAL;
2305 }
2306 } else if (!clk) {
2307 /* unnamed clock from the generic ethernet-phy binding */
2308 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
2309 }
2310
2311 if (IS_ERR(clk))
2312 return PTR_ERR(clk);
2313
2314 clk_disable_unprepare(clk);
2315 priv->clk = clk;
2316
2317 if (ksz8041_fiber_mode(phydev))
2318 phydev->port = PORT_FIBRE;
2319
2320 /* Support legacy board-file configuration */
2321 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2322 priv->rmii_ref_clk_sel = true;
2323 priv->rmii_ref_clk_sel_val = true;
2324 }
2325
2326 return 0;
2327 }
2328
lan8814_cable_test_start(struct phy_device * phydev)2329 static int lan8814_cable_test_start(struct phy_device *phydev)
2330 {
2331 /* If autoneg is enabled, we won't be able to test cross pair
2332 * short. In this case, the PHY will "detect" a link and
2333 * confuse the internal state machine - disable auto neg here.
2334 * Set the speed to 1000mbit and full duplex.
2335 */
2336 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2337 BMCR_SPEED1000 | BMCR_FULLDPLX);
2338 }
2339
ksz886x_cable_test_start(struct phy_device * phydev)2340 static int ksz886x_cable_test_start(struct phy_device *phydev)
2341 {
2342 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2343 return -EOPNOTSUPP;
2344
2345 /* If autoneg is enabled, we won't be able to test cross pair
2346 * short. In this case, the PHY will "detect" a link and
2347 * confuse the internal state machine - disable auto neg here.
2348 * If autoneg is disabled, we should set the speed to 10mbit.
2349 */
2350 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2351 }
2352
ksz886x_cable_test_result_trans(u16 status,u16 mask)2353 static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2354 {
2355 switch (FIELD_GET(mask, status)) {
2356 case KSZ8081_LMD_STAT_NORMAL:
2357 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2358 case KSZ8081_LMD_STAT_SHORT:
2359 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2360 case KSZ8081_LMD_STAT_OPEN:
2361 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2362 case KSZ8081_LMD_STAT_FAIL:
2363 fallthrough;
2364 default:
2365 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2366 }
2367 }
2368
ksz886x_cable_test_failed(u16 status,u16 mask)2369 static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2370 {
2371 return FIELD_GET(mask, status) ==
2372 KSZ8081_LMD_STAT_FAIL;
2373 }
2374
ksz886x_cable_test_fault_length_valid(u16 status,u16 mask)2375 static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2376 {
2377 switch (FIELD_GET(mask, status)) {
2378 case KSZ8081_LMD_STAT_OPEN:
2379 fallthrough;
2380 case KSZ8081_LMD_STAT_SHORT:
2381 return true;
2382 }
2383 return false;
2384 }
2385
ksz886x_cable_test_fault_length(struct phy_device * phydev,u16 status,u16 data_mask)2386 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2387 u16 status, u16 data_mask)
2388 {
2389 int dt;
2390
2391 /* According to the data sheet the distance to the fault is
2392 * DELTA_TIME * 0.4 meters for ksz phys.
2393 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2394 */
2395 dt = FIELD_GET(data_mask, status);
2396
2397 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2398 return ((dt - 22) * 800) / 10;
2399 else
2400 return (dt * 400) / 10;
2401 }
2402
ksz886x_cable_test_wait_for_completion(struct phy_device * phydev)2403 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2404 {
2405 const struct kszphy_type *type = phydev->drv->driver_data;
2406 int val, ret;
2407
2408 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2409 !(val & KSZ8081_LMD_ENABLE_TEST),
2410 30000, 100000, true);
2411
2412 return ret < 0 ? ret : 0;
2413 }
2414
lan8814_cable_test_one_pair(struct phy_device * phydev,int pair)2415 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2416 {
2417 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2418 ETHTOOL_A_CABLE_PAIR_B,
2419 ETHTOOL_A_CABLE_PAIR_C,
2420 ETHTOOL_A_CABLE_PAIR_D,
2421 };
2422 u32 fault_length;
2423 int ret;
2424 int val;
2425
2426 val = KSZ8081_LMD_ENABLE_TEST;
2427 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2428
2429 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2430 if (ret < 0)
2431 return ret;
2432
2433 ret = ksz886x_cable_test_wait_for_completion(phydev);
2434 if (ret)
2435 return ret;
2436
2437 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2438 if (val < 0)
2439 return val;
2440
2441 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2442 return -EAGAIN;
2443
2444 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2445 ksz886x_cable_test_result_trans(val,
2446 LAN8814_CABLE_DIAG_STAT_MASK
2447 ));
2448 if (ret)
2449 return ret;
2450
2451 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2452 return 0;
2453
2454 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2455 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2456
2457 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2458 }
2459
ksz886x_cable_test_one_pair(struct phy_device * phydev,int pair)2460 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2461 {
2462 static const int ethtool_pair[] = {
2463 ETHTOOL_A_CABLE_PAIR_A,
2464 ETHTOOL_A_CABLE_PAIR_B,
2465 };
2466 int ret, val, mdix;
2467 u32 fault_length;
2468
2469 /* There is no way to choice the pair, like we do one ksz9031.
2470 * We can workaround this limitation by using the MDI-X functionality.
2471 */
2472 if (pair == 0)
2473 mdix = ETH_TP_MDI;
2474 else
2475 mdix = ETH_TP_MDI_X;
2476
2477 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2478 case PHY_ID_KSZ8081:
2479 ret = ksz8081_config_mdix(phydev, mdix);
2480 break;
2481 case PHY_ID_KSZ886X:
2482 ret = ksz886x_config_mdix(phydev, mdix);
2483 break;
2484 default:
2485 ret = -ENODEV;
2486 }
2487
2488 if (ret)
2489 return ret;
2490
2491 /* Now we are ready to fire. This command will send a 100ns pulse
2492 * to the pair.
2493 */
2494 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2495 if (ret)
2496 return ret;
2497
2498 ret = ksz886x_cable_test_wait_for_completion(phydev);
2499 if (ret)
2500 return ret;
2501
2502 val = phy_read(phydev, KSZ8081_LMD);
2503 if (val < 0)
2504 return val;
2505
2506 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2507 return -EAGAIN;
2508
2509 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2510 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2511 if (ret)
2512 return ret;
2513
2514 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2515 return 0;
2516
2517 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2518
2519 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2520 }
2521
ksz886x_cable_test_get_status(struct phy_device * phydev,bool * finished)2522 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2523 bool *finished)
2524 {
2525 const struct kszphy_type *type = phydev->drv->driver_data;
2526 unsigned long pair_mask = type->pair_mask;
2527 int retries = 20;
2528 int ret = 0;
2529 int pair;
2530
2531 *finished = false;
2532
2533 /* Try harder if link partner is active */
2534 while (pair_mask && retries--) {
2535 for_each_set_bit(pair, &pair_mask, 4) {
2536 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2537 ret = lan8814_cable_test_one_pair(phydev, pair);
2538 else
2539 ret = ksz886x_cable_test_one_pair(phydev, pair);
2540 if (ret == -EAGAIN)
2541 continue;
2542 if (ret < 0)
2543 return ret;
2544 clear_bit(pair, &pair_mask);
2545 }
2546 /* If link partner is in autonegotiation mode it will send 2ms
2547 * of FLPs with at least 6ms of silence.
2548 * Add 2ms sleep to have better chances to hit this silence.
2549 */
2550 if (pair_mask)
2551 msleep(2);
2552 }
2553
2554 *finished = true;
2555
2556 return ret;
2557 }
2558
2559 #define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2560 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2561 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2562
2563 #define LAN8814_QSGMII_SOFT_RESET 0x43
2564 #define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2565 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2566 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2567 #define LAN8814_ALIGN_SWAP 0x4a
2568 #define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2569 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2570
2571 #define LAN8804_ALIGN_SWAP 0x4a
2572 #define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2573 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2574 #define LAN8814_CLOCK_MANAGEMENT 0xd
2575 #define LAN8814_LINK_QUALITY 0x8e
2576
lanphy_read_page_reg(struct phy_device * phydev,int page,u32 addr)2577 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2578 {
2579 int data;
2580
2581 phy_lock_mdio_bus(phydev);
2582 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2583 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2584 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2585 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2586 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2587 phy_unlock_mdio_bus(phydev);
2588
2589 return data;
2590 }
2591
lanphy_write_page_reg(struct phy_device * phydev,int page,u16 addr,u16 val)2592 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2593 u16 val)
2594 {
2595 phy_lock_mdio_bus(phydev);
2596 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2597 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2598 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2599 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2600
2601 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2602 if (val != 0)
2603 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2604 val);
2605 phy_unlock_mdio_bus(phydev);
2606 return val;
2607 }
2608
lan8814_config_ts_intr(struct phy_device * phydev,bool enable)2609 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2610 {
2611 u16 val = 0;
2612
2613 if (enable)
2614 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2615 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2616 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2617 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2618
2619 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2620 }
2621
lan8814_ptp_rx_ts_get(struct phy_device * phydev,u32 * seconds,u32 * nano_seconds,u16 * seq_id)2622 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2623 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2624 {
2625 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2626 *seconds = (*seconds << 16) |
2627 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2628
2629 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2630 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2631 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2632
2633 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2634 }
2635
lan8814_ptp_tx_ts_get(struct phy_device * phydev,u32 * seconds,u32 * nano_seconds,u16 * seq_id)2636 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2637 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2638 {
2639 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2640 *seconds = *seconds << 16 |
2641 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2642
2643 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2644 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2645 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2646
2647 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2648 }
2649
lan8814_ts_info(struct mii_timestamper * mii_ts,struct kernel_ethtool_ts_info * info)2650 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)
2651 {
2652 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2653 struct lan8814_shared_priv *shared = phy_package_get_priv(ptp_priv->phydev);
2654
2655 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2656 SOF_TIMESTAMPING_RX_HARDWARE |
2657 SOF_TIMESTAMPING_RAW_HARDWARE;
2658
2659 info->phc_index = ptp_clock_index(shared->ptp_clock);
2660
2661 info->tx_types =
2662 (1 << HWTSTAMP_TX_OFF) |
2663 (1 << HWTSTAMP_TX_ON) |
2664 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2665
2666 info->rx_filters =
2667 (1 << HWTSTAMP_FILTER_NONE) |
2668 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2669 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2670 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2671 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2672
2673 return 0;
2674 }
2675
lan8814_flush_fifo(struct phy_device * phydev,bool egress)2676 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2677 {
2678 int i;
2679
2680 for (i = 0; i < FIFO_SIZE; ++i)
2681 lanphy_read_page_reg(phydev, 5,
2682 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2683
2684 /* Read to clear overflow status bit */
2685 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2686 }
2687
lan8814_hwtstamp(struct mii_timestamper * mii_ts,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)2688 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2689 struct kernel_hwtstamp_config *config,
2690 struct netlink_ext_ack *extack)
2691 {
2692 struct kszphy_ptp_priv *ptp_priv =
2693 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2694 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2695 int txcfg = 0, rxcfg = 0;
2696 int pkt_ts_enable;
2697 int tx_mod;
2698
2699 ptp_priv->hwts_tx_type = config->tx_type;
2700 ptp_priv->rx_filter = config->rx_filter;
2701
2702 switch (config->rx_filter) {
2703 case HWTSTAMP_FILTER_NONE:
2704 ptp_priv->layer = 0;
2705 ptp_priv->version = 0;
2706 break;
2707 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2708 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2709 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2710 ptp_priv->layer = PTP_CLASS_L4;
2711 ptp_priv->version = PTP_CLASS_V2;
2712 break;
2713 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2714 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2715 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2716 ptp_priv->layer = PTP_CLASS_L2;
2717 ptp_priv->version = PTP_CLASS_V2;
2718 break;
2719 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2720 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2721 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2722 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2723 ptp_priv->version = PTP_CLASS_V2;
2724 break;
2725 default:
2726 return -ERANGE;
2727 }
2728
2729 if (ptp_priv->layer & PTP_CLASS_L2) {
2730 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2731 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2732 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2733 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2734 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2735 }
2736 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2737 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2738
2739 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2740 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2741 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2742 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2743
2744 tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2745 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2746 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2747 tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2748 } else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2749 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2750 tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2751 }
2752
2753 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2754 lan8814_config_ts_intr(ptp_priv->phydev, true);
2755 else
2756 lan8814_config_ts_intr(ptp_priv->phydev, false);
2757
2758 /* In case of multiple starts and stops, these needs to be cleared */
2759 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2760 list_del(&rx_ts->list);
2761 kfree(rx_ts);
2762 }
2763 skb_queue_purge(&ptp_priv->rx_queue);
2764 skb_queue_purge(&ptp_priv->tx_queue);
2765
2766 lan8814_flush_fifo(ptp_priv->phydev, false);
2767 lan8814_flush_fifo(ptp_priv->phydev, true);
2768
2769 return 0;
2770 }
2771
lan8814_txtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)2772 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2773 struct sk_buff *skb, int type)
2774 {
2775 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2776
2777 switch (ptp_priv->hwts_tx_type) {
2778 case HWTSTAMP_TX_ONESTEP_SYNC:
2779 if (ptp_msg_is_sync(skb, type)) {
2780 kfree_skb(skb);
2781 return;
2782 }
2783 fallthrough;
2784 case HWTSTAMP_TX_ON:
2785 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2786 skb_queue_tail(&ptp_priv->tx_queue, skb);
2787 break;
2788 case HWTSTAMP_TX_OFF:
2789 default:
2790 kfree_skb(skb);
2791 break;
2792 }
2793 }
2794
lan8814_get_sig_rx(struct sk_buff * skb,u16 * sig)2795 static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2796 {
2797 struct ptp_header *ptp_header;
2798 u32 type;
2799
2800 skb_push(skb, ETH_HLEN);
2801 type = ptp_classify_raw(skb);
2802 ptp_header = ptp_parse_header(skb, type);
2803 skb_pull_inline(skb, ETH_HLEN);
2804
2805 if (!ptp_header)
2806 return false;
2807
2808 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2809 return true;
2810 }
2811
lan8814_match_rx_skb(struct kszphy_ptp_priv * ptp_priv,struct sk_buff * skb)2812 static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2813 struct sk_buff *skb)
2814 {
2815 struct skb_shared_hwtstamps *shhwtstamps;
2816 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2817 unsigned long flags;
2818 bool ret = false;
2819 u16 skb_sig;
2820
2821 if (!lan8814_get_sig_rx(skb, &skb_sig))
2822 return ret;
2823
2824 /* Iterate over all RX timestamps and match it with the received skbs */
2825 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2826 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2827 /* Check if we found the signature we were looking for. */
2828 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2829 continue;
2830
2831 shhwtstamps = skb_hwtstamps(skb);
2832 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2833 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2834 rx_ts->nsec);
2835 list_del(&rx_ts->list);
2836 kfree(rx_ts);
2837
2838 ret = true;
2839 break;
2840 }
2841 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2842
2843 if (ret)
2844 netif_rx(skb);
2845 return ret;
2846 }
2847
lan8814_rxtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)2848 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2849 {
2850 struct kszphy_ptp_priv *ptp_priv =
2851 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2852
2853 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2854 type == PTP_CLASS_NONE)
2855 return false;
2856
2857 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2858 return false;
2859
2860 /* If we failed to match then add it to the queue for when the timestamp
2861 * will come
2862 */
2863 if (!lan8814_match_rx_skb(ptp_priv, skb))
2864 skb_queue_tail(&ptp_priv->rx_queue, skb);
2865
2866 return true;
2867 }
2868
lan8814_ptp_clock_set(struct phy_device * phydev,time64_t sec,u32 nsec)2869 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2870 time64_t sec, u32 nsec)
2871 {
2872 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
2873 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
2874 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
2875 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
2876 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
2877
2878 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2879 }
2880
lan8814_ptp_clock_get(struct phy_device * phydev,time64_t * sec,u32 * nsec)2881 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2882 time64_t *sec, u32 *nsec)
2883 {
2884 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2885
2886 *sec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI);
2887 *sec <<= 16;
2888 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2889 *sec <<= 16;
2890 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2891
2892 *nsec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2893 *nsec <<= 16;
2894 *nsec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2895 }
2896
lan8814_ptpci_gettime64(struct ptp_clock_info * ptpci,struct timespec64 * ts)2897 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2898 struct timespec64 *ts)
2899 {
2900 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2901 ptp_clock_info);
2902 struct phy_device *phydev = shared->phydev;
2903 u32 nano_seconds;
2904 time64_t seconds;
2905
2906 mutex_lock(&shared->shared_lock);
2907 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2908 mutex_unlock(&shared->shared_lock);
2909 ts->tv_sec = seconds;
2910 ts->tv_nsec = nano_seconds;
2911
2912 return 0;
2913 }
2914
lan8814_ptpci_settime64(struct ptp_clock_info * ptpci,const struct timespec64 * ts)2915 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2916 const struct timespec64 *ts)
2917 {
2918 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2919 ptp_clock_info);
2920 struct phy_device *phydev = shared->phydev;
2921
2922 mutex_lock(&shared->shared_lock);
2923 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2924 mutex_unlock(&shared->shared_lock);
2925
2926 return 0;
2927 }
2928
lan8814_ptp_set_target(struct phy_device * phydev,int event,s64 start_sec,u32 start_nsec)2929 static void lan8814_ptp_set_target(struct phy_device *phydev, int event,
2930 s64 start_sec, u32 start_nsec)
2931 {
2932 /* Set the start time */
2933 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
2934 lower_16_bits(start_sec));
2935 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
2936 upper_16_bits(start_sec));
2937
2938 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
2939 lower_16_bits(start_nsec));
2940 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
2941 upper_16_bits(start_nsec) & 0x3fff);
2942 }
2943
lan8814_ptp_update_target(struct phy_device * phydev,time64_t sec)2944 static void lan8814_ptp_update_target(struct phy_device *phydev, time64_t sec)
2945 {
2946 lan8814_ptp_set_target(phydev, LAN8814_EVENT_A,
2947 sec + LAN8814_BUFFER_TIME, 0);
2948 lan8814_ptp_set_target(phydev, LAN8814_EVENT_B,
2949 sec + LAN8814_BUFFER_TIME, 0);
2950 }
2951
lan8814_ptp_clock_step(struct phy_device * phydev,s64 time_step_ns)2952 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2953 s64 time_step_ns)
2954 {
2955 u32 nano_seconds_step;
2956 u64 abs_time_step_ns;
2957 time64_t set_seconds;
2958 u32 nano_seconds;
2959 u32 remainder;
2960 s32 seconds;
2961
2962 if (time_step_ns > 15000000000LL) {
2963 /* convert to clock set */
2964 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2965 set_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2966 &remainder);
2967 nano_seconds += remainder;
2968 if (nano_seconds >= 1000000000) {
2969 set_seconds++;
2970 nano_seconds -= 1000000000;
2971 }
2972 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2973 lan8814_ptp_update_target(phydev, set_seconds);
2974 return;
2975 } else if (time_step_ns < -15000000000LL) {
2976 /* convert to clock set */
2977 time_step_ns = -time_step_ns;
2978
2979 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2980 set_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2981 &remainder);
2982 nano_seconds_step = remainder;
2983 if (nano_seconds < nano_seconds_step) {
2984 set_seconds--;
2985 nano_seconds += 1000000000;
2986 }
2987 nano_seconds -= nano_seconds_step;
2988 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2989 lan8814_ptp_update_target(phydev, set_seconds);
2990 return;
2991 }
2992
2993 /* do clock step */
2994 if (time_step_ns >= 0) {
2995 abs_time_step_ns = (u64)time_step_ns;
2996 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2997 &remainder);
2998 nano_seconds = remainder;
2999 } else {
3000 abs_time_step_ns = (u64)(-time_step_ns);
3001 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
3002 &remainder));
3003 nano_seconds = remainder;
3004 if (nano_seconds > 0) {
3005 /* subtracting nano seconds is not allowed
3006 * convert to subtracting from seconds,
3007 * and adding to nanoseconds
3008 */
3009 seconds--;
3010 nano_seconds = (1000000000 - nano_seconds);
3011 }
3012 }
3013
3014 if (nano_seconds > 0) {
3015 /* add 8 ns to cover the likely normal increment */
3016 nano_seconds += 8;
3017 }
3018
3019 if (nano_seconds >= 1000000000) {
3020 /* carry into seconds */
3021 seconds++;
3022 nano_seconds -= 1000000000;
3023 }
3024
3025 while (seconds) {
3026 u32 nsec;
3027
3028 if (seconds > 0) {
3029 u32 adjustment_value = (u32)seconds;
3030 u16 adjustment_value_lo, adjustment_value_hi;
3031
3032 if (adjustment_value > 0xF)
3033 adjustment_value = 0xF;
3034
3035 adjustment_value_lo = adjustment_value & 0xffff;
3036 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3037
3038 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3039 adjustment_value_lo);
3040 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3041 PTP_LTC_STEP_ADJ_DIR_ |
3042 adjustment_value_hi);
3043 seconds -= ((s32)adjustment_value);
3044
3045 lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);
3046 set_seconds -= adjustment_value;
3047 lan8814_ptp_update_target(phydev, set_seconds);
3048 } else {
3049 u32 adjustment_value = (u32)(-seconds);
3050 u16 adjustment_value_lo, adjustment_value_hi;
3051
3052 if (adjustment_value > 0xF)
3053 adjustment_value = 0xF;
3054
3055 adjustment_value_lo = adjustment_value & 0xffff;
3056 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3057
3058 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3059 adjustment_value_lo);
3060 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3061 adjustment_value_hi);
3062 seconds += ((s32)adjustment_value);
3063
3064 lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);
3065 set_seconds += adjustment_value;
3066 lan8814_ptp_update_target(phydev, set_seconds);
3067 }
3068 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3069 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3070 }
3071 if (nano_seconds) {
3072 u16 nano_seconds_lo;
3073 u16 nano_seconds_hi;
3074
3075 nano_seconds_lo = nano_seconds & 0xffff;
3076 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
3077
3078 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3079 nano_seconds_lo);
3080 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3081 PTP_LTC_STEP_ADJ_DIR_ |
3082 nano_seconds_hi);
3083 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3084 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
3085 }
3086 }
3087
lan8814_ptpci_adjtime(struct ptp_clock_info * ptpci,s64 delta)3088 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
3089 {
3090 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3091 ptp_clock_info);
3092 struct phy_device *phydev = shared->phydev;
3093
3094 mutex_lock(&shared->shared_lock);
3095 lan8814_ptp_clock_step(phydev, delta);
3096 mutex_unlock(&shared->shared_lock);
3097
3098 return 0;
3099 }
3100
lan8814_ptpci_adjfine(struct ptp_clock_info * ptpci,long scaled_ppm)3101 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
3102 {
3103 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3104 ptp_clock_info);
3105 struct phy_device *phydev = shared->phydev;
3106 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
3107 bool positive = true;
3108 u32 kszphy_rate_adj;
3109
3110 if (scaled_ppm < 0) {
3111 scaled_ppm = -scaled_ppm;
3112 positive = false;
3113 }
3114
3115 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
3116 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
3117
3118 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
3119 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
3120
3121 if (positive)
3122 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
3123
3124 mutex_lock(&shared->shared_lock);
3125 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
3126 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
3127 mutex_unlock(&shared->shared_lock);
3128
3129 return 0;
3130 }
3131
lan8814_ptp_set_reload(struct phy_device * phydev,int event,s64 period_sec,u32 period_nsec)3132 static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,
3133 s64 period_sec, u32 period_nsec)
3134 {
3135 lanphy_write_page_reg(phydev, 4,
3136 LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),
3137 lower_16_bits(period_sec));
3138 lanphy_write_page_reg(phydev, 4,
3139 LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),
3140 upper_16_bits(period_sec));
3141
3142 lanphy_write_page_reg(phydev, 4,
3143 LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),
3144 lower_16_bits(period_nsec));
3145 lanphy_write_page_reg(phydev, 4,
3146 LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),
3147 upper_16_bits(period_nsec) & 0x3fff);
3148 }
3149
lan8814_ptp_enable_event(struct phy_device * phydev,int event,int pulse_width)3150 static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,
3151 int pulse_width)
3152 {
3153 u16 val;
3154
3155 val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3156 /* Set the pulse width of the event */
3157 val &= ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event));
3158 /* Make sure that the target clock will be incremented each time when
3159 * local time reaches or pass it
3160 */
3161 val |= LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width);
3162 val &= ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3163 /* Set the polarity high */
3164 val |= LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event);
3165 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3166 }
3167
lan8814_ptp_disable_event(struct phy_device * phydev,int event)3168 static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)
3169 {
3170 u16 val;
3171
3172 /* Set target to too far in the future, effectively disabling it */
3173 lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0);
3174
3175 /* And then reload once it recheas the target */
3176 val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3177 val |= LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event);
3178 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3179 }
3180
lan8814_ptp_perout_off(struct phy_device * phydev,int pin)3181 static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)
3182 {
3183 u16 val;
3184
3185 /* Disable gpio alternate function,
3186 * 1: select as gpio,
3187 * 0: select alt func
3188 */
3189 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3190 val |= LAN8814_GPIO_EN_BIT(pin);
3191 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3192
3193 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3194 val &= ~LAN8814_GPIO_DIR_BIT(pin);
3195 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3196
3197 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3198 val &= ~LAN8814_GPIO_BUF_BIT(pin);
3199 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3200 }
3201
lan8814_ptp_perout_on(struct phy_device * phydev,int pin)3202 static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3203 {
3204 int val;
3205
3206 /* Set as gpio output */
3207 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3208 val |= LAN8814_GPIO_DIR_BIT(pin);
3209 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3210
3211 /* Enable gpio 0:for alternate function, 1:gpio */
3212 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3213 val &= ~LAN8814_GPIO_EN_BIT(pin);
3214 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3215
3216 /* Set buffer type to push pull */
3217 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3218 val |= LAN8814_GPIO_BUF_BIT(pin);
3219 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3220 }
3221
lan8814_ptp_perout(struct ptp_clock_info * ptpci,struct ptp_clock_request * rq,int on)3222 static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,
3223 struct ptp_clock_request *rq, int on)
3224 {
3225 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3226 ptp_clock_info);
3227 struct phy_device *phydev = shared->phydev;
3228 struct timespec64 ts_on, ts_period;
3229 s64 on_nsec, period_nsec;
3230 int pulse_width;
3231 int pin, event;
3232
3233 /* Reject requests with unsupported flags */
3234 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
3235 return -EOPNOTSUPP;
3236
3237 mutex_lock(&shared->shared_lock);
3238 event = rq->perout.index;
3239 pin = ptp_find_pin(shared->ptp_clock, PTP_PF_PEROUT, event);
3240 if (pin < 0 || pin >= LAN8814_PTP_PEROUT_NUM) {
3241 mutex_unlock(&shared->shared_lock);
3242 return -EBUSY;
3243 }
3244
3245 if (!on) {
3246 lan8814_ptp_perout_off(phydev, pin);
3247 lan8814_ptp_disable_event(phydev, event);
3248 mutex_unlock(&shared->shared_lock);
3249 return 0;
3250 }
3251
3252 ts_on.tv_sec = rq->perout.on.sec;
3253 ts_on.tv_nsec = rq->perout.on.nsec;
3254 on_nsec = timespec64_to_ns(&ts_on);
3255
3256 ts_period.tv_sec = rq->perout.period.sec;
3257 ts_period.tv_nsec = rq->perout.period.nsec;
3258 period_nsec = timespec64_to_ns(&ts_period);
3259
3260 if (period_nsec < 200) {
3261 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
3262 phydev_name(phydev));
3263 mutex_unlock(&shared->shared_lock);
3264 return -EOPNOTSUPP;
3265 }
3266
3267 if (on_nsec >= period_nsec) {
3268 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
3269 phydev_name(phydev));
3270 mutex_unlock(&shared->shared_lock);
3271 return -EINVAL;
3272 }
3273
3274 switch (on_nsec) {
3275 case 200000000:
3276 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
3277 break;
3278 case 100000000:
3279 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
3280 break;
3281 case 50000000:
3282 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
3283 break;
3284 case 10000000:
3285 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
3286 break;
3287 case 5000000:
3288 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
3289 break;
3290 case 1000000:
3291 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
3292 break;
3293 case 500000:
3294 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
3295 break;
3296 case 100000:
3297 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
3298 break;
3299 case 50000:
3300 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
3301 break;
3302 case 10000:
3303 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
3304 break;
3305 case 5000:
3306 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
3307 break;
3308 case 1000:
3309 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
3310 break;
3311 case 500:
3312 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
3313 break;
3314 case 100:
3315 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3316 break;
3317 default:
3318 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
3319 phydev_name(phydev));
3320 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3321 break;
3322 }
3323
3324 /* Configure to pulse every period */
3325 lan8814_ptp_enable_event(phydev, event, pulse_width);
3326 lan8814_ptp_set_target(phydev, event, rq->perout.start.sec,
3327 rq->perout.start.nsec);
3328 lan8814_ptp_set_reload(phydev, event, rq->perout.period.sec,
3329 rq->perout.period.nsec);
3330 lan8814_ptp_perout_on(phydev, pin);
3331 mutex_unlock(&shared->shared_lock);
3332
3333 return 0;
3334 }
3335
lan8814_ptp_extts_on(struct phy_device * phydev,int pin,u32 flags)3336 static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3337 {
3338 u16 tmp;
3339
3340 /* Set as gpio input */
3341 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3342 tmp &= ~LAN8814_GPIO_DIR_BIT(pin);
3343 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3344
3345 /* Map the pin to ltc pin 0 of the capture map registers */
3346 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3347 tmp |= pin;
3348 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3349
3350 /* Enable capture on the edges of the ltc pin */
3351 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3352 if (flags & PTP_RISING_EDGE)
3353 tmp |= PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0);
3354 if (flags & PTP_FALLING_EDGE)
3355 tmp |= PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0);
3356 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3357
3358 /* Enable interrupt top interrupt */
3359 tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3360 tmp |= PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3361 lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3362 }
3363
lan8814_ptp_extts_off(struct phy_device * phydev,int pin)3364 static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3365 {
3366 u16 tmp;
3367
3368 /* Set as gpio out */
3369 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3370 tmp |= LAN8814_GPIO_DIR_BIT(pin);
3371 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3372
3373 /* Enable alternate, 0:for alternate function, 1:gpio */
3374 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3375 tmp &= ~LAN8814_GPIO_EN_BIT(pin);
3376 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), tmp);
3377
3378 /* Clear the mapping of pin to registers 0 of the capture registers */
3379 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3380 tmp &= ~GENMASK(3, 0);
3381 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3382
3383 /* Disable capture on both of the edges */
3384 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3385 tmp &= ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
3386 tmp &= ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
3387 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3388
3389 /* Disable interrupt top interrupt */
3390 tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3391 tmp &= ~PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3392 lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3393 }
3394
lan8814_ptp_extts(struct ptp_clock_info * ptpci,struct ptp_clock_request * rq,int on)3395 static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,
3396 struct ptp_clock_request *rq, int on)
3397 {
3398 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3399 ptp_clock_info);
3400 struct phy_device *phydev = shared->phydev;
3401 int pin;
3402
3403 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
3404 PTP_EXTTS_EDGES |
3405 PTP_STRICT_FLAGS))
3406 return -EOPNOTSUPP;
3407
3408 pin = ptp_find_pin(shared->ptp_clock, PTP_PF_EXTTS,
3409 rq->extts.index);
3410 if (pin == -1 || pin != LAN8814_PTP_EXTTS_NUM)
3411 return -EINVAL;
3412
3413 mutex_lock(&shared->shared_lock);
3414 if (on)
3415 lan8814_ptp_extts_on(phydev, pin, rq->extts.flags);
3416 else
3417 lan8814_ptp_extts_off(phydev, pin);
3418
3419 mutex_unlock(&shared->shared_lock);
3420
3421 return 0;
3422 }
3423
lan8814_ptpci_enable(struct ptp_clock_info * ptpci,struct ptp_clock_request * rq,int on)3424 static int lan8814_ptpci_enable(struct ptp_clock_info *ptpci,
3425 struct ptp_clock_request *rq, int on)
3426 {
3427 switch (rq->type) {
3428 case PTP_CLK_REQ_PEROUT:
3429 return lan8814_ptp_perout(ptpci, rq, on);
3430 case PTP_CLK_REQ_EXTTS:
3431 return lan8814_ptp_extts(ptpci, rq, on);
3432 default:
3433 return -EINVAL;
3434 }
3435 }
3436
lan8814_ptpci_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)3437 static int lan8814_ptpci_verify(struct ptp_clock_info *ptp, unsigned int pin,
3438 enum ptp_pin_function func, unsigned int chan)
3439 {
3440 switch (func) {
3441 case PTP_PF_NONE:
3442 case PTP_PF_PEROUT:
3443 /* Only pins 0 and 1 can generate perout signals. And for pin 0
3444 * there is only chan 0 (event A) and for pin 1 there is only
3445 * chan 1 (event B)
3446 */
3447 if (pin >= LAN8814_PTP_PEROUT_NUM || pin != chan)
3448 return -1;
3449 break;
3450 case PTP_PF_EXTTS:
3451 if (pin != LAN8814_PTP_EXTTS_NUM)
3452 return -1;
3453 break;
3454 default:
3455 return -1;
3456 }
3457
3458 return 0;
3459 }
3460
lan8814_get_sig_tx(struct sk_buff * skb,u16 * sig)3461 static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
3462 {
3463 struct ptp_header *ptp_header;
3464 u32 type;
3465
3466 type = ptp_classify_raw(skb);
3467 ptp_header = ptp_parse_header(skb, type);
3468
3469 if (!ptp_header)
3470 return false;
3471
3472 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
3473 return true;
3474 }
3475
lan8814_match_tx_skb(struct kszphy_ptp_priv * ptp_priv,u32 seconds,u32 nsec,u16 seq_id)3476 static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
3477 u32 seconds, u32 nsec, u16 seq_id)
3478 {
3479 struct skb_shared_hwtstamps shhwtstamps;
3480 struct sk_buff *skb, *skb_tmp;
3481 unsigned long flags;
3482 bool ret = false;
3483 u16 skb_sig;
3484
3485 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
3486 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
3487 if (!lan8814_get_sig_tx(skb, &skb_sig))
3488 continue;
3489
3490 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
3491 continue;
3492
3493 __skb_unlink(skb, &ptp_priv->tx_queue);
3494 ret = true;
3495 break;
3496 }
3497 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
3498
3499 if (ret) {
3500 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3501 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
3502 skb_complete_tx_timestamp(skb, &shhwtstamps);
3503 }
3504 }
3505
lan8814_dequeue_tx_skb(struct kszphy_ptp_priv * ptp_priv)3506 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
3507 {
3508 struct phy_device *phydev = ptp_priv->phydev;
3509 u32 seconds, nsec;
3510 u16 seq_id;
3511
3512 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
3513 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
3514 }
3515
lan8814_get_tx_ts(struct kszphy_ptp_priv * ptp_priv)3516 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3517 {
3518 struct phy_device *phydev = ptp_priv->phydev;
3519 u32 reg;
3520
3521 do {
3522 lan8814_dequeue_tx_skb(ptp_priv);
3523
3524 /* If other timestamps are available in the FIFO,
3525 * process them.
3526 */
3527 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3528 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
3529 }
3530
lan8814_match_skb(struct kszphy_ptp_priv * ptp_priv,struct lan8814_ptp_rx_ts * rx_ts)3531 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
3532 struct lan8814_ptp_rx_ts *rx_ts)
3533 {
3534 struct skb_shared_hwtstamps *shhwtstamps;
3535 struct sk_buff *skb, *skb_tmp;
3536 unsigned long flags;
3537 bool ret = false;
3538 u16 skb_sig;
3539
3540 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
3541 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
3542 if (!lan8814_get_sig_rx(skb, &skb_sig))
3543 continue;
3544
3545 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
3546 continue;
3547
3548 __skb_unlink(skb, &ptp_priv->rx_queue);
3549
3550 ret = true;
3551 break;
3552 }
3553 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
3554
3555 if (ret) {
3556 shhwtstamps = skb_hwtstamps(skb);
3557 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3558 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
3559 netif_rx(skb);
3560 }
3561
3562 return ret;
3563 }
3564
lan8814_match_rx_ts(struct kszphy_ptp_priv * ptp_priv,struct lan8814_ptp_rx_ts * rx_ts)3565 static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
3566 struct lan8814_ptp_rx_ts *rx_ts)
3567 {
3568 unsigned long flags;
3569
3570 /* If we failed to match the skb add it to the queue for when
3571 * the frame will come
3572 */
3573 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
3574 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
3575 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
3576 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
3577 } else {
3578 kfree(rx_ts);
3579 }
3580 }
3581
lan8814_get_rx_ts(struct kszphy_ptp_priv * ptp_priv)3582 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
3583 {
3584 struct phy_device *phydev = ptp_priv->phydev;
3585 struct lan8814_ptp_rx_ts *rx_ts;
3586 u32 reg;
3587
3588 do {
3589 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
3590 if (!rx_ts)
3591 return;
3592
3593 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
3594 &rx_ts->seq_id);
3595 lan8814_match_rx_ts(ptp_priv, rx_ts);
3596
3597 /* If other timestamps are available in the FIFO,
3598 * process them.
3599 */
3600 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3601 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
3602 }
3603
lan8814_handle_ptp_interrupt(struct phy_device * phydev,u16 status)3604 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
3605 {
3606 struct kszphy_priv *priv = phydev->priv;
3607 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3608
3609 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
3610 lan8814_get_tx_ts(ptp_priv);
3611
3612 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
3613 lan8814_get_rx_ts(ptp_priv);
3614
3615 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
3616 lan8814_flush_fifo(phydev, true);
3617 skb_queue_purge(&ptp_priv->tx_queue);
3618 }
3619
3620 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
3621 lan8814_flush_fifo(phydev, false);
3622 skb_queue_purge(&ptp_priv->rx_queue);
3623 }
3624 }
3625
lan8814_gpio_process_cap(struct lan8814_shared_priv * shared)3626 static int lan8814_gpio_process_cap(struct lan8814_shared_priv *shared)
3627 {
3628 struct phy_device *phydev = shared->phydev;
3629 struct ptp_clock_event ptp_event = {0};
3630 unsigned long nsec;
3631 s64 sec;
3632 u16 tmp;
3633
3634 /* This is 0 because whatever was the input pin it was mapped it to
3635 * ltc gpio pin 0
3636 */
3637 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_SEL);
3638 tmp |= PTP_GPIO_SEL_GPIO_SEL(0);
3639 lanphy_write_page_reg(phydev, 4, PTP_GPIO_SEL, tmp);
3640
3641 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS);
3642 if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
3643 !(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))
3644 return -1;
3645
3646 if (tmp & BIT(0)) {
3647 sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_HI_CAP);
3648 sec <<= 16;
3649 sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_LO_CAP);
3650
3651 nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3652 nsec <<= 16;
3653 nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3654 } else {
3655 sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_HI_CAP);
3656 sec <<= 16;
3657 sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_LO_CAP);
3658
3659 nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3660 nsec <<= 16;
3661 nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3662 }
3663
3664 ptp_event.index = 0;
3665 ptp_event.timestamp = ktime_set(sec, nsec);
3666 ptp_event.type = PTP_CLOCK_EXTTS;
3667 ptp_clock_event(shared->ptp_clock, &ptp_event);
3668
3669 return 0;
3670 }
3671
lan8814_handle_gpio_interrupt(struct phy_device * phydev,u16 status)3672 static int lan8814_handle_gpio_interrupt(struct phy_device *phydev, u16 status)
3673 {
3674 struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
3675 int ret;
3676
3677 mutex_lock(&shared->shared_lock);
3678 ret = lan8814_gpio_process_cap(shared);
3679 mutex_unlock(&shared->shared_lock);
3680
3681 return ret;
3682 }
3683
lan8804_config_init(struct phy_device * phydev)3684 static int lan8804_config_init(struct phy_device *phydev)
3685 {
3686 int val;
3687
3688 /* MDI-X setting for swap A,B transmit */
3689 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3690 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3691 val |= LAN8804_ALIGN_TX_A_B_SWAP;
3692 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3693
3694 /* Make sure that the PHY will not stop generating the clock when the
3695 * link partner goes down
3696 */
3697 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3698 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3699
3700 return 0;
3701 }
3702
lan8804_handle_interrupt(struct phy_device * phydev)3703 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3704 {
3705 int status;
3706
3707 status = phy_read(phydev, LAN8814_INTS);
3708 if (status < 0) {
3709 phy_error(phydev);
3710 return IRQ_NONE;
3711 }
3712
3713 if (status > 0)
3714 phy_trigger_machine(phydev);
3715
3716 return IRQ_HANDLED;
3717 }
3718
3719 #define LAN8804_OUTPUT_CONTROL 25
3720 #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3721 #define LAN8804_CONTROL 31
3722 #define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3723
lan8804_config_intr(struct phy_device * phydev)3724 static int lan8804_config_intr(struct phy_device *phydev)
3725 {
3726 int err;
3727
3728 /* This is an internal PHY of lan966x and is not possible to change the
3729 * polarity on the GIC found in lan966x, therefore change the polarity
3730 * of the interrupt in the PHY from being active low instead of active
3731 * high.
3732 */
3733 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3734
3735 /* By default interrupt buffer is open-drain in which case the interrupt
3736 * can be active only low. Therefore change the interrupt buffer to be
3737 * push-pull to be able to change interrupt polarity
3738 */
3739 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3740 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3741
3742 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3743 err = phy_read(phydev, LAN8814_INTS);
3744 if (err < 0)
3745 return err;
3746
3747 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3748 if (err)
3749 return err;
3750 } else {
3751 err = phy_write(phydev, LAN8814_INTC, 0);
3752 if (err)
3753 return err;
3754
3755 err = phy_read(phydev, LAN8814_INTS);
3756 if (err < 0)
3757 return err;
3758 }
3759
3760 return 0;
3761 }
3762
lan8814_handle_interrupt(struct phy_device * phydev)3763 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3764 {
3765 int ret = IRQ_NONE;
3766 int irq_status;
3767
3768 irq_status = phy_read(phydev, LAN8814_INTS);
3769 if (irq_status < 0) {
3770 phy_error(phydev);
3771 return IRQ_NONE;
3772 }
3773
3774 if (irq_status & LAN8814_INT_LINK) {
3775 phy_trigger_machine(phydev);
3776 ret = IRQ_HANDLED;
3777 }
3778
3779 while (true) {
3780 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3781 if (!irq_status)
3782 break;
3783
3784 lan8814_handle_ptp_interrupt(phydev, irq_status);
3785 ret = IRQ_HANDLED;
3786 }
3787
3788 if (!lan8814_handle_gpio_interrupt(phydev, irq_status))
3789 ret = IRQ_HANDLED;
3790
3791 return ret;
3792 }
3793
lan8814_ack_interrupt(struct phy_device * phydev)3794 static int lan8814_ack_interrupt(struct phy_device *phydev)
3795 {
3796 /* bit[12..0] int status, which is a read and clear register. */
3797 int rc;
3798
3799 rc = phy_read(phydev, LAN8814_INTS);
3800
3801 return (rc < 0) ? rc : 0;
3802 }
3803
lan8814_config_intr(struct phy_device * phydev)3804 static int lan8814_config_intr(struct phy_device *phydev)
3805 {
3806 int err;
3807
3808 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3809 LAN8814_INTR_CTRL_REG_POLARITY |
3810 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3811
3812 /* enable / disable interrupts */
3813 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3814 err = lan8814_ack_interrupt(phydev);
3815 if (err)
3816 return err;
3817
3818 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3819 } else {
3820 err = phy_write(phydev, LAN8814_INTC, 0);
3821 if (err)
3822 return err;
3823
3824 err = lan8814_ack_interrupt(phydev);
3825 }
3826
3827 return err;
3828 }
3829
lan8814_ptp_init(struct phy_device * phydev)3830 static void lan8814_ptp_init(struct phy_device *phydev)
3831 {
3832 struct kszphy_priv *priv = phydev->priv;
3833 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3834 u32 temp;
3835
3836 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3837 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3838 return;
3839
3840 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3841
3842 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3843 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3844 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3845
3846 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3847 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3848 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3849
3850 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3851 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3852
3853 /* Removing default registers configs related to L2 and IP */
3854 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3855 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3856 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3857 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3858
3859 /* Disable checking for minorVersionPTP field */
3860 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3861 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3862 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3863 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3864
3865 skb_queue_head_init(&ptp_priv->tx_queue);
3866 skb_queue_head_init(&ptp_priv->rx_queue);
3867 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3868 spin_lock_init(&ptp_priv->rx_ts_lock);
3869
3870 ptp_priv->phydev = phydev;
3871
3872 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3873 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3874 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3875 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3876
3877 phydev->mii_ts = &ptp_priv->mii_ts;
3878
3879 /* Timestamp selected by default to keep legacy API */
3880 phydev->default_timestamp = true;
3881 }
3882
lan8814_ptp_probe_once(struct phy_device * phydev)3883 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3884 {
3885 struct lan8814_shared_priv *shared = phy_package_get_priv(phydev);
3886
3887 /* Initialise shared lock for clock*/
3888 mutex_init(&shared->shared_lock);
3889
3890 shared->pin_config = devm_kmalloc_array(&phydev->mdio.dev,
3891 LAN8814_PTP_GPIO_NUM,
3892 sizeof(*shared->pin_config),
3893 GFP_KERNEL);
3894 if (!shared->pin_config)
3895 return -ENOMEM;
3896
3897 for (int i = 0; i < LAN8814_PTP_GPIO_NUM; i++) {
3898 struct ptp_pin_desc *ptp_pin = &shared->pin_config[i];
3899
3900 memset(ptp_pin, 0, sizeof(*ptp_pin));
3901 snprintf(ptp_pin->name,
3902 sizeof(ptp_pin->name), "lan8814_ptp_pin_%02d", i);
3903 ptp_pin->index = i;
3904 ptp_pin->func = PTP_PF_NONE;
3905 }
3906
3907 shared->ptp_clock_info.owner = THIS_MODULE;
3908 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3909 shared->ptp_clock_info.max_adj = 31249999;
3910 shared->ptp_clock_info.n_alarm = 0;
3911 shared->ptp_clock_info.n_ext_ts = LAN8814_PTP_EXTTS_NUM;
3912 shared->ptp_clock_info.n_pins = LAN8814_PTP_GPIO_NUM;
3913 shared->ptp_clock_info.pps = 0;
3914 shared->ptp_clock_info.pin_config = shared->pin_config;
3915 shared->ptp_clock_info.n_per_out = LAN8814_PTP_PEROUT_NUM;
3916 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3917 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3918 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3919 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3920 shared->ptp_clock_info.getcrosststamp = NULL;
3921 shared->ptp_clock_info.enable = lan8814_ptpci_enable;
3922 shared->ptp_clock_info.verify = lan8814_ptpci_verify;
3923
3924 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3925 &phydev->mdio.dev);
3926 if (IS_ERR(shared->ptp_clock)) {
3927 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3928 PTR_ERR(shared->ptp_clock));
3929 return -EINVAL;
3930 }
3931
3932 /* Check if PHC support is missing at the configuration level */
3933 if (!shared->ptp_clock)
3934 return 0;
3935
3936 phydev_dbg(phydev, "successfully registered ptp clock\n");
3937
3938 shared->phydev = phydev;
3939
3940 /* The EP.4 is shared between all the PHYs in the package and also it
3941 * can be accessed by any of the PHYs
3942 */
3943 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3944 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3945 PTP_OPERATING_MODE_STANDALONE_);
3946
3947 /* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */
3948 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_);
3949
3950 return 0;
3951 }
3952
lan8814_setup_led(struct phy_device * phydev,int val)3953 static void lan8814_setup_led(struct phy_device *phydev, int val)
3954 {
3955 int temp;
3956
3957 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3958
3959 if (val)
3960 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3961 else
3962 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3963
3964 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3965 }
3966
lan8814_config_init(struct phy_device * phydev)3967 static int lan8814_config_init(struct phy_device *phydev)
3968 {
3969 struct kszphy_priv *lan8814 = phydev->priv;
3970 int val;
3971
3972 /* Reset the PHY */
3973 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3974 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3975 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3976
3977 /* Disable ANEG with QSGMII PCS Host side */
3978 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3979 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3980 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3981
3982 /* MDI-X setting for swap A,B transmit */
3983 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3984 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3985 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3986 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3987
3988 if (lan8814->led_mode >= 0)
3989 lan8814_setup_led(phydev, lan8814->led_mode);
3990
3991 return 0;
3992 }
3993
3994 /* It is expected that there will not be any 'lan8814_take_coma_mode'
3995 * function called in suspend. Because the GPIO line can be shared, so if one of
3996 * the phys goes back in coma mode, then all the other PHYs will go, which is
3997 * wrong.
3998 */
lan8814_release_coma_mode(struct phy_device * phydev)3999 static int lan8814_release_coma_mode(struct phy_device *phydev)
4000 {
4001 struct gpio_desc *gpiod;
4002
4003 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
4004 GPIOD_OUT_HIGH_OPEN_DRAIN |
4005 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
4006 if (IS_ERR(gpiod))
4007 return PTR_ERR(gpiod);
4008
4009 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
4010 gpiod_set_value_cansleep(gpiod, 0);
4011
4012 return 0;
4013 }
4014
lan8814_clear_2psp_bit(struct phy_device * phydev)4015 static void lan8814_clear_2psp_bit(struct phy_device *phydev)
4016 {
4017 u16 val;
4018
4019 /* It was noticed that when traffic is passing through the PHY and the
4020 * cable is removed then the LED was still one even though there is no
4021 * link
4022 */
4023 val = lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE);
4024 val &= ~LAN8814_EEE_STATE_MASK2P5P;
4025 lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val);
4026 }
4027
lan8814_update_meas_time(struct phy_device * phydev)4028 static void lan8814_update_meas_time(struct phy_device *phydev)
4029 {
4030 u16 val;
4031
4032 /* By setting the measure time to a value of 0xb this will allow cables
4033 * longer than 100m to be used. This configuration can be used
4034 * regardless of the mode of operation of the PHY
4035 */
4036 val = lanphy_read_page_reg(phydev, 1, LAN8814_PD_CONTROLS);
4037 val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;
4038 val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;
4039 lanphy_write_page_reg(phydev, 1, LAN8814_PD_CONTROLS, val);
4040 }
4041
lan8814_probe(struct phy_device * phydev)4042 static int lan8814_probe(struct phy_device *phydev)
4043 {
4044 const struct kszphy_type *type = phydev->drv->driver_data;
4045 struct kszphy_priv *priv;
4046 u16 addr;
4047 int err;
4048
4049 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
4050 if (!priv)
4051 return -ENOMEM;
4052
4053 phydev->priv = priv;
4054
4055 priv->type = type;
4056
4057 kszphy_parse_led_mode(phydev);
4058
4059 /* Strap-in value for PHY address, below register read gives starting
4060 * phy address value
4061 */
4062 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
4063 devm_phy_package_join(&phydev->mdio.dev, phydev,
4064 addr, sizeof(struct lan8814_shared_priv));
4065
4066 if (phy_package_init_once(phydev)) {
4067 err = lan8814_release_coma_mode(phydev);
4068 if (err)
4069 return err;
4070
4071 err = lan8814_ptp_probe_once(phydev);
4072 if (err)
4073 return err;
4074 }
4075
4076 lan8814_ptp_init(phydev);
4077
4078 /* Errata workarounds */
4079 lan8814_clear_2psp_bit(phydev);
4080 lan8814_update_meas_time(phydev);
4081
4082 return 0;
4083 }
4084
4085 #define LAN8841_MMD_TIMER_REG 0
4086 #define LAN8841_MMD0_REGISTER_17 17
4087 #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
4088 #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
4089 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
4090 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
4091 #define LAN8841_MMD_ANALOG_REG 28
4092 #define LAN8841_ANALOG_CONTROL_1 1
4093 #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
4094 #define LAN8841_ANALOG_CONTROL_10 13
4095 #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
4096 #define LAN8841_ANALOG_CONTROL_11 14
4097 #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
4098 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
4099 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
4100 #define LAN8841_BTRX_POWER_DOWN 70
4101 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
4102 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
4103 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
4104 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
4105 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
4106 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
4107 #define LAN8841_ADC_CHANNEL_MASK 198
4108 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
4109 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
4110 #define LAN8841_PTP_RX_VERSION 374
4111 #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
4112 #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
4113 #define LAN8841_PTP_TX_VERSION 438
4114 #define LAN8841_PTP_CMD_CTL 256
4115 #define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
4116 #define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
4117 #define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
4118 #define LAN8841_PTP_RX_PARSE_CONFIG 368
4119 #define LAN8841_PTP_TX_PARSE_CONFIG 432
4120 #define LAN8841_PTP_RX_MODE 381
4121 #define LAN8841_PTP_INSERT_TS_EN BIT(0)
4122 #define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
4123
lan8841_config_init(struct phy_device * phydev)4124 static int lan8841_config_init(struct phy_device *phydev)
4125 {
4126 int ret;
4127
4128 ret = ksz9131_config_init(phydev);
4129 if (ret)
4130 return ret;
4131
4132 /* Initialize the HW by resetting everything */
4133 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4134 LAN8841_PTP_CMD_CTL,
4135 LAN8841_PTP_CMD_CTL_PTP_RESET,
4136 LAN8841_PTP_CMD_CTL_PTP_RESET);
4137
4138 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4139 LAN8841_PTP_CMD_CTL,
4140 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
4141 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
4142
4143 /* Don't process any frames */
4144 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4145 LAN8841_PTP_RX_PARSE_CONFIG, 0);
4146 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4147 LAN8841_PTP_TX_PARSE_CONFIG, 0);
4148 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4149 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
4150 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4151 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
4152 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4153 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
4154 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4155 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
4156
4157 /* Disable checking for minorVersionPTP field */
4158 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4159 LAN8841_PTP_RX_VERSION, 0xff00);
4160 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4161 LAN8841_PTP_TX_VERSION, 0xff00);
4162
4163 /* 100BT Clause 40 improvenent errata */
4164 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4165 LAN8841_ANALOG_CONTROL_1,
4166 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
4167 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4168 LAN8841_ANALOG_CONTROL_10,
4169 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
4170
4171 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
4172 * Magnetics
4173 */
4174 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4175 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
4176 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
4177 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4178 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
4179 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
4180 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4181 LAN8841_BTRX_POWER_DOWN,
4182 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
4183 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
4184 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
4185 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
4186 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
4187 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
4188 }
4189
4190 /* LDO Adjustment errata */
4191 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4192 LAN8841_ANALOG_CONTROL_11,
4193 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
4194
4195 /* 100BT RGMII latency tuning errata */
4196 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
4197 LAN8841_ADC_CHANNEL_MASK, 0x0);
4198 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
4199 LAN8841_MMD0_REGISTER_17,
4200 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
4201 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
4202
4203 return 0;
4204 }
4205
4206 #define LAN8841_OUTPUT_CTRL 25
4207 #define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
4208 #define LAN8841_INT_PTP BIT(9)
4209
lan8841_config_intr(struct phy_device * phydev)4210 static int lan8841_config_intr(struct phy_device *phydev)
4211 {
4212 int err;
4213
4214 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
4215 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
4216
4217 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4218 err = phy_read(phydev, LAN8814_INTS);
4219 if (err < 0)
4220 return err;
4221
4222 /* Enable / disable interrupts. It is OK to enable PTP interrupt
4223 * even if it PTP is not enabled. Because the underneath blocks
4224 * will not enable the PTP so we will never get the PTP
4225 * interrupt.
4226 */
4227 err = phy_write(phydev, LAN8814_INTC,
4228 LAN8814_INT_LINK | LAN8841_INT_PTP);
4229 } else {
4230 err = phy_write(phydev, LAN8814_INTC, 0);
4231 if (err)
4232 return err;
4233
4234 err = phy_read(phydev, LAN8814_INTS);
4235 if (err < 0)
4236 return err;
4237
4238 /* Getting a positive value doesn't mean that is an error, it
4239 * just indicates what was the status. Therefore make sure to
4240 * clear the value and say that there is no error.
4241 */
4242 err = 0;
4243 }
4244
4245 return err;
4246 }
4247
4248 #define LAN8841_PTP_TX_EGRESS_SEC_LO 453
4249 #define LAN8841_PTP_TX_EGRESS_SEC_HI 452
4250 #define LAN8841_PTP_TX_EGRESS_NS_LO 451
4251 #define LAN8841_PTP_TX_EGRESS_NS_HI 450
4252 #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
4253 #define LAN8841_PTP_TX_MSG_HEADER2 455
4254
lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv * ptp_priv,u32 * sec,u32 * nsec,u16 * seq)4255 static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
4256 u32 *sec, u32 *nsec, u16 *seq)
4257 {
4258 struct phy_device *phydev = ptp_priv->phydev;
4259
4260 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
4261 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
4262 return false;
4263
4264 *nsec = ((*nsec & 0x3fff) << 16);
4265 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
4266
4267 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
4268 *sec = *sec << 16;
4269 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
4270
4271 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
4272
4273 return true;
4274 }
4275
lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv * ptp_priv)4276 static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
4277 {
4278 u32 sec, nsec;
4279 u16 seq;
4280
4281 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
4282 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
4283 }
4284
4285 #define LAN8841_PTP_INT_STS 259
4286 #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
4287 #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
4288 #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
4289
lan8841_ptp_flush_fifo(struct kszphy_ptp_priv * ptp_priv)4290 static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
4291 {
4292 struct phy_device *phydev = ptp_priv->phydev;
4293 int i;
4294
4295 for (i = 0; i < FIFO_SIZE; ++i)
4296 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
4297
4298 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
4299 }
4300
4301 #define LAN8841_PTP_GPIO_CAP_STS 506
4302 #define LAN8841_PTP_GPIO_SEL 327
4303 #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
4304 #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
4305 #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
4306 #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
4307 #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
4308 #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
4309 #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
4310 #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
4311 #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
4312
lan8841_gpio_process_cap(struct kszphy_ptp_priv * ptp_priv)4313 static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
4314 {
4315 struct phy_device *phydev = ptp_priv->phydev;
4316 struct ptp_clock_event ptp_event = {0};
4317 int pin, ret, tmp;
4318 s32 sec, nsec;
4319
4320 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
4321 if (pin == -1)
4322 return;
4323
4324 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
4325 if (tmp < 0)
4326 return;
4327
4328 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
4329 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
4330 if (ret)
4331 return;
4332
4333 mutex_lock(&ptp_priv->ptp_lock);
4334 if (tmp & BIT(pin)) {
4335 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
4336 sec <<= 16;
4337 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
4338
4339 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
4340 nsec <<= 16;
4341 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
4342 } else {
4343 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
4344 sec <<= 16;
4345 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
4346
4347 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
4348 nsec <<= 16;
4349 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
4350 }
4351 mutex_unlock(&ptp_priv->ptp_lock);
4352 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
4353 if (ret)
4354 return;
4355
4356 ptp_event.index = 0;
4357 ptp_event.timestamp = ktime_set(sec, nsec);
4358 ptp_event.type = PTP_CLOCK_EXTTS;
4359 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
4360 }
4361
lan8841_handle_ptp_interrupt(struct phy_device * phydev)4362 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
4363 {
4364 struct kszphy_priv *priv = phydev->priv;
4365 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4366 u16 status;
4367
4368 do {
4369 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
4370
4371 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
4372 lan8841_ptp_process_tx_ts(ptp_priv);
4373
4374 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
4375 lan8841_gpio_process_cap(ptp_priv);
4376
4377 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
4378 lan8841_ptp_flush_fifo(ptp_priv);
4379 skb_queue_purge(&ptp_priv->tx_queue);
4380 }
4381
4382 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
4383 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
4384 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
4385 }
4386
4387 #define LAN8841_INTS_PTP BIT(9)
4388
lan8841_handle_interrupt(struct phy_device * phydev)4389 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
4390 {
4391 irqreturn_t ret = IRQ_NONE;
4392 int irq_status;
4393
4394 irq_status = phy_read(phydev, LAN8814_INTS);
4395 if (irq_status < 0) {
4396 phy_error(phydev);
4397 return IRQ_NONE;
4398 }
4399
4400 if (irq_status & LAN8814_INT_LINK) {
4401 phy_trigger_machine(phydev);
4402 ret = IRQ_HANDLED;
4403 }
4404
4405 if (irq_status & LAN8841_INTS_PTP) {
4406 lan8841_handle_ptp_interrupt(phydev);
4407 ret = IRQ_HANDLED;
4408 }
4409
4410 return ret;
4411 }
4412
lan8841_ts_info(struct mii_timestamper * mii_ts,struct kernel_ethtool_ts_info * info)4413 static int lan8841_ts_info(struct mii_timestamper *mii_ts,
4414 struct kernel_ethtool_ts_info *info)
4415 {
4416 struct kszphy_ptp_priv *ptp_priv;
4417
4418 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4419
4420 info->phc_index = ptp_priv->ptp_clock ?
4421 ptp_clock_index(ptp_priv->ptp_clock) : -1;
4422 if (info->phc_index == -1)
4423 return 0;
4424
4425 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
4426 SOF_TIMESTAMPING_RX_HARDWARE |
4427 SOF_TIMESTAMPING_RAW_HARDWARE;
4428
4429 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
4430 (1 << HWTSTAMP_TX_ON) |
4431 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
4432
4433 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
4434 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
4435 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
4436 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
4437
4438 return 0;
4439 }
4440
4441 #define LAN8841_PTP_INT_EN 260
4442 #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
4443 #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
4444
lan8841_ptp_enable_processing(struct kszphy_ptp_priv * ptp_priv,bool enable)4445 static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
4446 bool enable)
4447 {
4448 struct phy_device *phydev = ptp_priv->phydev;
4449
4450 if (enable) {
4451 /* Enable interrupts on the TX side */
4452 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4453 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4454 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
4455 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4456 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
4457
4458 /* Enable the modification of the frame on RX side,
4459 * this will add the ns and 2 bits of sec in the reserved field
4460 * of the PTP header
4461 */
4462 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4463 LAN8841_PTP_RX_MODE,
4464 LAN8841_PTP_INSERT_TS_EN |
4465 LAN8841_PTP_INSERT_TS_32BIT,
4466 LAN8841_PTP_INSERT_TS_EN |
4467 LAN8841_PTP_INSERT_TS_32BIT);
4468
4469 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
4470 } else {
4471 /* Disable interrupts on the TX side */
4472 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4473 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4474 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
4475
4476 /* Disable modification of the RX frames */
4477 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4478 LAN8841_PTP_RX_MODE,
4479 LAN8841_PTP_INSERT_TS_EN |
4480 LAN8841_PTP_INSERT_TS_32BIT, 0);
4481
4482 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4483 }
4484 }
4485
4486 #define LAN8841_PTP_RX_TIMESTAMP_EN 379
4487 #define LAN8841_PTP_TX_TIMESTAMP_EN 443
4488 #define LAN8841_PTP_TX_MOD 445
4489
lan8841_hwtstamp(struct mii_timestamper * mii_ts,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)4490 static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
4491 struct kernel_hwtstamp_config *config,
4492 struct netlink_ext_ack *extack)
4493 {
4494 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4495 struct phy_device *phydev = ptp_priv->phydev;
4496 int txcfg = 0, rxcfg = 0;
4497 int pkt_ts_enable;
4498
4499 ptp_priv->hwts_tx_type = config->tx_type;
4500 ptp_priv->rx_filter = config->rx_filter;
4501
4502 switch (config->rx_filter) {
4503 case HWTSTAMP_FILTER_NONE:
4504 ptp_priv->layer = 0;
4505 ptp_priv->version = 0;
4506 break;
4507 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4508 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4509 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4510 ptp_priv->layer = PTP_CLASS_L4;
4511 ptp_priv->version = PTP_CLASS_V2;
4512 break;
4513 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4514 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4515 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4516 ptp_priv->layer = PTP_CLASS_L2;
4517 ptp_priv->version = PTP_CLASS_V2;
4518 break;
4519 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4520 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4521 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4522 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
4523 ptp_priv->version = PTP_CLASS_V2;
4524 break;
4525 default:
4526 return -ERANGE;
4527 }
4528
4529 /* Setup parsing of the frames and enable the timestamping for ptp
4530 * frames
4531 */
4532 if (ptp_priv->layer & PTP_CLASS_L2) {
4533 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
4534 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
4535 } else if (ptp_priv->layer & PTP_CLASS_L4) {
4536 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
4537 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
4538 }
4539
4540 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
4541 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
4542
4543 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
4544 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
4545 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
4546 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
4547
4548 /* Enable / disable of the TX timestamp in the SYNC frames */
4549 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
4550 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
4551 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
4552 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
4553
4554 /* Now enable/disable the timestamping */
4555 lan8841_ptp_enable_processing(ptp_priv,
4556 config->rx_filter != HWTSTAMP_FILTER_NONE);
4557
4558 skb_queue_purge(&ptp_priv->tx_queue);
4559
4560 lan8841_ptp_flush_fifo(ptp_priv);
4561
4562 return 0;
4563 }
4564
lan8841_rxtstamp(struct mii_timestamper * mii_ts,struct sk_buff * skb,int type)4565 static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
4566 struct sk_buff *skb, int type)
4567 {
4568 struct kszphy_ptp_priv *ptp_priv =
4569 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4570 struct ptp_header *header = ptp_parse_header(skb, type);
4571 struct skb_shared_hwtstamps *shhwtstamps;
4572 struct timespec64 ts;
4573 unsigned long flags;
4574 u32 ts_header;
4575
4576 if (!header)
4577 return false;
4578
4579 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
4580 type == PTP_CLASS_NONE)
4581 return false;
4582
4583 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
4584 return false;
4585
4586 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4587 ts.tv_sec = ptp_priv->seconds;
4588 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4589 ts_header = __be32_to_cpu(header->reserved2);
4590
4591 shhwtstamps = skb_hwtstamps(skb);
4592 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4593
4594 /* Check for any wrap arounds for the second part */
4595 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
4596 ts.tv_sec -= GENMASK(1, 0) + 1;
4597 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
4598 ts.tv_sec += 1;
4599
4600 shhwtstamps->hwtstamp =
4601 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
4602 ts_header & GENMASK(29, 0));
4603 header->reserved2 = 0;
4604
4605 netif_rx(skb);
4606
4607 return true;
4608 }
4609
4610 #define LAN8841_EVENT_A 0
4611 #define LAN8841_EVENT_B 1
4612 #define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
4613 #define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
4614 #define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
4615 #define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
4616
lan8841_ptp_set_target(struct kszphy_ptp_priv * ptp_priv,u8 event,s64 sec,u32 nsec)4617 static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
4618 s64 sec, u32 nsec)
4619 {
4620 struct phy_device *phydev = ptp_priv->phydev;
4621 int ret;
4622
4623 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
4624 upper_16_bits(sec));
4625 if (ret)
4626 return ret;
4627
4628 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
4629 lower_16_bits(sec));
4630 if (ret)
4631 return ret;
4632
4633 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
4634 upper_16_bits(nsec));
4635 if (ret)
4636 return ret;
4637
4638 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
4639 lower_16_bits(nsec));
4640 }
4641
4642 #define LAN8841_BUFFER_TIME 2
4643
lan8841_ptp_update_target(struct kszphy_ptp_priv * ptp_priv,const struct timespec64 * ts)4644 static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
4645 const struct timespec64 *ts)
4646 {
4647 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
4648 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
4649 }
4650
4651 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
4652 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
4653 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
4654 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
4655
lan8841_ptp_set_reload(struct kszphy_ptp_priv * ptp_priv,u8 event,s64 sec,u32 nsec)4656 static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
4657 s64 sec, u32 nsec)
4658 {
4659 struct phy_device *phydev = ptp_priv->phydev;
4660 int ret;
4661
4662 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
4663 upper_16_bits(sec));
4664 if (ret)
4665 return ret;
4666
4667 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
4668 lower_16_bits(sec));
4669 if (ret)
4670 return ret;
4671
4672 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
4673 upper_16_bits(nsec));
4674 if (ret)
4675 return ret;
4676
4677 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
4678 lower_16_bits(nsec));
4679 }
4680
4681 #define LAN8841_PTP_LTC_SET_SEC_HI 262
4682 #define LAN8841_PTP_LTC_SET_SEC_MID 263
4683 #define LAN8841_PTP_LTC_SET_SEC_LO 264
4684 #define LAN8841_PTP_LTC_SET_NS_HI 265
4685 #define LAN8841_PTP_LTC_SET_NS_LO 266
4686 #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
4687
lan8841_ptp_settime64(struct ptp_clock_info * ptp,const struct timespec64 * ts)4688 static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
4689 const struct timespec64 *ts)
4690 {
4691 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4692 ptp_clock_info);
4693 struct phy_device *phydev = ptp_priv->phydev;
4694 unsigned long flags;
4695 int ret;
4696
4697 /* Set the value to be stored */
4698 mutex_lock(&ptp_priv->ptp_lock);
4699 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
4700 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
4701 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
4702 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
4703 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
4704
4705 /* Set the command to load the LTC */
4706 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4707 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
4708 ret = lan8841_ptp_update_target(ptp_priv, ts);
4709 mutex_unlock(&ptp_priv->ptp_lock);
4710
4711 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4712 ptp_priv->seconds = ts->tv_sec;
4713 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4714
4715 return ret;
4716 }
4717
4718 #define LAN8841_PTP_LTC_RD_SEC_HI 358
4719 #define LAN8841_PTP_LTC_RD_SEC_MID 359
4720 #define LAN8841_PTP_LTC_RD_SEC_LO 360
4721 #define LAN8841_PTP_LTC_RD_NS_HI 361
4722 #define LAN8841_PTP_LTC_RD_NS_LO 362
4723 #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
4724
lan8841_ptp_gettime64(struct ptp_clock_info * ptp,struct timespec64 * ts)4725 static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
4726 struct timespec64 *ts)
4727 {
4728 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4729 ptp_clock_info);
4730 struct phy_device *phydev = ptp_priv->phydev;
4731 time64_t s;
4732 s64 ns;
4733
4734 mutex_lock(&ptp_priv->ptp_lock);
4735 /* Issue the command to read the LTC */
4736 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4737 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4738
4739 /* Read the LTC */
4740 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4741 s <<= 16;
4742 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4743 s <<= 16;
4744 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4745
4746 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
4747 ns <<= 16;
4748 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
4749 mutex_unlock(&ptp_priv->ptp_lock);
4750
4751 set_normalized_timespec64(ts, s, ns);
4752 return 0;
4753 }
4754
lan8841_ptp_getseconds(struct ptp_clock_info * ptp,struct timespec64 * ts)4755 static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4756 struct timespec64 *ts)
4757 {
4758 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4759 ptp_clock_info);
4760 struct phy_device *phydev = ptp_priv->phydev;
4761 time64_t s;
4762
4763 mutex_lock(&ptp_priv->ptp_lock);
4764 /* Issue the command to read the LTC */
4765 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4766 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4767
4768 /* Read the LTC */
4769 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4770 s <<= 16;
4771 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4772 s <<= 16;
4773 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4774 mutex_unlock(&ptp_priv->ptp_lock);
4775
4776 set_normalized_timespec64(ts, s, 0);
4777 }
4778
4779 #define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4780 #define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4781 #define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4782 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4783 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4784
lan8841_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)4785 static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4786 {
4787 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4788 ptp_clock_info);
4789 struct phy_device *phydev = ptp_priv->phydev;
4790 struct timespec64 ts;
4791 bool add = true;
4792 u32 nsec;
4793 s32 sec;
4794 int ret;
4795
4796 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4797 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4798 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4799 * increment so the value can be bigger than 15 sec. Therefore limit the
4800 * possible adjustments so we will not have these corner cases
4801 */
4802 if (delta > 10000000000LL || delta < -10000000000LL) {
4803 /* The timeadjustment is too big, so fall back using set time */
4804 u64 now;
4805
4806 ptp->gettime64(ptp, &ts);
4807
4808 now = ktime_to_ns(timespec64_to_ktime(ts));
4809 ts = ns_to_timespec64(now + delta);
4810
4811 ptp->settime64(ptp, &ts);
4812 return 0;
4813 }
4814
4815 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4816 if (delta < 0 && nsec != 0) {
4817 /* It is not allowed to adjust low the nsec part, therefore
4818 * subtract more from second part and add to nanosecond such
4819 * that would roll over, so the second part will increase
4820 */
4821 sec--;
4822 nsec = NSEC_PER_SEC - nsec;
4823 }
4824
4825 /* Calculate the adjustments and the direction */
4826 if (delta < 0)
4827 add = false;
4828
4829 if (nsec > 0)
4830 /* add 8 ns to cover the likely normal increment */
4831 nsec += 8;
4832
4833 if (nsec >= NSEC_PER_SEC) {
4834 /* carry into seconds */
4835 sec++;
4836 nsec -= NSEC_PER_SEC;
4837 }
4838
4839 mutex_lock(&ptp_priv->ptp_lock);
4840 if (sec) {
4841 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4842 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4843 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4844 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4845 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4846 }
4847
4848 if (nsec) {
4849 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4850 nsec & 0xffff);
4851 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4852 (nsec >> 16) & 0x3fff);
4853 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4854 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4855 }
4856 mutex_unlock(&ptp_priv->ptp_lock);
4857
4858 /* Update the target clock */
4859 ptp->gettime64(ptp, &ts);
4860 mutex_lock(&ptp_priv->ptp_lock);
4861 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4862 mutex_unlock(&ptp_priv->ptp_lock);
4863
4864 return ret;
4865 }
4866
4867 #define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4868 #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4869 #define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4870
lan8841_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)4871 static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4872 {
4873 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4874 ptp_clock_info);
4875 struct phy_device *phydev = ptp_priv->phydev;
4876 bool faster = true;
4877 u32 rate;
4878
4879 if (!scaled_ppm)
4880 return 0;
4881
4882 if (scaled_ppm < 0) {
4883 scaled_ppm = -scaled_ppm;
4884 faster = false;
4885 }
4886
4887 rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4888 rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4889
4890 mutex_lock(&ptp_priv->ptp_lock);
4891 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4892 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4893 : upper_16_bits(rate) & 0x3fff);
4894 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4895 mutex_unlock(&ptp_priv->ptp_lock);
4896
4897 return 0;
4898 }
4899
lan8841_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)4900 static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4901 enum ptp_pin_function func, unsigned int chan)
4902 {
4903 switch (func) {
4904 case PTP_PF_NONE:
4905 case PTP_PF_PEROUT:
4906 case PTP_PF_EXTTS:
4907 break;
4908 default:
4909 return -1;
4910 }
4911
4912 return 0;
4913 }
4914
4915 #define LAN8841_PTP_GPIO_NUM 10
4916 #define LAN8841_GPIO_EN 128
4917 #define LAN8841_GPIO_DIR 129
4918 #define LAN8841_GPIO_BUF 130
4919
lan8841_ptp_perout_off(struct kszphy_ptp_priv * ptp_priv,int pin)4920 static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4921 {
4922 struct phy_device *phydev = ptp_priv->phydev;
4923 int ret;
4924
4925 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4926 if (ret)
4927 return ret;
4928
4929 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4930 if (ret)
4931 return ret;
4932
4933 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4934 }
4935
lan8841_ptp_perout_on(struct kszphy_ptp_priv * ptp_priv,int pin)4936 static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4937 {
4938 struct phy_device *phydev = ptp_priv->phydev;
4939 int ret;
4940
4941 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4942 if (ret)
4943 return ret;
4944
4945 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4946 if (ret)
4947 return ret;
4948
4949 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4950 }
4951
4952 #define LAN8841_GPIO_DATA_SEL1 131
4953 #define LAN8841_GPIO_DATA_SEL2 132
4954 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4955 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4956 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4957 #define LAN8841_PTP_GENERAL_CONFIG 257
4958 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4959 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4960 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4961 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4962 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4963 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4964
lan8841_ptp_remove_event(struct kszphy_ptp_priv * ptp_priv,int pin,u8 event)4965 static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4966 u8 event)
4967 {
4968 struct phy_device *phydev = ptp_priv->phydev;
4969 u16 tmp;
4970 int ret;
4971
4972 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4973 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4974 * depending on the pin, it requires to read a different register
4975 */
4976 if (pin < 5) {
4977 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4978 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4979 } else {
4980 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4981 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4982 }
4983 if (ret)
4984 return ret;
4985
4986 /* Disable the event */
4987 if (event == LAN8841_EVENT_A)
4988 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4989 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4990 else
4991 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4992 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4993 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4994 }
4995
lan8841_ptp_enable_event(struct kszphy_ptp_priv * ptp_priv,int pin,u8 event,int pulse_width)4996 static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4997 u8 event, int pulse_width)
4998 {
4999 struct phy_device *phydev = ptp_priv->phydev;
5000 u16 tmp;
5001 int ret;
5002
5003 /* Enable the event */
5004 if (event == LAN8841_EVENT_A)
5005 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
5006 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5007 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
5008 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
5009 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
5010 else
5011 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
5012 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5013 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
5014 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
5015 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
5016 if (ret)
5017 return ret;
5018
5019 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
5020 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
5021 * depending on the pin, it requires to read a different register
5022 */
5023 if (event == LAN8841_EVENT_A)
5024 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
5025 else
5026 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
5027
5028 if (pin < 5)
5029 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
5030 tmp << (3 * pin));
5031 else
5032 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
5033 tmp << (3 * (pin - 5)));
5034
5035 return ret;
5036 }
5037
5038 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
5039 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
5040 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
5041 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
5042 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
5043 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
5044 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
5045 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
5046 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
5047 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
5048 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
5049 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
5050 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
5051 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
5052
lan8841_ptp_perout(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)5053 static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
5054 struct ptp_clock_request *rq, int on)
5055 {
5056 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5057 ptp_clock_info);
5058 struct phy_device *phydev = ptp_priv->phydev;
5059 struct timespec64 ts_on, ts_period;
5060 s64 on_nsec, period_nsec;
5061 int pulse_width;
5062 int pin;
5063 int ret;
5064
5065 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
5066 return -EOPNOTSUPP;
5067
5068 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
5069 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5070 return -EINVAL;
5071
5072 if (!on) {
5073 ret = lan8841_ptp_perout_off(ptp_priv, pin);
5074 if (ret)
5075 return ret;
5076
5077 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
5078 }
5079
5080 ts_on.tv_sec = rq->perout.on.sec;
5081 ts_on.tv_nsec = rq->perout.on.nsec;
5082 on_nsec = timespec64_to_ns(&ts_on);
5083
5084 ts_period.tv_sec = rq->perout.period.sec;
5085 ts_period.tv_nsec = rq->perout.period.nsec;
5086 period_nsec = timespec64_to_ns(&ts_period);
5087
5088 if (period_nsec < 200) {
5089 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
5090 phydev_name(phydev));
5091 return -EOPNOTSUPP;
5092 }
5093
5094 if (on_nsec >= period_nsec) {
5095 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
5096 phydev_name(phydev));
5097 return -EINVAL;
5098 }
5099
5100 switch (on_nsec) {
5101 case 200000000:
5102 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
5103 break;
5104 case 100000000:
5105 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
5106 break;
5107 case 50000000:
5108 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
5109 break;
5110 case 10000000:
5111 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
5112 break;
5113 case 5000000:
5114 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
5115 break;
5116 case 1000000:
5117 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
5118 break;
5119 case 500000:
5120 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
5121 break;
5122 case 100000:
5123 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
5124 break;
5125 case 50000:
5126 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
5127 break;
5128 case 10000:
5129 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
5130 break;
5131 case 5000:
5132 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
5133 break;
5134 case 1000:
5135 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
5136 break;
5137 case 500:
5138 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
5139 break;
5140 case 100:
5141 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5142 break;
5143 default:
5144 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
5145 phydev_name(phydev));
5146 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5147 break;
5148 }
5149
5150 mutex_lock(&ptp_priv->ptp_lock);
5151 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
5152 rq->perout.start.nsec);
5153 mutex_unlock(&ptp_priv->ptp_lock);
5154 if (ret)
5155 return ret;
5156
5157 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
5158 rq->perout.period.nsec);
5159 if (ret)
5160 return ret;
5161
5162 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
5163 pulse_width);
5164 if (ret)
5165 return ret;
5166
5167 ret = lan8841_ptp_perout_on(ptp_priv, pin);
5168 if (ret)
5169 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
5170
5171 return ret;
5172 }
5173
5174 #define LAN8841_PTP_GPIO_CAP_EN 496
5175 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
5176 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
5177 #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
5178
lan8841_ptp_extts_on(struct kszphy_ptp_priv * ptp_priv,int pin,u32 flags)5179 static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
5180 u32 flags)
5181 {
5182 struct phy_device *phydev = ptp_priv->phydev;
5183 u16 tmp = 0;
5184 int ret;
5185
5186 /* Set GPIO to be intput */
5187 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
5188 if (ret)
5189 return ret;
5190
5191 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
5192 if (ret)
5193 return ret;
5194
5195 /* Enable capture on the edges of the pin */
5196 if (flags & PTP_RISING_EDGE)
5197 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
5198 if (flags & PTP_FALLING_EDGE)
5199 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
5200 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
5201 if (ret)
5202 return ret;
5203
5204 /* Enable interrupt */
5205 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
5206 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5207 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
5208 }
5209
lan8841_ptp_extts_off(struct kszphy_ptp_priv * ptp_priv,int pin)5210 static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
5211 {
5212 struct phy_device *phydev = ptp_priv->phydev;
5213 int ret;
5214
5215 /* Set GPIO to be output */
5216 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
5217 if (ret)
5218 return ret;
5219
5220 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
5221 if (ret)
5222 return ret;
5223
5224 /* Disable capture on both of the edges */
5225 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
5226 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
5227 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
5228 0);
5229 if (ret)
5230 return ret;
5231
5232 /* Disable interrupt */
5233 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
5234 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5235 0);
5236 }
5237
lan8841_ptp_extts(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)5238 static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
5239 struct ptp_clock_request *rq, int on)
5240 {
5241 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5242 ptp_clock_info);
5243 int pin;
5244 int ret;
5245
5246 /* Reject requests with unsupported flags */
5247 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
5248 PTP_EXTTS_EDGES |
5249 PTP_STRICT_FLAGS))
5250 return -EOPNOTSUPP;
5251
5252 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
5253 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5254 return -EINVAL;
5255
5256 mutex_lock(&ptp_priv->ptp_lock);
5257 if (on)
5258 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
5259 else
5260 ret = lan8841_ptp_extts_off(ptp_priv, pin);
5261 mutex_unlock(&ptp_priv->ptp_lock);
5262
5263 return ret;
5264 }
5265
lan8841_ptp_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)5266 static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
5267 struct ptp_clock_request *rq, int on)
5268 {
5269 switch (rq->type) {
5270 case PTP_CLK_REQ_EXTTS:
5271 return lan8841_ptp_extts(ptp, rq, on);
5272 case PTP_CLK_REQ_PEROUT:
5273 return lan8841_ptp_perout(ptp, rq, on);
5274 default:
5275 return -EOPNOTSUPP;
5276 }
5277
5278 return 0;
5279 }
5280
lan8841_ptp_do_aux_work(struct ptp_clock_info * ptp)5281 static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
5282 {
5283 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5284 ptp_clock_info);
5285 struct timespec64 ts;
5286 unsigned long flags;
5287
5288 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
5289
5290 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5291 ptp_priv->seconds = ts.tv_sec;
5292 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
5293
5294 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
5295 }
5296
5297 static struct ptp_clock_info lan8841_ptp_clock_info = {
5298 .owner = THIS_MODULE,
5299 .name = "lan8841 ptp",
5300 .max_adj = 31249999,
5301 .gettime64 = lan8841_ptp_gettime64,
5302 .settime64 = lan8841_ptp_settime64,
5303 .adjtime = lan8841_ptp_adjtime,
5304 .adjfine = lan8841_ptp_adjfine,
5305 .verify = lan8841_ptp_verify,
5306 .enable = lan8841_ptp_enable,
5307 .do_aux_work = lan8841_ptp_do_aux_work,
5308 .n_per_out = LAN8841_PTP_GPIO_NUM,
5309 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
5310 .n_pins = LAN8841_PTP_GPIO_NUM,
5311 };
5312
5313 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
5314 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
5315
lan8841_probe(struct phy_device * phydev)5316 static int lan8841_probe(struct phy_device *phydev)
5317 {
5318 struct kszphy_ptp_priv *ptp_priv;
5319 struct kszphy_priv *priv;
5320 int err;
5321
5322 err = kszphy_probe(phydev);
5323 if (err)
5324 return err;
5325
5326 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5327 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
5328 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
5329 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
5330
5331 /* Register the clock */
5332 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
5333 return 0;
5334
5335 priv = phydev->priv;
5336 ptp_priv = &priv->ptp_priv;
5337
5338 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
5339 LAN8841_PTP_GPIO_NUM,
5340 sizeof(*ptp_priv->pin_config),
5341 GFP_KERNEL);
5342 if (!ptp_priv->pin_config)
5343 return -ENOMEM;
5344
5345 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
5346 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
5347
5348 snprintf(p->name, sizeof(p->name), "pin%d", i);
5349 p->index = i;
5350 p->func = PTP_PF_NONE;
5351 }
5352
5353 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
5354 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
5355 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
5356 &phydev->mdio.dev);
5357 if (IS_ERR(ptp_priv->ptp_clock)) {
5358 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
5359 PTR_ERR(ptp_priv->ptp_clock));
5360 return -EINVAL;
5361 }
5362
5363 if (!ptp_priv->ptp_clock)
5364 return 0;
5365
5366 /* Initialize the SW */
5367 skb_queue_head_init(&ptp_priv->tx_queue);
5368 ptp_priv->phydev = phydev;
5369 mutex_init(&ptp_priv->ptp_lock);
5370 spin_lock_init(&ptp_priv->seconds_lock);
5371
5372 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
5373 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
5374 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
5375 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
5376
5377 phydev->mii_ts = &ptp_priv->mii_ts;
5378
5379 /* Timestamp selected by default to keep legacy API */
5380 phydev->default_timestamp = true;
5381
5382 return 0;
5383 }
5384
lan8804_resume(struct phy_device * phydev)5385 static int lan8804_resume(struct phy_device *phydev)
5386 {
5387 return kszphy_resume(phydev);
5388 }
5389
lan8804_suspend(struct phy_device * phydev)5390 static int lan8804_suspend(struct phy_device *phydev)
5391 {
5392 return kszphy_generic_suspend(phydev);
5393 }
5394
lan8841_resume(struct phy_device * phydev)5395 static int lan8841_resume(struct phy_device *phydev)
5396 {
5397 return kszphy_generic_resume(phydev);
5398 }
5399
lan8841_suspend(struct phy_device * phydev)5400 static int lan8841_suspend(struct phy_device *phydev)
5401 {
5402 struct kszphy_priv *priv = phydev->priv;
5403 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
5404
5405 if (ptp_priv->ptp_clock)
5406 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
5407
5408 return kszphy_generic_suspend(phydev);
5409 }
5410
5411 static struct phy_driver ksphy_driver[] = {
5412 {
5413 .phy_id = PHY_ID_KS8737,
5414 .phy_id_mask = MICREL_PHY_ID_MASK,
5415 .name = "Micrel KS8737",
5416 /* PHY_BASIC_FEATURES */
5417 .driver_data = &ks8737_type,
5418 .probe = kszphy_probe,
5419 .config_init = kszphy_config_init,
5420 .config_intr = kszphy_config_intr,
5421 .handle_interrupt = kszphy_handle_interrupt,
5422 .suspend = kszphy_suspend,
5423 .resume = kszphy_resume,
5424 }, {
5425 .phy_id = PHY_ID_KSZ8021,
5426 .phy_id_mask = 0x00ffffff,
5427 .name = "Micrel KSZ8021 or KSZ8031",
5428 /* PHY_BASIC_FEATURES */
5429 .driver_data = &ksz8021_type,
5430 .probe = kszphy_probe,
5431 .config_init = kszphy_config_init,
5432 .config_intr = kszphy_config_intr,
5433 .handle_interrupt = kszphy_handle_interrupt,
5434 .get_sset_count = kszphy_get_sset_count,
5435 .get_strings = kszphy_get_strings,
5436 .get_stats = kszphy_get_stats,
5437 .suspend = kszphy_suspend,
5438 .resume = kszphy_resume,
5439 }, {
5440 .phy_id = PHY_ID_KSZ8031,
5441 .phy_id_mask = 0x00ffffff,
5442 .name = "Micrel KSZ8031",
5443 /* PHY_BASIC_FEATURES */
5444 .driver_data = &ksz8021_type,
5445 .probe = kszphy_probe,
5446 .config_init = kszphy_config_init,
5447 .config_intr = kszphy_config_intr,
5448 .handle_interrupt = kszphy_handle_interrupt,
5449 .get_sset_count = kszphy_get_sset_count,
5450 .get_strings = kszphy_get_strings,
5451 .get_stats = kszphy_get_stats,
5452 .suspend = kszphy_suspend,
5453 .resume = kszphy_resume,
5454 }, {
5455 .phy_id = PHY_ID_KSZ8041,
5456 .phy_id_mask = MICREL_PHY_ID_MASK,
5457 .name = "Micrel KSZ8041",
5458 /* PHY_BASIC_FEATURES */
5459 .driver_data = &ksz8041_type,
5460 .probe = kszphy_probe,
5461 .config_init = ksz8041_config_init,
5462 .config_aneg = ksz8041_config_aneg,
5463 .config_intr = kszphy_config_intr,
5464 .handle_interrupt = kszphy_handle_interrupt,
5465 .get_sset_count = kszphy_get_sset_count,
5466 .get_strings = kszphy_get_strings,
5467 .get_stats = kszphy_get_stats,
5468 .suspend = ksz8041_suspend,
5469 .resume = ksz8041_resume,
5470 }, {
5471 .phy_id = PHY_ID_KSZ8041RNLI,
5472 .phy_id_mask = MICREL_PHY_ID_MASK,
5473 .name = "Micrel KSZ8041RNLI",
5474 /* PHY_BASIC_FEATURES */
5475 .driver_data = &ksz8041_type,
5476 .probe = kszphy_probe,
5477 .config_init = kszphy_config_init,
5478 .config_intr = kszphy_config_intr,
5479 .handle_interrupt = kszphy_handle_interrupt,
5480 .get_sset_count = kszphy_get_sset_count,
5481 .get_strings = kszphy_get_strings,
5482 .get_stats = kszphy_get_stats,
5483 .suspend = kszphy_suspend,
5484 .resume = kszphy_resume,
5485 }, {
5486 .name = "Micrel KSZ8051",
5487 /* PHY_BASIC_FEATURES */
5488 .driver_data = &ksz8051_type,
5489 .probe = kszphy_probe,
5490 .config_init = kszphy_config_init,
5491 .config_intr = kszphy_config_intr,
5492 .handle_interrupt = kszphy_handle_interrupt,
5493 .get_sset_count = kszphy_get_sset_count,
5494 .get_strings = kszphy_get_strings,
5495 .get_stats = kszphy_get_stats,
5496 .match_phy_device = ksz8051_match_phy_device,
5497 .suspend = kszphy_suspend,
5498 .resume = kszphy_resume,
5499 }, {
5500 .phy_id = PHY_ID_KSZ8001,
5501 .name = "Micrel KSZ8001 or KS8721",
5502 .phy_id_mask = 0x00fffffc,
5503 /* PHY_BASIC_FEATURES */
5504 .driver_data = &ksz8041_type,
5505 .probe = kszphy_probe,
5506 .config_init = kszphy_config_init,
5507 .config_intr = kszphy_config_intr,
5508 .handle_interrupt = kszphy_handle_interrupt,
5509 .get_sset_count = kszphy_get_sset_count,
5510 .get_strings = kszphy_get_strings,
5511 .get_stats = kszphy_get_stats,
5512 .suspend = kszphy_suspend,
5513 .resume = kszphy_resume,
5514 }, {
5515 .phy_id = PHY_ID_KSZ8081,
5516 .name = "Micrel KSZ8081 or KSZ8091",
5517 .phy_id_mask = MICREL_PHY_ID_MASK,
5518 .flags = PHY_POLL_CABLE_TEST,
5519 /* PHY_BASIC_FEATURES */
5520 .driver_data = &ksz8081_type,
5521 .probe = kszphy_probe,
5522 .config_init = ksz8081_config_init,
5523 .soft_reset = genphy_soft_reset,
5524 .config_aneg = ksz8081_config_aneg,
5525 .read_status = ksz8081_read_status,
5526 .config_intr = kszphy_config_intr,
5527 .handle_interrupt = kszphy_handle_interrupt,
5528 .get_sset_count = kszphy_get_sset_count,
5529 .get_strings = kszphy_get_strings,
5530 .get_stats = kszphy_get_stats,
5531 .suspend = kszphy_suspend,
5532 .resume = kszphy_resume,
5533 .cable_test_start = ksz886x_cable_test_start,
5534 .cable_test_get_status = ksz886x_cable_test_get_status,
5535 }, {
5536 .phy_id = PHY_ID_KSZ8061,
5537 .name = "Micrel KSZ8061",
5538 .phy_id_mask = MICREL_PHY_ID_MASK,
5539 /* PHY_BASIC_FEATURES */
5540 .probe = kszphy_probe,
5541 .config_init = ksz8061_config_init,
5542 .soft_reset = genphy_soft_reset,
5543 .config_intr = kszphy_config_intr,
5544 .handle_interrupt = kszphy_handle_interrupt,
5545 .suspend = ksz8061_suspend,
5546 .resume = ksz8061_resume,
5547 }, {
5548 .phy_id = PHY_ID_KSZ9021,
5549 .phy_id_mask = 0x000ffffe,
5550 .name = "Micrel KSZ9021 Gigabit PHY",
5551 /* PHY_GBIT_FEATURES */
5552 .driver_data = &ksz9021_type,
5553 .probe = kszphy_probe,
5554 .get_features = ksz9031_get_features,
5555 .config_init = ksz9021_config_init,
5556 .config_intr = kszphy_config_intr,
5557 .handle_interrupt = kszphy_handle_interrupt,
5558 .get_sset_count = kszphy_get_sset_count,
5559 .get_strings = kszphy_get_strings,
5560 .get_stats = kszphy_get_stats,
5561 .suspend = kszphy_suspend,
5562 .resume = kszphy_resume,
5563 .read_mmd = genphy_read_mmd_unsupported,
5564 .write_mmd = genphy_write_mmd_unsupported,
5565 }, {
5566 .phy_id = PHY_ID_KSZ9031,
5567 .phy_id_mask = MICREL_PHY_ID_MASK,
5568 .name = "Micrel KSZ9031 Gigabit PHY",
5569 .flags = PHY_POLL_CABLE_TEST,
5570 .driver_data = &ksz9021_type,
5571 .probe = kszphy_probe,
5572 .get_features = ksz9031_get_features,
5573 .config_init = ksz9031_config_init,
5574 .soft_reset = genphy_soft_reset,
5575 .read_status = ksz9031_read_status,
5576 .config_intr = kszphy_config_intr,
5577 .handle_interrupt = kszphy_handle_interrupt,
5578 .get_sset_count = kszphy_get_sset_count,
5579 .get_strings = kszphy_get_strings,
5580 .get_stats = kszphy_get_stats,
5581 .suspend = kszphy_suspend,
5582 .resume = kszphy_resume,
5583 .cable_test_start = ksz9x31_cable_test_start,
5584 .cable_test_get_status = ksz9x31_cable_test_get_status,
5585 .set_loopback = ksz9031_set_loopback,
5586 }, {
5587 .phy_id = PHY_ID_LAN8814,
5588 .phy_id_mask = MICREL_PHY_ID_MASK,
5589 .name = "Microchip INDY Gigabit Quad PHY",
5590 .flags = PHY_POLL_CABLE_TEST,
5591 .config_init = lan8814_config_init,
5592 .driver_data = &lan8814_type,
5593 .probe = lan8814_probe,
5594 .soft_reset = genphy_soft_reset,
5595 .read_status = ksz9031_read_status,
5596 .get_sset_count = kszphy_get_sset_count,
5597 .get_strings = kszphy_get_strings,
5598 .get_stats = kszphy_get_stats,
5599 .suspend = genphy_suspend,
5600 .resume = kszphy_resume,
5601 .config_intr = lan8814_config_intr,
5602 .handle_interrupt = lan8814_handle_interrupt,
5603 .cable_test_start = lan8814_cable_test_start,
5604 .cable_test_get_status = ksz886x_cable_test_get_status,
5605 }, {
5606 .phy_id = PHY_ID_LAN8804,
5607 .phy_id_mask = MICREL_PHY_ID_MASK,
5608 .name = "Microchip LAN966X Gigabit PHY",
5609 .config_init = lan8804_config_init,
5610 .driver_data = &ksz9021_type,
5611 .probe = kszphy_probe,
5612 .soft_reset = genphy_soft_reset,
5613 .read_status = ksz9031_read_status,
5614 .get_sset_count = kszphy_get_sset_count,
5615 .get_strings = kszphy_get_strings,
5616 .get_stats = kszphy_get_stats,
5617 .suspend = lan8804_suspend,
5618 .resume = lan8804_resume,
5619 .config_intr = lan8804_config_intr,
5620 .handle_interrupt = lan8804_handle_interrupt,
5621 }, {
5622 .phy_id = PHY_ID_LAN8841,
5623 .phy_id_mask = MICREL_PHY_ID_MASK,
5624 .name = "Microchip LAN8841 Gigabit PHY",
5625 .flags = PHY_POLL_CABLE_TEST,
5626 .driver_data = &lan8841_type,
5627 .config_init = lan8841_config_init,
5628 .probe = lan8841_probe,
5629 .soft_reset = genphy_soft_reset,
5630 .config_intr = lan8841_config_intr,
5631 .handle_interrupt = lan8841_handle_interrupt,
5632 .get_sset_count = kszphy_get_sset_count,
5633 .get_strings = kszphy_get_strings,
5634 .get_stats = kszphy_get_stats,
5635 .suspend = lan8841_suspend,
5636 .resume = lan8841_resume,
5637 .cable_test_start = lan8814_cable_test_start,
5638 .cable_test_get_status = ksz886x_cable_test_get_status,
5639 }, {
5640 .phy_id = PHY_ID_KSZ9131,
5641 .phy_id_mask = MICREL_PHY_ID_MASK,
5642 .name = "Microchip KSZ9131 Gigabit PHY",
5643 /* PHY_GBIT_FEATURES */
5644 .flags = PHY_POLL_CABLE_TEST,
5645 .driver_data = &ksz9131_type,
5646 .probe = kszphy_probe,
5647 .soft_reset = genphy_soft_reset,
5648 .config_init = ksz9131_config_init,
5649 .config_intr = kszphy_config_intr,
5650 .config_aneg = ksz9131_config_aneg,
5651 .read_status = ksz9131_read_status,
5652 .handle_interrupt = kszphy_handle_interrupt,
5653 .get_sset_count = kszphy_get_sset_count,
5654 .get_strings = kszphy_get_strings,
5655 .get_stats = kszphy_get_stats,
5656 .suspend = kszphy_suspend,
5657 .resume = kszphy_resume,
5658 .cable_test_start = ksz9x31_cable_test_start,
5659 .cable_test_get_status = ksz9x31_cable_test_get_status,
5660 .get_features = ksz9477_get_features,
5661 }, {
5662 .phy_id = PHY_ID_KSZ8873MLL,
5663 .phy_id_mask = MICREL_PHY_ID_MASK,
5664 .name = "Micrel KSZ8873MLL Switch",
5665 /* PHY_BASIC_FEATURES */
5666 .config_init = kszphy_config_init,
5667 .config_aneg = ksz8873mll_config_aneg,
5668 .read_status = ksz8873mll_read_status,
5669 .suspend = genphy_suspend,
5670 .resume = genphy_resume,
5671 }, {
5672 .phy_id = PHY_ID_KSZ886X,
5673 .phy_id_mask = MICREL_PHY_ID_MASK,
5674 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
5675 .driver_data = &ksz886x_type,
5676 /* PHY_BASIC_FEATURES */
5677 .flags = PHY_POLL_CABLE_TEST,
5678 .config_init = kszphy_config_init,
5679 .config_aneg = ksz886x_config_aneg,
5680 .read_status = ksz886x_read_status,
5681 .suspend = genphy_suspend,
5682 .resume = genphy_resume,
5683 .cable_test_start = ksz886x_cable_test_start,
5684 .cable_test_get_status = ksz886x_cable_test_get_status,
5685 }, {
5686 .name = "Micrel KSZ87XX Switch",
5687 /* PHY_BASIC_FEATURES */
5688 .config_init = kszphy_config_init,
5689 .match_phy_device = ksz8795_match_phy_device,
5690 .suspend = genphy_suspend,
5691 .resume = genphy_resume,
5692 }, {
5693 .phy_id = PHY_ID_KSZ9477,
5694 .phy_id_mask = MICREL_PHY_ID_MASK,
5695 .name = "Microchip KSZ9477",
5696 /* PHY_GBIT_FEATURES */
5697 .config_init = ksz9477_config_init,
5698 .config_intr = kszphy_config_intr,
5699 .handle_interrupt = kszphy_handle_interrupt,
5700 .suspend = genphy_suspend,
5701 .resume = ksz9477_resume,
5702 } };
5703
5704 module_phy_driver(ksphy_driver);
5705
5706 MODULE_DESCRIPTION("Micrel PHY driver");
5707 MODULE_AUTHOR("David J. Choi");
5708 MODULE_LICENSE("GPL");
5709
5710 static const struct mdio_device_id __maybe_unused micrel_tbl[] = {
5711 { PHY_ID_KSZ9021, 0x000ffffe },
5712 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
5713 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
5714 { PHY_ID_KSZ8001, 0x00fffffc },
5715 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
5716 { PHY_ID_KSZ8021, 0x00ffffff },
5717 { PHY_ID_KSZ8031, 0x00ffffff },
5718 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
5719 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
5720 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
5721 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
5722 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
5723 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
5724 { PHY_ID_KSZ9477, MICREL_PHY_ID_MASK },
5725 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
5726 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
5727 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
5728 { }
5729 };
5730
5731 MODULE_DEVICE_TABLE(mdio, micrel_tbl);
5732