1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
3 
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/string.h>
9 #include <linux/etherdevice.h>
10 #include <net/ip.h>
11 #include <linux/phy.h>
12 #include <linux/if_vlan.h>
13 
14 #include "../libwx/wx_type.h"
15 #include "../libwx/wx_hw.h"
16 #include "../libwx/wx_lib.h"
17 #include "../libwx/wx_ptp.h"
18 #include "ngbe_type.h"
19 #include "ngbe_mdio.h"
20 #include "ngbe_hw.h"
21 #include "ngbe_ethtool.h"
22 
23 char ngbe_driver_name[] = "ngbe";
24 
25 /* ngbe_pci_tbl - PCI Device ID Table
26  *
27  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
28  *   Class, Class Mask, private data (not used) }
29  */
30 static const struct pci_device_id ngbe_pci_tbl[] = {
31 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860AL_W), 0},
32 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A2), 0},
33 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A2S), 0},
34 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A4), 0},
35 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A4S), 0},
36 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860AL2), 0},
37 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860AL2S), 0},
38 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860AL4), 0},
39 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860AL4S), 0},
40 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860LC), 0},
41 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A1), 0},
42 	{ PCI_VDEVICE(WANGXUN, NGBE_DEV_ID_EM_WX1860A1L), 0},
43 	/* required last entry */
44 	{ .device = 0 }
45 };
46 
47 /**
48  *  ngbe_init_type_code - Initialize the shared code
49  *  @wx: pointer to hardware structure
50  **/
ngbe_init_type_code(struct wx * wx)51 static void ngbe_init_type_code(struct wx *wx)
52 {
53 	int wol_mask = 0, ncsi_mask = 0;
54 	u16 type_mask = 0, val;
55 
56 	wx->mac.type = wx_mac_em;
57 	type_mask = (u16)(wx->subsystem_device_id & NGBE_OEM_MASK);
58 	ncsi_mask = wx->subsystem_device_id & NGBE_NCSI_MASK;
59 	wol_mask = wx->subsystem_device_id & NGBE_WOL_MASK;
60 
61 	val = rd32(wx, WX_CFG_PORT_ST);
62 	wx->mac_type = (val & BIT(7)) >> 7 ?
63 		       em_mac_type_rgmii :
64 		       em_mac_type_mdi;
65 
66 	wx->wol_hw_supported = (wol_mask == NGBE_WOL_SUP) ? 1 : 0;
67 	wx->ncsi_enabled = (ncsi_mask == NGBE_NCSI_MASK ||
68 			   type_mask == NGBE_SUBID_OCP_CARD) ? 1 : 0;
69 
70 	switch (type_mask) {
71 	case NGBE_SUBID_LY_YT8521S_SFP:
72 	case NGBE_SUBID_LY_M88E1512_SFP:
73 	case NGBE_SUBID_YT8521S_SFP_GPIO:
74 	case NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO:
75 		wx->gpio_ctrl = 1;
76 		break;
77 	default:
78 		wx->gpio_ctrl = 0;
79 		break;
80 	}
81 }
82 
83 /**
84  * ngbe_sw_init - Initialize general software structures
85  * @wx: board private structure to initialize
86  **/
ngbe_sw_init(struct wx * wx)87 static int ngbe_sw_init(struct wx *wx)
88 {
89 	struct pci_dev *pdev = wx->pdev;
90 	u16 msix_count = 0;
91 	int err = 0;
92 
93 	wx->mac.num_rar_entries = NGBE_RAR_ENTRIES;
94 	wx->mac.max_rx_queues = NGBE_MAX_RX_QUEUES;
95 	wx->mac.max_tx_queues = NGBE_MAX_TX_QUEUES;
96 	wx->mac.mcft_size = NGBE_MC_TBL_SIZE;
97 	wx->mac.vft_size = NGBE_SP_VFT_TBL_SIZE;
98 	wx->mac.rx_pb_size = NGBE_RX_PB_SIZE;
99 	wx->mac.tx_pb_size = NGBE_TDB_PB_SZ;
100 
101 	/* PCI config space info */
102 	err = wx_sw_init(wx);
103 	if (err < 0)
104 		return err;
105 
106 	/* mac type, phy type , oem type */
107 	ngbe_init_type_code(wx);
108 
109 	/* Set common capability flags and settings */
110 	wx->max_q_vectors = NGBE_MAX_MSIX_VECTORS;
111 	err = wx_get_pcie_msix_counts(wx, &msix_count, NGBE_MAX_MSIX_VECTORS);
112 	if (err)
113 		dev_err(&pdev->dev, "Do not support MSI-X\n");
114 	wx->mac.max_msix_vectors = msix_count;
115 
116 	wx->ring_feature[RING_F_RSS].limit = min_t(int, NGBE_MAX_RSS_INDICES,
117 						   num_online_cpus());
118 	wx->rss_enabled = true;
119 
120 	/* enable itr by default in dynamic mode */
121 	wx->rx_itr_setting = 1;
122 	wx->tx_itr_setting = 1;
123 
124 	/* set default ring sizes */
125 	wx->tx_ring_count = NGBE_DEFAULT_TXD;
126 	wx->rx_ring_count = NGBE_DEFAULT_RXD;
127 
128 	/* set default work limits */
129 	wx->tx_work_limit = NGBE_DEFAULT_TX_WORK;
130 	wx->rx_work_limit = NGBE_DEFAULT_RX_WORK;
131 
132 	return 0;
133 }
134 
135 /**
136  * ngbe_irq_enable - Enable default interrupt generation settings
137  * @wx: board private structure
138  * @queues: enable all queues interrupts
139  **/
ngbe_irq_enable(struct wx * wx,bool queues)140 static void ngbe_irq_enable(struct wx *wx, bool queues)
141 {
142 	u32 mask;
143 
144 	/* enable misc interrupt */
145 	mask = NGBE_PX_MISC_IEN_MASK;
146 
147 	wr32(wx, WX_GPIO_DDR, WX_GPIO_DDR_0);
148 	wr32(wx, WX_GPIO_INTEN, WX_GPIO_INTEN_0 | WX_GPIO_INTEN_1);
149 	wr32(wx, WX_GPIO_INTTYPE_LEVEL, 0x0);
150 	wr32(wx, WX_GPIO_POLARITY, wx->gpio_ctrl ? 0 : 0x3);
151 
152 	wr32(wx, WX_PX_MISC_IEN, mask);
153 
154 	/* mask interrupt */
155 	if (queues)
156 		wx_intr_enable(wx, NGBE_INTR_ALL);
157 	else
158 		wx_intr_enable(wx, NGBE_INTR_MISC);
159 }
160 
161 /**
162  * ngbe_intr - msi/legacy mode Interrupt Handler
163  * @irq: interrupt number
164  * @data: pointer to a network interface device structure
165  **/
ngbe_intr(int __always_unused irq,void * data)166 static irqreturn_t ngbe_intr(int __always_unused irq, void *data)
167 {
168 	struct wx_q_vector *q_vector;
169 	struct wx *wx  = data;
170 	struct pci_dev *pdev;
171 	u32 eicr, eicr_misc;
172 
173 	q_vector = wx->q_vector[0];
174 	pdev = wx->pdev;
175 
176 	eicr = wx_misc_isb(wx, WX_ISB_VEC0);
177 	if (!eicr) {
178 		/* shared interrupt alert!
179 		 * the interrupt that we masked before the EICR read.
180 		 */
181 		if (netif_running(wx->netdev))
182 			ngbe_irq_enable(wx, true);
183 		return IRQ_NONE;        /* Not our interrupt */
184 	}
185 	wx->isb_mem[WX_ISB_VEC0] = 0;
186 	if (!(pdev->msi_enabled))
187 		wr32(wx, WX_PX_INTA, 1);
188 
189 	eicr_misc = wx_misc_isb(wx, WX_ISB_MISC);
190 	if (unlikely(eicr_misc & NGBE_PX_MISC_IC_TIMESYNC))
191 		wx_ptp_check_pps_event(wx);
192 
193 	wx->isb_mem[WX_ISB_MISC] = 0;
194 	/* would disable interrupts here but it is auto disabled */
195 	napi_schedule_irqoff(&q_vector->napi);
196 
197 	if (netif_running(wx->netdev))
198 		ngbe_irq_enable(wx, false);
199 
200 	return IRQ_HANDLED;
201 }
202 
ngbe_msix_other(int __always_unused irq,void * data)203 static irqreturn_t ngbe_msix_other(int __always_unused irq, void *data)
204 {
205 	struct wx *wx = data;
206 	u32 eicr;
207 
208 	eicr = wx_misc_isb(wx, WX_ISB_MISC);
209 
210 	if (unlikely(eicr & NGBE_PX_MISC_IC_TIMESYNC))
211 		wx_ptp_check_pps_event(wx);
212 
213 	/* re-enable the original interrupt state, no lsc, no queues */
214 	if (netif_running(wx->netdev))
215 		ngbe_irq_enable(wx, false);
216 
217 	return IRQ_HANDLED;
218 }
219 
220 /**
221  * ngbe_request_msix_irqs - Initialize MSI-X interrupts
222  * @wx: board private structure
223  *
224  * ngbe_request_msix_irqs allocates MSI-X vectors and requests
225  * interrupts from the kernel.
226  **/
ngbe_request_msix_irqs(struct wx * wx)227 static int ngbe_request_msix_irqs(struct wx *wx)
228 {
229 	struct net_device *netdev = wx->netdev;
230 	int vector, err;
231 
232 	for (vector = 0; vector < wx->num_q_vectors; vector++) {
233 		struct wx_q_vector *q_vector = wx->q_vector[vector];
234 		struct msix_entry *entry = &wx->msix_q_entries[vector];
235 
236 		if (q_vector->tx.ring && q_vector->rx.ring)
237 			snprintf(q_vector->name, sizeof(q_vector->name) - 1,
238 				 "%s-TxRx-%d", netdev->name, entry->entry);
239 		else
240 			/* skip this unused q_vector */
241 			continue;
242 
243 		err = request_irq(entry->vector, wx_msix_clean_rings, 0,
244 				  q_vector->name, q_vector);
245 		if (err) {
246 			wx_err(wx, "request_irq failed for MSIX interrupt %s Error: %d\n",
247 			       q_vector->name, err);
248 			goto free_queue_irqs;
249 		}
250 	}
251 
252 	err = request_irq(wx->msix_entry->vector,
253 			  ngbe_msix_other, 0, netdev->name, wx);
254 
255 	if (err) {
256 		wx_err(wx, "request_irq for msix_other failed: %d\n", err);
257 		goto free_queue_irqs;
258 	}
259 
260 	return 0;
261 
262 free_queue_irqs:
263 	while (vector) {
264 		vector--;
265 		free_irq(wx->msix_q_entries[vector].vector,
266 			 wx->q_vector[vector]);
267 	}
268 	wx_reset_interrupt_capability(wx);
269 	return err;
270 }
271 
272 /**
273  * ngbe_request_irq - initialize interrupts
274  * @wx: board private structure
275  *
276  * Attempts to configure interrupts using the best available
277  * capabilities of the hardware and kernel.
278  **/
ngbe_request_irq(struct wx * wx)279 static int ngbe_request_irq(struct wx *wx)
280 {
281 	struct net_device *netdev = wx->netdev;
282 	struct pci_dev *pdev = wx->pdev;
283 	int err;
284 
285 	if (pdev->msix_enabled)
286 		err = ngbe_request_msix_irqs(wx);
287 	else if (pdev->msi_enabled)
288 		err = request_irq(pdev->irq, ngbe_intr, 0,
289 				  netdev->name, wx);
290 	else
291 		err = request_irq(pdev->irq, ngbe_intr, IRQF_SHARED,
292 				  netdev->name, wx);
293 
294 	if (err)
295 		wx_err(wx, "request_irq failed, Error %d\n", err);
296 
297 	return err;
298 }
299 
ngbe_disable_device(struct wx * wx)300 static void ngbe_disable_device(struct wx *wx)
301 {
302 	struct net_device *netdev = wx->netdev;
303 	u32 i;
304 
305 	/* disable all enabled rx queues */
306 	for (i = 0; i < wx->num_rx_queues; i++)
307 		/* this call also flushes the previous write */
308 		wx_disable_rx_queue(wx, wx->rx_ring[i]);
309 	/* disable receives */
310 	wx_disable_rx(wx);
311 	wx_napi_disable_all(wx);
312 	netif_tx_stop_all_queues(netdev);
313 	netif_tx_disable(netdev);
314 	if (wx->gpio_ctrl)
315 		ngbe_sfp_modules_txrx_powerctl(wx, false);
316 	wx_irq_disable(wx);
317 	/* disable transmits in the hardware now that interrupts are off */
318 	for (i = 0; i < wx->num_tx_queues; i++) {
319 		u8 reg_idx = wx->tx_ring[i]->reg_idx;
320 
321 		wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH);
322 	}
323 
324 	wx_update_stats(wx);
325 }
326 
ngbe_down(struct wx * wx)327 void ngbe_down(struct wx *wx)
328 {
329 	phylink_stop(wx->phylink);
330 	ngbe_disable_device(wx);
331 	if (test_bit(WX_STATE_PTP_RUNNING, wx->state))
332 		wx_ptp_reset(wx);
333 	wx_clean_all_tx_rings(wx);
334 	wx_clean_all_rx_rings(wx);
335 }
336 
ngbe_up(struct wx * wx)337 void ngbe_up(struct wx *wx)
338 {
339 	wx_configure_vectors(wx);
340 
341 	/* make sure to complete pre-operations */
342 	smp_mb__before_atomic();
343 	wx_napi_enable_all(wx);
344 	/* enable transmits */
345 	netif_tx_start_all_queues(wx->netdev);
346 
347 	/* clear any pending interrupts, may auto mask */
348 	rd32(wx, WX_PX_IC(0));
349 	rd32(wx, WX_PX_MISC_IC);
350 	ngbe_irq_enable(wx, true);
351 	if (wx->gpio_ctrl)
352 		ngbe_sfp_modules_txrx_powerctl(wx, true);
353 
354 	phylink_start(wx->phylink);
355 }
356 
357 /**
358  * ngbe_open - Called when a network interface is made active
359  * @netdev: network interface device structure
360  *
361  * Returns 0 on success, negative value on failure
362  *
363  * The open entry point is called when a network interface is made
364  * active by the system (IFF_UP).
365  **/
ngbe_open(struct net_device * netdev)366 static int ngbe_open(struct net_device *netdev)
367 {
368 	struct wx *wx = netdev_priv(netdev);
369 	int err;
370 
371 	wx_control_hw(wx, true);
372 
373 	err = wx_setup_resources(wx);
374 	if (err)
375 		return err;
376 
377 	wx_configure(wx);
378 
379 	err = ngbe_request_irq(wx);
380 	if (err)
381 		goto err_free_resources;
382 
383 	err = phylink_connect_phy(wx->phylink, wx->phydev);
384 	if (err)
385 		goto err_free_irq;
386 
387 	err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues);
388 	if (err)
389 		goto err_dis_phy;
390 
391 	err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues);
392 	if (err)
393 		goto err_dis_phy;
394 
395 	wx_ptp_init(wx);
396 
397 	ngbe_up(wx);
398 
399 	return 0;
400 err_dis_phy:
401 	phylink_disconnect_phy(wx->phylink);
402 err_free_irq:
403 	wx_free_irq(wx);
404 err_free_resources:
405 	wx_free_isb_resources(wx);
406 	wx_free_resources(wx);
407 	return err;
408 }
409 
410 /**
411  * ngbe_close - Disables a network interface
412  * @netdev: network interface device structure
413  *
414  * Returns 0, this is not allowed to fail
415  *
416  * The close entry point is called when an interface is de-activated
417  * by the OS.  The hardware is still under the drivers control, but
418  * needs to be disabled.  A global MAC reset is issued to stop the
419  * hardware, and all transmit and receive resources are freed.
420  **/
ngbe_close(struct net_device * netdev)421 static int ngbe_close(struct net_device *netdev)
422 {
423 	struct wx *wx = netdev_priv(netdev);
424 
425 	wx_ptp_stop(wx);
426 	ngbe_down(wx);
427 	wx_free_irq(wx);
428 	wx_free_isb_resources(wx);
429 	wx_free_resources(wx);
430 	phylink_disconnect_phy(wx->phylink);
431 	wx_control_hw(wx, false);
432 
433 	return 0;
434 }
435 
ngbe_dev_shutdown(struct pci_dev * pdev,bool * enable_wake)436 static void ngbe_dev_shutdown(struct pci_dev *pdev, bool *enable_wake)
437 {
438 	struct wx *wx = pci_get_drvdata(pdev);
439 	struct net_device *netdev;
440 	u32 wufc = wx->wol;
441 
442 	netdev = wx->netdev;
443 	rtnl_lock();
444 	netif_device_detach(netdev);
445 
446 	if (netif_running(netdev))
447 		ngbe_close(netdev);
448 	wx_clear_interrupt_scheme(wx);
449 	rtnl_unlock();
450 
451 	if (wufc) {
452 		wx_set_rx_mode(netdev);
453 		wx_configure_rx(wx);
454 		wr32(wx, NGBE_PSR_WKUP_CTL, wufc);
455 	} else {
456 		wr32(wx, NGBE_PSR_WKUP_CTL, 0);
457 	}
458 	pci_wake_from_d3(pdev, !!wufc);
459 	*enable_wake = !!wufc;
460 	wx_control_hw(wx, false);
461 
462 	pci_disable_device(pdev);
463 }
464 
ngbe_shutdown(struct pci_dev * pdev)465 static void ngbe_shutdown(struct pci_dev *pdev)
466 {
467 	struct wx *wx = pci_get_drvdata(pdev);
468 	bool wake;
469 
470 	wake = !!wx->wol;
471 
472 	ngbe_dev_shutdown(pdev, &wake);
473 
474 	if (system_state == SYSTEM_POWER_OFF) {
475 		pci_wake_from_d3(pdev, wake);
476 		pci_set_power_state(pdev, PCI_D3hot);
477 	}
478 }
479 
480 /**
481  * ngbe_setup_tc - routine to configure net_device for multiple traffic
482  * classes.
483  *
484  * @dev: net device to configure
485  * @tc: number of traffic classes to enable
486  */
ngbe_setup_tc(struct net_device * dev,u8 tc)487 int ngbe_setup_tc(struct net_device *dev, u8 tc)
488 {
489 	struct wx *wx = netdev_priv(dev);
490 
491 	/* Hardware has to reinitialize queues and interrupts to
492 	 * match packet buffer alignment. Unfortunately, the
493 	 * hardware is not flexible enough to do this dynamically.
494 	 */
495 	if (netif_running(dev))
496 		ngbe_close(dev);
497 
498 	wx_clear_interrupt_scheme(wx);
499 
500 	if (tc)
501 		netdev_set_num_tc(dev, tc);
502 	else
503 		netdev_reset_tc(dev);
504 
505 	wx_init_interrupt_scheme(wx);
506 
507 	if (netif_running(dev))
508 		ngbe_open(dev);
509 
510 	return 0;
511 }
512 
513 static const struct net_device_ops ngbe_netdev_ops = {
514 	.ndo_open               = ngbe_open,
515 	.ndo_stop               = ngbe_close,
516 	.ndo_change_mtu         = wx_change_mtu,
517 	.ndo_start_xmit         = wx_xmit_frame,
518 	.ndo_set_rx_mode        = wx_set_rx_mode,
519 	.ndo_set_features       = wx_set_features,
520 	.ndo_fix_features       = wx_fix_features,
521 	.ndo_validate_addr      = eth_validate_addr,
522 	.ndo_set_mac_address    = wx_set_mac,
523 	.ndo_get_stats64        = wx_get_stats64,
524 	.ndo_vlan_rx_add_vid    = wx_vlan_rx_add_vid,
525 	.ndo_vlan_rx_kill_vid   = wx_vlan_rx_kill_vid,
526 	.ndo_hwtstamp_set       = wx_hwtstamp_set,
527 	.ndo_hwtstamp_get       = wx_hwtstamp_get,
528 };
529 
530 /**
531  * ngbe_probe - Device Initialization Routine
532  * @pdev: PCI device information struct
533  * @ent: entry in ngbe_pci_tbl
534  *
535  * Returns 0 on success, negative on failure
536  *
537  * ngbe_probe initializes an wx identified by a pci_dev structure.
538  * The OS initialization, configuring of the wx private structure,
539  * and a hardware reset occur.
540  **/
ngbe_probe(struct pci_dev * pdev,const struct pci_device_id __always_unused * ent)541 static int ngbe_probe(struct pci_dev *pdev,
542 		      const struct pci_device_id __always_unused *ent)
543 {
544 	struct net_device *netdev;
545 	u32 e2rom_cksum_cap = 0;
546 	struct wx *wx = NULL;
547 	static int func_nums;
548 	u16 e2rom_ver = 0;
549 	u32 etrack_id = 0;
550 	u32 saved_ver = 0;
551 	int err;
552 
553 	err = pci_enable_device_mem(pdev);
554 	if (err)
555 		return err;
556 
557 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
558 	if (err) {
559 		dev_err(&pdev->dev,
560 			"No usable DMA configuration, aborting\n");
561 		goto err_pci_disable_dev;
562 	}
563 
564 	err = pci_request_selected_regions(pdev,
565 					   pci_select_bars(pdev, IORESOURCE_MEM),
566 					   ngbe_driver_name);
567 	if (err) {
568 		dev_err(&pdev->dev,
569 			"pci_request_selected_regions failed %d\n", err);
570 		goto err_pci_disable_dev;
571 	}
572 
573 	pci_set_master(pdev);
574 
575 	netdev = devm_alloc_etherdev_mqs(&pdev->dev,
576 					 sizeof(struct wx),
577 					 NGBE_MAX_TX_QUEUES,
578 					 NGBE_MAX_RX_QUEUES);
579 	if (!netdev) {
580 		err = -ENOMEM;
581 		goto err_pci_release_regions;
582 	}
583 
584 	SET_NETDEV_DEV(netdev, &pdev->dev);
585 
586 	wx = netdev_priv(netdev);
587 	wx->netdev = netdev;
588 	wx->pdev = pdev;
589 	wx->msg_enable = BIT(3) - 1;
590 
591 	wx->hw_addr = devm_ioremap(&pdev->dev,
592 				   pci_resource_start(pdev, 0),
593 				   pci_resource_len(pdev, 0));
594 	if (!wx->hw_addr) {
595 		err = -EIO;
596 		goto err_pci_release_regions;
597 	}
598 
599 	wx->driver_name = ngbe_driver_name;
600 	ngbe_set_ethtool_ops(netdev);
601 	netdev->netdev_ops = &ngbe_netdev_ops;
602 
603 	netdev->features = NETIF_F_SG | NETIF_F_IP_CSUM |
604 			   NETIF_F_TSO | NETIF_F_TSO6 |
605 			   NETIF_F_RXHASH | NETIF_F_RXCSUM;
606 	netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID;
607 	netdev->vlan_features |= netdev->features;
608 	netdev->features |= NETIF_F_IPV6_CSUM | NETIF_F_VLAN_FEATURES;
609 	/* copy netdev features into list of user selectable features */
610 	netdev->hw_features |= netdev->features | NETIF_F_RXALL;
611 	netdev->hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC;
612 	netdev->features |= NETIF_F_HIGHDMA;
613 	netdev->hw_features |= NETIF_F_GRO;
614 	netdev->features |= NETIF_F_GRO;
615 
616 	netdev->priv_flags |= IFF_UNICAST_FLT;
617 	netdev->priv_flags |= IFF_SUPP_NOFCS;
618 	netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
619 
620 	netdev->min_mtu = ETH_MIN_MTU;
621 	netdev->max_mtu = WX_MAX_JUMBO_FRAME_SIZE -
622 			  (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
623 
624 	wx->bd_number = func_nums;
625 	/* setup the private structure */
626 	err = ngbe_sw_init(wx);
627 	if (err)
628 		goto err_pci_release_regions;
629 
630 	/* check if flash load is done after hw power up */
631 	err = wx_check_flash_load(wx, NGBE_SPI_ILDR_STATUS_PERST);
632 	if (err)
633 		goto err_free_mac_table;
634 	err = wx_check_flash_load(wx, NGBE_SPI_ILDR_STATUS_PWRRST);
635 	if (err)
636 		goto err_free_mac_table;
637 
638 	err = wx_mng_present(wx);
639 	if (err) {
640 		dev_err(&pdev->dev, "Management capability is not present\n");
641 		goto err_free_mac_table;
642 	}
643 
644 	err = ngbe_reset_hw(wx);
645 	if (err) {
646 		dev_err(&pdev->dev, "HW Init failed: %d\n", err);
647 		goto err_free_mac_table;
648 	}
649 
650 	if (wx->bus.func == 0) {
651 		wr32(wx, NGBE_CALSUM_CAP_STATUS, 0x0);
652 		wr32(wx, NGBE_EEPROM_VERSION_STORE_REG, 0x0);
653 	} else {
654 		e2rom_cksum_cap = rd32(wx, NGBE_CALSUM_CAP_STATUS);
655 		saved_ver = rd32(wx, NGBE_EEPROM_VERSION_STORE_REG);
656 	}
657 
658 	wx_init_eeprom_params(wx);
659 	if (wx->bus.func == 0 || e2rom_cksum_cap == 0) {
660 		/* make sure the EEPROM is ready */
661 		err = ngbe_eeprom_chksum_hostif(wx);
662 		if (err) {
663 			dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
664 			err = -EIO;
665 			goto err_free_mac_table;
666 		}
667 	}
668 
669 	wx->wol = 0;
670 	if (wx->wol_hw_supported)
671 		wx->wol = NGBE_PSR_WKUP_CTL_MAG;
672 
673 	netdev->ethtool->wol_enabled = !!(wx->wol);
674 	wr32(wx, NGBE_PSR_WKUP_CTL, wx->wol);
675 	device_set_wakeup_enable(&pdev->dev, wx->wol);
676 
677 	/* Save off EEPROM version number and Option Rom version which
678 	 * together make a unique identify for the eeprom
679 	 */
680 	if (saved_ver) {
681 		etrack_id = saved_ver;
682 	} else {
683 		wx_read_ee_hostif(wx,
684 				  wx->eeprom.sw_region_offset + NGBE_EEPROM_VERSION_H,
685 				  &e2rom_ver);
686 		etrack_id = e2rom_ver << 16;
687 		wx_read_ee_hostif(wx,
688 				  wx->eeprom.sw_region_offset + NGBE_EEPROM_VERSION_L,
689 				  &e2rom_ver);
690 		etrack_id |= e2rom_ver;
691 		wr32(wx, NGBE_EEPROM_VERSION_STORE_REG, etrack_id);
692 	}
693 	snprintf(wx->eeprom_id, sizeof(wx->eeprom_id),
694 		 "0x%08x", etrack_id);
695 
696 	eth_hw_addr_set(netdev, wx->mac.perm_addr);
697 	wx_mac_set_default_filter(wx, wx->mac.perm_addr);
698 
699 	err = wx_init_interrupt_scheme(wx);
700 	if (err)
701 		goto err_free_mac_table;
702 
703 	/* phy Interface Configuration */
704 	err = ngbe_mdio_init(wx);
705 	if (err)
706 		goto err_clear_interrupt_scheme;
707 
708 	err = register_netdev(netdev);
709 	if (err)
710 		goto err_register;
711 
712 	pci_set_drvdata(pdev, wx);
713 
714 	return 0;
715 
716 err_register:
717 	phylink_destroy(wx->phylink);
718 	wx_control_hw(wx, false);
719 err_clear_interrupt_scheme:
720 	wx_clear_interrupt_scheme(wx);
721 err_free_mac_table:
722 	kfree(wx->rss_key);
723 	kfree(wx->mac_table);
724 err_pci_release_regions:
725 	pci_release_selected_regions(pdev,
726 				     pci_select_bars(pdev, IORESOURCE_MEM));
727 err_pci_disable_dev:
728 	pci_disable_device(pdev);
729 	return err;
730 }
731 
732 /**
733  * ngbe_remove - Device Removal Routine
734  * @pdev: PCI device information struct
735  *
736  * ngbe_remove is called by the PCI subsystem to alert the driver
737  * that it should release a PCI device.  The could be caused by a
738  * Hot-Plug event, or because the driver is going to be removed from
739  * memory.
740  **/
ngbe_remove(struct pci_dev * pdev)741 static void ngbe_remove(struct pci_dev *pdev)
742 {
743 	struct wx *wx = pci_get_drvdata(pdev);
744 	struct net_device *netdev;
745 
746 	netdev = wx->netdev;
747 	unregister_netdev(netdev);
748 	phylink_destroy(wx->phylink);
749 	pci_release_selected_regions(pdev,
750 				     pci_select_bars(pdev, IORESOURCE_MEM));
751 
752 	kfree(wx->rss_key);
753 	kfree(wx->mac_table);
754 	wx_clear_interrupt_scheme(wx);
755 
756 	pci_disable_device(pdev);
757 }
758 
ngbe_suspend(struct pci_dev * pdev,pm_message_t state)759 static int ngbe_suspend(struct pci_dev *pdev, pm_message_t state)
760 {
761 	bool wake;
762 
763 	ngbe_dev_shutdown(pdev, &wake);
764 	device_set_wakeup_enable(&pdev->dev, wake);
765 
766 	return 0;
767 }
768 
ngbe_resume(struct pci_dev * pdev)769 static int ngbe_resume(struct pci_dev *pdev)
770 {
771 	struct net_device *netdev;
772 	struct wx *wx;
773 	u32 err;
774 
775 	wx = pci_get_drvdata(pdev);
776 	netdev = wx->netdev;
777 
778 	err = pci_enable_device_mem(pdev);
779 	if (err) {
780 		wx_err(wx, "Cannot enable PCI device from suspend\n");
781 		return err;
782 	}
783 	pci_set_master(pdev);
784 	device_wakeup_disable(&pdev->dev);
785 
786 	ngbe_reset_hw(wx);
787 	rtnl_lock();
788 	err = wx_init_interrupt_scheme(wx);
789 	if (!err && netif_running(netdev))
790 		err = ngbe_open(netdev);
791 	if (!err)
792 		netif_device_attach(netdev);
793 	rtnl_unlock();
794 
795 	return 0;
796 }
797 
798 static struct pci_driver ngbe_driver = {
799 	.name     = ngbe_driver_name,
800 	.id_table = ngbe_pci_tbl,
801 	.probe    = ngbe_probe,
802 	.remove   = ngbe_remove,
803 	.suspend  = ngbe_suspend,
804 	.resume   = ngbe_resume,
805 	.shutdown = ngbe_shutdown,
806 };
807 
808 module_pci_driver(ngbe_driver);
809 
810 MODULE_DEVICE_TABLE(pci, ngbe_pci_tbl);
811 MODULE_AUTHOR("Beijing WangXun Technology Co., Ltd, <software@net-swift.com>");
812 MODULE_DESCRIPTION("WangXun(R) Gigabit PCI Express Network Driver");
813 MODULE_LICENSE("GPL");
814