1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Texas Instruments ICSSG Ethernet Driver
4  *
5  * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
6  * Copyright (C) Siemens AG, 2024
7  *
8  */
9 
10 #include <linux/dma-mapping.h>
11 #include <linux/dma/ti-cppi5.h>
12 #include <linux/etherdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/of.h>
16 #include <linux/of_mdio.h>
17 #include <linux/phy.h>
18 #include <linux/remoteproc/pruss.h>
19 #include <linux/regmap.h>
20 #include <linux/remoteproc.h>
21 
22 #include "icssg_prueth.h"
23 #include "../k3-cppi-desc-pool.h"
24 
25 /* Netif debug messages possible */
26 #define PRUETH_EMAC_DEBUG       (NETIF_MSG_DRV | \
27 				 NETIF_MSG_PROBE | \
28 				 NETIF_MSG_LINK | \
29 				 NETIF_MSG_TIMER | \
30 				 NETIF_MSG_IFDOWN | \
31 				 NETIF_MSG_IFUP | \
32 				 NETIF_MSG_RX_ERR | \
33 				 NETIF_MSG_TX_ERR | \
34 				 NETIF_MSG_TX_QUEUED | \
35 				 NETIF_MSG_INTR | \
36 				 NETIF_MSG_TX_DONE | \
37 				 NETIF_MSG_RX_STATUS | \
38 				 NETIF_MSG_PKTDATA | \
39 				 NETIF_MSG_HW | \
40 				 NETIF_MSG_WOL)
41 
42 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx)
43 
prueth_cleanup_rx_chns(struct prueth_emac * emac,struct prueth_rx_chn * rx_chn,int max_rflows)44 void prueth_cleanup_rx_chns(struct prueth_emac *emac,
45 			    struct prueth_rx_chn *rx_chn,
46 			    int max_rflows)
47 {
48 	if (rx_chn->pg_pool) {
49 		page_pool_destroy(rx_chn->pg_pool);
50 		rx_chn->pg_pool = NULL;
51 	}
52 
53 	if (rx_chn->desc_pool)
54 		k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
55 
56 	if (rx_chn->rx_chn)
57 		k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
58 }
59 EXPORT_SYMBOL_GPL(prueth_cleanup_rx_chns);
60 
prueth_cleanup_tx_chns(struct prueth_emac * emac)61 void prueth_cleanup_tx_chns(struct prueth_emac *emac)
62 {
63 	int i;
64 
65 	for (i = 0; i < emac->tx_ch_num; i++) {
66 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
67 
68 		if (tx_chn->desc_pool)
69 			k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
70 
71 		if (tx_chn->tx_chn)
72 			k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
73 
74 		/* Assume prueth_cleanup_tx_chns() is called at the
75 		 * end after all channel resources are freed
76 		 */
77 		memset(tx_chn, 0, sizeof(*tx_chn));
78 	}
79 }
80 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_chns);
81 
prueth_ndev_del_tx_napi(struct prueth_emac * emac,int num)82 void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num)
83 {
84 	int i;
85 
86 	for (i = 0; i < num; i++) {
87 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
88 
89 		if (tx_chn->irq)
90 			free_irq(tx_chn->irq, tx_chn);
91 		netif_napi_del(&tx_chn->napi_tx);
92 	}
93 }
94 EXPORT_SYMBOL_GPL(prueth_ndev_del_tx_napi);
95 
prueth_xmit_free(struct prueth_tx_chn * tx_chn,struct cppi5_host_desc_t * desc)96 void prueth_xmit_free(struct prueth_tx_chn *tx_chn,
97 		      struct cppi5_host_desc_t *desc)
98 {
99 	struct cppi5_host_desc_t *first_desc, *next_desc;
100 	dma_addr_t buf_dma, next_desc_dma;
101 	struct prueth_swdata *swdata;
102 	struct page *page;
103 	u32 buf_dma_len;
104 
105 	first_desc = desc;
106 	next_desc = first_desc;
107 
108 	swdata = cppi5_hdesc_get_swdata(desc);
109 	if (swdata->type == PRUETH_SWDATA_PAGE) {
110 		page = swdata->data.page;
111 		page_pool_recycle_direct(page->pp, swdata->data.page);
112 		goto free_desc;
113 	}
114 
115 	cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
116 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
117 
118 	dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len,
119 			 DMA_TO_DEVICE);
120 
121 	next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
122 	k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
123 	while (next_desc_dma) {
124 		next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
125 						       next_desc_dma);
126 		cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
127 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
128 
129 		dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len,
130 			       DMA_TO_DEVICE);
131 
132 		next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
133 		k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
134 
135 		k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
136 	}
137 
138 free_desc:
139 	k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
140 }
141 EXPORT_SYMBOL_GPL(prueth_xmit_free);
142 
emac_tx_complete_packets(struct prueth_emac * emac,int chn,int budget,bool * tdown)143 int emac_tx_complete_packets(struct prueth_emac *emac, int chn,
144 			     int budget, bool *tdown)
145 {
146 	struct net_device *ndev = emac->ndev;
147 	struct cppi5_host_desc_t *desc_tx;
148 	struct netdev_queue *netif_txq;
149 	struct prueth_swdata *swdata;
150 	struct prueth_tx_chn *tx_chn;
151 	unsigned int total_bytes = 0;
152 	struct xdp_frame *xdpf;
153 	struct sk_buff *skb;
154 	dma_addr_t desc_dma;
155 	int res, num_tx = 0;
156 
157 	tx_chn = &emac->tx_chns[chn];
158 
159 	while (true) {
160 		res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
161 		if (res == -ENODATA)
162 			break;
163 
164 		/* teardown completion */
165 		if (cppi5_desc_is_tdcm(desc_dma)) {
166 			if (atomic_dec_and_test(&emac->tdown_cnt))
167 				complete(&emac->tdown_complete);
168 			*tdown = true;
169 			break;
170 		}
171 
172 		desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
173 						     desc_dma);
174 		swdata = cppi5_hdesc_get_swdata(desc_tx);
175 
176 		switch (swdata->type) {
177 		case PRUETH_SWDATA_SKB:
178 			skb = swdata->data.skb;
179 			dev_sw_netstats_tx_add(skb->dev, 1, skb->len);
180 			total_bytes += skb->len;
181 			napi_consume_skb(skb, budget);
182 			break;
183 		case PRUETH_SWDATA_XDPF:
184 			xdpf = swdata->data.xdpf;
185 			dev_sw_netstats_tx_add(ndev, 1, xdpf->len);
186 			total_bytes += xdpf->len;
187 			xdp_return_frame(xdpf);
188 			break;
189 		default:
190 			prueth_xmit_free(tx_chn, desc_tx);
191 			ndev->stats.tx_dropped++;
192 			continue;
193 		}
194 
195 		prueth_xmit_free(tx_chn, desc_tx);
196 		num_tx++;
197 	}
198 
199 	if (!num_tx)
200 		return 0;
201 
202 	netif_txq = netdev_get_tx_queue(ndev, chn);
203 	netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
204 
205 	if (netif_tx_queue_stopped(netif_txq)) {
206 		/* If the TX queue was stopped, wake it now
207 		 * if we have enough room.
208 		 */
209 		__netif_tx_lock(netif_txq, smp_processor_id());
210 		if (netif_running(ndev) &&
211 		    (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
212 		     MAX_SKB_FRAGS))
213 			netif_tx_wake_queue(netif_txq);
214 		__netif_tx_unlock(netif_txq);
215 	}
216 
217 	return num_tx;
218 }
219 
emac_tx_timer_callback(struct hrtimer * timer)220 static enum hrtimer_restart emac_tx_timer_callback(struct hrtimer *timer)
221 {
222 	struct prueth_tx_chn *tx_chns =
223 			container_of(timer, struct prueth_tx_chn, tx_hrtimer);
224 
225 	enable_irq(tx_chns->irq);
226 	return HRTIMER_NORESTART;
227 }
228 
emac_napi_tx_poll(struct napi_struct * napi_tx,int budget)229 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget)
230 {
231 	struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx);
232 	struct prueth_emac *emac = tx_chn->emac;
233 	bool tdown = false;
234 	int num_tx_packets;
235 
236 	num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget,
237 						  &tdown);
238 
239 	if (num_tx_packets >= budget)
240 		return budget;
241 
242 	if (napi_complete_done(napi_tx, num_tx_packets)) {
243 		if (unlikely(tx_chn->tx_pace_timeout_ns && !tdown)) {
244 			hrtimer_start(&tx_chn->tx_hrtimer,
245 				      ns_to_ktime(tx_chn->tx_pace_timeout_ns),
246 				      HRTIMER_MODE_REL_PINNED);
247 		} else {
248 			enable_irq(tx_chn->irq);
249 		}
250 	}
251 
252 	return num_tx_packets;
253 }
254 
prueth_tx_irq(int irq,void * dev_id)255 static irqreturn_t prueth_tx_irq(int irq, void *dev_id)
256 {
257 	struct prueth_tx_chn *tx_chn = dev_id;
258 
259 	disable_irq_nosync(irq);
260 	napi_schedule(&tx_chn->napi_tx);
261 
262 	return IRQ_HANDLED;
263 }
264 
prueth_ndev_add_tx_napi(struct prueth_emac * emac)265 int prueth_ndev_add_tx_napi(struct prueth_emac *emac)
266 {
267 	struct prueth *prueth = emac->prueth;
268 	int i, ret;
269 
270 	for (i = 0; i < emac->tx_ch_num; i++) {
271 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
272 
273 		netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll);
274 		hrtimer_setup(&tx_chn->tx_hrtimer, &emac_tx_timer_callback, CLOCK_MONOTONIC,
275 			      HRTIMER_MODE_REL_PINNED);
276 		ret = request_irq(tx_chn->irq, prueth_tx_irq,
277 				  IRQF_TRIGGER_HIGH, tx_chn->name,
278 				  tx_chn);
279 		if (ret) {
280 			netif_napi_del(&tx_chn->napi_tx);
281 			dev_err(prueth->dev, "unable to request TX IRQ %d\n",
282 				tx_chn->irq);
283 			goto fail;
284 		}
285 	}
286 
287 	return 0;
288 fail:
289 	prueth_ndev_del_tx_napi(emac, i);
290 	return ret;
291 }
292 EXPORT_SYMBOL_GPL(prueth_ndev_add_tx_napi);
293 
prueth_init_tx_chns(struct prueth_emac * emac)294 int prueth_init_tx_chns(struct prueth_emac *emac)
295 {
296 	static const struct k3_ring_cfg ring_cfg = {
297 		.elm_size = K3_RINGACC_RING_ELSIZE_8,
298 		.mode = K3_RINGACC_RING_MODE_RING,
299 		.flags = 0,
300 		.size = PRUETH_MAX_TX_DESC,
301 	};
302 	struct k3_udma_glue_tx_channel_cfg tx_cfg;
303 	struct device *dev = emac->prueth->dev;
304 	struct net_device *ndev = emac->ndev;
305 	int ret, slice, i;
306 	u32 hdesc_size;
307 
308 	slice = prueth_emac_slice(emac);
309 	if (slice < 0)
310 		return slice;
311 
312 	init_completion(&emac->tdown_complete);
313 
314 	hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE,
315 					   PRUETH_NAV_SW_DATA_SIZE);
316 	memset(&tx_cfg, 0, sizeof(tx_cfg));
317 	tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE;
318 	tx_cfg.tx_cfg = ring_cfg;
319 	tx_cfg.txcq_cfg = ring_cfg;
320 
321 	for (i = 0; i < emac->tx_ch_num; i++) {
322 		struct prueth_tx_chn *tx_chn = &emac->tx_chns[i];
323 
324 		/* To differentiate channels for SLICE0 vs SLICE1 */
325 		snprintf(tx_chn->name, sizeof(tx_chn->name),
326 			 "tx%d-%d", slice, i);
327 
328 		tx_chn->emac = emac;
329 		tx_chn->id = i;
330 		tx_chn->descs_num = PRUETH_MAX_TX_DESC;
331 
332 		tx_chn->tx_chn =
333 			k3_udma_glue_request_tx_chn(dev, tx_chn->name,
334 						    &tx_cfg);
335 		if (IS_ERR(tx_chn->tx_chn)) {
336 			ret = PTR_ERR(tx_chn->tx_chn);
337 			tx_chn->tx_chn = NULL;
338 			netdev_err(ndev,
339 				   "Failed to request tx dma ch: %d\n", ret);
340 			goto fail;
341 		}
342 
343 		tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn);
344 		tx_chn->desc_pool =
345 			k3_cppi_desc_pool_create_name(tx_chn->dma_dev,
346 						      tx_chn->descs_num,
347 						      hdesc_size,
348 						      tx_chn->name);
349 		if (IS_ERR(tx_chn->desc_pool)) {
350 			ret = PTR_ERR(tx_chn->desc_pool);
351 			tx_chn->desc_pool = NULL;
352 			netdev_err(ndev, "Failed to create tx pool: %d\n", ret);
353 			goto fail;
354 		}
355 
356 		ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
357 		if (ret < 0) {
358 			netdev_err(ndev, "failed to get tx irq\n");
359 			goto fail;
360 		}
361 		tx_chn->irq = ret;
362 
363 		snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d",
364 			 dev_name(dev), tx_chn->id);
365 	}
366 
367 	return 0;
368 
369 fail:
370 	prueth_cleanup_tx_chns(emac);
371 	return ret;
372 }
373 EXPORT_SYMBOL_GPL(prueth_init_tx_chns);
374 
prueth_init_rx_chns(struct prueth_emac * emac,struct prueth_rx_chn * rx_chn,char * name,u32 max_rflows,u32 max_desc_num)375 int prueth_init_rx_chns(struct prueth_emac *emac,
376 			struct prueth_rx_chn *rx_chn,
377 			char *name, u32 max_rflows,
378 			u32 max_desc_num)
379 {
380 	struct k3_udma_glue_rx_channel_cfg rx_cfg;
381 	struct device *dev = emac->prueth->dev;
382 	struct net_device *ndev = emac->ndev;
383 	u32 fdqring_id, hdesc_size;
384 	int i, ret = 0, slice;
385 	int flow_id_base;
386 
387 	slice = prueth_emac_slice(emac);
388 	if (slice < 0)
389 		return slice;
390 
391 	/* To differentiate channels for SLICE0 vs SLICE1 */
392 	snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice);
393 
394 	hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE,
395 					   PRUETH_NAV_SW_DATA_SIZE);
396 	memset(&rx_cfg, 0, sizeof(rx_cfg));
397 	rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE;
398 	rx_cfg.flow_id_num = max_rflows;
399 	rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */
400 
401 	/* init all flows */
402 	rx_chn->dev = dev;
403 	rx_chn->descs_num = max_desc_num;
404 
405 	rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name,
406 						     &rx_cfg);
407 	if (IS_ERR(rx_chn->rx_chn)) {
408 		ret = PTR_ERR(rx_chn->rx_chn);
409 		rx_chn->rx_chn = NULL;
410 		netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret);
411 		goto fail;
412 	}
413 
414 	rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);
415 	rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,
416 							  rx_chn->descs_num,
417 							  hdesc_size,
418 							  rx_chn->name);
419 	if (IS_ERR(rx_chn->desc_pool)) {
420 		ret = PTR_ERR(rx_chn->desc_pool);
421 		rx_chn->desc_pool = NULL;
422 		netdev_err(ndev, "Failed to create rx pool: %d\n", ret);
423 		goto fail;
424 	}
425 
426 	flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
427 	if (emac->is_sr1 && !strcmp(name, "rxmgm")) {
428 		emac->rx_mgm_flow_id_base = flow_id_base;
429 		netdev_dbg(ndev, "mgm flow id base = %d\n", flow_id_base);
430 	} else {
431 		emac->rx_flow_id_base = flow_id_base;
432 		netdev_dbg(ndev, "flow id base = %d\n", flow_id_base);
433 	}
434 
435 	fdqring_id = K3_RINGACC_RING_ID_ANY;
436 	for (i = 0; i < rx_cfg.flow_id_num; i++) {
437 		struct k3_ring_cfg rxring_cfg = {
438 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
439 			.mode = K3_RINGACC_RING_MODE_RING,
440 			.flags = 0,
441 		};
442 		struct k3_ring_cfg fdqring_cfg = {
443 			.elm_size = K3_RINGACC_RING_ELSIZE_8,
444 			.flags = K3_RINGACC_RING_SHARED,
445 		};
446 		struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
447 			.rx_cfg = rxring_cfg,
448 			.rxfdq_cfg = fdqring_cfg,
449 			.ring_rxq_id = K3_RINGACC_RING_ID_ANY,
450 			.src_tag_lo_sel =
451 				K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
452 		};
453 
454 		rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
455 		rx_flow_cfg.rx_cfg.size = max_desc_num;
456 		rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
457 		rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode;
458 
459 		ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
460 						i, &rx_flow_cfg);
461 		if (ret) {
462 			netdev_err(ndev, "Failed to init rx flow%d %d\n",
463 				   i, ret);
464 			goto fail;
465 		}
466 		if (!i)
467 			fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
468 								     i);
469 		ret = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
470 		if (ret < 0) {
471 			netdev_err(ndev, "Failed to get rx dma irq");
472 			goto fail;
473 		}
474 		rx_chn->irq[i] = ret;
475 	}
476 
477 	return 0;
478 
479 fail:
480 	prueth_cleanup_rx_chns(emac, rx_chn, max_rflows);
481 	return ret;
482 }
483 EXPORT_SYMBOL_GPL(prueth_init_rx_chns);
484 
prueth_dma_rx_push_mapped(struct prueth_emac * emac,struct prueth_rx_chn * rx_chn,struct page * page,u32 buf_len)485 int prueth_dma_rx_push_mapped(struct prueth_emac *emac,
486 			      struct prueth_rx_chn *rx_chn,
487 			      struct page *page, u32 buf_len)
488 {
489 	struct net_device *ndev = emac->ndev;
490 	struct cppi5_host_desc_t *desc_rx;
491 	struct prueth_swdata *swdata;
492 	dma_addr_t desc_dma;
493 	dma_addr_t buf_dma;
494 
495 	buf_dma = page_pool_get_dma_addr(page) + PRUETH_HEADROOM;
496 	desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
497 	if (!desc_rx) {
498 		netdev_err(ndev, "rx push: failed to allocate descriptor\n");
499 		return -ENOMEM;
500 	}
501 	desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
502 
503 	cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
504 			 PRUETH_NAV_PS_DATA_SIZE);
505 	k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma);
506 	cppi5_hdesc_attach_buf(desc_rx, buf_dma, buf_len, buf_dma, buf_len);
507 
508 	swdata = cppi5_hdesc_get_swdata(desc_rx);
509 	swdata->type = PRUETH_SWDATA_PAGE;
510 	swdata->data.page = page;
511 
512 	return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, PRUETH_RX_FLOW_DATA,
513 					desc_rx, desc_dma);
514 }
515 EXPORT_SYMBOL_GPL(prueth_dma_rx_push_mapped);
516 
icssg_ts_to_ns(u32 hi_sw,u32 hi,u32 lo,u32 cycle_time_ns)517 u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns)
518 {
519 	u32 iepcount_lo, iepcount_hi, hi_rollover_count;
520 	u64 ns;
521 
522 	iepcount_lo = lo & GENMASK(19, 0);
523 	iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20;
524 	hi_rollover_count = hi >> 11;
525 
526 	ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw);
527 	ns = ns * cycle_time_ns + iepcount_lo;
528 
529 	return ns;
530 }
531 EXPORT_SYMBOL_GPL(icssg_ts_to_ns);
532 
emac_rx_timestamp(struct prueth_emac * emac,struct sk_buff * skb,u32 * psdata)533 void emac_rx_timestamp(struct prueth_emac *emac,
534 		       struct sk_buff *skb, u32 *psdata)
535 {
536 	struct skb_shared_hwtstamps *ssh;
537 	u64 ns;
538 
539 	if (emac->is_sr1) {
540 		ns = (u64)psdata[1] << 32 | psdata[0];
541 	} else {
542 		u32 hi_sw = readl(emac->prueth->shram.va +
543 				  TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET);
544 		ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0],
545 				    IEP_DEFAULT_CYCLE_TIME_NS);
546 	}
547 
548 	ssh = skb_hwtstamps(skb);
549 	memset(ssh, 0, sizeof(*ssh));
550 	ssh->hwtstamp = ns_to_ktime(ns);
551 }
552 
553 /**
554  * emac_xmit_xdp_frame - transmits an XDP frame
555  * @emac: emac device
556  * @xdpf: data to transmit
557  * @page: page from page pool if already DMA mapped
558  * @q_idx: queue id
559  *
560  * Return: XDP state
561  */
emac_xmit_xdp_frame(struct prueth_emac * emac,struct xdp_frame * xdpf,struct page * page,unsigned int q_idx)562 u32 emac_xmit_xdp_frame(struct prueth_emac *emac,
563 			struct xdp_frame *xdpf,
564 			struct page *page,
565 			unsigned int q_idx)
566 {
567 	struct cppi5_host_desc_t *first_desc;
568 	struct net_device *ndev = emac->ndev;
569 	struct netdev_queue *netif_txq;
570 	struct prueth_tx_chn *tx_chn;
571 	dma_addr_t desc_dma, buf_dma;
572 	struct prueth_swdata *swdata;
573 	u32 *epib;
574 	int ret;
575 
576 	if (q_idx >= PRUETH_MAX_TX_QUEUES) {
577 		netdev_err(ndev, "xdp tx: invalid q_id %d\n", q_idx);
578 		return ICSSG_XDP_CONSUMED;	/* drop */
579 	}
580 
581 	tx_chn = &emac->tx_chns[q_idx];
582 
583 	first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
584 	if (!first_desc) {
585 		netdev_dbg(ndev, "xdp tx: failed to allocate descriptor\n");
586 		return ICSSG_XDP_CONSUMED;	/* drop */
587 	}
588 
589 	if (page) { /* already DMA mapped by page_pool */
590 		buf_dma = page_pool_get_dma_addr(page);
591 		buf_dma += xdpf->headroom + sizeof(struct xdp_frame);
592 	} else { /* Map the linear buffer */
593 		buf_dma = dma_map_single(tx_chn->dma_dev, xdpf->data, xdpf->len, DMA_TO_DEVICE);
594 		if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) {
595 			netdev_err(ndev, "xdp tx: failed to map data buffer\n");
596 			goto drop_free_descs;	/* drop */
597 		}
598 	}
599 
600 	cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
601 			 PRUETH_NAV_PS_DATA_SIZE);
602 	cppi5_hdesc_set_pkttype(first_desc, 0);
603 	epib = first_desc->epib;
604 	epib[0] = 0;
605 	epib[1] = 0;
606 
607 	/* set dst tag to indicate internal qid at the firmware which is at
608 	 * bit8..bit15. bit0..bit7 indicates port num for directed
609 	 * packets in case of switch mode operation
610 	 */
611 	cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8)));
612 	k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
613 	cppi5_hdesc_attach_buf(first_desc, buf_dma, xdpf->len, buf_dma, xdpf->len);
614 	swdata = cppi5_hdesc_get_swdata(first_desc);
615 	if (page) {
616 		swdata->type = PRUETH_SWDATA_PAGE;
617 		swdata->data.page = page;
618 	} else {
619 		swdata->type = PRUETH_SWDATA_XDPF;
620 		swdata->data.xdpf = xdpf;
621 	}
622 
623 	/* Report BQL before sending the packet */
624 	netif_txq = netdev_get_tx_queue(ndev, tx_chn->id);
625 	netdev_tx_sent_queue(netif_txq, xdpf->len);
626 
627 	cppi5_hdesc_set_pktlen(first_desc, xdpf->len);
628 	desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
629 
630 	ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
631 	if (ret) {
632 		netdev_err(ndev, "xdp tx: push failed: %d\n", ret);
633 		netdev_tx_completed_queue(netif_txq, 1, xdpf->len);
634 		goto drop_free_descs;
635 	}
636 
637 	return ICSSG_XDP_TX;
638 
639 drop_free_descs:
640 	prueth_xmit_free(tx_chn, first_desc);
641 	return ICSSG_XDP_CONSUMED;
642 }
643 EXPORT_SYMBOL_GPL(emac_xmit_xdp_frame);
644 
645 /**
646  * emac_run_xdp - run an XDP program
647  * @emac: emac device
648  * @xdp: XDP buffer containing the frame
649  * @page: page with RX data if already DMA mapped
650  * @len: Rx descriptor packet length
651  *
652  * Return: XDP state
653  */
emac_run_xdp(struct prueth_emac * emac,struct xdp_buff * xdp,struct page * page,u32 * len)654 static u32 emac_run_xdp(struct prueth_emac *emac, struct xdp_buff *xdp,
655 			struct page *page, u32 *len)
656 {
657 	struct net_device *ndev = emac->ndev;
658 	struct netdev_queue *netif_txq;
659 	int cpu = smp_processor_id();
660 	struct bpf_prog *xdp_prog;
661 	struct xdp_frame *xdpf;
662 	u32 pkt_len = *len;
663 	u32 act, result;
664 	int q_idx, err;
665 
666 	xdp_prog = READ_ONCE(emac->xdp_prog);
667 	act = bpf_prog_run_xdp(xdp_prog, xdp);
668 	switch (act) {
669 	case XDP_PASS:
670 		return ICSSG_XDP_PASS;
671 	case XDP_TX:
672 		/* Send packet to TX ring for immediate transmission */
673 		xdpf = xdp_convert_buff_to_frame(xdp);
674 		if (unlikely(!xdpf)) {
675 			ndev->stats.tx_dropped++;
676 			goto drop;
677 		}
678 
679 		q_idx = cpu % emac->tx_ch_num;
680 		netif_txq = netdev_get_tx_queue(ndev, q_idx);
681 		__netif_tx_lock(netif_txq, cpu);
682 		result = emac_xmit_xdp_frame(emac, xdpf, page, q_idx);
683 		__netif_tx_unlock(netif_txq);
684 		if (result == ICSSG_XDP_CONSUMED) {
685 			ndev->stats.tx_dropped++;
686 			goto drop;
687 		}
688 
689 		dev_sw_netstats_rx_add(ndev, xdpf->len);
690 		return result;
691 	case XDP_REDIRECT:
692 		err = xdp_do_redirect(emac->ndev, xdp, xdp_prog);
693 		if (err)
694 			goto drop;
695 
696 		dev_sw_netstats_rx_add(ndev, pkt_len);
697 		return ICSSG_XDP_REDIR;
698 	default:
699 		bpf_warn_invalid_xdp_action(emac->ndev, xdp_prog, act);
700 		fallthrough;
701 	case XDP_ABORTED:
702 drop:
703 		trace_xdp_exception(emac->ndev, xdp_prog, act);
704 		fallthrough; /* handle aborts by dropping packet */
705 	case XDP_DROP:
706 		ndev->stats.rx_dropped++;
707 		page_pool_recycle_direct(emac->rx_chns.pg_pool, page);
708 		return ICSSG_XDP_CONSUMED;
709 	}
710 }
711 
emac_rx_packet(struct prueth_emac * emac,u32 flow_id,u32 * xdp_state)712 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id, u32 *xdp_state)
713 {
714 	struct prueth_rx_chn *rx_chn = &emac->rx_chns;
715 	u32 buf_dma_len, pkt_len, port_id = 0;
716 	struct net_device *ndev = emac->ndev;
717 	struct cppi5_host_desc_t *desc_rx;
718 	struct prueth_swdata *swdata;
719 	dma_addr_t desc_dma, buf_dma;
720 	struct page *page, *new_page;
721 	struct page_pool *pool;
722 	struct sk_buff *skb;
723 	struct xdp_buff xdp;
724 	u32 *psdata;
725 	void *pa;
726 	int ret;
727 
728 	*xdp_state = 0;
729 	pool = rx_chn->pg_pool;
730 	ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma);
731 	if (ret) {
732 		if (ret != -ENODATA)
733 			netdev_err(ndev, "rx pop: failed: %d\n", ret);
734 		return ret;
735 	}
736 
737 	if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */
738 		return 0;
739 
740 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
741 	swdata = cppi5_hdesc_get_swdata(desc_rx);
742 	if (swdata->type != PRUETH_SWDATA_PAGE) {
743 		netdev_err(ndev, "rx_pkt: invalid swdata->type %d\n", swdata->type);
744 		k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
745 		return 0;
746 	}
747 
748 	page = swdata->data.page;
749 	page_pool_dma_sync_for_cpu(pool, page, 0, PAGE_SIZE);
750 	cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
751 	k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
752 	pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
753 	/* firmware adds 4 CRC bytes, strip them */
754 	pkt_len -= 4;
755 	cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
756 
757 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
758 
759 	/* if allocation fails we drop the packet but push the
760 	 * descriptor back to the ring with old page to prevent a stall
761 	 */
762 	new_page = page_pool_dev_alloc_pages(pool);
763 	if (unlikely(!new_page)) {
764 		new_page = page;
765 		ndev->stats.rx_dropped++;
766 		goto requeue;
767 	}
768 
769 	pa = page_address(page);
770 	if (emac->xdp_prog) {
771 		xdp_init_buff(&xdp, PAGE_SIZE, &rx_chn->xdp_rxq);
772 		xdp_prepare_buff(&xdp, pa, PRUETH_HEADROOM, pkt_len, false);
773 
774 		*xdp_state = emac_run_xdp(emac, &xdp, page, &pkt_len);
775 		if (*xdp_state == ICSSG_XDP_PASS)
776 			skb = xdp_build_skb_from_buff(&xdp);
777 		else
778 			goto requeue;
779 	} else {
780 		/* prepare skb and send to n/w stack */
781 		skb = napi_build_skb(pa, PAGE_SIZE);
782 	}
783 
784 	if (!skb) {
785 		ndev->stats.rx_dropped++;
786 		page_pool_recycle_direct(pool, page);
787 		goto requeue;
788 	}
789 
790 	skb_reserve(skb, PRUETH_HEADROOM);
791 	skb_put(skb, pkt_len);
792 	skb->dev = ndev;
793 
794 	psdata = cppi5_hdesc_get_psdata(desc_rx);
795 	/* RX HW timestamp */
796 	if (emac->rx_ts_enabled)
797 		emac_rx_timestamp(emac, skb, psdata);
798 
799 	if (emac->prueth->is_switch_mode)
800 		skb->offload_fwd_mark = emac->offload_fwd_mark;
801 	skb->protocol = eth_type_trans(skb, ndev);
802 
803 	skb_mark_for_recycle(skb);
804 	napi_gro_receive(&emac->napi_rx, skb);
805 	ndev->stats.rx_bytes += pkt_len;
806 	ndev->stats.rx_packets++;
807 
808 requeue:
809 	/* queue another RX DMA */
810 	ret = prueth_dma_rx_push_mapped(emac, &emac->rx_chns, new_page,
811 					PRUETH_MAX_PKT_SIZE);
812 	if (WARN_ON(ret < 0)) {
813 		page_pool_recycle_direct(pool, new_page);
814 		ndev->stats.rx_errors++;
815 		ndev->stats.rx_dropped++;
816 	}
817 
818 	return ret;
819 }
820 
prueth_rx_cleanup(void * data,dma_addr_t desc_dma)821 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma)
822 {
823 	struct prueth_rx_chn *rx_chn = data;
824 	struct cppi5_host_desc_t *desc_rx;
825 	struct prueth_swdata *swdata;
826 	struct page_pool *pool;
827 	struct page *page;
828 
829 	pool = rx_chn->pg_pool;
830 	desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
831 	swdata = cppi5_hdesc_get_swdata(desc_rx);
832 	if (swdata->type == PRUETH_SWDATA_PAGE) {
833 		page = swdata->data.page;
834 		page_pool_recycle_direct(pool, page);
835 	}
836 
837 	k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
838 }
839 
prueth_tx_ts_cookie_get(struct prueth_emac * emac)840 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac)
841 {
842 	int i;
843 
844 	/* search and get the next free slot */
845 	for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) {
846 		if (!emac->tx_ts_skb[i]) {
847 			emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */
848 			return i;
849 		}
850 	}
851 
852 	return -EBUSY;
853 }
854 
855 /**
856  * icssg_ndo_start_xmit - EMAC Transmit function
857  * @skb: SKB pointer
858  * @ndev: EMAC network adapter
859  *
860  * Called by the system to transmit a packet  - we queue the packet in
861  * EMAC hardware transmit queue
862  * Doesn't wait for completion we'll check for TX completion in
863  * emac_tx_complete_packets().
864  *
865  * Return: enum netdev_tx
866  */
icssg_ndo_start_xmit(struct sk_buff * skb,struct net_device * ndev)867 enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev)
868 {
869 	struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
870 	struct prueth_emac *emac = netdev_priv(ndev);
871 	struct prueth *prueth = emac->prueth;
872 	struct netdev_queue *netif_txq;
873 	struct prueth_swdata *swdata;
874 	struct prueth_tx_chn *tx_chn;
875 	dma_addr_t desc_dma, buf_dma;
876 	u32 pkt_len, dst_tag_id;
877 	int i, ret = 0, q_idx;
878 	bool in_tx_ts = 0;
879 	int tx_ts_cookie;
880 	u32 *epib;
881 
882 	pkt_len = skb_headlen(skb);
883 	q_idx = skb_get_queue_mapping(skb);
884 
885 	tx_chn = &emac->tx_chns[q_idx];
886 	netif_txq = netdev_get_tx_queue(ndev, q_idx);
887 
888 	/* Map the linear buffer */
889 	buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE);
890 	if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) {
891 		netdev_err(ndev, "tx: failed to map skb buffer\n");
892 		ret = NETDEV_TX_OK;
893 		goto drop_free_skb;
894 	}
895 
896 	first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
897 	if (!first_desc) {
898 		netdev_dbg(ndev, "tx: failed to allocate descriptor\n");
899 		dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE);
900 		goto drop_stop_q_busy;
901 	}
902 
903 	cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
904 			 PRUETH_NAV_PS_DATA_SIZE);
905 	cppi5_hdesc_set_pkttype(first_desc, 0);
906 	epib = first_desc->epib;
907 	epib[0] = 0;
908 	epib[1] = 0;
909 	if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
910 	    emac->tx_ts_enabled) {
911 		tx_ts_cookie = prueth_tx_ts_cookie_get(emac);
912 		if (tx_ts_cookie >= 0) {
913 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
914 			/* Request TX timestamp */
915 			epib[0] = (u32)tx_ts_cookie;
916 			epib[1] = 0x80000000;	/* TX TS request */
917 			emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb);
918 			in_tx_ts = 1;
919 		}
920 	}
921 
922 	/* set dst tag to indicate internal qid at the firmware which is at
923 	 * bit8..bit15. bit0..bit7 indicates port num for directed
924 	 * packets in case of switch mode operation and port num 0
925 	 * for undirected packets in case of HSR offload mode
926 	 */
927 	dst_tag_id = emac->port_id | (q_idx << 8);
928 
929 	if (prueth->is_hsr_offload_mode &&
930 	    (ndev->features & NETIF_F_HW_HSR_DUP))
931 		dst_tag_id = PRUETH_UNDIRECTED_PKT_DST_TAG;
932 
933 	if (prueth->is_hsr_offload_mode &&
934 	    (ndev->features & NETIF_F_HW_HSR_TAG_INS))
935 		epib[1] |= PRUETH_UNDIRECTED_PKT_TAG_INS;
936 
937 	cppi5_desc_set_tags_ids(&first_desc->hdr, 0, dst_tag_id);
938 	k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
939 	cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
940 	swdata = cppi5_hdesc_get_swdata(first_desc);
941 	swdata->type = PRUETH_SWDATA_SKB;
942 	swdata->data.skb = skb;
943 
944 	/* Handle the case where skb is fragmented in pages */
945 	cur_desc = first_desc;
946 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
947 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
948 		u32 frag_size = skb_frag_size(frag);
949 
950 		next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
951 		if (!next_desc) {
952 			netdev_err(ndev,
953 				   "tx: failed to allocate frag. descriptor\n");
954 			goto free_desc_stop_q_busy_cleanup_tx_ts;
955 		}
956 
957 		buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size,
958 					   DMA_TO_DEVICE);
959 		if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) {
960 			netdev_err(ndev, "tx: Failed to map skb page\n");
961 			k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
962 			ret = NETDEV_TX_OK;
963 			goto cleanup_tx_ts;
964 		}
965 
966 		cppi5_hdesc_reset_hbdesc(next_desc);
967 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
968 		cppi5_hdesc_attach_buf(next_desc,
969 				       buf_dma, frag_size, buf_dma, frag_size);
970 
971 		desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
972 						      next_desc);
973 		k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma);
974 		cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
975 
976 		pkt_len += frag_size;
977 		cur_desc = next_desc;
978 	}
979 	WARN_ON_ONCE(pkt_len != skb->len);
980 
981 	/* report bql before sending packet */
982 	netdev_tx_sent_queue(netif_txq, pkt_len);
983 
984 	cppi5_hdesc_set_pktlen(first_desc, pkt_len);
985 	desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
986 	/* cppi5_desc_dump(first_desc, 64); */
987 
988 	skb_tx_timestamp(skb);  /* SW timestamp if SKBTX_IN_PROGRESS not set */
989 	ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
990 	if (ret) {
991 		netdev_err(ndev, "tx: push failed: %d\n", ret);
992 		netdev_tx_completed_queue(netif_txq, 1, pkt_len);
993 		goto drop_free_descs;
994 	}
995 
996 	if (in_tx_ts)
997 		atomic_inc(&emac->tx_ts_pending);
998 
999 	if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
1000 		netif_tx_stop_queue(netif_txq);
1001 		/* Barrier, so that stop_queue visible to other cpus */
1002 		smp_mb__after_atomic();
1003 
1004 		if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
1005 		    MAX_SKB_FRAGS)
1006 			netif_tx_wake_queue(netif_txq);
1007 	}
1008 
1009 	return NETDEV_TX_OK;
1010 
1011 cleanup_tx_ts:
1012 	if (in_tx_ts) {
1013 		dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]);
1014 		emac->tx_ts_skb[tx_ts_cookie] = NULL;
1015 	}
1016 
1017 drop_free_descs:
1018 	prueth_xmit_free(tx_chn, first_desc);
1019 
1020 drop_free_skb:
1021 	dev_kfree_skb_any(skb);
1022 
1023 	/* error */
1024 	ndev->stats.tx_dropped++;
1025 	netdev_err(ndev, "tx: error: %d\n", ret);
1026 
1027 	return ret;
1028 
1029 free_desc_stop_q_busy_cleanup_tx_ts:
1030 	if (in_tx_ts) {
1031 		dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]);
1032 		emac->tx_ts_skb[tx_ts_cookie] = NULL;
1033 	}
1034 	prueth_xmit_free(tx_chn, first_desc);
1035 
1036 drop_stop_q_busy:
1037 	netif_tx_stop_queue(netif_txq);
1038 	return NETDEV_TX_BUSY;
1039 }
1040 EXPORT_SYMBOL_GPL(icssg_ndo_start_xmit);
1041 
prueth_tx_cleanup(void * data,dma_addr_t desc_dma)1042 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma)
1043 {
1044 	struct prueth_tx_chn *tx_chn = data;
1045 	struct cppi5_host_desc_t *desc_tx;
1046 	struct prueth_swdata *swdata;
1047 	struct xdp_frame *xdpf;
1048 	struct sk_buff *skb;
1049 
1050 	desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
1051 	swdata = cppi5_hdesc_get_swdata(desc_tx);
1052 
1053 	switch (swdata->type) {
1054 	case PRUETH_SWDATA_SKB:
1055 		skb = swdata->data.skb;
1056 		dev_kfree_skb_any(skb);
1057 		break;
1058 	case PRUETH_SWDATA_XDPF:
1059 		xdpf = swdata->data.xdpf;
1060 		xdp_return_frame(xdpf);
1061 		break;
1062 	default:
1063 		break;
1064 	}
1065 
1066 	prueth_xmit_free(tx_chn, desc_tx);
1067 }
1068 
prueth_rx_irq(int irq,void * dev_id)1069 irqreturn_t prueth_rx_irq(int irq, void *dev_id)
1070 {
1071 	struct prueth_emac *emac = dev_id;
1072 
1073 	disable_irq_nosync(irq);
1074 	napi_schedule(&emac->napi_rx);
1075 
1076 	return IRQ_HANDLED;
1077 }
1078 EXPORT_SYMBOL_GPL(prueth_rx_irq);
1079 
prueth_cleanup_tx_ts(struct prueth_emac * emac)1080 void prueth_cleanup_tx_ts(struct prueth_emac *emac)
1081 {
1082 	int i;
1083 
1084 	for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) {
1085 		if (emac->tx_ts_skb[i]) {
1086 			dev_kfree_skb_any(emac->tx_ts_skb[i]);
1087 			emac->tx_ts_skb[i] = NULL;
1088 		}
1089 	}
1090 }
1091 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_ts);
1092 
icssg_napi_rx_poll(struct napi_struct * napi_rx,int budget)1093 int icssg_napi_rx_poll(struct napi_struct *napi_rx, int budget)
1094 {
1095 	struct prueth_emac *emac = prueth_napi_to_emac(napi_rx);
1096 	int rx_flow = emac->is_sr1 ?
1097 		PRUETH_RX_FLOW_DATA_SR1 : PRUETH_RX_FLOW_DATA;
1098 	int flow = emac->is_sr1 ?
1099 		PRUETH_MAX_RX_FLOWS_SR1 : PRUETH_MAX_RX_FLOWS;
1100 	int xdp_state_or = 0;
1101 	int num_rx = 0;
1102 	int cur_budget;
1103 	u32 xdp_state;
1104 	int ret;
1105 
1106 	while (flow--) {
1107 		cur_budget = budget - num_rx;
1108 
1109 		while (cur_budget--) {
1110 			ret = emac_rx_packet(emac, flow, &xdp_state);
1111 			xdp_state_or |= xdp_state;
1112 			if (ret)
1113 				break;
1114 			num_rx++;
1115 		}
1116 
1117 		if (num_rx >= budget)
1118 			break;
1119 	}
1120 
1121 	if (xdp_state_or & ICSSG_XDP_REDIR)
1122 		xdp_do_flush();
1123 
1124 	if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) {
1125 		if (unlikely(emac->rx_pace_timeout_ns)) {
1126 			hrtimer_start(&emac->rx_hrtimer,
1127 				      ns_to_ktime(emac->rx_pace_timeout_ns),
1128 				      HRTIMER_MODE_REL_PINNED);
1129 		} else {
1130 			enable_irq(emac->rx_chns.irq[rx_flow]);
1131 		}
1132 	}
1133 
1134 	return num_rx;
1135 }
1136 EXPORT_SYMBOL_GPL(icssg_napi_rx_poll);
1137 
prueth_create_page_pool(struct prueth_emac * emac,struct device * dma_dev,int size)1138 static struct page_pool *prueth_create_page_pool(struct prueth_emac *emac,
1139 						 struct device *dma_dev,
1140 						 int size)
1141 {
1142 	struct page_pool_params pp_params = { 0 };
1143 	struct page_pool *pool;
1144 
1145 	pp_params.order = 0;
1146 	pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1147 	pp_params.pool_size = size;
1148 	pp_params.nid = dev_to_node(emac->prueth->dev);
1149 	pp_params.dma_dir = DMA_BIDIRECTIONAL;
1150 	pp_params.dev = dma_dev;
1151 	pp_params.napi = &emac->napi_rx;
1152 	pp_params.max_len = PAGE_SIZE;
1153 
1154 	pool = page_pool_create(&pp_params);
1155 	if (IS_ERR(pool))
1156 		netdev_err(emac->ndev, "cannot create rx page pool\n");
1157 
1158 	return pool;
1159 }
1160 
prueth_prepare_rx_chan(struct prueth_emac * emac,struct prueth_rx_chn * chn,int buf_size)1161 int prueth_prepare_rx_chan(struct prueth_emac *emac,
1162 			   struct prueth_rx_chn *chn,
1163 			   int buf_size)
1164 {
1165 	struct page_pool *pool;
1166 	struct page *page;
1167 	int i, ret;
1168 
1169 	pool = prueth_create_page_pool(emac, chn->dma_dev, chn->descs_num);
1170 	if (IS_ERR(pool))
1171 		return PTR_ERR(pool);
1172 
1173 	chn->pg_pool = pool;
1174 
1175 	for (i = 0; i < chn->descs_num; i++) {
1176 		/* NOTE: we're not using memory efficiently here.
1177 		 * 1 full page (4KB?) used here instead of
1178 		 * PRUETH_MAX_PKT_SIZE (~1.5KB?)
1179 		 */
1180 		page = page_pool_dev_alloc_pages(pool);
1181 		if (!page) {
1182 			netdev_err(emac->ndev, "couldn't allocate rx page\n");
1183 			ret = -ENOMEM;
1184 			goto recycle_alloc_pg;
1185 		}
1186 
1187 		ret = prueth_dma_rx_push_mapped(emac, chn, page, buf_size);
1188 		if (ret < 0) {
1189 			netdev_err(emac->ndev,
1190 				   "cannot submit page for rx chan %s ret %d\n",
1191 				   chn->name, ret);
1192 			page_pool_recycle_direct(pool, page);
1193 			goto recycle_alloc_pg;
1194 		}
1195 	}
1196 
1197 	return 0;
1198 
1199 recycle_alloc_pg:
1200 	prueth_reset_rx_chan(&emac->rx_chns, PRUETH_MAX_RX_FLOWS, false);
1201 
1202 	return ret;
1203 }
1204 EXPORT_SYMBOL_GPL(prueth_prepare_rx_chan);
1205 
prueth_reset_tx_chan(struct prueth_emac * emac,int ch_num,bool free_skb)1206 void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num,
1207 			  bool free_skb)
1208 {
1209 	int i;
1210 
1211 	for (i = 0; i < ch_num; i++) {
1212 		if (free_skb)
1213 			k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn,
1214 						  &emac->tx_chns[i],
1215 						  prueth_tx_cleanup);
1216 		k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn);
1217 	}
1218 }
1219 EXPORT_SYMBOL_GPL(prueth_reset_tx_chan);
1220 
prueth_reset_rx_chan(struct prueth_rx_chn * chn,int num_flows,bool disable)1221 void prueth_reset_rx_chan(struct prueth_rx_chn *chn,
1222 			  int num_flows, bool disable)
1223 {
1224 	int i;
1225 
1226 	for (i = 0; i < num_flows; i++)
1227 		k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn,
1228 					  prueth_rx_cleanup);
1229 	if (disable)
1230 		k3_udma_glue_disable_rx_chn(chn->rx_chn);
1231 }
1232 EXPORT_SYMBOL_GPL(prueth_reset_rx_chan);
1233 
icssg_ndo_tx_timeout(struct net_device * ndev,unsigned int txqueue)1234 void icssg_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1235 {
1236 	ndev->stats.tx_errors++;
1237 }
1238 EXPORT_SYMBOL_GPL(icssg_ndo_tx_timeout);
1239 
emac_set_ts_config(struct net_device * ndev,struct ifreq * ifr)1240 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr)
1241 {
1242 	struct prueth_emac *emac = netdev_priv(ndev);
1243 	struct hwtstamp_config config;
1244 
1245 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1246 		return -EFAULT;
1247 
1248 	switch (config.tx_type) {
1249 	case HWTSTAMP_TX_OFF:
1250 		emac->tx_ts_enabled = 0;
1251 		break;
1252 	case HWTSTAMP_TX_ON:
1253 		emac->tx_ts_enabled = 1;
1254 		break;
1255 	default:
1256 		return -ERANGE;
1257 	}
1258 
1259 	switch (config.rx_filter) {
1260 	case HWTSTAMP_FILTER_NONE:
1261 		emac->rx_ts_enabled = 0;
1262 		break;
1263 	case HWTSTAMP_FILTER_ALL:
1264 	case HWTSTAMP_FILTER_SOME:
1265 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1266 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1267 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1268 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1269 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1270 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1271 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1272 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1273 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1274 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
1275 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
1276 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1277 	case HWTSTAMP_FILTER_NTP_ALL:
1278 		emac->rx_ts_enabled = 1;
1279 		config.rx_filter = HWTSTAMP_FILTER_ALL;
1280 		break;
1281 	default:
1282 		return -ERANGE;
1283 	}
1284 
1285 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1286 		-EFAULT : 0;
1287 }
1288 
emac_get_ts_config(struct net_device * ndev,struct ifreq * ifr)1289 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr)
1290 {
1291 	struct prueth_emac *emac = netdev_priv(ndev);
1292 	struct hwtstamp_config config;
1293 
1294 	config.flags = 0;
1295 	config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1296 	config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1297 
1298 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1299 			    -EFAULT : 0;
1300 }
1301 
icssg_ndo_ioctl(struct net_device * ndev,struct ifreq * ifr,int cmd)1302 int icssg_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
1303 {
1304 	switch (cmd) {
1305 	case SIOCGHWTSTAMP:
1306 		return emac_get_ts_config(ndev, ifr);
1307 	case SIOCSHWTSTAMP:
1308 		return emac_set_ts_config(ndev, ifr);
1309 	default:
1310 		break;
1311 	}
1312 
1313 	return phy_do_ioctl(ndev, ifr, cmd);
1314 }
1315 EXPORT_SYMBOL_GPL(icssg_ndo_ioctl);
1316 
icssg_ndo_get_stats64(struct net_device * ndev,struct rtnl_link_stats64 * stats)1317 void icssg_ndo_get_stats64(struct net_device *ndev,
1318 			   struct rtnl_link_stats64 *stats)
1319 {
1320 	struct prueth_emac *emac = netdev_priv(ndev);
1321 
1322 	emac_update_hardware_stats(emac);
1323 
1324 	stats->rx_packets     = emac_get_stat_by_name(emac, "rx_packets");
1325 	stats->rx_bytes       = emac_get_stat_by_name(emac, "rx_bytes");
1326 	stats->tx_packets     = emac_get_stat_by_name(emac, "tx_packets");
1327 	stats->tx_bytes       = emac_get_stat_by_name(emac, "tx_bytes");
1328 	stats->rx_crc_errors  = emac_get_stat_by_name(emac, "rx_crc_errors");
1329 	stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors");
1330 	stats->multicast      = emac_get_stat_by_name(emac, "rx_multicast_frames");
1331 
1332 	stats->rx_errors  = ndev->stats.rx_errors;
1333 	stats->rx_dropped = ndev->stats.rx_dropped;
1334 	stats->tx_errors  = ndev->stats.tx_errors;
1335 	stats->tx_dropped = ndev->stats.tx_dropped;
1336 }
1337 EXPORT_SYMBOL_GPL(icssg_ndo_get_stats64);
1338 
icssg_ndo_get_phys_port_name(struct net_device * ndev,char * name,size_t len)1339 int icssg_ndo_get_phys_port_name(struct net_device *ndev, char *name,
1340 				 size_t len)
1341 {
1342 	struct prueth_emac *emac = netdev_priv(ndev);
1343 	int ret;
1344 
1345 	ret = snprintf(name, len, "p%d", emac->port_id);
1346 	if (ret >= len)
1347 		return -EINVAL;
1348 
1349 	return 0;
1350 }
1351 EXPORT_SYMBOL_GPL(icssg_ndo_get_phys_port_name);
1352 
1353 /* get emac_port corresponding to eth_node name */
prueth_node_port(struct device_node * eth_node)1354 int prueth_node_port(struct device_node *eth_node)
1355 {
1356 	u32 port_id;
1357 	int ret;
1358 
1359 	ret = of_property_read_u32(eth_node, "reg", &port_id);
1360 	if (ret)
1361 		return ret;
1362 
1363 	if (port_id == 0)
1364 		return PRUETH_PORT_MII0;
1365 	else if (port_id == 1)
1366 		return PRUETH_PORT_MII1;
1367 	else
1368 		return PRUETH_PORT_INVALID;
1369 }
1370 EXPORT_SYMBOL_GPL(prueth_node_port);
1371 
1372 /* get MAC instance corresponding to eth_node name */
prueth_node_mac(struct device_node * eth_node)1373 int prueth_node_mac(struct device_node *eth_node)
1374 {
1375 	u32 port_id;
1376 	int ret;
1377 
1378 	ret = of_property_read_u32(eth_node, "reg", &port_id);
1379 	if (ret)
1380 		return ret;
1381 
1382 	if (port_id == 0)
1383 		return PRUETH_MAC0;
1384 	else if (port_id == 1)
1385 		return PRUETH_MAC1;
1386 	else
1387 		return PRUETH_MAC_INVALID;
1388 }
1389 EXPORT_SYMBOL_GPL(prueth_node_mac);
1390 
prueth_netdev_exit(struct prueth * prueth,struct device_node * eth_node)1391 void prueth_netdev_exit(struct prueth *prueth,
1392 			struct device_node *eth_node)
1393 {
1394 	struct prueth_emac *emac;
1395 	enum prueth_mac mac;
1396 
1397 	mac = prueth_node_mac(eth_node);
1398 	if (mac == PRUETH_MAC_INVALID)
1399 		return;
1400 
1401 	emac = prueth->emac[mac];
1402 	if (!emac)
1403 		return;
1404 
1405 	if (of_phy_is_fixed_link(emac->phy_node))
1406 		of_phy_deregister_fixed_link(emac->phy_node);
1407 
1408 	netif_napi_del(&emac->napi_rx);
1409 
1410 	pruss_release_mem_region(prueth->pruss, &emac->dram);
1411 	destroy_workqueue(emac->cmd_wq);
1412 	free_netdev(emac->ndev);
1413 	prueth->emac[mac] = NULL;
1414 }
1415 EXPORT_SYMBOL_GPL(prueth_netdev_exit);
1416 
prueth_get_cores(struct prueth * prueth,int slice,bool is_sr1)1417 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1)
1418 {
1419 	struct device *dev = prueth->dev;
1420 	enum pruss_pru_id pruss_id;
1421 	struct device_node *np;
1422 	int idx = -1, ret;
1423 
1424 	np = dev->of_node;
1425 
1426 	switch (slice) {
1427 	case ICSS_SLICE0:
1428 		idx = 0;
1429 		break;
1430 	case ICSS_SLICE1:
1431 		idx = is_sr1 ? 2 : 3;
1432 		break;
1433 	default:
1434 		return -EINVAL;
1435 	}
1436 
1437 	prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id);
1438 	if (IS_ERR(prueth->pru[slice])) {
1439 		ret = PTR_ERR(prueth->pru[slice]);
1440 		prueth->pru[slice] = NULL;
1441 		return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice);
1442 	}
1443 	prueth->pru_id[slice] = pruss_id;
1444 
1445 	idx++;
1446 	prueth->rtu[slice] = pru_rproc_get(np, idx, NULL);
1447 	if (IS_ERR(prueth->rtu[slice])) {
1448 		ret = PTR_ERR(prueth->rtu[slice]);
1449 		prueth->rtu[slice] = NULL;
1450 		return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice);
1451 	}
1452 
1453 	if (is_sr1)
1454 		return 0;
1455 
1456 	idx++;
1457 	prueth->txpru[slice] = pru_rproc_get(np, idx, NULL);
1458 	if (IS_ERR(prueth->txpru[slice])) {
1459 		ret = PTR_ERR(prueth->txpru[slice]);
1460 		prueth->txpru[slice] = NULL;
1461 		return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice);
1462 	}
1463 
1464 	return 0;
1465 }
1466 EXPORT_SYMBOL_GPL(prueth_get_cores);
1467 
prueth_put_cores(struct prueth * prueth,int slice)1468 void prueth_put_cores(struct prueth *prueth, int slice)
1469 {
1470 	if (prueth->txpru[slice])
1471 		pru_rproc_put(prueth->txpru[slice]);
1472 
1473 	if (prueth->rtu[slice])
1474 		pru_rproc_put(prueth->rtu[slice]);
1475 
1476 	if (prueth->pru[slice])
1477 		pru_rproc_put(prueth->pru[slice]);
1478 }
1479 EXPORT_SYMBOL_GPL(prueth_put_cores);
1480 
1481 #ifdef CONFIG_PM_SLEEP
prueth_suspend(struct device * dev)1482 static int prueth_suspend(struct device *dev)
1483 {
1484 	struct prueth *prueth = dev_get_drvdata(dev);
1485 	struct net_device *ndev;
1486 	int i, ret;
1487 
1488 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1489 		ndev = prueth->registered_netdevs[i];
1490 
1491 		if (!ndev)
1492 			continue;
1493 
1494 		if (netif_running(ndev)) {
1495 			netif_device_detach(ndev);
1496 			ret = ndev->netdev_ops->ndo_stop(ndev);
1497 			if (ret < 0) {
1498 				netdev_err(ndev, "failed to stop: %d", ret);
1499 				return ret;
1500 			}
1501 		}
1502 	}
1503 
1504 	return 0;
1505 }
1506 
prueth_resume(struct device * dev)1507 static int prueth_resume(struct device *dev)
1508 {
1509 	struct prueth *prueth = dev_get_drvdata(dev);
1510 	struct net_device *ndev;
1511 	int i, ret;
1512 
1513 	for (i = 0; i < PRUETH_NUM_MACS; i++) {
1514 		ndev = prueth->registered_netdevs[i];
1515 
1516 		if (!ndev)
1517 			continue;
1518 
1519 		if (netif_running(ndev)) {
1520 			ret = ndev->netdev_ops->ndo_open(ndev);
1521 			if (ret < 0) {
1522 				netdev_err(ndev, "failed to start: %d", ret);
1523 				return ret;
1524 			}
1525 			netif_device_attach(ndev);
1526 		}
1527 	}
1528 
1529 	return 0;
1530 }
1531 #endif /* CONFIG_PM_SLEEP */
1532 
1533 const struct dev_pm_ops prueth_dev_pm_ops = {
1534 	SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume)
1535 };
1536 EXPORT_SYMBOL_GPL(prueth_dev_pm_ops);
1537 
1538 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
1539 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>");
1540 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver Common Module");
1541 MODULE_LICENSE("GPL");
1542