1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Loongson Corporation
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/pci.h>
7 #include <linux/dmi.h>
8 #include <linux/device.h>
9 #include <linux/of_irq.h>
10 #include "stmmac.h"
11 #include "dwmac_dma.h"
12 #include "dwmac1000.h"
13
14 #define DRIVER_NAME "dwmac-loongson-pci"
15
16 /* Normal Loongson Tx Summary */
17 #define DMA_INTR_ENA_NIE_TX_LOONGSON 0x00040000
18 /* Normal Loongson Rx Summary */
19 #define DMA_INTR_ENA_NIE_RX_LOONGSON 0x00020000
20
21 #define DMA_INTR_NORMAL_LOONGSON (DMA_INTR_ENA_NIE_TX_LOONGSON | \
22 DMA_INTR_ENA_NIE_RX_LOONGSON | \
23 DMA_INTR_ENA_RIE | DMA_INTR_ENA_TIE)
24
25 /* Abnormal Loongson Tx Summary */
26 #define DMA_INTR_ENA_AIE_TX_LOONGSON 0x00010000
27 /* Abnormal Loongson Rx Summary */
28 #define DMA_INTR_ENA_AIE_RX_LOONGSON 0x00008000
29
30 #define DMA_INTR_ABNORMAL_LOONGSON (DMA_INTR_ENA_AIE_TX_LOONGSON | \
31 DMA_INTR_ENA_AIE_RX_LOONGSON | \
32 DMA_INTR_ENA_FBE | DMA_INTR_ENA_UNE)
33
34 #define DMA_INTR_DEFAULT_MASK_LOONGSON (DMA_INTR_NORMAL_LOONGSON | \
35 DMA_INTR_ABNORMAL_LOONGSON)
36
37 /* Normal Loongson Tx Interrupt Summary */
38 #define DMA_STATUS_NIS_TX_LOONGSON 0x00040000
39 /* Normal Loongson Rx Interrupt Summary */
40 #define DMA_STATUS_NIS_RX_LOONGSON 0x00020000
41
42 /* Abnormal Loongson Tx Interrupt Summary */
43 #define DMA_STATUS_AIS_TX_LOONGSON 0x00010000
44 /* Abnormal Loongson Rx Interrupt Summary */
45 #define DMA_STATUS_AIS_RX_LOONGSON 0x00008000
46
47 /* Fatal Loongson Tx Bus Error Interrupt */
48 #define DMA_STATUS_FBI_TX_LOONGSON 0x00002000
49 /* Fatal Loongson Rx Bus Error Interrupt */
50 #define DMA_STATUS_FBI_RX_LOONGSON 0x00001000
51
52 #define DMA_STATUS_MSK_COMMON_LOONGSON (DMA_STATUS_NIS_TX_LOONGSON | \
53 DMA_STATUS_NIS_RX_LOONGSON | \
54 DMA_STATUS_AIS_TX_LOONGSON | \
55 DMA_STATUS_AIS_RX_LOONGSON | \
56 DMA_STATUS_FBI_TX_LOONGSON | \
57 DMA_STATUS_FBI_RX_LOONGSON)
58
59 #define DMA_STATUS_MSK_RX_LOONGSON (DMA_STATUS_ERI | DMA_STATUS_RWT | \
60 DMA_STATUS_RPS | DMA_STATUS_RU | \
61 DMA_STATUS_RI | DMA_STATUS_OVF | \
62 DMA_STATUS_MSK_COMMON_LOONGSON)
63
64 #define DMA_STATUS_MSK_TX_LOONGSON (DMA_STATUS_ETI | DMA_STATUS_UNF | \
65 DMA_STATUS_TJT | DMA_STATUS_TU | \
66 DMA_STATUS_TPS | DMA_STATUS_TI | \
67 DMA_STATUS_MSK_COMMON_LOONGSON)
68
69 #define PCI_DEVICE_ID_LOONGSON_GMAC 0x7a03
70 #define PCI_DEVICE_ID_LOONGSON_GNET 0x7a13
71 #define DWMAC_CORE_LS_MULTICHAN 0x10 /* Loongson custom ID */
72 #define CHANNEL_NUM 8
73
74 struct loongson_data {
75 u32 loongson_id;
76 struct device *dev;
77 };
78
79 struct stmmac_pci_info {
80 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
81 };
82
loongson_default_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)83 static void loongson_default_data(struct pci_dev *pdev,
84 struct plat_stmmacenet_data *plat)
85 {
86 /* Get bus_id, this can be overwritten later */
87 plat->bus_id = pci_dev_id(pdev);
88
89 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
90 plat->has_gmac = 1;
91 plat->force_sf_dma_mode = 1;
92
93 /* Set default value for multicast hash bins */
94 plat->multicast_filter_bins = 256;
95
96 plat->mac_interface = PHY_INTERFACE_MODE_NA;
97
98 /* Set default value for unicast filter entries */
99 plat->unicast_filter_entries = 1;
100
101 /* Set the maxmtu to a default of JUMBO_LEN */
102 plat->maxmtu = JUMBO_LEN;
103
104 /* Disable Priority config by default */
105 plat->tx_queues_cfg[0].use_prio = false;
106 plat->rx_queues_cfg[0].use_prio = false;
107
108 /* Disable RX queues routing by default */
109 plat->rx_queues_cfg[0].pkt_route = 0x0;
110
111 plat->clk_ref_rate = 125000000;
112 plat->clk_ptp_rate = 125000000;
113
114 /* Default to phy auto-detection */
115 plat->phy_addr = -1;
116
117 plat->dma_cfg->pbl = 32;
118 plat->dma_cfg->pblx8 = true;
119 }
120
loongson_gmac_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)121 static int loongson_gmac_data(struct pci_dev *pdev,
122 struct plat_stmmacenet_data *plat)
123 {
124 struct loongson_data *ld;
125 int i;
126
127 ld = plat->bsp_priv;
128
129 loongson_default_data(pdev, plat);
130
131 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN) {
132 plat->rx_queues_to_use = CHANNEL_NUM;
133 plat->tx_queues_to_use = CHANNEL_NUM;
134
135 /* Only channel 0 supports checksum,
136 * so turn off checksum to enable multiple channels.
137 */
138 for (i = 1; i < CHANNEL_NUM; i++)
139 plat->tx_queues_cfg[i].coe_unsupported = 1;
140 } else {
141 plat->tx_queues_to_use = 1;
142 plat->rx_queues_to_use = 1;
143 }
144
145 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
146
147 return 0;
148 }
149
150 static struct stmmac_pci_info loongson_gmac_pci_info = {
151 .setup = loongson_gmac_data,
152 };
153
loongson_gnet_fix_speed(void * priv,int speed,unsigned int mode)154 static void loongson_gnet_fix_speed(void *priv, int speed, unsigned int mode)
155 {
156 struct loongson_data *ld = (struct loongson_data *)priv;
157 struct net_device *ndev = dev_get_drvdata(ld->dev);
158 struct stmmac_priv *ptr = netdev_priv(ndev);
159
160 /* The integrated PHY has a weird problem with switching from the low
161 * speeds to 1000Mbps mode. The speedup procedure requires the PHY-link
162 * re-negotiation.
163 */
164 if (speed == SPEED_1000) {
165 if (readl(ptr->ioaddr + MAC_CTRL_REG) &
166 GMAC_CONTROL_PS)
167 /* Word around hardware bug, restart autoneg */
168 phy_restart_aneg(ndev->phydev);
169 }
170 }
171
loongson_gnet_data(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)172 static int loongson_gnet_data(struct pci_dev *pdev,
173 struct plat_stmmacenet_data *plat)
174 {
175 struct loongson_data *ld;
176 int i;
177
178 ld = plat->bsp_priv;
179
180 loongson_default_data(pdev, plat);
181
182 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN) {
183 plat->rx_queues_to_use = CHANNEL_NUM;
184 plat->tx_queues_to_use = CHANNEL_NUM;
185
186 /* Only channel 0 supports checksum,
187 * so turn off checksum to enable multiple channels.
188 */
189 for (i = 1; i < CHANNEL_NUM; i++)
190 plat->tx_queues_cfg[i].coe_unsupported = 1;
191 } else {
192 plat->tx_queues_to_use = 1;
193 plat->rx_queues_to_use = 1;
194 }
195
196 plat->phy_interface = PHY_INTERFACE_MODE_GMII;
197 plat->mdio_bus_data->phy_mask = ~(u32)BIT(2);
198 plat->fix_mac_speed = loongson_gnet_fix_speed;
199
200 return 0;
201 }
202
203 static struct stmmac_pci_info loongson_gnet_pci_info = {
204 .setup = loongson_gnet_data,
205 };
206
loongson_dwmac_dma_init_channel(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_dma_cfg * dma_cfg,u32 chan)207 static void loongson_dwmac_dma_init_channel(struct stmmac_priv *priv,
208 void __iomem *ioaddr,
209 struct stmmac_dma_cfg *dma_cfg,
210 u32 chan)
211 {
212 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
213 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
214 u32 value;
215
216 value = readl(ioaddr + DMA_CHAN_BUS_MODE(chan));
217
218 if (dma_cfg->pblx8)
219 value |= DMA_BUS_MODE_MAXPBL;
220
221 value |= DMA_BUS_MODE_USP;
222 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK);
223 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT);
224 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
225
226 /* Set the Fixed burst mode */
227 if (dma_cfg->fixed_burst)
228 value |= DMA_BUS_MODE_FB;
229
230 /* Mixed Burst has no effect when fb is set */
231 if (dma_cfg->mixed_burst)
232 value |= DMA_BUS_MODE_MB;
233
234 if (dma_cfg->atds)
235 value |= DMA_BUS_MODE_ATDS;
236
237 if (dma_cfg->aal)
238 value |= DMA_BUS_MODE_AAL;
239
240 writel(value, ioaddr + DMA_CHAN_BUS_MODE(chan));
241
242 /* Mask interrupts by writing to CSR7 */
243 writel(DMA_INTR_DEFAULT_MASK_LOONGSON, ioaddr +
244 DMA_CHAN_INTR_ENA(chan));
245 }
246
loongson_dwmac_dma_interrupt(struct stmmac_priv * priv,void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 chan,u32 dir)247 static int loongson_dwmac_dma_interrupt(struct stmmac_priv *priv,
248 void __iomem *ioaddr,
249 struct stmmac_extra_stats *x,
250 u32 chan, u32 dir)
251 {
252 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats);
253 u32 abnor_intr_status;
254 u32 nor_intr_status;
255 u32 fb_intr_status;
256 u32 intr_status;
257 int ret = 0;
258
259 /* read the status register (CSR5) */
260 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));
261
262 if (dir == DMA_DIR_RX)
263 intr_status &= DMA_STATUS_MSK_RX_LOONGSON;
264 else if (dir == DMA_DIR_TX)
265 intr_status &= DMA_STATUS_MSK_TX_LOONGSON;
266
267 nor_intr_status = intr_status & (DMA_STATUS_NIS_TX_LOONGSON |
268 DMA_STATUS_NIS_RX_LOONGSON);
269 abnor_intr_status = intr_status & (DMA_STATUS_AIS_TX_LOONGSON |
270 DMA_STATUS_AIS_RX_LOONGSON);
271 fb_intr_status = intr_status & (DMA_STATUS_FBI_TX_LOONGSON |
272 DMA_STATUS_FBI_RX_LOONGSON);
273
274 /* ABNORMAL interrupts */
275 if (unlikely(abnor_intr_status)) {
276 if (unlikely(intr_status & DMA_STATUS_UNF)) {
277 ret = tx_hard_error_bump_tc;
278 x->tx_undeflow_irq++;
279 }
280 if (unlikely(intr_status & DMA_STATUS_TJT))
281 x->tx_jabber_irq++;
282 if (unlikely(intr_status & DMA_STATUS_OVF))
283 x->rx_overflow_irq++;
284 if (unlikely(intr_status & DMA_STATUS_RU))
285 x->rx_buf_unav_irq++;
286 if (unlikely(intr_status & DMA_STATUS_RPS))
287 x->rx_process_stopped_irq++;
288 if (unlikely(intr_status & DMA_STATUS_RWT))
289 x->rx_watchdog_irq++;
290 if (unlikely(intr_status & DMA_STATUS_ETI))
291 x->tx_early_irq++;
292 if (unlikely(intr_status & DMA_STATUS_TPS)) {
293 x->tx_process_stopped_irq++;
294 ret = tx_hard_error;
295 }
296 if (unlikely(fb_intr_status)) {
297 x->fatal_bus_error_irq++;
298 ret = tx_hard_error;
299 }
300 }
301 /* TX/RX NORMAL interrupts */
302 if (likely(nor_intr_status)) {
303 if (likely(intr_status & DMA_STATUS_RI)) {
304 u32 value = readl(ioaddr + DMA_INTR_ENA);
305 /* to schedule NAPI on real RIE event. */
306 if (likely(value & DMA_INTR_ENA_RIE)) {
307 u64_stats_update_begin(&stats->syncp);
308 u64_stats_inc(&stats->rx_normal_irq_n[chan]);
309 u64_stats_update_end(&stats->syncp);
310 ret |= handle_rx;
311 }
312 }
313 if (likely(intr_status & DMA_STATUS_TI)) {
314 u64_stats_update_begin(&stats->syncp);
315 u64_stats_inc(&stats->tx_normal_irq_n[chan]);
316 u64_stats_update_end(&stats->syncp);
317 ret |= handle_tx;
318 }
319 if (unlikely(intr_status & DMA_STATUS_ERI))
320 x->rx_early_irq++;
321 }
322 /* Optional hardware blocks, interrupts should be disabled */
323 if (unlikely(intr_status &
324 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
325 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
326
327 /* Clear the interrupt by writing a logic 1 to the CSR5[19-0] */
328 writel((intr_status & 0x7ffff), ioaddr + DMA_CHAN_STATUS(chan));
329
330 return ret;
331 }
332
loongson_dwmac_setup(void * apriv)333 static struct mac_device_info *loongson_dwmac_setup(void *apriv)
334 {
335 struct stmmac_priv *priv = apriv;
336 struct mac_device_info *mac;
337 struct stmmac_dma_ops *dma;
338 struct loongson_data *ld;
339 struct pci_dev *pdev;
340
341 ld = priv->plat->bsp_priv;
342 pdev = to_pci_dev(priv->device);
343
344 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
345 if (!mac)
346 return NULL;
347
348 dma = devm_kzalloc(priv->device, sizeof(*dma), GFP_KERNEL);
349 if (!dma)
350 return NULL;
351
352 /* The Loongson GMAC and GNET devices are based on the DW GMAC
353 * v3.50a and v3.73a IP-cores. But the HW designers have changed the
354 * GMAC_VERSION.SNPSVER field to the custom 0x10 value on the
355 * network controllers with the multi-channels feature
356 * available to emphasize the differences: multiple DMA-channels,
357 * AV feature and GMAC_INT_STATUS CSR flags layout. Get back the
358 * original value so the correct HW-interface would be selected.
359 */
360 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN) {
361 priv->synopsys_id = DWMAC_CORE_3_70;
362 *dma = dwmac1000_dma_ops;
363 dma->init_chan = loongson_dwmac_dma_init_channel;
364 dma->dma_interrupt = loongson_dwmac_dma_interrupt;
365 mac->dma = dma;
366 }
367
368 priv->dev->priv_flags |= IFF_UNICAST_FLT;
369
370 /* Pre-initialize the respective "mac" fields as it's done in
371 * dwmac1000_setup()
372 */
373 mac->pcsr = priv->ioaddr;
374 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
375 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
376 mac->mcast_bits_log2 = 0;
377
378 if (mac->multicast_filter_bins)
379 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
380
381 /* Loongson GMAC doesn't support the flow control. LS2K2000
382 * GNET doesn't support the half-duplex link mode.
383 */
384 if (pdev->device == PCI_DEVICE_ID_LOONGSON_GMAC) {
385 mac->link.caps = MAC_10 | MAC_100 | MAC_1000;
386 } else {
387 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN)
388 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
389 MAC_10 | MAC_100 | MAC_1000;
390 else
391 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
392 MAC_10FD | MAC_100FD | MAC_1000FD;
393 }
394
395 mac->link.duplex = GMAC_CONTROL_DM;
396 mac->link.speed10 = GMAC_CONTROL_PS;
397 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
398 mac->link.speed1000 = 0;
399 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
400 mac->mii.addr = GMAC_MII_ADDR;
401 mac->mii.data = GMAC_MII_DATA;
402 mac->mii.addr_shift = 11;
403 mac->mii.addr_mask = 0x0000F800;
404 mac->mii.reg_shift = 6;
405 mac->mii.reg_mask = 0x000007C0;
406 mac->mii.clk_csr_shift = 2;
407 mac->mii.clk_csr_mask = GENMASK(5, 2);
408
409 return mac;
410 }
411
loongson_dwmac_msi_config(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)412 static int loongson_dwmac_msi_config(struct pci_dev *pdev,
413 struct plat_stmmacenet_data *plat,
414 struct stmmac_resources *res)
415 {
416 int i, ret, vecs;
417
418 vecs = roundup_pow_of_two(CHANNEL_NUM * 2 + 1);
419 ret = pci_alloc_irq_vectors(pdev, vecs, vecs, PCI_IRQ_MSI);
420 if (ret < 0) {
421 dev_warn(&pdev->dev, "Failed to allocate MSI IRQs\n");
422 return ret;
423 }
424
425 res->irq = pci_irq_vector(pdev, 0);
426
427 for (i = 0; i < plat->rx_queues_to_use; i++) {
428 res->rx_irq[CHANNEL_NUM - 1 - i] =
429 pci_irq_vector(pdev, 1 + i * 2);
430 }
431
432 for (i = 0; i < plat->tx_queues_to_use; i++) {
433 res->tx_irq[CHANNEL_NUM - 1 - i] =
434 pci_irq_vector(pdev, 2 + i * 2);
435 }
436
437 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
438
439 return 0;
440 }
441
loongson_dwmac_msi_clear(struct pci_dev * pdev)442 static void loongson_dwmac_msi_clear(struct pci_dev *pdev)
443 {
444 pci_free_irq_vectors(pdev);
445 }
446
loongson_dwmac_dt_config(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)447 static int loongson_dwmac_dt_config(struct pci_dev *pdev,
448 struct plat_stmmacenet_data *plat,
449 struct stmmac_resources *res)
450 {
451 struct device_node *np = dev_of_node(&pdev->dev);
452 int ret;
453
454 plat->mdio_node = of_get_child_by_name(np, "mdio");
455 if (plat->mdio_node) {
456 dev_info(&pdev->dev, "Found MDIO subnode\n");
457 plat->mdio_bus_data->needs_reset = true;
458 }
459
460 ret = of_alias_get_id(np, "ethernet");
461 if (ret >= 0)
462 plat->bus_id = ret;
463
464 res->irq = of_irq_get_byname(np, "macirq");
465 if (res->irq < 0) {
466 dev_err(&pdev->dev, "IRQ macirq not found\n");
467 ret = -ENODEV;
468 goto err_put_node;
469 }
470
471 res->wol_irq = of_irq_get_byname(np, "eth_wake_irq");
472 if (res->wol_irq < 0) {
473 dev_info(&pdev->dev,
474 "IRQ eth_wake_irq not found, using macirq\n");
475 res->wol_irq = res->irq;
476 }
477
478 res->lpi_irq = of_irq_get_byname(np, "eth_lpi");
479 if (res->lpi_irq < 0) {
480 dev_err(&pdev->dev, "IRQ eth_lpi not found\n");
481 ret = -ENODEV;
482 goto err_put_node;
483 }
484
485 ret = device_get_phy_mode(&pdev->dev);
486 if (ret < 0) {
487 dev_err(&pdev->dev, "phy_mode not found\n");
488 ret = -ENODEV;
489 goto err_put_node;
490 }
491
492 plat->phy_interface = ret;
493
494 return 0;
495
496 err_put_node:
497 of_node_put(plat->mdio_node);
498
499 return ret;
500 }
501
loongson_dwmac_dt_clear(struct pci_dev * pdev,struct plat_stmmacenet_data * plat)502 static void loongson_dwmac_dt_clear(struct pci_dev *pdev,
503 struct plat_stmmacenet_data *plat)
504 {
505 of_node_put(plat->mdio_node);
506 }
507
loongson_dwmac_acpi_config(struct pci_dev * pdev,struct plat_stmmacenet_data * plat,struct stmmac_resources * res)508 static int loongson_dwmac_acpi_config(struct pci_dev *pdev,
509 struct plat_stmmacenet_data *plat,
510 struct stmmac_resources *res)
511 {
512 if (!pdev->irq)
513 return -EINVAL;
514
515 res->irq = pdev->irq;
516
517 return 0;
518 }
519
520 /* Loongson's DWMAC device may take nearly two seconds to complete DMA reset */
loongson_dwmac_fix_reset(void * priv,void __iomem * ioaddr)521 static int loongson_dwmac_fix_reset(void *priv, void __iomem *ioaddr)
522 {
523 u32 value = readl(ioaddr + DMA_BUS_MODE);
524
525 value |= DMA_BUS_MODE_SFT_RESET;
526 writel(value, ioaddr + DMA_BUS_MODE);
527
528 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
529 !(value & DMA_BUS_MODE_SFT_RESET),
530 10000, 2000000);
531 }
532
loongson_dwmac_probe(struct pci_dev * pdev,const struct pci_device_id * id)533 static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id *id)
534 {
535 struct plat_stmmacenet_data *plat;
536 struct stmmac_resources res = {};
537 struct stmmac_pci_info *info;
538 struct loongson_data *ld;
539 int ret;
540
541 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
542 if (!plat)
543 return -ENOMEM;
544
545 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
546 sizeof(*plat->mdio_bus_data),
547 GFP_KERNEL);
548 if (!plat->mdio_bus_data)
549 return -ENOMEM;
550
551 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
552 if (!plat->dma_cfg)
553 return -ENOMEM;
554
555 ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL);
556 if (!ld)
557 return -ENOMEM;
558
559 /* Enable pci device */
560 ret = pci_enable_device(pdev);
561 if (ret) {
562 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", __func__);
563 return ret;
564 }
565
566 pci_set_master(pdev);
567
568 /* Get the base address of device */
569 res.addr = pcim_iomap_region(pdev, 0, DRIVER_NAME);
570 ret = PTR_ERR_OR_ZERO(res.addr);
571 if (ret)
572 goto err_disable_device;
573
574 plat->bsp_priv = ld;
575 plat->setup = loongson_dwmac_setup;
576 plat->fix_soc_reset = loongson_dwmac_fix_reset;
577 ld->dev = &pdev->dev;
578 ld->loongson_id = readl(res.addr + GMAC_VERSION) & 0xff;
579
580 info = (struct stmmac_pci_info *)id->driver_data;
581 ret = info->setup(pdev, plat);
582 if (ret)
583 goto err_disable_device;
584
585 plat->tx_fifo_size = SZ_16K * plat->tx_queues_to_use;
586 plat->rx_fifo_size = SZ_16K * plat->rx_queues_to_use;
587
588 if (dev_of_node(&pdev->dev))
589 ret = loongson_dwmac_dt_config(pdev, plat, &res);
590 else
591 ret = loongson_dwmac_acpi_config(pdev, plat, &res);
592 if (ret)
593 goto err_disable_device;
594
595 /* Use the common MAC IRQ if per-channel MSIs allocation failed */
596 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN)
597 loongson_dwmac_msi_config(pdev, plat, &res);
598
599 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
600 if (ret)
601 goto err_plat_clear;
602
603 return 0;
604
605 err_plat_clear:
606 if (dev_of_node(&pdev->dev))
607 loongson_dwmac_dt_clear(pdev, plat);
608 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN)
609 loongson_dwmac_msi_clear(pdev);
610 err_disable_device:
611 pci_disable_device(pdev);
612 return ret;
613 }
614
loongson_dwmac_remove(struct pci_dev * pdev)615 static void loongson_dwmac_remove(struct pci_dev *pdev)
616 {
617 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
618 struct stmmac_priv *priv = netdev_priv(ndev);
619 struct loongson_data *ld;
620
621 ld = priv->plat->bsp_priv;
622 stmmac_dvr_remove(&pdev->dev);
623
624 if (dev_of_node(&pdev->dev))
625 loongson_dwmac_dt_clear(pdev, priv->plat);
626
627 if (ld->loongson_id == DWMAC_CORE_LS_MULTICHAN)
628 loongson_dwmac_msi_clear(pdev);
629
630 pci_disable_device(pdev);
631 }
632
loongson_dwmac_suspend(struct device * dev)633 static int __maybe_unused loongson_dwmac_suspend(struct device *dev)
634 {
635 struct pci_dev *pdev = to_pci_dev(dev);
636 int ret;
637
638 ret = stmmac_suspend(dev);
639 if (ret)
640 return ret;
641
642 ret = pci_save_state(pdev);
643 if (ret)
644 return ret;
645
646 pci_disable_device(pdev);
647 pci_wake_from_d3(pdev, true);
648 return 0;
649 }
650
loongson_dwmac_resume(struct device * dev)651 static int __maybe_unused loongson_dwmac_resume(struct device *dev)
652 {
653 struct pci_dev *pdev = to_pci_dev(dev);
654 int ret;
655
656 pci_restore_state(pdev);
657 pci_set_power_state(pdev, PCI_D0);
658
659 ret = pci_enable_device(pdev);
660 if (ret)
661 return ret;
662
663 pci_set_master(pdev);
664
665 return stmmac_resume(dev);
666 }
667
668 static SIMPLE_DEV_PM_OPS(loongson_dwmac_pm_ops, loongson_dwmac_suspend,
669 loongson_dwmac_resume);
670
671 static const struct pci_device_id loongson_dwmac_id_table[] = {
672 { PCI_DEVICE_DATA(LOONGSON, GMAC, &loongson_gmac_pci_info) },
673 { PCI_DEVICE_DATA(LOONGSON, GNET, &loongson_gnet_pci_info) },
674 {}
675 };
676 MODULE_DEVICE_TABLE(pci, loongson_dwmac_id_table);
677
678 static struct pci_driver loongson_dwmac_driver = {
679 .name = DRIVER_NAME,
680 .id_table = loongson_dwmac_id_table,
681 .probe = loongson_dwmac_probe,
682 .remove = loongson_dwmac_remove,
683 .driver = {
684 .pm = &loongson_dwmac_pm_ops,
685 },
686 };
687
688 module_pci_driver(loongson_dwmac_driver);
689
690 MODULE_DESCRIPTION("Loongson DWMAC PCI driver");
691 MODULE_AUTHOR("Qing Zhang <zhangqing@loongson.cn>");
692 MODULE_AUTHOR("Yanteng Si <siyanteng@loongson.cn>");
693 MODULE_LICENSE("GPL v2");
694