1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #include <linux/of.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_address.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/if_vlan.h>
19 #include <linux/reset.h>
20 #include <linux/tcp.h>
21 #include <linux/interrupt.h>
22 #include <linux/pinctrl/devinfo.h>
23 #include <linux/phylink.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
25 #include <linux/jhash.h>
26 #include <linux/bitfield.h>
27 #include <net/dsa.h>
28 #include <net/dst_metadata.h>
29 #include <net/page_pool/helpers.h>
30
31 #include "mtk_eth_soc.h"
32 #include "mtk_wed.h"
33
34 static int mtk_msg_level = -1;
35 module_param_named(msg_level, mtk_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define MTK_ETHTOOL_STAT(x) { #x, \
39 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
40
41 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \
42 offsetof(struct mtk_hw_stats, xdp_stats.x) / \
43 sizeof(u64) }
44
45 static const struct mtk_reg_map mtk_reg_map = {
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
48 .pdma = {
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
57 .adma_rx_dbg0 = 0x0a38,
58 .int_grp = 0x0a50,
59 },
60 .qdma = {
61 .qtx_cfg = 0x1800,
62 .qtx_sch = 0x1804,
63 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
70 .tx_sch_rate = 0x1a14,
71 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
81 },
82 .gdm1_cnt = 0x2400,
83 .gdma_to_ppe = {
84 [0] = 0x4444,
85 },
86 .ppe_base = 0x0c00,
87 .wdma_base = {
88 [0] = 0x2800,
89 [1] = 0x2c00,
90 },
91 .pse_iq_sta = 0x0110,
92 .pse_oq_sta = 0x0118,
93 };
94
95 static const struct mtk_reg_map mt7628_reg_map = {
96 .tx_irq_mask = 0x0a28,
97 .tx_irq_status = 0x0a20,
98 .pdma = {
99 .rx_ptr = 0x0900,
100 .rx_cnt_cfg = 0x0904,
101 .pcrx_ptr = 0x0908,
102 .glo_cfg = 0x0a04,
103 .rst_idx = 0x0a08,
104 .delay_irq = 0x0a0c,
105 .irq_status = 0x0a20,
106 .irq_mask = 0x0a28,
107 .int_grp = 0x0a50,
108 },
109 };
110
111 static const struct mtk_reg_map mt7986_reg_map = {
112 .tx_irq_mask = 0x461c,
113 .tx_irq_status = 0x4618,
114 .pdma = {
115 .rx_ptr = 0x4100,
116 .rx_cnt_cfg = 0x4104,
117 .pcrx_ptr = 0x4108,
118 .glo_cfg = 0x4204,
119 .rst_idx = 0x4208,
120 .delay_irq = 0x420c,
121 .irq_status = 0x4220,
122 .irq_mask = 0x4228,
123 .adma_rx_dbg0 = 0x4238,
124 .int_grp = 0x4250,
125 },
126 .qdma = {
127 .qtx_cfg = 0x4400,
128 .qtx_sch = 0x4404,
129 .rx_ptr = 0x4500,
130 .rx_cnt_cfg = 0x4504,
131 .qcrx_ptr = 0x4508,
132 .glo_cfg = 0x4604,
133 .rst_idx = 0x4608,
134 .delay_irq = 0x460c,
135 .fc_th = 0x4610,
136 .int_grp = 0x4620,
137 .hred = 0x4644,
138 .ctx_ptr = 0x4700,
139 .dtx_ptr = 0x4704,
140 .crx_ptr = 0x4710,
141 .drx_ptr = 0x4714,
142 .fq_head = 0x4720,
143 .fq_tail = 0x4724,
144 .fq_count = 0x4728,
145 .fq_blen = 0x472c,
146 .tx_sch_rate = 0x4798,
147 },
148 .gdm1_cnt = 0x1c00,
149 .gdma_to_ppe = {
150 [0] = 0x3333,
151 [1] = 0x4444,
152 },
153 .ppe_base = 0x2000,
154 .wdma_base = {
155 [0] = 0x4800,
156 [1] = 0x4c00,
157 },
158 .pse_iq_sta = 0x0180,
159 .pse_oq_sta = 0x01a0,
160 };
161
162 static const struct mtk_reg_map mt7988_reg_map = {
163 .tx_irq_mask = 0x461c,
164 .tx_irq_status = 0x4618,
165 .pdma = {
166 .rx_ptr = 0x6900,
167 .rx_cnt_cfg = 0x6904,
168 .pcrx_ptr = 0x6908,
169 .glo_cfg = 0x6a04,
170 .rst_idx = 0x6a08,
171 .delay_irq = 0x6a0c,
172 .irq_status = 0x6a20,
173 .irq_mask = 0x6a28,
174 .adma_rx_dbg0 = 0x6a38,
175 .int_grp = 0x6a50,
176 },
177 .qdma = {
178 .qtx_cfg = 0x4400,
179 .qtx_sch = 0x4404,
180 .rx_ptr = 0x4500,
181 .rx_cnt_cfg = 0x4504,
182 .qcrx_ptr = 0x4508,
183 .glo_cfg = 0x4604,
184 .rst_idx = 0x4608,
185 .delay_irq = 0x460c,
186 .fc_th = 0x4610,
187 .int_grp = 0x4620,
188 .hred = 0x4644,
189 .ctx_ptr = 0x4700,
190 .dtx_ptr = 0x4704,
191 .crx_ptr = 0x4710,
192 .drx_ptr = 0x4714,
193 .fq_head = 0x4720,
194 .fq_tail = 0x4724,
195 .fq_count = 0x4728,
196 .fq_blen = 0x472c,
197 .tx_sch_rate = 0x4798,
198 },
199 .gdm1_cnt = 0x1c00,
200 .gdma_to_ppe = {
201 [0] = 0x3333,
202 [1] = 0x4444,
203 [2] = 0xcccc,
204 },
205 .ppe_base = 0x2000,
206 .wdma_base = {
207 [0] = 0x4800,
208 [1] = 0x4c00,
209 [2] = 0x5000,
210 },
211 .pse_iq_sta = 0x0180,
212 .pse_oq_sta = 0x01a0,
213 };
214
215 /* strings used by ethtool */
216 static const struct mtk_ethtool_stats {
217 char str[ETH_GSTRING_LEN];
218 u32 offset;
219 } mtk_ethtool_stats[] = {
220 MTK_ETHTOOL_STAT(tx_bytes),
221 MTK_ETHTOOL_STAT(tx_packets),
222 MTK_ETHTOOL_STAT(tx_skip),
223 MTK_ETHTOOL_STAT(tx_collisions),
224 MTK_ETHTOOL_STAT(rx_bytes),
225 MTK_ETHTOOL_STAT(rx_packets),
226 MTK_ETHTOOL_STAT(rx_overflow),
227 MTK_ETHTOOL_STAT(rx_fcs_errors),
228 MTK_ETHTOOL_STAT(rx_short_errors),
229 MTK_ETHTOOL_STAT(rx_long_errors),
230 MTK_ETHTOOL_STAT(rx_checksum_errors),
231 MTK_ETHTOOL_STAT(rx_flow_control_packets),
232 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect),
233 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass),
234 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop),
235 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx),
236 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors),
237 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit),
238 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors),
239 };
240
241 static const char * const mtk_clks_source_name[] = {
242 "ethif",
243 "sgmiitop",
244 "esw",
245 "gp0",
246 "gp1",
247 "gp2",
248 "gp3",
249 "xgp1",
250 "xgp2",
251 "xgp3",
252 "crypto",
253 "fe",
254 "trgpll",
255 "sgmii_tx250m",
256 "sgmii_rx250m",
257 "sgmii_cdr_ref",
258 "sgmii_cdr_fb",
259 "sgmii2_tx250m",
260 "sgmii2_rx250m",
261 "sgmii2_cdr_ref",
262 "sgmii2_cdr_fb",
263 "sgmii_ck",
264 "eth2pll",
265 "wocpu0",
266 "wocpu1",
267 "netsys0",
268 "netsys1",
269 "ethwarp_wocpu2",
270 "ethwarp_wocpu1",
271 "ethwarp_wocpu0",
272 "top_sgm0_sel",
273 "top_sgm1_sel",
274 "top_eth_gmii_sel",
275 "top_eth_refck_50m_sel",
276 "top_eth_sys_200m_sel",
277 "top_eth_sys_sel",
278 "top_eth_xgmii_sel",
279 "top_eth_mii_sel",
280 "top_netsys_sel",
281 "top_netsys_500m_sel",
282 "top_netsys_pao_2x_sel",
283 "top_netsys_sync_250m_sel",
284 "top_netsys_ppefb_250m_sel",
285 "top_netsys_warp_sel",
286 };
287
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)288 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
289 {
290 __raw_writel(val, eth->base + reg);
291 }
292
mtk_r32(struct mtk_eth * eth,unsigned reg)293 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
294 {
295 return __raw_readl(eth->base + reg);
296 }
297
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned int reg)298 u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
299 {
300 u32 val;
301
302 val = mtk_r32(eth, reg);
303 val &= ~mask;
304 val |= set;
305 mtk_w32(eth, val, reg);
306 return reg;
307 }
308
mtk_mdio_busy_wait(struct mtk_eth * eth)309 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
310 {
311 unsigned long t_start = jiffies;
312
313 while (1) {
314 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
315 return 0;
316 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
317 break;
318 cond_resched();
319 }
320
321 dev_err(eth->dev, "mdio: MDIO timeout\n");
322 return -ETIMEDOUT;
323 }
324
_mtk_mdio_write_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg,u32 write_data)325 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
326 u32 write_data)
327 {
328 int ret;
329
330 ret = mtk_mdio_busy_wait(eth);
331 if (ret < 0)
332 return ret;
333
334 mtk_w32(eth, PHY_IAC_ACCESS |
335 PHY_IAC_START_C22 |
336 PHY_IAC_CMD_WRITE |
337 PHY_IAC_REG(phy_reg) |
338 PHY_IAC_ADDR(phy_addr) |
339 PHY_IAC_DATA(write_data),
340 MTK_PHY_IAC);
341
342 ret = mtk_mdio_busy_wait(eth);
343 if (ret < 0)
344 return ret;
345
346 return 0;
347 }
348
_mtk_mdio_write_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg,u32 write_data)349 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
350 u32 devad, u32 phy_reg, u32 write_data)
351 {
352 int ret;
353
354 ret = mtk_mdio_busy_wait(eth);
355 if (ret < 0)
356 return ret;
357
358 mtk_w32(eth, PHY_IAC_ACCESS |
359 PHY_IAC_START_C45 |
360 PHY_IAC_CMD_C45_ADDR |
361 PHY_IAC_REG(devad) |
362 PHY_IAC_ADDR(phy_addr) |
363 PHY_IAC_DATA(phy_reg),
364 MTK_PHY_IAC);
365
366 ret = mtk_mdio_busy_wait(eth);
367 if (ret < 0)
368 return ret;
369
370 mtk_w32(eth, PHY_IAC_ACCESS |
371 PHY_IAC_START_C45 |
372 PHY_IAC_CMD_WRITE |
373 PHY_IAC_REG(devad) |
374 PHY_IAC_ADDR(phy_addr) |
375 PHY_IAC_DATA(write_data),
376 MTK_PHY_IAC);
377
378 ret = mtk_mdio_busy_wait(eth);
379 if (ret < 0)
380 return ret;
381
382 return 0;
383 }
384
_mtk_mdio_read_c22(struct mtk_eth * eth,u32 phy_addr,u32 phy_reg)385 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
386 {
387 int ret;
388
389 ret = mtk_mdio_busy_wait(eth);
390 if (ret < 0)
391 return ret;
392
393 mtk_w32(eth, PHY_IAC_ACCESS |
394 PHY_IAC_START_C22 |
395 PHY_IAC_CMD_C22_READ |
396 PHY_IAC_REG(phy_reg) |
397 PHY_IAC_ADDR(phy_addr),
398 MTK_PHY_IAC);
399
400 ret = mtk_mdio_busy_wait(eth);
401 if (ret < 0)
402 return ret;
403
404 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
405 }
406
_mtk_mdio_read_c45(struct mtk_eth * eth,u32 phy_addr,u32 devad,u32 phy_reg)407 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
408 u32 devad, u32 phy_reg)
409 {
410 int ret;
411
412 ret = mtk_mdio_busy_wait(eth);
413 if (ret < 0)
414 return ret;
415
416 mtk_w32(eth, PHY_IAC_ACCESS |
417 PHY_IAC_START_C45 |
418 PHY_IAC_CMD_C45_ADDR |
419 PHY_IAC_REG(devad) |
420 PHY_IAC_ADDR(phy_addr) |
421 PHY_IAC_DATA(phy_reg),
422 MTK_PHY_IAC);
423
424 ret = mtk_mdio_busy_wait(eth);
425 if (ret < 0)
426 return ret;
427
428 mtk_w32(eth, PHY_IAC_ACCESS |
429 PHY_IAC_START_C45 |
430 PHY_IAC_CMD_C45_READ |
431 PHY_IAC_REG(devad) |
432 PHY_IAC_ADDR(phy_addr),
433 MTK_PHY_IAC);
434
435 ret = mtk_mdio_busy_wait(eth);
436 if (ret < 0)
437 return ret;
438
439 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
440 }
441
mtk_mdio_write_c22(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)442 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr,
443 int phy_reg, u16 val)
444 {
445 struct mtk_eth *eth = bus->priv;
446
447 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val);
448 }
449
mtk_mdio_write_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg,u16 val)450 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr,
451 int devad, int phy_reg, u16 val)
452 {
453 struct mtk_eth *eth = bus->priv;
454
455 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val);
456 }
457
mtk_mdio_read_c22(struct mii_bus * bus,int phy_addr,int phy_reg)458 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg)
459 {
460 struct mtk_eth *eth = bus->priv;
461
462 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg);
463 }
464
mtk_mdio_read_c45(struct mii_bus * bus,int phy_addr,int devad,int phy_reg)465 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad,
466 int phy_reg)
467 {
468 struct mtk_eth *eth = bus->priv;
469
470 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg);
471 }
472
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)473 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
474 phy_interface_t interface)
475 {
476 u32 val;
477
478 val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
479 ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
480
481 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
482 ETHSYS_TRGMII_MT7621_MASK, val);
483
484 return 0;
485 }
486
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)487 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
488 phy_interface_t interface)
489 {
490 int ret;
491
492 if (interface == PHY_INTERFACE_MODE_TRGMII) {
493 mtk_w32(eth, TRGMII_MODE, INTF_MODE);
494 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000);
495 if (ret)
496 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
497 return;
498 }
499
500 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
501 }
502
mtk_setup_bridge_switch(struct mtk_eth * eth)503 static void mtk_setup_bridge_switch(struct mtk_eth *eth)
504 {
505 /* Force Port1 XGMAC Link Up */
506 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
507 MTK_XGMAC_STS(MTK_GMAC1_ID));
508
509 /* Adjust GSW bridge IPG to 11 */
510 mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
511 (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
512 (GSW_IPG_11 << GSWRX_IPG_SHIFT),
513 MTK_GSW_CFG);
514 }
515
mtk_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)516 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
517 phy_interface_t interface)
518 {
519 struct mtk_mac *mac = container_of(config, struct mtk_mac,
520 phylink_config);
521 struct mtk_eth *eth = mac->hw;
522 unsigned int sid;
523
524 if (interface == PHY_INTERFACE_MODE_SGMII ||
525 phy_interface_mode_is_8023z(interface)) {
526 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
527 0 : mac->id;
528
529 return eth->sgmii_pcs[sid];
530 }
531
532 return NULL;
533 }
534
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)535 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
536 const struct phylink_link_state *state)
537 {
538 struct mtk_mac *mac = container_of(config, struct mtk_mac,
539 phylink_config);
540 struct mtk_eth *eth = mac->hw;
541 int val, ge_mode, err = 0;
542 u32 i;
543
544 /* MT76x8 has no hardware settings between for the MAC */
545 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
546 mac->interface != state->interface) {
547 /* Setup soc pin functions */
548 switch (state->interface) {
549 case PHY_INTERFACE_MODE_TRGMII:
550 case PHY_INTERFACE_MODE_RGMII_TXID:
551 case PHY_INTERFACE_MODE_RGMII_RXID:
552 case PHY_INTERFACE_MODE_RGMII_ID:
553 case PHY_INTERFACE_MODE_RGMII:
554 case PHY_INTERFACE_MODE_MII:
555 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
556 err = mtk_gmac_rgmii_path_setup(eth, mac->id);
557 if (err)
558 goto init_err;
559 }
560 break;
561 case PHY_INTERFACE_MODE_1000BASEX:
562 case PHY_INTERFACE_MODE_2500BASEX:
563 case PHY_INTERFACE_MODE_SGMII:
564 err = mtk_gmac_sgmii_path_setup(eth, mac->id);
565 if (err)
566 goto init_err;
567 break;
568 case PHY_INTERFACE_MODE_GMII:
569 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
570 err = mtk_gmac_gephy_path_setup(eth, mac->id);
571 if (err)
572 goto init_err;
573 }
574 break;
575 case PHY_INTERFACE_MODE_INTERNAL:
576 break;
577 default:
578 goto err_phy;
579 }
580
581 /* Setup clock for 1st gmac */
582 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
583 !phy_interface_mode_is_8023z(state->interface) &&
584 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
585 if (MTK_HAS_CAPS(mac->hw->soc->caps,
586 MTK_TRGMII_MT7621_CLK)) {
587 if (mt7621_gmac0_rgmii_adjust(mac->hw,
588 state->interface))
589 goto err_phy;
590 } else {
591 mtk_gmac0_rgmii_adjust(mac->hw,
592 state->interface);
593
594 /* mt7623_pad_clk_setup */
595 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
596 mtk_w32(mac->hw,
597 TD_DM_DRVP(8) | TD_DM_DRVN(8),
598 TRGMII_TD_ODT(i));
599
600 /* Assert/release MT7623 RXC reset */
601 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
602 TRGMII_RCK_CTRL);
603 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
604 }
605 }
606
607 switch (state->interface) {
608 case PHY_INTERFACE_MODE_MII:
609 case PHY_INTERFACE_MODE_GMII:
610 ge_mode = 1;
611 break;
612 default:
613 ge_mode = 0;
614 break;
615 }
616
617 /* put the gmac into the right mode */
618 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
619 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
620 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
621 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
622
623 mac->interface = state->interface;
624 }
625
626 /* SGMII */
627 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
628 phy_interface_mode_is_8023z(state->interface)) {
629 /* The path GMAC to SGMII will be enabled once the SGMIISYS is
630 * being setup done.
631 */
632 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
633
634 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
635 SYSCFG0_SGMII_MASK,
636 ~(u32)SYSCFG0_SGMII_MASK);
637
638 /* Save the syscfg0 value for mac_finish */
639 mac->syscfg0 = val;
640 } else if (phylink_autoneg_inband(mode)) {
641 dev_err(eth->dev,
642 "In-band mode not supported in non SGMII mode!\n");
643 return;
644 }
645
646 /* Setup gmac */
647 if (mtk_is_netsys_v3_or_greater(eth) &&
648 mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
649 mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
650 mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
651
652 mtk_setup_bridge_switch(eth);
653 }
654
655 return;
656
657 err_phy:
658 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
659 mac->id, phy_modes(state->interface));
660 return;
661
662 init_err:
663 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
664 mac->id, phy_modes(state->interface), err);
665 }
666
mtk_mac_finish(struct phylink_config * config,unsigned int mode,phy_interface_t interface)667 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
668 phy_interface_t interface)
669 {
670 struct mtk_mac *mac = container_of(config, struct mtk_mac,
671 phylink_config);
672 struct mtk_eth *eth = mac->hw;
673 u32 mcr_cur, mcr_new;
674
675 /* Enable SGMII */
676 if (interface == PHY_INTERFACE_MODE_SGMII ||
677 phy_interface_mode_is_8023z(interface))
678 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
679 SYSCFG0_SGMII_MASK, mac->syscfg0);
680
681 /* Setup gmac */
682 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
683 mcr_new = mcr_cur;
684 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
685 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_RX_FIFO_CLR_DIS;
686
687 /* Only update control register when needed! */
688 if (mcr_new != mcr_cur)
689 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
690
691 return 0;
692 }
693
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)694 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
695 phy_interface_t interface)
696 {
697 struct mtk_mac *mac = container_of(config, struct mtk_mac,
698 phylink_config);
699 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
700
701 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
702 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
703 }
704
mtk_set_queue_speed(struct mtk_eth * eth,unsigned int idx,int speed)705 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
706 int speed)
707 {
708 const struct mtk_soc_data *soc = eth->soc;
709 u32 ofs, val;
710
711 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
712 return;
713
714 val = MTK_QTX_SCH_MIN_RATE_EN |
715 /* minimum: 10 Mbps */
716 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
717 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
718 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
719 if (mtk_is_netsys_v1(eth))
720 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
721
722 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
723 switch (speed) {
724 case SPEED_10:
725 val |= MTK_QTX_SCH_MAX_RATE_EN |
726 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
727 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) |
728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
729 break;
730 case SPEED_100:
731 val |= MTK_QTX_SCH_MAX_RATE_EN |
732 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) |
733 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3) |
734 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
735 break;
736 case SPEED_1000:
737 val |= MTK_QTX_SCH_MAX_RATE_EN |
738 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) |
739 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
740 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
741 break;
742 default:
743 break;
744 }
745 } else {
746 switch (speed) {
747 case SPEED_10:
748 val |= MTK_QTX_SCH_MAX_RATE_EN |
749 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
750 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) |
751 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
752 break;
753 case SPEED_100:
754 val |= MTK_QTX_SCH_MAX_RATE_EN |
755 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
756 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) |
757 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1);
758 break;
759 case SPEED_1000:
760 val |= MTK_QTX_SCH_MAX_RATE_EN |
761 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) |
762 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 6) |
763 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10);
764 break;
765 default:
766 break;
767 }
768 }
769
770 ofs = MTK_QTX_OFFSET * idx;
771 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
772 }
773
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)774 static void mtk_mac_link_up(struct phylink_config *config,
775 struct phy_device *phy,
776 unsigned int mode, phy_interface_t interface,
777 int speed, int duplex, bool tx_pause, bool rx_pause)
778 {
779 struct mtk_mac *mac = container_of(config, struct mtk_mac,
780 phylink_config);
781 u32 mcr;
782
783 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
784 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
785 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
786 MAC_MCR_FORCE_RX_FC);
787
788 /* Configure speed */
789 mac->speed = speed;
790 switch (speed) {
791 case SPEED_2500:
792 case SPEED_1000:
793 mcr |= MAC_MCR_SPEED_1000;
794 break;
795 case SPEED_100:
796 mcr |= MAC_MCR_SPEED_100;
797 break;
798 }
799
800 /* Configure duplex */
801 if (duplex == DUPLEX_FULL)
802 mcr |= MAC_MCR_FORCE_DPX;
803
804 /* Configure pause modes - phylink will avoid these for half duplex */
805 if (tx_pause)
806 mcr |= MAC_MCR_FORCE_TX_FC;
807 if (rx_pause)
808 mcr |= MAC_MCR_FORCE_RX_FC;
809
810 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK;
811 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
812 }
813
mtk_mac_disable_tx_lpi(struct phylink_config * config)814 static void mtk_mac_disable_tx_lpi(struct phylink_config *config)
815 {
816 struct mtk_mac *mac = container_of(config, struct mtk_mac,
817 phylink_config);
818 struct mtk_eth *eth = mac->hw;
819
820 mtk_m32(eth, MAC_MCR_EEE100M | MAC_MCR_EEE1G, 0, MTK_MAC_MCR(mac->id));
821 }
822
mtk_mac_enable_tx_lpi(struct phylink_config * config,u32 timer,bool tx_clk_stop)823 static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,
824 bool tx_clk_stop)
825 {
826 struct mtk_mac *mac = container_of(config, struct mtk_mac,
827 phylink_config);
828 struct mtk_eth *eth = mac->hw;
829 u32 val;
830
831 /* Tx idle timer in ms */
832 timer = DIV_ROUND_UP(timer, 1000);
833
834 /* If the timer is zero, then set LPI_MODE, which allows the
835 * system to enter LPI mode immediately rather than waiting for
836 * the LPI threshold.
837 */
838 if (!timer)
839 val = MAC_EEE_LPI_MODE;
840 else if (FIELD_FIT(MAC_EEE_LPI_TXIDLE_THD, timer))
841 val = FIELD_PREP(MAC_EEE_LPI_TXIDLE_THD, timer);
842 else
843 val = MAC_EEE_LPI_TXIDLE_THD;
844
845 if (tx_clk_stop)
846 val |= MAC_EEE_CKG_TXIDLE;
847
848 /* PHY Wake-up time, this field does not have a reset value, so use the
849 * reset value from MT7531 (36us for 100M and 17us for 1000M).
850 */
851 val |= FIELD_PREP(MAC_EEE_WAKEUP_TIME_1000, 17) |
852 FIELD_PREP(MAC_EEE_WAKEUP_TIME_100, 36);
853
854 mtk_w32(eth, val, MTK_MAC_EEECR(mac->id));
855 mtk_m32(eth, 0, MAC_MCR_EEE100M | MAC_MCR_EEE1G, MTK_MAC_MCR(mac->id));
856
857 return 0;
858 }
859
860 static const struct phylink_mac_ops mtk_phylink_ops = {
861 .mac_select_pcs = mtk_mac_select_pcs,
862 .mac_config = mtk_mac_config,
863 .mac_finish = mtk_mac_finish,
864 .mac_link_down = mtk_mac_link_down,
865 .mac_link_up = mtk_mac_link_up,
866 .mac_disable_tx_lpi = mtk_mac_disable_tx_lpi,
867 .mac_enable_tx_lpi = mtk_mac_enable_tx_lpi,
868 };
869
mtk_mdio_config(struct mtk_eth * eth)870 static void mtk_mdio_config(struct mtk_eth *eth)
871 {
872 u32 val;
873
874 /* Configure MDC Divider */
875 val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider);
876
877 /* Configure MDC Turbo Mode */
878 if (mtk_is_netsys_v3_or_greater(eth))
879 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
880 else
881 val |= PPSC_MDC_TURBO;
882
883 mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
884 }
885
mtk_mdio_init(struct mtk_eth * eth)886 static int mtk_mdio_init(struct mtk_eth *eth)
887 {
888 unsigned int max_clk = 2500000;
889 struct device_node *mii_np;
890 int ret;
891 u32 val;
892
893 mii_np = of_get_available_child_by_name(eth->dev->of_node, "mdio-bus");
894 if (!mii_np) {
895 dev_err(eth->dev, "no %s child node found", "mdio-bus");
896 return -ENODEV;
897 }
898
899 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
900 if (!eth->mii_bus) {
901 ret = -ENOMEM;
902 goto err_put_node;
903 }
904
905 eth->mii_bus->name = "mdio";
906 eth->mii_bus->read = mtk_mdio_read_c22;
907 eth->mii_bus->write = mtk_mdio_write_c22;
908 eth->mii_bus->read_c45 = mtk_mdio_read_c45;
909 eth->mii_bus->write_c45 = mtk_mdio_write_c45;
910 eth->mii_bus->priv = eth;
911 eth->mii_bus->parent = eth->dev;
912
913 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
914
915 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) {
916 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) {
917 dev_err(eth->dev, "MDIO clock frequency out of range");
918 ret = -EINVAL;
919 goto err_put_node;
920 }
921 max_clk = val;
922 }
923 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
924 mtk_mdio_config(eth);
925 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider);
926 ret = of_mdiobus_register(eth->mii_bus, mii_np);
927
928 err_put_node:
929 of_node_put(mii_np);
930 return ret;
931 }
932
mtk_mdio_cleanup(struct mtk_eth * eth)933 static void mtk_mdio_cleanup(struct mtk_eth *eth)
934 {
935 if (!eth->mii_bus)
936 return;
937
938 mdiobus_unregister(eth->mii_bus);
939 }
940
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)941 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
942 {
943 unsigned long flags;
944 u32 val;
945
946 spin_lock_irqsave(ð->tx_irq_lock, flags);
947 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
948 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);
949 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
950 }
951
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)952 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
953 {
954 unsigned long flags;
955 u32 val;
956
957 spin_lock_irqsave(ð->tx_irq_lock, flags);
958 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);
959 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);
960 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
961 }
962
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)963 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
964 {
965 unsigned long flags;
966 u32 val;
967
968 spin_lock_irqsave(ð->rx_irq_lock, flags);
969 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
970 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);
971 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
972 }
973
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)974 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
975 {
976 unsigned long flags;
977 u32 val;
978
979 spin_lock_irqsave(ð->rx_irq_lock, flags);
980 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);
981 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);
982 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
983 }
984
mtk_set_mac_address(struct net_device * dev,void * p)985 static int mtk_set_mac_address(struct net_device *dev, void *p)
986 {
987 int ret = eth_mac_addr(dev, p);
988 struct mtk_mac *mac = netdev_priv(dev);
989 struct mtk_eth *eth = mac->hw;
990 const char *macaddr = dev->dev_addr;
991
992 if (ret)
993 return ret;
994
995 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
996 return -EBUSY;
997
998 spin_lock_bh(&mac->hw->page_lock);
999 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1000 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
1001 MT7628_SDM_MAC_ADRH);
1002 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
1003 (macaddr[4] << 8) | macaddr[5],
1004 MT7628_SDM_MAC_ADRL);
1005 } else {
1006 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
1007 MTK_GDMA_MAC_ADRH(mac->id));
1008 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
1009 (macaddr[4] << 8) | macaddr[5],
1010 MTK_GDMA_MAC_ADRL(mac->id));
1011 }
1012 spin_unlock_bh(&mac->hw->page_lock);
1013
1014 return 0;
1015 }
1016
mtk_stats_update_mac(struct mtk_mac * mac)1017 void mtk_stats_update_mac(struct mtk_mac *mac)
1018 {
1019 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1020 struct mtk_eth *eth = mac->hw;
1021
1022 u64_stats_update_begin(&hw_stats->syncp);
1023
1024 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1025 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
1026 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
1027 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
1028 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
1029 hw_stats->rx_checksum_errors +=
1030 mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
1031 } else {
1032 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
1033 unsigned int offs = hw_stats->reg_offset;
1034 u64 stats;
1035
1036 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);
1037 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);
1038 if (stats)
1039 hw_stats->rx_bytes += (stats << 32);
1040 hw_stats->rx_packets +=
1041 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);
1042 hw_stats->rx_overflow +=
1043 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);
1044 hw_stats->rx_fcs_errors +=
1045 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);
1046 hw_stats->rx_short_errors +=
1047 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);
1048 hw_stats->rx_long_errors +=
1049 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);
1050 hw_stats->rx_checksum_errors +=
1051 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
1052 hw_stats->rx_flow_control_packets +=
1053 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
1054
1055 if (mtk_is_netsys_v3_or_greater(eth)) {
1056 hw_stats->tx_skip +=
1057 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);
1058 hw_stats->tx_collisions +=
1059 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);
1060 hw_stats->tx_bytes +=
1061 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);
1062 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);
1063 if (stats)
1064 hw_stats->tx_bytes += (stats << 32);
1065 hw_stats->tx_packets +=
1066 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);
1067 } else {
1068 hw_stats->tx_skip +=
1069 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);
1070 hw_stats->tx_collisions +=
1071 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);
1072 hw_stats->tx_bytes +=
1073 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);
1074 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);
1075 if (stats)
1076 hw_stats->tx_bytes += (stats << 32);
1077 hw_stats->tx_packets +=
1078 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);
1079 }
1080 }
1081
1082 u64_stats_update_end(&hw_stats->syncp);
1083 }
1084
mtk_stats_update(struct mtk_eth * eth)1085 static void mtk_stats_update(struct mtk_eth *eth)
1086 {
1087 int i;
1088
1089 for (i = 0; i < MTK_MAX_DEVS; i++) {
1090 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
1091 continue;
1092 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
1093 mtk_stats_update_mac(eth->mac[i]);
1094 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
1095 }
1096 }
1097 }
1098
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)1099 static void mtk_get_stats64(struct net_device *dev,
1100 struct rtnl_link_stats64 *storage)
1101 {
1102 struct mtk_mac *mac = netdev_priv(dev);
1103 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1104 unsigned int start;
1105
1106 if (netif_running(dev) && netif_device_present(dev)) {
1107 if (spin_trylock_bh(&hw_stats->stats_lock)) {
1108 mtk_stats_update_mac(mac);
1109 spin_unlock_bh(&hw_stats->stats_lock);
1110 }
1111 }
1112
1113 do {
1114 start = u64_stats_fetch_begin(&hw_stats->syncp);
1115 storage->rx_packets = hw_stats->rx_packets;
1116 storage->tx_packets = hw_stats->tx_packets;
1117 storage->rx_bytes = hw_stats->rx_bytes;
1118 storage->tx_bytes = hw_stats->tx_bytes;
1119 storage->collisions = hw_stats->tx_collisions;
1120 storage->rx_length_errors = hw_stats->rx_short_errors +
1121 hw_stats->rx_long_errors;
1122 storage->rx_over_errors = hw_stats->rx_overflow;
1123 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
1124 storage->rx_errors = hw_stats->rx_checksum_errors;
1125 storage->tx_aborted_errors = hw_stats->tx_skip;
1126 } while (u64_stats_fetch_retry(&hw_stats->syncp, start));
1127
1128 storage->tx_errors = dev->stats.tx_errors;
1129 storage->rx_dropped = dev->stats.rx_dropped;
1130 storage->tx_dropped = dev->stats.tx_dropped;
1131 }
1132
mtk_max_frag_size(int mtu)1133 static inline int mtk_max_frag_size(int mtu)
1134 {
1135 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
1136 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)
1137 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
1138
1139 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
1140 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1141 }
1142
mtk_max_buf_size(int frag_size)1143 static inline int mtk_max_buf_size(int frag_size)
1144 {
1145 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
1146 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1147
1148 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);
1149
1150 return buf_size;
1151 }
1152
mtk_rx_get_desc(struct mtk_eth * eth,struct mtk_rx_dma_v2 * rxd,struct mtk_rx_dma_v2 * dma_rxd)1153 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd,
1154 struct mtk_rx_dma_v2 *dma_rxd)
1155 {
1156 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
1157 if (!(rxd->rxd2 & RX_DMA_DONE))
1158 return false;
1159
1160 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
1161 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
1162 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
1163 if (mtk_is_netsys_v3_or_greater(eth)) {
1164 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
1165 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
1166 }
1167
1168 return true;
1169 }
1170
mtk_max_lro_buf_alloc(gfp_t gfp_mask)1171 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
1172 {
1173 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH);
1174 unsigned long data;
1175
1176 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN,
1177 get_order(size));
1178
1179 return (void *)data;
1180 }
1181
1182 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)1183 static int mtk_init_fq_dma(struct mtk_eth *eth)
1184 {
1185 const struct mtk_soc_data *soc = eth->soc;
1186 dma_addr_t phy_ring_tail;
1187 int cnt = soc->tx.fq_dma_size;
1188 dma_addr_t dma_addr;
1189 int i, j, len;
1190
1191 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
1192 eth->scratch_ring = eth->sram_base;
1193 else
1194 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
1195 cnt * soc->tx.desc_size,
1196 ð->phy_scratch_ring,
1197 GFP_KERNEL);
1198
1199 if (unlikely(!eth->scratch_ring))
1200 return -ENOMEM;
1201
1202 phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
1203
1204 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) {
1205 len = min_t(int, cnt - j * MTK_FQ_DMA_LENGTH, MTK_FQ_DMA_LENGTH);
1206 eth->scratch_head[j] = kcalloc(len, MTK_QDMA_PAGE_SIZE, GFP_KERNEL);
1207
1208 if (unlikely(!eth->scratch_head[j]))
1209 return -ENOMEM;
1210
1211 dma_addr = dma_map_single(eth->dma_dev,
1212 eth->scratch_head[j], len * MTK_QDMA_PAGE_SIZE,
1213 DMA_FROM_DEVICE);
1214
1215 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
1216 return -ENOMEM;
1217
1218 for (i = 0; i < len; i++) {
1219 struct mtk_tx_dma_v2 *txd;
1220
1221 txd = eth->scratch_ring + (j * MTK_FQ_DMA_LENGTH + i) * soc->tx.desc_size;
1222 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
1223 if (j * MTK_FQ_DMA_LENGTH + i < cnt)
1224 txd->txd2 = eth->phy_scratch_ring +
1225 (j * MTK_FQ_DMA_LENGTH + i + 1) * soc->tx.desc_size;
1226
1227 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
1228 if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
1229 txd->txd3 |= TX_DMA_PREP_ADDR64(dma_addr + i * MTK_QDMA_PAGE_SIZE);
1230
1231 txd->txd4 = 0;
1232 if (mtk_is_netsys_v2_or_greater(eth)) {
1233 txd->txd5 = 0;
1234 txd->txd6 = 0;
1235 txd->txd7 = 0;
1236 txd->txd8 = 0;
1237 }
1238 }
1239 }
1240
1241 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);
1242 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);
1243 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);
1244 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);
1245
1246 return 0;
1247 }
1248
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)1249 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
1250 {
1251 return ring->dma + (desc - ring->phys);
1252 }
1253
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,void * txd,u32 txd_size)1254 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
1255 void *txd, u32 txd_size)
1256 {
1257 int idx = (txd - ring->dma) / txd_size;
1258
1259 return &ring->buf[idx];
1260 }
1261
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)1262 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
1263 struct mtk_tx_dma *dma)
1264 {
1265 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma;
1266 }
1267
txd_to_idx(struct mtk_tx_ring * ring,void * dma,u32 txd_size)1268 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size)
1269 {
1270 return (dma - ring->dma) / txd_size;
1271 }
1272
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct xdp_frame_bulk * bq,bool napi)1273 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1274 struct xdp_frame_bulk *bq, bool napi)
1275 {
1276 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1277 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
1278 dma_unmap_single(eth->dma_dev,
1279 dma_unmap_addr(tx_buf, dma_addr0),
1280 dma_unmap_len(tx_buf, dma_len0),
1281 DMA_TO_DEVICE);
1282 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
1283 dma_unmap_page(eth->dma_dev,
1284 dma_unmap_addr(tx_buf, dma_addr0),
1285 dma_unmap_len(tx_buf, dma_len0),
1286 DMA_TO_DEVICE);
1287 }
1288 } else {
1289 if (dma_unmap_len(tx_buf, dma_len0)) {
1290 dma_unmap_page(eth->dma_dev,
1291 dma_unmap_addr(tx_buf, dma_addr0),
1292 dma_unmap_len(tx_buf, dma_len0),
1293 DMA_TO_DEVICE);
1294 }
1295
1296 if (dma_unmap_len(tx_buf, dma_len1)) {
1297 dma_unmap_page(eth->dma_dev,
1298 dma_unmap_addr(tx_buf, dma_addr1),
1299 dma_unmap_len(tx_buf, dma_len1),
1300 DMA_TO_DEVICE);
1301 }
1302 }
1303
1304 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
1305 if (tx_buf->type == MTK_TYPE_SKB) {
1306 struct sk_buff *skb = tx_buf->data;
1307
1308 if (napi)
1309 napi_consume_skb(skb, napi);
1310 else
1311 dev_kfree_skb_any(skb);
1312 } else {
1313 struct xdp_frame *xdpf = tx_buf->data;
1314
1315 if (napi && tx_buf->type == MTK_TYPE_XDP_TX)
1316 xdp_return_frame_rx_napi(xdpf);
1317 else if (bq)
1318 xdp_return_frame_bulk(xdpf, bq);
1319 else
1320 xdp_return_frame(xdpf);
1321 }
1322 }
1323 tx_buf->flags = 0;
1324 tx_buf->data = NULL;
1325 }
1326
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)1327 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
1328 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
1329 size_t size, int idx)
1330 {
1331 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1332 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1333 dma_unmap_len_set(tx_buf, dma_len0, size);
1334 } else {
1335 if (idx & 1) {
1336 txd->txd3 = mapped_addr;
1337 txd->txd2 |= TX_DMA_PLEN1(size);
1338 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
1339 dma_unmap_len_set(tx_buf, dma_len1, size);
1340 } else {
1341 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1342 txd->txd1 = mapped_addr;
1343 txd->txd2 = TX_DMA_PLEN0(size);
1344 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
1345 dma_unmap_len_set(tx_buf, dma_len0, size);
1346 }
1347 }
1348 }
1349
mtk_tx_set_dma_desc_v1(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1350 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd,
1351 struct mtk_tx_dma_desc_info *info)
1352 {
1353 struct mtk_mac *mac = netdev_priv(dev);
1354 struct mtk_eth *eth = mac->hw;
1355 struct mtk_tx_dma *desc = txd;
1356 u32 data;
1357
1358 WRITE_ONCE(desc->txd1, info->addr);
1359
1360 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) |
1361 FIELD_PREP(TX_DMA_PQID, info->qid);
1362 if (info->last)
1363 data |= TX_DMA_LS0;
1364 WRITE_ONCE(desc->txd3, data);
1365
1366 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */
1367 if (info->first) {
1368 if (info->gso)
1369 data |= TX_DMA_TSO;
1370 /* tx checksum offload */
1371 if (info->csum)
1372 data |= TX_DMA_CHKSUM;
1373 /* vlan header offload */
1374 if (info->vlan)
1375 data |= TX_DMA_INS_VLAN | info->vlan_tci;
1376 }
1377 WRITE_ONCE(desc->txd4, data);
1378 }
1379
mtk_tx_set_dma_desc_v2(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1380 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd,
1381 struct mtk_tx_dma_desc_info *info)
1382 {
1383 struct mtk_mac *mac = netdev_priv(dev);
1384 struct mtk_tx_dma_v2 *desc = txd;
1385 struct mtk_eth *eth = mac->hw;
1386 u32 data;
1387
1388 WRITE_ONCE(desc->txd1, info->addr);
1389
1390 data = TX_DMA_PLEN0(info->size);
1391 if (info->last)
1392 data |= TX_DMA_LS0;
1393
1394 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
1395 data |= TX_DMA_PREP_ADDR64(info->addr);
1396
1397 WRITE_ONCE(desc->txd3, data);
1398
1399 /* set forward port */
1400 switch (mac->id) {
1401 case MTK_GMAC1_ID:
1402 data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
1403 break;
1404 case MTK_GMAC2_ID:
1405 data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
1406 break;
1407 case MTK_GMAC3_ID:
1408 data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
1409 break;
1410 }
1411
1412 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
1413 WRITE_ONCE(desc->txd4, data);
1414
1415 data = 0;
1416 if (info->first) {
1417 if (info->gso)
1418 data |= TX_DMA_TSO_V2;
1419 /* tx checksum offload */
1420 if (info->csum)
1421 data |= TX_DMA_CHKSUM_V2;
1422 if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev))
1423 data |= TX_DMA_SPTAG_V3;
1424 }
1425 WRITE_ONCE(desc->txd5, data);
1426
1427 data = 0;
1428 if (info->first && info->vlan)
1429 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci;
1430 WRITE_ONCE(desc->txd6, data);
1431
1432 WRITE_ONCE(desc->txd7, 0);
1433 WRITE_ONCE(desc->txd8, 0);
1434 }
1435
mtk_tx_set_dma_desc(struct net_device * dev,void * txd,struct mtk_tx_dma_desc_info * info)1436 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd,
1437 struct mtk_tx_dma_desc_info *info)
1438 {
1439 struct mtk_mac *mac = netdev_priv(dev);
1440 struct mtk_eth *eth = mac->hw;
1441
1442 if (mtk_is_netsys_v2_or_greater(eth))
1443 mtk_tx_set_dma_desc_v2(dev, txd, info);
1444 else
1445 mtk_tx_set_dma_desc_v1(dev, txd, info);
1446 }
1447
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)1448 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
1449 int tx_num, struct mtk_tx_ring *ring, bool gso)
1450 {
1451 struct mtk_tx_dma_desc_info txd_info = {
1452 .size = skb_headlen(skb),
1453 .gso = gso,
1454 .csum = skb->ip_summed == CHECKSUM_PARTIAL,
1455 .vlan = skb_vlan_tag_present(skb),
1456 .qid = skb_get_queue_mapping(skb),
1457 .vlan_tci = skb_vlan_tag_get(skb),
1458 .first = true,
1459 .last = !skb_is_nonlinear(skb),
1460 };
1461 struct netdev_queue *txq;
1462 struct mtk_mac *mac = netdev_priv(dev);
1463 struct mtk_eth *eth = mac->hw;
1464 const struct mtk_soc_data *soc = eth->soc;
1465 struct mtk_tx_dma *itxd, *txd;
1466 struct mtk_tx_dma *itxd_pdma, *txd_pdma;
1467 struct mtk_tx_buf *itx_buf, *tx_buf;
1468 int i, n_desc = 1;
1469 int queue = skb_get_queue_mapping(skb);
1470 int k = 0;
1471
1472 txq = netdev_get_tx_queue(dev, queue);
1473 itxd = ring->next_free;
1474 itxd_pdma = qdma_to_pdma(ring, itxd);
1475 if (itxd == ring->last_free)
1476 return -ENOMEM;
1477
1478 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
1479 memset(itx_buf, 0, sizeof(*itx_buf));
1480
1481 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
1482 DMA_TO_DEVICE);
1483 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1484 return -ENOMEM;
1485
1486 mtk_tx_set_dma_desc(dev, itxd, &txd_info);
1487
1488 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1489 itx_buf->mac_id = mac->id;
1490 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
1491 k++);
1492
1493 /* TX SG offload */
1494 txd = itxd;
1495 txd_pdma = qdma_to_pdma(ring, txd);
1496
1497 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1498 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1499 unsigned int offset = 0;
1500 int frag_size = skb_frag_size(frag);
1501
1502 while (frag_size) {
1503 bool new_desc = true;
1504
1505 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) ||
1506 (i & 0x1)) {
1507 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1508 txd_pdma = qdma_to_pdma(ring, txd);
1509 if (txd == ring->last_free)
1510 goto err_dma;
1511
1512 n_desc++;
1513 } else {
1514 new_desc = false;
1515 }
1516
1517 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1518 txd_info.size = min_t(unsigned int, frag_size,
1519 soc->tx.dma_max_len);
1520 txd_info.qid = queue;
1521 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
1522 !(frag_size - txd_info.size);
1523 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
1524 offset, txd_info.size,
1525 DMA_TO_DEVICE);
1526 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr)))
1527 goto err_dma;
1528
1529 mtk_tx_set_dma_desc(dev, txd, &txd_info);
1530
1531 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1532 soc->tx.desc_size);
1533 if (new_desc)
1534 memset(tx_buf, 0, sizeof(*tx_buf));
1535 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1536 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1537 tx_buf->mac_id = mac->id;
1538
1539 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
1540 txd_info.size, k++);
1541
1542 frag_size -= txd_info.size;
1543 offset += txd_info.size;
1544 }
1545 }
1546
1547 /* store skb to cleanup */
1548 itx_buf->type = MTK_TYPE_SKB;
1549 itx_buf->data = skb;
1550
1551 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1552 if (k & 0x1)
1553 txd_pdma->txd2 |= TX_DMA_LS0;
1554 else
1555 txd_pdma->txd2 |= TX_DMA_LS1;
1556 }
1557
1558 netdev_tx_sent_queue(txq, skb->len);
1559 skb_tx_timestamp(skb);
1560
1561 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1562 atomic_sub(n_desc, &ring->free_count);
1563
1564 /* make sure that all changes to the dma ring are flushed before we
1565 * continue
1566 */
1567 wmb();
1568
1569 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1570 if (netif_xmit_stopped(txq) || !netdev_xmit_more())
1571 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1572 } else {
1573 int next_idx;
1574
1575 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
1576 ring->dma_size);
1577 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1578 }
1579
1580 return 0;
1581
1582 err_dma:
1583 do {
1584 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
1585
1586 /* unmap dma */
1587 mtk_tx_unmap(eth, tx_buf, NULL, false);
1588
1589 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1590 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA))
1591 itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1592
1593 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1594 itxd_pdma = qdma_to_pdma(ring, itxd);
1595 } while (itxd != txd);
1596
1597 return -ENOMEM;
1598 }
1599
mtk_cal_txd_req(struct mtk_eth * eth,struct sk_buff * skb)1600 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb)
1601 {
1602 int i, nfrags = 1;
1603 skb_frag_t *frag;
1604
1605 if (skb_is_gso(skb)) {
1606 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1607 frag = &skb_shinfo(skb)->frags[i];
1608 nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1609 eth->soc->tx.dma_max_len);
1610 }
1611 } else {
1612 nfrags += skb_shinfo(skb)->nr_frags;
1613 }
1614
1615 return nfrags;
1616 }
1617
mtk_queue_stopped(struct mtk_eth * eth)1618 static int mtk_queue_stopped(struct mtk_eth *eth)
1619 {
1620 int i;
1621
1622 for (i = 0; i < MTK_MAX_DEVS; i++) {
1623 if (!eth->netdev[i])
1624 continue;
1625 if (netif_queue_stopped(eth->netdev[i]))
1626 return 1;
1627 }
1628
1629 return 0;
1630 }
1631
mtk_wake_queue(struct mtk_eth * eth)1632 static void mtk_wake_queue(struct mtk_eth *eth)
1633 {
1634 int i;
1635
1636 for (i = 0; i < MTK_MAX_DEVS; i++) {
1637 if (!eth->netdev[i])
1638 continue;
1639 netif_tx_wake_all_queues(eth->netdev[i]);
1640 }
1641 }
1642
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1643 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1644 {
1645 struct mtk_mac *mac = netdev_priv(dev);
1646 struct mtk_eth *eth = mac->hw;
1647 struct mtk_tx_ring *ring = ð->tx_ring;
1648 struct net_device_stats *stats = &dev->stats;
1649 bool gso = false;
1650 int tx_num;
1651
1652 /* normally we can rely on the stack not calling this more than once,
1653 * however we have 2 queues running on the same ring so we need to lock
1654 * the ring access
1655 */
1656 spin_lock(ð->page_lock);
1657
1658 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1659 goto drop;
1660
1661 tx_num = mtk_cal_txd_req(eth, skb);
1662 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1663 netif_tx_stop_all_queues(dev);
1664 netif_err(eth, tx_queued, dev,
1665 "Tx Ring full when queue awake!\n");
1666 spin_unlock(ð->page_lock);
1667 return NETDEV_TX_BUSY;
1668 }
1669
1670 /* TSO: fill MSS info in tcp checksum field */
1671 if (skb_is_gso(skb)) {
1672 if (skb_cow_head(skb, 0)) {
1673 netif_warn(eth, tx_err, dev,
1674 "GSO expand head fail.\n");
1675 goto drop;
1676 }
1677
1678 if (skb_shinfo(skb)->gso_type &
1679 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1680 gso = true;
1681 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1682 }
1683 }
1684
1685 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1686 goto drop;
1687
1688 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1689 netif_tx_stop_all_queues(dev);
1690
1691 spin_unlock(ð->page_lock);
1692
1693 return NETDEV_TX_OK;
1694
1695 drop:
1696 spin_unlock(ð->page_lock);
1697 stats->tx_dropped++;
1698 dev_kfree_skb_any(skb);
1699 return NETDEV_TX_OK;
1700 }
1701
mtk_get_rx_ring(struct mtk_eth * eth)1702 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1703 {
1704 int i;
1705 struct mtk_rx_ring *ring;
1706 int idx;
1707
1708 if (!eth->hwlro)
1709 return ð->rx_ring[0];
1710
1711 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1712 struct mtk_rx_dma *rxd;
1713
1714 ring = ð->rx_ring[i];
1715 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1716 rxd = ring->dma + idx * eth->soc->rx.desc_size;
1717 if (rxd->rxd2 & RX_DMA_DONE) {
1718 ring->calc_idx_update = true;
1719 return ring;
1720 }
1721 }
1722
1723 return NULL;
1724 }
1725
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1726 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1727 {
1728 struct mtk_rx_ring *ring;
1729 int i;
1730
1731 if (!eth->hwlro) {
1732 ring = ð->rx_ring[0];
1733 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1734 } else {
1735 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1736 ring = ð->rx_ring[i];
1737 if (ring->calc_idx_update) {
1738 ring->calc_idx_update = false;
1739 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1740 }
1741 }
1742 }
1743 }
1744
mtk_page_pool_enabled(struct mtk_eth * eth)1745 static bool mtk_page_pool_enabled(struct mtk_eth *eth)
1746 {
1747 return mtk_is_netsys_v2_or_greater(eth);
1748 }
1749
mtk_create_page_pool(struct mtk_eth * eth,struct xdp_rxq_info * xdp_q,int id,int size)1750 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
1751 struct xdp_rxq_info *xdp_q,
1752 int id, int size)
1753 {
1754 struct page_pool_params pp_params = {
1755 .order = 0,
1756 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
1757 .pool_size = size,
1758 .nid = NUMA_NO_NODE,
1759 .dev = eth->dma_dev,
1760 .offset = MTK_PP_HEADROOM,
1761 .max_len = MTK_PP_MAX_BUF_SIZE,
1762 };
1763 struct page_pool *pp;
1764 int err;
1765
1766 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL
1767 : DMA_FROM_DEVICE;
1768 pp = page_pool_create(&pp_params);
1769 if (IS_ERR(pp))
1770 return pp;
1771
1772 err = __xdp_rxq_info_reg(xdp_q, eth->dummy_dev, id,
1773 eth->rx_napi.napi_id, PAGE_SIZE);
1774 if (err < 0)
1775 goto err_free_pp;
1776
1777 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp);
1778 if (err)
1779 goto err_unregister_rxq;
1780
1781 return pp;
1782
1783 err_unregister_rxq:
1784 xdp_rxq_info_unreg(xdp_q);
1785 err_free_pp:
1786 page_pool_destroy(pp);
1787
1788 return ERR_PTR(err);
1789 }
1790
mtk_page_pool_get_buff(struct page_pool * pp,dma_addr_t * dma_addr,gfp_t gfp_mask)1791 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr,
1792 gfp_t gfp_mask)
1793 {
1794 struct page *page;
1795
1796 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN);
1797 if (!page)
1798 return NULL;
1799
1800 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM;
1801 return page_address(page);
1802 }
1803
mtk_rx_put_buff(struct mtk_rx_ring * ring,void * data,bool napi)1804 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi)
1805 {
1806 if (ring->page_pool)
1807 page_pool_put_full_page(ring->page_pool,
1808 virt_to_head_page(data), napi);
1809 else
1810 skb_free_frag(data);
1811 }
1812
mtk_xdp_frame_map(struct mtk_eth * eth,struct net_device * dev,struct mtk_tx_dma_desc_info * txd_info,struct mtk_tx_dma * txd,struct mtk_tx_buf * tx_buf,void * data,u16 headroom,int index,bool dma_map)1813 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev,
1814 struct mtk_tx_dma_desc_info *txd_info,
1815 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf,
1816 void *data, u16 headroom, int index, bool dma_map)
1817 {
1818 struct mtk_tx_ring *ring = ð->tx_ring;
1819 struct mtk_mac *mac = netdev_priv(dev);
1820 struct mtk_tx_dma *txd_pdma;
1821
1822 if (dma_map) { /* ndo_xdp_xmit */
1823 txd_info->addr = dma_map_single(eth->dma_dev, data,
1824 txd_info->size, DMA_TO_DEVICE);
1825 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr)))
1826 return -ENOMEM;
1827
1828 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
1829 } else {
1830 struct page *page = virt_to_head_page(data);
1831
1832 txd_info->addr = page_pool_get_dma_addr(page) +
1833 sizeof(struct xdp_frame) + headroom;
1834 dma_sync_single_for_device(eth->dma_dev, txd_info->addr,
1835 txd_info->size, DMA_BIDIRECTIONAL);
1836 }
1837 mtk_tx_set_dma_desc(dev, txd, txd_info);
1838
1839 tx_buf->mac_id = mac->id;
1840 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
1841 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
1842
1843 txd_pdma = qdma_to_pdma(ring, txd);
1844 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size,
1845 index);
1846
1847 return 0;
1848 }
1849
mtk_xdp_submit_frame(struct mtk_eth * eth,struct xdp_frame * xdpf,struct net_device * dev,bool dma_map)1850 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf,
1851 struct net_device *dev, bool dma_map)
1852 {
1853 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
1854 const struct mtk_soc_data *soc = eth->soc;
1855 struct mtk_tx_ring *ring = ð->tx_ring;
1856 struct mtk_mac *mac = netdev_priv(dev);
1857 struct mtk_tx_dma_desc_info txd_info = {
1858 .size = xdpf->len,
1859 .first = true,
1860 .last = !xdp_frame_has_frags(xdpf),
1861 .qid = mac->id,
1862 };
1863 int err, index = 0, n_desc = 1, nr_frags;
1864 struct mtk_tx_buf *htx_buf, *tx_buf;
1865 struct mtk_tx_dma *htxd, *txd;
1866 void *data = xdpf->data;
1867
1868 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
1869 return -EBUSY;
1870
1871 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
1872 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags))
1873 return -EBUSY;
1874
1875 spin_lock(ð->page_lock);
1876
1877 txd = ring->next_free;
1878 if (txd == ring->last_free) {
1879 spin_unlock(ð->page_lock);
1880 return -ENOMEM;
1881 }
1882 htxd = txd;
1883
1884 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
1885 memset(tx_buf, 0, sizeof(*tx_buf));
1886 htx_buf = tx_buf;
1887
1888 for (;;) {
1889 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf,
1890 data, xdpf->headroom, index, dma_map);
1891 if (err < 0)
1892 goto unmap;
1893
1894 if (txd_info.last)
1895 break;
1896
1897 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) {
1898 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1899 if (txd == ring->last_free)
1900 goto unmap;
1901
1902 tx_buf = mtk_desc_to_tx_buf(ring, txd,
1903 soc->tx.desc_size);
1904 memset(tx_buf, 0, sizeof(*tx_buf));
1905 n_desc++;
1906 }
1907
1908 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
1909 txd_info.size = skb_frag_size(&sinfo->frags[index]);
1910 txd_info.last = index + 1 == nr_frags;
1911 txd_info.qid = mac->id;
1912 data = skb_frag_address(&sinfo->frags[index]);
1913
1914 index++;
1915 }
1916 /* store xdpf for cleanup */
1917 htx_buf->data = xdpf;
1918
1919 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1920 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd);
1921
1922 if (index & 1)
1923 txd_pdma->txd2 |= TX_DMA_LS0;
1924 else
1925 txd_pdma->txd2 |= TX_DMA_LS1;
1926 }
1927
1928 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1929 atomic_sub(n_desc, &ring->free_count);
1930
1931 /* make sure that all changes to the dma ring are flushed before we
1932 * continue
1933 */
1934 wmb();
1935
1936 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1937 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
1938 } else {
1939 int idx;
1940
1941 idx = txd_to_idx(ring, txd, soc->tx.desc_size);
1942 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
1943 MT7628_TX_CTX_IDX0);
1944 }
1945
1946 spin_unlock(ð->page_lock);
1947
1948 return 0;
1949
1950 unmap:
1951 while (htxd != txd) {
1952 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
1953 mtk_tx_unmap(eth, tx_buf, NULL, false);
1954
1955 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1956 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
1957 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd);
1958
1959 txd_pdma->txd2 = TX_DMA_DESP2_DEF;
1960 }
1961
1962 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2);
1963 }
1964
1965 spin_unlock(ð->page_lock);
1966
1967 return err;
1968 }
1969
mtk_xdp_xmit(struct net_device * dev,int num_frame,struct xdp_frame ** frames,u32 flags)1970 static int mtk_xdp_xmit(struct net_device *dev, int num_frame,
1971 struct xdp_frame **frames, u32 flags)
1972 {
1973 struct mtk_mac *mac = netdev_priv(dev);
1974 struct mtk_hw_stats *hw_stats = mac->hw_stats;
1975 struct mtk_eth *eth = mac->hw;
1976 int i, nxmit = 0;
1977
1978 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
1979 return -EINVAL;
1980
1981 for (i = 0; i < num_frame; i++) {
1982 if (mtk_xdp_submit_frame(eth, frames[i], dev, true))
1983 break;
1984 nxmit++;
1985 }
1986
1987 u64_stats_update_begin(&hw_stats->syncp);
1988 hw_stats->xdp_stats.tx_xdp_xmit += nxmit;
1989 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit;
1990 u64_stats_update_end(&hw_stats->syncp);
1991
1992 return nxmit;
1993 }
1994
mtk_xdp_run(struct mtk_eth * eth,struct mtk_rx_ring * ring,struct xdp_buff * xdp,struct net_device * dev)1995 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring,
1996 struct xdp_buff *xdp, struct net_device *dev)
1997 {
1998 struct mtk_mac *mac = netdev_priv(dev);
1999 struct mtk_hw_stats *hw_stats = mac->hw_stats;
2000 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop;
2001 struct bpf_prog *prog;
2002 u32 act = XDP_PASS;
2003
2004 rcu_read_lock();
2005
2006 prog = rcu_dereference(eth->prog);
2007 if (!prog)
2008 goto out;
2009
2010 act = bpf_prog_run_xdp(prog, xdp);
2011 switch (act) {
2012 case XDP_PASS:
2013 count = &hw_stats->xdp_stats.rx_xdp_pass;
2014 goto update_stats;
2015 case XDP_REDIRECT:
2016 if (unlikely(xdp_do_redirect(dev, xdp, prog))) {
2017 act = XDP_DROP;
2018 break;
2019 }
2020
2021 count = &hw_stats->xdp_stats.rx_xdp_redirect;
2022 goto update_stats;
2023 case XDP_TX: {
2024 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2025
2026 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) {
2027 count = &hw_stats->xdp_stats.rx_xdp_tx_errors;
2028 act = XDP_DROP;
2029 break;
2030 }
2031
2032 count = &hw_stats->xdp_stats.rx_xdp_tx;
2033 goto update_stats;
2034 }
2035 default:
2036 bpf_warn_invalid_xdp_action(dev, prog, act);
2037 fallthrough;
2038 case XDP_ABORTED:
2039 trace_xdp_exception(dev, prog, act);
2040 fallthrough;
2041 case XDP_DROP:
2042 break;
2043 }
2044
2045 page_pool_put_full_page(ring->page_pool,
2046 virt_to_head_page(xdp->data), true);
2047
2048 update_stats:
2049 u64_stats_update_begin(&hw_stats->syncp);
2050 *count = *count + 1;
2051 u64_stats_update_end(&hw_stats->syncp);
2052 out:
2053 rcu_read_unlock();
2054
2055 return act;
2056 }
2057
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)2058 static int mtk_poll_rx(struct napi_struct *napi, int budget,
2059 struct mtk_eth *eth)
2060 {
2061 struct dim_sample dim_sample = {};
2062 struct mtk_rx_ring *ring;
2063 bool xdp_flush = false;
2064 int idx;
2065 struct sk_buff *skb;
2066 u64 addr64 = 0;
2067 u8 *data, *new_data;
2068 struct mtk_rx_dma_v2 *rxd, trxd;
2069 int done = 0, bytes = 0;
2070 dma_addr_t dma_addr = DMA_MAPPING_ERROR;
2071 int ppe_idx = 0;
2072
2073 while (done < budget) {
2074 unsigned int pktlen, *rxdcsum;
2075 struct net_device *netdev;
2076 u32 hash, reason;
2077 int mac = 0;
2078
2079 ring = mtk_get_rx_ring(eth);
2080 if (unlikely(!ring))
2081 goto rx_done;
2082
2083 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
2084 rxd = ring->dma + idx * eth->soc->rx.desc_size;
2085 data = ring->data[idx];
2086
2087 if (!mtk_rx_get_desc(eth, &trxd, rxd))
2088 break;
2089
2090 /* find out which mac the packet come from. values start at 1 */
2091 if (mtk_is_netsys_v3_or_greater(eth)) {
2092 u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
2093
2094 switch (val) {
2095 case PSE_GDM1_PORT:
2096 case PSE_GDM2_PORT:
2097 mac = val - 1;
2098 break;
2099 case PSE_GDM3_PORT:
2100 mac = MTK_GMAC3_ID;
2101 break;
2102 default:
2103 break;
2104 }
2105 } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
2106 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) {
2107 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
2108 }
2109
2110 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
2111 !eth->netdev[mac]))
2112 goto release_desc;
2113
2114 netdev = eth->netdev[mac];
2115 ppe_idx = eth->mac[mac]->ppe_idx;
2116
2117 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
2118 goto release_desc;
2119
2120 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
2121
2122 /* alloc new buffer */
2123 if (ring->page_pool) {
2124 struct page *page = virt_to_head_page(data);
2125 struct xdp_buff xdp;
2126 u32 ret, metasize;
2127
2128 new_data = mtk_page_pool_get_buff(ring->page_pool,
2129 &dma_addr,
2130 GFP_ATOMIC);
2131 if (unlikely(!new_data)) {
2132 netdev->stats.rx_dropped++;
2133 goto release_desc;
2134 }
2135
2136 dma_sync_single_for_cpu(eth->dma_dev,
2137 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM,
2138 pktlen, page_pool_get_dma_dir(ring->page_pool));
2139
2140 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q);
2141 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen,
2142 true);
2143 xdp_buff_clear_frags_flag(&xdp);
2144
2145 ret = mtk_xdp_run(eth, ring, &xdp, netdev);
2146 if (ret == XDP_REDIRECT)
2147 xdp_flush = true;
2148
2149 if (ret != XDP_PASS)
2150 goto skip_rx;
2151
2152 skb = build_skb(data, PAGE_SIZE);
2153 if (unlikely(!skb)) {
2154 page_pool_put_full_page(ring->page_pool,
2155 page, true);
2156 netdev->stats.rx_dropped++;
2157 goto skip_rx;
2158 }
2159
2160 skb_reserve(skb, xdp.data - xdp.data_hard_start);
2161 skb_put(skb, xdp.data_end - xdp.data);
2162 metasize = xdp.data - xdp.data_meta;
2163 if (metasize)
2164 skb_metadata_set(skb, metasize);
2165 skb_mark_for_recycle(skb);
2166 } else {
2167 if (ring->frag_size <= PAGE_SIZE)
2168 new_data = napi_alloc_frag(ring->frag_size);
2169 else
2170 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC);
2171
2172 if (unlikely(!new_data)) {
2173 netdev->stats.rx_dropped++;
2174 goto release_desc;
2175 }
2176
2177 dma_addr = dma_map_single(eth->dma_dev,
2178 new_data + NET_SKB_PAD + eth->ip_align,
2179 ring->buf_size, DMA_FROM_DEVICE);
2180 if (unlikely(dma_mapping_error(eth->dma_dev,
2181 dma_addr))) {
2182 skb_free_frag(new_data);
2183 netdev->stats.rx_dropped++;
2184 goto release_desc;
2185 }
2186
2187 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2188 addr64 = RX_DMA_GET_ADDR64(trxd.rxd2);
2189
2190 dma_unmap_single(eth->dma_dev, ((u64)trxd.rxd1 | addr64),
2191 ring->buf_size, DMA_FROM_DEVICE);
2192
2193 skb = build_skb(data, ring->frag_size);
2194 if (unlikely(!skb)) {
2195 netdev->stats.rx_dropped++;
2196 skb_free_frag(data);
2197 goto skip_rx;
2198 }
2199
2200 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
2201 skb_put(skb, pktlen);
2202 }
2203
2204 skb->dev = netdev;
2205 bytes += skb->len;
2206
2207 if (mtk_is_netsys_v3_or_greater(eth)) {
2208 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
2209 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
2210 if (hash != MTK_RXD5_FOE_ENTRY)
2211 skb_set_hash(skb, jhash_1word(hash, 0),
2212 PKT_HASH_TYPE_L4);
2213 rxdcsum = &trxd.rxd3;
2214 } else {
2215 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);
2216 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;
2217 if (hash != MTK_RXD4_FOE_ENTRY)
2218 skb_set_hash(skb, jhash_1word(hash, 0),
2219 PKT_HASH_TYPE_L4);
2220 rxdcsum = &trxd.rxd4;
2221 }
2222
2223 if (*rxdcsum & eth->soc->rx.dma_l4_valid)
2224 skb->ip_summed = CHECKSUM_UNNECESSARY;
2225 else
2226 skb_checksum_none_assert(skb);
2227 skb->protocol = eth_type_trans(skb, netdev);
2228
2229 /* When using VLAN untagging in combination with DSA, the
2230 * hardware treats the MTK special tag as a VLAN and untags it.
2231 */
2232 if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) &&
2233 netdev_uses_dsa(netdev)) {
2234 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
2235
2236 if (port < ARRAY_SIZE(eth->dsa_meta) &&
2237 eth->dsa_meta[port])
2238 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst);
2239 }
2240
2241 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
2242 mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash);
2243
2244 skb_record_rx_queue(skb, 0);
2245 napi_gro_receive(napi, skb);
2246
2247 skip_rx:
2248 ring->data[idx] = new_data;
2249 rxd->rxd1 = (unsigned int)dma_addr;
2250 release_desc:
2251 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
2252 if (unlikely(dma_addr == DMA_MAPPING_ERROR))
2253 addr64 = FIELD_GET(RX_DMA_ADDR64_MASK,
2254 rxd->rxd2);
2255 else
2256 addr64 = RX_DMA_PREP_ADDR64(dma_addr);
2257 }
2258
2259 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2260 rxd->rxd2 = RX_DMA_LSO;
2261 else
2262 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size) | addr64;
2263
2264 ring->calc_idx = idx;
2265 done++;
2266 }
2267
2268 rx_done:
2269 if (done) {
2270 /* make sure that all changes to the dma ring are flushed before
2271 * we continue
2272 */
2273 wmb();
2274 mtk_update_rx_cpu_idx(eth);
2275 }
2276
2277 eth->rx_packets += done;
2278 eth->rx_bytes += bytes;
2279 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,
2280 &dim_sample);
2281 net_dim(ð->rx_dim, &dim_sample);
2282
2283 if (xdp_flush)
2284 xdp_do_flush();
2285
2286 return done;
2287 }
2288
2289 struct mtk_poll_state {
2290 struct netdev_queue *txq;
2291 unsigned int total;
2292 unsigned int done;
2293 unsigned int bytes;
2294 };
2295
2296 static void
mtk_poll_tx_done(struct mtk_eth * eth,struct mtk_poll_state * state,u8 mac,struct sk_buff * skb)2297 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac,
2298 struct sk_buff *skb)
2299 {
2300 struct netdev_queue *txq;
2301 struct net_device *dev;
2302 unsigned int bytes = skb->len;
2303
2304 state->total++;
2305 eth->tx_packets++;
2306 eth->tx_bytes += bytes;
2307
2308 dev = eth->netdev[mac];
2309 if (!dev)
2310 return;
2311
2312 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
2313 if (state->txq == txq) {
2314 state->done++;
2315 state->bytes += bytes;
2316 return;
2317 }
2318
2319 if (state->txq)
2320 netdev_tx_completed_queue(state->txq, state->done, state->bytes);
2321
2322 state->txq = txq;
2323 state->done = 1;
2324 state->bytes = bytes;
2325 }
2326
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2327 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
2328 struct mtk_poll_state *state)
2329 {
2330 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2331 struct mtk_tx_ring *ring = ð->tx_ring;
2332 struct mtk_tx_buf *tx_buf;
2333 struct xdp_frame_bulk bq;
2334 struct mtk_tx_dma *desc;
2335 u32 cpu, dma;
2336
2337 cpu = ring->last_free_ptr;
2338 dma = mtk_r32(eth, reg_map->qdma.drx_ptr);
2339
2340 desc = mtk_qdma_phys_to_virt(ring, cpu);
2341 xdp_frame_bulk_init(&bq);
2342
2343 while ((cpu != dma) && budget) {
2344 u32 next_cpu = desc->txd2;
2345
2346 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
2347 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
2348 break;
2349
2350 tx_buf = mtk_desc_to_tx_buf(ring, desc,
2351 eth->soc->tx.desc_size);
2352 if (!tx_buf->data)
2353 break;
2354
2355 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2356 if (tx_buf->type == MTK_TYPE_SKB)
2357 mtk_poll_tx_done(eth, state, tx_buf->mac_id,
2358 tx_buf->data);
2359
2360 budget--;
2361 }
2362 mtk_tx_unmap(eth, tx_buf, &bq, true);
2363
2364 ring->last_free = desc;
2365 atomic_inc(&ring->free_count);
2366
2367 cpu = next_cpu;
2368 }
2369 xdp_flush_frame_bulk(&bq);
2370
2371 ring->last_free_ptr = cpu;
2372 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);
2373
2374 return budget;
2375 }
2376
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,struct mtk_poll_state * state)2377 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
2378 struct mtk_poll_state *state)
2379 {
2380 struct mtk_tx_ring *ring = ð->tx_ring;
2381 struct mtk_tx_buf *tx_buf;
2382 struct xdp_frame_bulk bq;
2383 struct mtk_tx_dma *desc;
2384 u32 cpu, dma;
2385
2386 cpu = ring->cpu_idx;
2387 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
2388 xdp_frame_bulk_init(&bq);
2389
2390 while ((cpu != dma) && budget) {
2391 tx_buf = &ring->buf[cpu];
2392 if (!tx_buf->data)
2393 break;
2394
2395 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
2396 if (tx_buf->type == MTK_TYPE_SKB)
2397 mtk_poll_tx_done(eth, state, 0, tx_buf->data);
2398 budget--;
2399 }
2400 mtk_tx_unmap(eth, tx_buf, &bq, true);
2401
2402 desc = ring->dma + cpu * eth->soc->tx.desc_size;
2403 ring->last_free = desc;
2404 atomic_inc(&ring->free_count);
2405
2406 cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
2407 }
2408 xdp_flush_frame_bulk(&bq);
2409
2410 ring->cpu_idx = cpu;
2411
2412 return budget;
2413 }
2414
mtk_poll_tx(struct mtk_eth * eth,int budget)2415 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
2416 {
2417 struct mtk_tx_ring *ring = ð->tx_ring;
2418 struct dim_sample dim_sample = {};
2419 struct mtk_poll_state state = {};
2420
2421 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2422 budget = mtk_poll_tx_qdma(eth, budget, &state);
2423 else
2424 budget = mtk_poll_tx_pdma(eth, budget, &state);
2425
2426 if (state.txq)
2427 netdev_tx_completed_queue(state.txq, state.done, state.bytes);
2428
2429 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
2430 &dim_sample);
2431 net_dim(ð->tx_dim, &dim_sample);
2432
2433 if (mtk_queue_stopped(eth) &&
2434 (atomic_read(&ring->free_count) > ring->thresh))
2435 mtk_wake_queue(eth);
2436
2437 return state.total;
2438 }
2439
mtk_handle_status_irq(struct mtk_eth * eth)2440 static void mtk_handle_status_irq(struct mtk_eth *eth)
2441 {
2442 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
2443
2444 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
2445 mtk_stats_update(eth);
2446 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
2447 MTK_INT_STATUS2);
2448 }
2449 }
2450
mtk_napi_tx(struct napi_struct * napi,int budget)2451 static int mtk_napi_tx(struct napi_struct *napi, int budget)
2452 {
2453 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
2454 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2455 int tx_done = 0;
2456
2457 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2458 mtk_handle_status_irq(eth);
2459 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);
2460 tx_done = mtk_poll_tx(eth, budget);
2461
2462 if (unlikely(netif_msg_intr(eth))) {
2463 dev_info(eth->dev,
2464 "done tx %d, intr 0x%08x/0x%x\n", tx_done,
2465 mtk_r32(eth, reg_map->tx_irq_status),
2466 mtk_r32(eth, reg_map->tx_irq_mask));
2467 }
2468
2469 if (tx_done == budget)
2470 return budget;
2471
2472 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
2473 return budget;
2474
2475 if (napi_complete_done(napi, tx_done))
2476 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2477
2478 return tx_done;
2479 }
2480
mtk_napi_rx(struct napi_struct * napi,int budget)2481 static int mtk_napi_rx(struct napi_struct *napi, int budget)
2482 {
2483 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
2484 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2485 int rx_done_total = 0;
2486
2487 mtk_handle_status_irq(eth);
2488
2489 do {
2490 int rx_done;
2491
2492 mtk_w32(eth, eth->soc->rx.irq_done_mask,
2493 reg_map->pdma.irq_status);
2494 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
2495 rx_done_total += rx_done;
2496
2497 if (unlikely(netif_msg_intr(eth))) {
2498 dev_info(eth->dev,
2499 "done rx %d, intr 0x%08x/0x%x\n", rx_done,
2500 mtk_r32(eth, reg_map->pdma.irq_status),
2501 mtk_r32(eth, reg_map->pdma.irq_mask));
2502 }
2503
2504 if (rx_done_total == budget)
2505 return budget;
2506
2507 } while (mtk_r32(eth, reg_map->pdma.irq_status) &
2508 eth->soc->rx.irq_done_mask);
2509
2510 if (napi_complete_done(napi, rx_done_total))
2511 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
2512
2513 return rx_done_total;
2514 }
2515
mtk_tx_alloc(struct mtk_eth * eth)2516 static int mtk_tx_alloc(struct mtk_eth *eth)
2517 {
2518 const struct mtk_soc_data *soc = eth->soc;
2519 struct mtk_tx_ring *ring = ð->tx_ring;
2520 int i, sz = soc->tx.desc_size;
2521 struct mtk_tx_dma_v2 *txd;
2522 int ring_size;
2523 u32 ofs, val;
2524
2525 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
2526 ring_size = MTK_QDMA_RING_SIZE;
2527 else
2528 ring_size = soc->tx.dma_size;
2529
2530 ring->buf = kcalloc(ring_size, sizeof(*ring->buf),
2531 GFP_KERNEL);
2532 if (!ring->buf)
2533 goto no_tx_mem;
2534
2535 if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
2536 ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
2537 ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
2538 } else {
2539 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2540 &ring->phys, GFP_KERNEL);
2541 }
2542
2543 if (!ring->dma)
2544 goto no_tx_mem;
2545
2546 for (i = 0; i < ring_size; i++) {
2547 int next = (i + 1) % ring_size;
2548 u32 next_ptr = ring->phys + next * sz;
2549
2550 txd = ring->dma + i * sz;
2551 txd->txd2 = next_ptr;
2552 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
2553 txd->txd4 = 0;
2554 if (mtk_is_netsys_v2_or_greater(eth)) {
2555 txd->txd5 = 0;
2556 txd->txd6 = 0;
2557 txd->txd7 = 0;
2558 txd->txd8 = 0;
2559 }
2560 }
2561
2562 /* On MT7688 (PDMA only) this driver uses the ring->dma structs
2563 * only as the framework. The real HW descriptors are the PDMA
2564 * descriptors in ring->dma_pdma.
2565 */
2566 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2567 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
2568 &ring->phys_pdma, GFP_KERNEL);
2569 if (!ring->dma_pdma)
2570 goto no_tx_mem;
2571
2572 for (i = 0; i < ring_size; i++) {
2573 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
2574 ring->dma_pdma[i].txd4 = 0;
2575 }
2576 }
2577
2578 ring->dma_size = ring_size;
2579 atomic_set(&ring->free_count, ring_size - 2);
2580 ring->next_free = ring->dma;
2581 ring->last_free = (void *)txd;
2582 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz));
2583 ring->thresh = MAX_SKB_FRAGS;
2584
2585 /* make sure that all changes to the dma ring are flushed before we
2586 * continue
2587 */
2588 wmb();
2589
2590 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
2591 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
2592 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
2593 mtk_w32(eth,
2594 ring->phys + ((ring_size - 1) * sz),
2595 soc->reg_map->qdma.crx_ptr);
2596 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
2597
2598 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) {
2599 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES;
2600 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
2601
2602 val = MTK_QTX_SCH_MIN_RATE_EN |
2603 /* minimum: 10 Mbps */
2604 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
2605 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
2606 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
2607 if (mtk_is_netsys_v1(eth))
2608 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
2609 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
2610 ofs += MTK_QTX_OFFSET;
2611 }
2612 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16);
2613 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);
2614 if (mtk_is_netsys_v2_or_greater(eth))
2615 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
2616 } else {
2617 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
2618 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
2619 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
2620 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
2621 }
2622
2623 return 0;
2624
2625 no_tx_mem:
2626 return -ENOMEM;
2627 }
2628
mtk_tx_clean(struct mtk_eth * eth)2629 static void mtk_tx_clean(struct mtk_eth *eth)
2630 {
2631 const struct mtk_soc_data *soc = eth->soc;
2632 struct mtk_tx_ring *ring = ð->tx_ring;
2633 int i;
2634
2635 if (ring->buf) {
2636 for (i = 0; i < ring->dma_size; i++)
2637 mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
2638 kfree(ring->buf);
2639 ring->buf = NULL;
2640 }
2641 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
2642 dma_free_coherent(eth->dma_dev,
2643 ring->dma_size * soc->tx.desc_size,
2644 ring->dma, ring->phys);
2645 ring->dma = NULL;
2646 }
2647
2648 if (ring->dma_pdma) {
2649 dma_free_coherent(eth->dma_dev,
2650 ring->dma_size * soc->tx.desc_size,
2651 ring->dma_pdma, ring->phys_pdma);
2652 ring->dma_pdma = NULL;
2653 }
2654 }
2655
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)2656 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
2657 {
2658 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
2659 const struct mtk_soc_data *soc = eth->soc;
2660 struct mtk_rx_ring *ring;
2661 int rx_data_len, rx_dma_size, tx_ring_size;
2662 int i;
2663
2664 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2665 tx_ring_size = MTK_QDMA_RING_SIZE;
2666 else
2667 tx_ring_size = soc->tx.dma_size;
2668
2669 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2670 if (ring_no)
2671 return -EINVAL;
2672 ring = ð->rx_ring_qdma;
2673 } else {
2674 ring = ð->rx_ring[ring_no];
2675 }
2676
2677 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
2678 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
2679 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
2680 } else {
2681 rx_data_len = ETH_DATA_LEN;
2682 rx_dma_size = soc->rx.dma_size;
2683 }
2684
2685 ring->frag_size = mtk_max_frag_size(rx_data_len);
2686 ring->buf_size = mtk_max_buf_size(ring->frag_size);
2687 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
2688 GFP_KERNEL);
2689 if (!ring->data)
2690 return -ENOMEM;
2691
2692 if (mtk_page_pool_enabled(eth)) {
2693 struct page_pool *pp;
2694
2695 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
2696 rx_dma_size);
2697 if (IS_ERR(pp))
2698 return PTR_ERR(pp);
2699
2700 ring->page_pool = pp;
2701 }
2702
2703 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
2704 rx_flag != MTK_RX_FLAGS_NORMAL) {
2705 ring->dma = dma_alloc_coherent(eth->dma_dev,
2706 rx_dma_size * eth->soc->rx.desc_size,
2707 &ring->phys, GFP_KERNEL);
2708 } else {
2709 struct mtk_tx_ring *tx_ring = ð->tx_ring;
2710
2711 ring->dma = tx_ring->dma + tx_ring_size *
2712 eth->soc->tx.desc_size * (ring_no + 1);
2713 ring->phys = tx_ring->phys + tx_ring_size *
2714 eth->soc->tx.desc_size * (ring_no + 1);
2715 }
2716
2717 if (!ring->dma)
2718 return -ENOMEM;
2719
2720 for (i = 0; i < rx_dma_size; i++) {
2721 struct mtk_rx_dma_v2 *rxd;
2722 dma_addr_t dma_addr;
2723 void *data;
2724
2725 rxd = ring->dma + i * eth->soc->rx.desc_size;
2726 if (ring->page_pool) {
2727 data = mtk_page_pool_get_buff(ring->page_pool,
2728 &dma_addr, GFP_KERNEL);
2729 if (!data)
2730 return -ENOMEM;
2731 } else {
2732 if (ring->frag_size <= PAGE_SIZE)
2733 data = netdev_alloc_frag(ring->frag_size);
2734 else
2735 data = mtk_max_lro_buf_alloc(GFP_KERNEL);
2736
2737 if (!data)
2738 return -ENOMEM;
2739
2740 dma_addr = dma_map_single(eth->dma_dev,
2741 data + NET_SKB_PAD + eth->ip_align,
2742 ring->buf_size, DMA_FROM_DEVICE);
2743 if (unlikely(dma_mapping_error(eth->dma_dev,
2744 dma_addr))) {
2745 skb_free_frag(data);
2746 return -ENOMEM;
2747 }
2748 }
2749 rxd->rxd1 = (unsigned int)dma_addr;
2750 ring->data[i] = data;
2751
2752 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2753 rxd->rxd2 = RX_DMA_LSO;
2754 else
2755 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
2756
2757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2758 rxd->rxd2 |= RX_DMA_PREP_ADDR64(dma_addr);
2759
2760 rxd->rxd3 = 0;
2761 rxd->rxd4 = 0;
2762 if (mtk_is_netsys_v3_or_greater(eth)) {
2763 rxd->rxd5 = 0;
2764 rxd->rxd6 = 0;
2765 rxd->rxd7 = 0;
2766 rxd->rxd8 = 0;
2767 }
2768 }
2769
2770 ring->dma_size = rx_dma_size;
2771 ring->calc_idx_update = false;
2772 ring->calc_idx = rx_dma_size - 1;
2773 if (rx_flag == MTK_RX_FLAGS_QDMA)
2774 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +
2775 ring_no * MTK_QRX_OFFSET;
2776 else
2777 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +
2778 ring_no * MTK_QRX_OFFSET;
2779 /* make sure that all changes to the dma ring are flushed before we
2780 * continue
2781 */
2782 wmb();
2783
2784 if (rx_flag == MTK_RX_FLAGS_QDMA) {
2785 mtk_w32(eth, ring->phys,
2786 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2787 mtk_w32(eth, rx_dma_size,
2788 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2789 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2790 reg_map->qdma.rst_idx);
2791 } else {
2792 mtk_w32(eth, ring->phys,
2793 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);
2794 mtk_w32(eth, rx_dma_size,
2795 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);
2796 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no),
2797 reg_map->pdma.rst_idx);
2798 }
2799 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
2800
2801 return 0;
2802 }
2803
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring,bool in_sram)2804 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
2805 {
2806 u64 addr64 = 0;
2807 int i;
2808
2809 if (ring->data && ring->dma) {
2810 for (i = 0; i < ring->dma_size; i++) {
2811 struct mtk_rx_dma *rxd;
2812
2813 if (!ring->data[i])
2814 continue;
2815
2816 rxd = ring->dma + i * eth->soc->rx.desc_size;
2817 if (!rxd->rxd1)
2818 continue;
2819
2820 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA))
2821 addr64 = RX_DMA_GET_ADDR64(rxd->rxd2);
2822
2823 dma_unmap_single(eth->dma_dev, ((u64)rxd->rxd1 | addr64),
2824 ring->buf_size, DMA_FROM_DEVICE);
2825 mtk_rx_put_buff(ring, ring->data[i], false);
2826 }
2827 kfree(ring->data);
2828 ring->data = NULL;
2829 }
2830
2831 if (!in_sram && ring->dma) {
2832 dma_free_coherent(eth->dma_dev,
2833 ring->dma_size * eth->soc->rx.desc_size,
2834 ring->dma, ring->phys);
2835 ring->dma = NULL;
2836 }
2837
2838 if (ring->page_pool) {
2839 if (xdp_rxq_info_is_reg(&ring->xdp_q))
2840 xdp_rxq_info_unreg(&ring->xdp_q);
2841 page_pool_destroy(ring->page_pool);
2842 ring->page_pool = NULL;
2843 }
2844 }
2845
mtk_hwlro_rx_init(struct mtk_eth * eth)2846 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
2847 {
2848 int i;
2849 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
2850 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
2851
2852 /* set LRO rings to auto-learn modes */
2853 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
2854
2855 /* validate LRO ring */
2856 ring_ctrl_dw2 |= MTK_RING_VLD;
2857
2858 /* set AGE timer (unit: 20us) */
2859 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
2860 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
2861
2862 /* set max AGG timer (unit: 20us) */
2863 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
2864
2865 /* set max LRO AGG count */
2866 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
2867 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
2868
2869 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2870 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
2871 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
2872 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
2873 }
2874
2875 /* IPv4 checksum update enable */
2876 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
2877
2878 /* switch priority comparison to packet count mode */
2879 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
2880
2881 /* bandwidth threshold setting */
2882 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
2883
2884 /* auto-learn score delta setting */
2885 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
2886
2887 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
2888 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
2889 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
2890
2891 /* set HW LRO mode & the max aggregation count for rx packets */
2892 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
2893
2894 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
2895 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
2896
2897 /* enable HW LRO */
2898 lro_ctrl_dw0 |= MTK_LRO_EN;
2899
2900 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
2901 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
2902
2903 return 0;
2904 }
2905
mtk_hwlro_rx_uninit(struct mtk_eth * eth)2906 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
2907 {
2908 int i;
2909 u32 val;
2910
2911 /* relinquish lro rings, flush aggregated packets */
2912 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
2913
2914 /* wait for relinquishments done */
2915 for (i = 0; i < 10; i++) {
2916 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
2917 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
2918 msleep(20);
2919 continue;
2920 }
2921 break;
2922 }
2923
2924 /* invalidate lro rings */
2925 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2926 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
2927
2928 /* disable HW LRO */
2929 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
2930 }
2931
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)2932 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
2933 {
2934 u32 reg_val;
2935
2936 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2937
2938 /* invalidate the IP setting */
2939 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2940
2941 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
2942
2943 /* validate the IP setting */
2944 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2945 }
2946
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)2947 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
2948 {
2949 u32 reg_val;
2950
2951 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
2952
2953 /* invalidate the IP setting */
2954 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
2955
2956 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
2957 }
2958
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)2959 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
2960 {
2961 int cnt = 0;
2962 int i;
2963
2964 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
2965 if (mac->hwlro_ip[i])
2966 cnt++;
2967 }
2968
2969 return cnt;
2970 }
2971
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2972 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
2973 struct ethtool_rxnfc *cmd)
2974 {
2975 struct ethtool_rx_flow_spec *fsp =
2976 (struct ethtool_rx_flow_spec *)&cmd->fs;
2977 struct mtk_mac *mac = netdev_priv(dev);
2978 struct mtk_eth *eth = mac->hw;
2979 int hwlro_idx;
2980
2981 if ((fsp->flow_type != TCP_V4_FLOW) ||
2982 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
2983 (fsp->location > 1))
2984 return -EINVAL;
2985
2986 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
2987 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
2988
2989 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2990
2991 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
2992
2993 return 0;
2994 }
2995
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)2996 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
2997 struct ethtool_rxnfc *cmd)
2998 {
2999 struct ethtool_rx_flow_spec *fsp =
3000 (struct ethtool_rx_flow_spec *)&cmd->fs;
3001 struct mtk_mac *mac = netdev_priv(dev);
3002 struct mtk_eth *eth = mac->hw;
3003 int hwlro_idx;
3004
3005 if (fsp->location > 1)
3006 return -EINVAL;
3007
3008 mac->hwlro_ip[fsp->location] = 0;
3009 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
3010
3011 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
3012
3013 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
3014
3015 return 0;
3016 }
3017
mtk_hwlro_netdev_disable(struct net_device * dev)3018 static void mtk_hwlro_netdev_disable(struct net_device *dev)
3019 {
3020 struct mtk_mac *mac = netdev_priv(dev);
3021 struct mtk_eth *eth = mac->hw;
3022 int i, hwlro_idx;
3023
3024 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
3025 mac->hwlro_ip[i] = 0;
3026 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
3027
3028 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
3029 }
3030
3031 mac->hwlro_ip_cnt = 0;
3032 }
3033
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)3034 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
3035 struct ethtool_rxnfc *cmd)
3036 {
3037 struct mtk_mac *mac = netdev_priv(dev);
3038 struct ethtool_rx_flow_spec *fsp =
3039 (struct ethtool_rx_flow_spec *)&cmd->fs;
3040
3041 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip))
3042 return -EINVAL;
3043
3044 /* only tcp dst ipv4 is meaningful, others are meaningless */
3045 fsp->flow_type = TCP_V4_FLOW;
3046 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
3047 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
3048
3049 fsp->h_u.tcp_ip4_spec.ip4src = 0;
3050 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
3051 fsp->h_u.tcp_ip4_spec.psrc = 0;
3052 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
3053 fsp->h_u.tcp_ip4_spec.pdst = 0;
3054 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
3055 fsp->h_u.tcp_ip4_spec.tos = 0;
3056 fsp->m_u.tcp_ip4_spec.tos = 0xff;
3057
3058 return 0;
3059 }
3060
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3061 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
3062 struct ethtool_rxnfc *cmd,
3063 u32 *rule_locs)
3064 {
3065 struct mtk_mac *mac = netdev_priv(dev);
3066 int cnt = 0;
3067 int i;
3068
3069 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
3070 if (cnt == cmd->rule_cnt)
3071 return -EMSGSIZE;
3072
3073 if (mac->hwlro_ip[i]) {
3074 rule_locs[cnt] = i;
3075 cnt++;
3076 }
3077 }
3078
3079 cmd->rule_cnt = cnt;
3080
3081 return 0;
3082 }
3083
mtk_fix_features(struct net_device * dev,netdev_features_t features)3084 static netdev_features_t mtk_fix_features(struct net_device *dev,
3085 netdev_features_t features)
3086 {
3087 if (!(features & NETIF_F_LRO)) {
3088 struct mtk_mac *mac = netdev_priv(dev);
3089 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
3090
3091 if (ip_cnt) {
3092 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
3093
3094 features |= NETIF_F_LRO;
3095 }
3096 }
3097
3098 return features;
3099 }
3100
mtk_set_features(struct net_device * dev,netdev_features_t features)3101 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
3102 {
3103 netdev_features_t diff = dev->features ^ features;
3104
3105 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
3106 mtk_hwlro_netdev_disable(dev);
3107
3108 return 0;
3109 }
3110
3111 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)3112 static int mtk_dma_busy_wait(struct mtk_eth *eth)
3113 {
3114 unsigned int reg;
3115 int ret;
3116 u32 val;
3117
3118 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3119 reg = eth->soc->reg_map->qdma.glo_cfg;
3120 else
3121 reg = eth->soc->reg_map->pdma.glo_cfg;
3122
3123 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
3124 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
3125 5, MTK_DMA_BUSY_TIMEOUT_US);
3126 if (ret)
3127 dev_err(eth->dev, "DMA init timeout\n");
3128
3129 return ret;
3130 }
3131
mtk_dma_init(struct mtk_eth * eth)3132 static int mtk_dma_init(struct mtk_eth *eth)
3133 {
3134 int err;
3135 u32 i;
3136
3137 if (mtk_dma_busy_wait(eth))
3138 return -EBUSY;
3139
3140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3141 /* QDMA needs scratch memory for internal reordering of the
3142 * descriptors
3143 */
3144 err = mtk_init_fq_dma(eth);
3145 if (err)
3146 return err;
3147 }
3148
3149 err = mtk_tx_alloc(eth);
3150 if (err)
3151 return err;
3152
3153 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3154 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
3155 if (err)
3156 return err;
3157 }
3158
3159 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
3160 if (err)
3161 return err;
3162
3163 if (eth->hwlro) {
3164 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
3165 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
3166 if (err)
3167 return err;
3168 }
3169 err = mtk_hwlro_rx_init(eth);
3170 if (err)
3171 return err;
3172 }
3173
3174 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3175 /* Enable random early drop and set drop threshold
3176 * automatically
3177 */
3178 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
3179 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);
3180 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);
3181 }
3182
3183 return 0;
3184 }
3185
mtk_dma_free(struct mtk_eth * eth)3186 static void mtk_dma_free(struct mtk_eth *eth)
3187 {
3188 const struct mtk_soc_data *soc = eth->soc;
3189 int i, j, txqs = 1;
3190
3191 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3192 txqs = MTK_QDMA_NUM_QUEUES;
3193
3194 for (i = 0; i < MTK_MAX_DEVS; i++) {
3195 if (!eth->netdev[i])
3196 continue;
3197
3198 for (j = 0; j < txqs; j++)
3199 netdev_tx_reset_subqueue(eth->netdev[i], j);
3200 }
3201
3202 if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
3203 dma_free_coherent(eth->dma_dev,
3204 MTK_QDMA_RING_SIZE * soc->tx.desc_size,
3205 eth->scratch_ring, eth->phy_scratch_ring);
3206 eth->scratch_ring = NULL;
3207 eth->phy_scratch_ring = 0;
3208 }
3209 mtk_tx_clean(eth);
3210 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
3211 mtk_rx_clean(eth, ð->rx_ring_qdma, false);
3212
3213 if (eth->hwlro) {
3214 mtk_hwlro_rx_uninit(eth);
3215 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
3216 mtk_rx_clean(eth, ð->rx_ring[i], false);
3217 }
3218
3219 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) {
3220 kfree(eth->scratch_head[i]);
3221 eth->scratch_head[i] = NULL;
3222 }
3223 }
3224
mtk_hw_reset_check(struct mtk_eth * eth)3225 static bool mtk_hw_reset_check(struct mtk_eth *eth)
3226 {
3227 u32 val = mtk_r32(eth, MTK_INT_STATUS2);
3228
3229 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) ||
3230 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) ||
3231 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL);
3232 }
3233
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)3234 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
3235 {
3236 struct mtk_mac *mac = netdev_priv(dev);
3237 struct mtk_eth *eth = mac->hw;
3238
3239 if (test_bit(MTK_RESETTING, ð->state))
3240 return;
3241
3242 if (!mtk_hw_reset_check(eth))
3243 return;
3244
3245 eth->netdev[mac->id]->stats.tx_errors++;
3246 netif_err(eth, tx_err, dev, "transmit timed out\n");
3247
3248 schedule_work(ð->pending_work);
3249 }
3250
mtk_handle_irq_rx(int irq,void * _eth)3251 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
3252 {
3253 struct mtk_eth *eth = _eth;
3254
3255 eth->rx_events++;
3256 if (likely(napi_schedule_prep(ð->rx_napi))) {
3257 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3258 __napi_schedule(ð->rx_napi);
3259 }
3260
3261 return IRQ_HANDLED;
3262 }
3263
mtk_handle_irq_tx(int irq,void * _eth)3264 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
3265 {
3266 struct mtk_eth *eth = _eth;
3267
3268 eth->tx_events++;
3269 if (likely(napi_schedule_prep(ð->tx_napi))) {
3270 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3271 __napi_schedule(ð->tx_napi);
3272 }
3273
3274 return IRQ_HANDLED;
3275 }
3276
mtk_handle_irq(int irq,void * _eth)3277 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
3278 {
3279 struct mtk_eth *eth = _eth;
3280 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3281
3282 if (mtk_r32(eth, reg_map->pdma.irq_mask) &
3283 eth->soc->rx.irq_done_mask) {
3284 if (mtk_r32(eth, reg_map->pdma.irq_status) &
3285 eth->soc->rx.irq_done_mask)
3286 mtk_handle_irq_rx(irq, _eth);
3287 }
3288 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
3289 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)
3290 mtk_handle_irq_tx(irq, _eth);
3291 }
3292
3293 return IRQ_HANDLED;
3294 }
3295
3296 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)3297 static void mtk_poll_controller(struct net_device *dev)
3298 {
3299 struct mtk_mac *mac = netdev_priv(dev);
3300 struct mtk_eth *eth = mac->hw;
3301
3302 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3303 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3304 mtk_handle_irq_rx(eth->irq[2], dev);
3305 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3306 mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
3307 }
3308 #endif
3309
mtk_start_dma(struct mtk_eth * eth)3310 static int mtk_start_dma(struct mtk_eth *eth)
3311 {
3312 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
3313 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3314 int err;
3315
3316 err = mtk_dma_init(eth);
3317 if (err) {
3318 mtk_dma_free(eth);
3319 return err;
3320 }
3321
3322 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
3323 val = mtk_r32(eth, reg_map->qdma.glo_cfg);
3324 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3325 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
3326 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
3327
3328 if (mtk_is_netsys_v2_or_greater(eth))
3329 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
3330 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
3331 MTK_CHK_DDONE_EN;
3332 else
3333 val |= MTK_RX_BT_32DWORDS;
3334 mtk_w32(eth, val, reg_map->qdma.glo_cfg);
3335
3336 mtk_w32(eth,
3337 MTK_RX_DMA_EN | rx_2b_offset |
3338 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
3339 reg_map->pdma.glo_cfg);
3340 } else {
3341 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
3342 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
3343 reg_map->pdma.glo_cfg);
3344 }
3345
3346 return 0;
3347 }
3348
mtk_gdm_config(struct mtk_eth * eth,u32 id,u32 config)3349 static void mtk_gdm_config(struct mtk_eth *eth, u32 id, u32 config)
3350 {
3351 u32 val;
3352
3353 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3354 return;
3355
3356 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(id));
3357
3358 /* default setup the forward port to send frame to PDMA */
3359 val &= ~0xffff;
3360
3361 /* Enable RX checksum */
3362 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
3363
3364 val |= config;
3365
3366 if (eth->netdev[id] && netdev_uses_dsa(eth->netdev[id]))
3367 val |= MTK_GDMA_SPECIAL_TAG;
3368
3369 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(id));
3370 }
3371
3372
mtk_uses_dsa(struct net_device * dev)3373 static bool mtk_uses_dsa(struct net_device *dev)
3374 {
3375 #if IS_ENABLED(CONFIG_NET_DSA)
3376 return netdev_uses_dsa(dev) &&
3377 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
3378 #else
3379 return false;
3380 #endif
3381 }
3382
mtk_device_event(struct notifier_block * n,unsigned long event,void * ptr)3383 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr)
3384 {
3385 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier);
3386 struct mtk_eth *eth = mac->hw;
3387 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3388 struct ethtool_link_ksettings s;
3389 struct net_device *ldev;
3390 struct list_head *iter;
3391 struct dsa_port *dp;
3392
3393 if (event != NETDEV_CHANGE)
3394 return NOTIFY_DONE;
3395
3396 netdev_for_each_lower_dev(dev, ldev, iter) {
3397 if (netdev_priv(ldev) == mac)
3398 goto found;
3399 }
3400
3401 return NOTIFY_DONE;
3402
3403 found:
3404 if (!dsa_user_dev_check(dev))
3405 return NOTIFY_DONE;
3406
3407 if (__ethtool_get_link_ksettings(dev, &s))
3408 return NOTIFY_DONE;
3409
3410 if (s.base.speed == 0 || s.base.speed == ((__u32)-1))
3411 return NOTIFY_DONE;
3412
3413 dp = dsa_port_from_netdev(dev);
3414 if (dp->index >= MTK_QDMA_NUM_QUEUES)
3415 return NOTIFY_DONE;
3416
3417 if (mac->speed > 0 && mac->speed <= s.base.speed)
3418 s.base.speed = 0;
3419
3420 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed);
3421
3422 return NOTIFY_DONE;
3423 }
3424
mtk_open(struct net_device * dev)3425 static int mtk_open(struct net_device *dev)
3426 {
3427 struct mtk_mac *mac = netdev_priv(dev);
3428 struct mtk_eth *eth = mac->hw;
3429 struct mtk_mac *target_mac;
3430 int i, err, ppe_num;
3431
3432 ppe_num = eth->soc->ppe_num;
3433
3434 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
3435 if (err) {
3436 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
3437 err);
3438 return err;
3439 }
3440
3441 /* we run 2 netdevs on the same dma ring so we only bring it up once */
3442 if (!refcount_read(ð->dma_refcnt)) {
3443 const struct mtk_soc_data *soc = eth->soc;
3444 u32 gdm_config;
3445 int i;
3446
3447 err = mtk_start_dma(eth);
3448 if (err) {
3449 phylink_disconnect_phy(mac->phylink);
3450 return err;
3451 }
3452
3453 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3454 mtk_ppe_start(eth->ppe[i]);
3455
3456 for (i = 0; i < MTK_MAX_DEVS; i++) {
3457 if (!eth->netdev[i])
3458 continue;
3459
3460 target_mac = netdev_priv(eth->netdev[i]);
3461 if (!soc->offload_version) {
3462 target_mac->ppe_idx = 0;
3463 gdm_config = MTK_GDMA_TO_PDMA;
3464 } else if (ppe_num >= 3 && target_mac->id == 2) {
3465 target_mac->ppe_idx = 2;
3466 gdm_config = soc->reg_map->gdma_to_ppe[2];
3467 } else if (ppe_num >= 2 && target_mac->id == 1) {
3468 target_mac->ppe_idx = 1;
3469 gdm_config = soc->reg_map->gdma_to_ppe[1];
3470 } else {
3471 target_mac->ppe_idx = 0;
3472 gdm_config = soc->reg_map->gdma_to_ppe[0];
3473 }
3474 mtk_gdm_config(eth, target_mac->id, gdm_config);
3475 }
3476
3477 napi_enable(ð->tx_napi);
3478 napi_enable(ð->rx_napi);
3479 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
3480 mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
3481 refcount_set(ð->dma_refcnt, 1);
3482 } else {
3483 refcount_inc(ð->dma_refcnt);
3484 }
3485
3486 phylink_start(mac->phylink);
3487 netif_tx_start_all_queues(dev);
3488
3489 if (mtk_is_netsys_v2_or_greater(eth))
3490 return 0;
3491
3492 if (mtk_uses_dsa(dev) && !eth->prog) {
3493 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
3494 struct metadata_dst *md_dst = eth->dsa_meta[i];
3495
3496 if (md_dst)
3497 continue;
3498
3499 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX,
3500 GFP_KERNEL);
3501 if (!md_dst)
3502 return -ENOMEM;
3503
3504 md_dst->u.port_info.port_id = i;
3505 eth->dsa_meta[i] = md_dst;
3506 }
3507 } else {
3508 /* Hardware DSA untagging and VLAN RX offloading need to be
3509 * disabled if at least one MAC does not use DSA.
3510 */
3511 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
3512
3513 val &= ~MTK_CDMP_STAG_EN;
3514 mtk_w32(eth, val, MTK_CDMP_IG_CTRL);
3515
3516 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL);
3517 }
3518
3519 return 0;
3520 }
3521
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)3522 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
3523 {
3524 u32 val;
3525 int i;
3526
3527 /* stop the dma engine */
3528 spin_lock_bh(ð->page_lock);
3529 val = mtk_r32(eth, glo_cfg);
3530 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
3531 glo_cfg);
3532 spin_unlock_bh(ð->page_lock);
3533
3534 /* wait for dma stop */
3535 for (i = 0; i < 10; i++) {
3536 val = mtk_r32(eth, glo_cfg);
3537 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
3538 msleep(20);
3539 continue;
3540 }
3541 break;
3542 }
3543 }
3544
mtk_stop(struct net_device * dev)3545 static int mtk_stop(struct net_device *dev)
3546 {
3547 struct mtk_mac *mac = netdev_priv(dev);
3548 struct mtk_eth *eth = mac->hw;
3549 int i;
3550
3551 phylink_stop(mac->phylink);
3552
3553 netif_tx_disable(dev);
3554
3555 phylink_disconnect_phy(mac->phylink);
3556
3557 /* only shutdown DMA if this is the last user */
3558 if (!refcount_dec_and_test(ð->dma_refcnt))
3559 return 0;
3560
3561 for (i = 0; i < MTK_MAX_DEVS; i++)
3562 mtk_gdm_config(eth, i, MTK_GDMA_DROP_ALL);
3563
3564 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
3565 mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
3566 napi_disable(ð->tx_napi);
3567 napi_disable(ð->rx_napi);
3568
3569 cancel_work_sync(ð->rx_dim.work);
3570 cancel_work_sync(ð->tx_dim.work);
3571
3572 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3573 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);
3574 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);
3575
3576 mtk_dma_free(eth);
3577
3578 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
3579 mtk_ppe_stop(eth->ppe[i]);
3580
3581 return 0;
3582 }
3583
mtk_xdp_setup(struct net_device * dev,struct bpf_prog * prog,struct netlink_ext_ack * extack)3584 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog,
3585 struct netlink_ext_ack *extack)
3586 {
3587 struct mtk_mac *mac = netdev_priv(dev);
3588 struct mtk_eth *eth = mac->hw;
3589 struct bpf_prog *old_prog;
3590 bool need_update;
3591
3592 if (eth->hwlro) {
3593 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO");
3594 return -EOPNOTSUPP;
3595 }
3596
3597 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) {
3598 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
3599 return -EOPNOTSUPP;
3600 }
3601
3602 need_update = !!eth->prog != !!prog;
3603 if (netif_running(dev) && need_update)
3604 mtk_stop(dev);
3605
3606 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held());
3607 if (old_prog)
3608 bpf_prog_put(old_prog);
3609
3610 if (netif_running(dev) && need_update)
3611 return mtk_open(dev);
3612
3613 return 0;
3614 }
3615
mtk_xdp(struct net_device * dev,struct netdev_bpf * xdp)3616 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3617 {
3618 switch (xdp->command) {
3619 case XDP_SETUP_PROG:
3620 return mtk_xdp_setup(dev, xdp->prog, xdp->extack);
3621 default:
3622 return -EINVAL;
3623 }
3624 }
3625
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)3626 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
3627 {
3628 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3629 reset_bits,
3630 reset_bits);
3631
3632 usleep_range(1000, 1100);
3633 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
3634 reset_bits,
3635 ~reset_bits);
3636 mdelay(10);
3637 }
3638
mtk_clk_disable(struct mtk_eth * eth)3639 static void mtk_clk_disable(struct mtk_eth *eth)
3640 {
3641 int clk;
3642
3643 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
3644 clk_disable_unprepare(eth->clks[clk]);
3645 }
3646
mtk_clk_enable(struct mtk_eth * eth)3647 static int mtk_clk_enable(struct mtk_eth *eth)
3648 {
3649 int clk, ret;
3650
3651 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
3652 ret = clk_prepare_enable(eth->clks[clk]);
3653 if (ret)
3654 goto err_disable_clks;
3655 }
3656
3657 return 0;
3658
3659 err_disable_clks:
3660 while (--clk >= 0)
3661 clk_disable_unprepare(eth->clks[clk]);
3662
3663 return ret;
3664 }
3665
mtk_dim_rx(struct work_struct * work)3666 static void mtk_dim_rx(struct work_struct *work)
3667 {
3668 struct dim *dim = container_of(work, struct dim, work);
3669 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
3670 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3671 struct dim_cq_moder cur_profile;
3672 u32 val, cur;
3673
3674 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,
3675 dim->profile_ix);
3676 spin_lock_bh(ð->dim_lock);
3677
3678 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3679 val &= MTK_PDMA_DELAY_TX_MASK;
3680 val |= MTK_PDMA_DELAY_RX_EN;
3681
3682 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3683 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;
3684
3685 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3686 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
3687
3688 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3689 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3690 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3691
3692 spin_unlock_bh(ð->dim_lock);
3693
3694 dim->state = DIM_START_MEASURE;
3695 }
3696
mtk_dim_tx(struct work_struct * work)3697 static void mtk_dim_tx(struct work_struct *work)
3698 {
3699 struct dim *dim = container_of(work, struct dim, work);
3700 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
3701 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3702 struct dim_cq_moder cur_profile;
3703 u32 val, cur;
3704
3705 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,
3706 dim->profile_ix);
3707 spin_lock_bh(ð->dim_lock);
3708
3709 val = mtk_r32(eth, reg_map->pdma.delay_irq);
3710 val &= MTK_PDMA_DELAY_RX_MASK;
3711 val |= MTK_PDMA_DELAY_TX_EN;
3712
3713 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);
3714 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;
3715
3716 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
3717 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
3718
3719 mtk_w32(eth, val, reg_map->pdma.delay_irq);
3720 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
3721 mtk_w32(eth, val, reg_map->qdma.delay_irq);
3722
3723 spin_unlock_bh(ð->dim_lock);
3724
3725 dim->state = DIM_START_MEASURE;
3726 }
3727
mtk_set_mcr_max_rx(struct mtk_mac * mac,u32 val)3728 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)
3729 {
3730 struct mtk_eth *eth = mac->hw;
3731 u32 mcr_cur, mcr_new;
3732
3733 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3734 return;
3735
3736 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
3737 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;
3738
3739 if (val <= 1518)
3740 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);
3741 else if (val <= 1536)
3742 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);
3743 else if (val <= 1552)
3744 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);
3745 else
3746 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);
3747
3748 if (mcr_new != mcr_cur)
3749 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
3750 }
3751
mtk_hw_reset(struct mtk_eth * eth)3752 static void mtk_hw_reset(struct mtk_eth *eth)
3753 {
3754 u32 val;
3755
3756 if (mtk_is_netsys_v2_or_greater(eth))
3757 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
3758
3759 if (mtk_is_netsys_v3_or_greater(eth)) {
3760 val = RSTCTRL_PPE0_V3;
3761
3762 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3763 val |= RSTCTRL_PPE1_V3;
3764
3765 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3766 val |= RSTCTRL_PPE2;
3767
3768 val |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3769 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3770 val = RSTCTRL_PPE0_V2;
3771
3772 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3773 val |= RSTCTRL_PPE1;
3774 } else {
3775 val = RSTCTRL_PPE0;
3776 }
3777
3778 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
3779
3780 if (mtk_is_netsys_v3_or_greater(eth))
3781 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3782 0x6f8ff);
3783 else if (mtk_is_netsys_v2_or_greater(eth))
3784 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
3785 0x3ffffff);
3786 }
3787
mtk_hw_reset_read(struct mtk_eth * eth)3788 static u32 mtk_hw_reset_read(struct mtk_eth *eth)
3789 {
3790 u32 val;
3791
3792 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val);
3793 return val;
3794 }
3795
mtk_hw_warm_reset(struct mtk_eth * eth)3796 static void mtk_hw_warm_reset(struct mtk_eth *eth)
3797 {
3798 u32 rst_mask, val;
3799
3800 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE,
3801 RSTCTRL_FE);
3802 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val,
3803 val & RSTCTRL_FE, 1, 1000)) {
3804 dev_err(eth->dev, "warm reset failed\n");
3805 mtk_hw_reset(eth);
3806 return;
3807 }
3808
3809 if (mtk_is_netsys_v3_or_greater(eth)) {
3810 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V3;
3811 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3812 rst_mask |= RSTCTRL_PPE1_V3;
3813 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
3814 rst_mask |= RSTCTRL_PPE2;
3815
3816 rst_mask |= RSTCTRL_WDMA0 | RSTCTRL_WDMA1 | RSTCTRL_WDMA2;
3817 } else if (mtk_is_netsys_v2_or_greater(eth)) {
3818 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
3819 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
3820 rst_mask |= RSTCTRL_PPE1;
3821 } else {
3822 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
3823 }
3824
3825 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
3826
3827 udelay(1);
3828 val = mtk_hw_reset_read(eth);
3829 if (!(val & rst_mask))
3830 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n",
3831 val, rst_mask);
3832
3833 rst_mask |= RSTCTRL_FE;
3834 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask);
3835
3836 udelay(1);
3837 val = mtk_hw_reset_read(eth);
3838 if (val & rst_mask)
3839 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n",
3840 val, rst_mask);
3841 }
3842
mtk_hw_check_dma_hang(struct mtk_eth * eth)3843 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
3844 {
3845 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3846 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
3847 bool oq_hang, cdm1_busy, adma_busy;
3848 bool wtx_busy, cdm_full, oq_free;
3849 u32 wdidx, val, gdm1_fc, gdm2_fc;
3850 bool qfsm_hang, qfwd_hang;
3851 bool ret = false;
3852
3853 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3854 return false;
3855
3856 /* WDMA sanity checks */
3857 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);
3858
3859 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);
3860 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val);
3861
3862 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);
3863 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val);
3864
3865 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&
3866 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&
3867 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));
3868
3869 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) {
3870 if (++eth->reset.wdma_hang_count > 2) {
3871 eth->reset.wdma_hang_count = 0;
3872 ret = true;
3873 }
3874 goto out;
3875 }
3876
3877 /* QDMA sanity checks */
3878 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);
3879 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);
3880
3881 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0;
3882 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
3883 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
3884 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
3885 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
3886 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
3887
3888 if (qfsm_hang && qfwd_hang &&
3889 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
3890 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
3891 if (++eth->reset.qdma_hang_count > 2) {
3892 eth->reset.qdma_hang_count = 0;
3893 ret = true;
3894 }
3895 goto out;
3896 }
3897
3898 /* ADMA sanity checks */
3899 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));
3900 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16));
3901 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&
3902 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));
3903
3904 if (oq_hang && cdm1_busy && adma_busy) {
3905 if (++eth->reset.adma_hang_count > 2) {
3906 eth->reset.adma_hang_count = 0;
3907 ret = true;
3908 }
3909 goto out;
3910 }
3911
3912 eth->reset.wdma_hang_count = 0;
3913 eth->reset.qdma_hang_count = 0;
3914 eth->reset.adma_hang_count = 0;
3915 out:
3916 eth->reset.wdidx = wdidx;
3917
3918 return ret;
3919 }
3920
mtk_hw_reset_monitor_work(struct work_struct * work)3921 static void mtk_hw_reset_monitor_work(struct work_struct *work)
3922 {
3923 struct delayed_work *del_work = to_delayed_work(work);
3924 struct mtk_eth *eth = container_of(del_work, struct mtk_eth,
3925 reset.monitor_work);
3926
3927 if (test_bit(MTK_RESETTING, ð->state))
3928 goto out;
3929
3930 /* DMA stuck checks */
3931 if (mtk_hw_check_dma_hang(eth))
3932 schedule_work(ð->pending_work);
3933
3934 out:
3935 schedule_delayed_work(ð->reset.monitor_work,
3936 MTK_DMA_MONITOR_TIMEOUT);
3937 }
3938
mtk_hw_init(struct mtk_eth * eth,bool reset)3939 static int mtk_hw_init(struct mtk_eth *eth, bool reset)
3940 {
3941 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
3942 ETHSYS_DMA_AG_MAP_PPE;
3943 const struct mtk_reg_map *reg_map = eth->soc->reg_map;
3944 int i, val, ret;
3945
3946 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state))
3947 return 0;
3948
3949 if (!reset) {
3950 pm_runtime_enable(eth->dev);
3951 pm_runtime_get_sync(eth->dev);
3952
3953 ret = mtk_clk_enable(eth);
3954 if (ret)
3955 goto err_disable_pm;
3956 }
3957
3958 if (eth->ethsys)
3959 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
3960 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);
3961
3962 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3963 ret = device_reset(eth->dev);
3964 if (ret) {
3965 dev_err(eth->dev, "MAC reset failed!\n");
3966 goto err_disable_pm;
3967 }
3968
3969 /* set interrupt delays based on current Net DIM sample */
3970 mtk_dim_rx(ð->rx_dim.work);
3971 mtk_dim_tx(ð->tx_dim.work);
3972
3973 /* disable delay and normal interrupt */
3974 mtk_tx_irq_disable(eth, ~0);
3975 mtk_rx_irq_disable(eth, ~0);
3976
3977 return 0;
3978 }
3979
3980 msleep(100);
3981
3982 if (reset)
3983 mtk_hw_warm_reset(eth);
3984 else
3985 mtk_hw_reset(eth);
3986
3987 /* No MT7628/88 support yet */
3988 if (reset && !MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
3989 mtk_mdio_config(eth);
3990
3991 if (mtk_is_netsys_v3_or_greater(eth)) {
3992 /* Set FE to PDMAv2 if necessary */
3993 val = mtk_r32(eth, MTK_FE_GLO_MISC);
3994 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
3995 }
3996
3997 if (eth->pctl) {
3998 /* Set GE2 driving and slew rate */
3999 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
4000
4001 /* set GE2 TDSEL */
4002 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
4003
4004 /* set GE2 TUNE */
4005 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
4006 }
4007
4008 /* Set linkdown as the default for each GMAC. Its own MCR would be set
4009 * up with the more appropriate value when mtk_mac_config call is being
4010 * invoked.
4011 */
4012 for (i = 0; i < MTK_MAX_DEVS; i++) {
4013 struct net_device *dev = eth->netdev[i];
4014
4015 if (!dev)
4016 continue;
4017
4018 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
4019 mtk_set_mcr_max_rx(netdev_priv(dev),
4020 dev->mtu + MTK_RX_ETH_HLEN);
4021 }
4022
4023 /* Indicates CDM to parse the MTK special tag from CPU
4024 * which also is working out for untag packets.
4025 */
4026 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
4027 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
4028 if (mtk_is_netsys_v1(eth)) {
4029 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
4030 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
4031
4032 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
4033 }
4034
4035 /* set interrupt delays based on current Net DIM sample */
4036 mtk_dim_rx(ð->rx_dim.work);
4037 mtk_dim_tx(ð->tx_dim.work);
4038
4039 /* disable delay and normal interrupt */
4040 mtk_tx_irq_disable(eth, ~0);
4041 mtk_rx_irq_disable(eth, ~0);
4042
4043 /* FE int grouping */
4044 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
4045 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
4046 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
4047 mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
4048 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
4049
4050 if (mtk_is_netsys_v3_or_greater(eth)) {
4051 /* PSE dummy page mechanism */
4052 mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
4053 PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
4054
4055 /* PSE free buffer drop threshold */
4056 mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
4057
4058 /* PSE should not drop port8, port9 and port13 packets from
4059 * WDMA Tx
4060 */
4061 mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
4062
4063 /* PSE should drop packets to port8, port9 and port13 on WDMA Rx
4064 * ring full
4065 */
4066 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
4067 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
4068 mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
4069
4070 /* GDM and CDM Threshold */
4071 mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
4072 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
4073
4074 /* Disable GDM1 RX CRC stripping */
4075 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
4076
4077 /* PSE GDM3 MIB counter has incorrect hw default values,
4078 * so the driver ought to read clear the values beforehand
4079 * in case ethtool retrieve wrong mib values.
4080 */
4081 for (i = 0; i < 0x80; i += 0x4)
4082 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);
4083 } else if (!mtk_is_netsys_v1(eth)) {
4084 /* PSE should not drop port8 and port9 packets from WDMA Tx */
4085 mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
4086
4087 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
4088 mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
4089
4090 /* PSE Free Queue Flow Control */
4091 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
4092
4093 /* PSE config input queue threshold */
4094 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1));
4095 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2));
4096 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3));
4097 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4));
4098 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5));
4099 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6));
4100 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7));
4101 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8));
4102
4103 /* PSE config output queue threshold */
4104 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1));
4105 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2));
4106 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3));
4107 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4));
4108 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5));
4109 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6));
4110 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7));
4111 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8));
4112
4113 /* GDM and CDM Threshold */
4114 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES);
4115 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES);
4116 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES);
4117 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES);
4118 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES);
4119 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES);
4120 }
4121
4122 return 0;
4123
4124 err_disable_pm:
4125 if (!reset) {
4126 pm_runtime_put_sync(eth->dev);
4127 pm_runtime_disable(eth->dev);
4128 }
4129
4130 return ret;
4131 }
4132
mtk_hw_deinit(struct mtk_eth * eth)4133 static int mtk_hw_deinit(struct mtk_eth *eth)
4134 {
4135 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
4136 return 0;
4137
4138 mtk_clk_disable(eth);
4139
4140 pm_runtime_put_sync(eth->dev);
4141 pm_runtime_disable(eth->dev);
4142
4143 return 0;
4144 }
4145
mtk_uninit(struct net_device * dev)4146 static void mtk_uninit(struct net_device *dev)
4147 {
4148 struct mtk_mac *mac = netdev_priv(dev);
4149 struct mtk_eth *eth = mac->hw;
4150
4151 phylink_disconnect_phy(mac->phylink);
4152 mtk_tx_irq_disable(eth, ~0);
4153 mtk_rx_irq_disable(eth, ~0);
4154 }
4155
mtk_change_mtu(struct net_device * dev,int new_mtu)4156 static int mtk_change_mtu(struct net_device *dev, int new_mtu)
4157 {
4158 int length = new_mtu + MTK_RX_ETH_HLEN;
4159 struct mtk_mac *mac = netdev_priv(dev);
4160 struct mtk_eth *eth = mac->hw;
4161
4162 if (rcu_access_pointer(eth->prog) &&
4163 length > MTK_PP_MAX_BUF_SIZE) {
4164 netdev_err(dev, "Invalid MTU for XDP mode\n");
4165 return -EINVAL;
4166 }
4167
4168 mtk_set_mcr_max_rx(mac, length);
4169 WRITE_ONCE(dev->mtu, new_mtu);
4170
4171 return 0;
4172 }
4173
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4174 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4175 {
4176 struct mtk_mac *mac = netdev_priv(dev);
4177
4178 switch (cmd) {
4179 case SIOCGMIIPHY:
4180 case SIOCGMIIREG:
4181 case SIOCSMIIREG:
4182 return phylink_mii_ioctl(mac->phylink, ifr, cmd);
4183 default:
4184 break;
4185 }
4186
4187 return -EOPNOTSUPP;
4188 }
4189
mtk_prepare_for_reset(struct mtk_eth * eth)4190 static void mtk_prepare_for_reset(struct mtk_eth *eth)
4191 {
4192 u32 val;
4193 int i;
4194
4195 /* set FE PPE ports link down */
4196 for (i = MTK_GMAC1_ID;
4197 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4198 i += 2) {
4199 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) | MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4200 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4201 val |= MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4203 val |= MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4204 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4205 }
4206
4207 /* adjust PPE configurations to prepare for reset */
4208 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
4209 mtk_ppe_prepare_reset(eth->ppe[i]);
4210
4211 /* disable NETSYS interrupts */
4212 mtk_w32(eth, 0, MTK_FE_INT_ENABLE);
4213
4214 /* force link down GMAC */
4215 for (i = 0; i < 2; i++) {
4216 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK;
4217 mtk_w32(eth, val, MTK_MAC_MCR(i));
4218 }
4219 }
4220
mtk_pending_work(struct work_struct * work)4221 static void mtk_pending_work(struct work_struct *work)
4222 {
4223 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
4224 unsigned long restart = 0;
4225 u32 val;
4226 int i;
4227
4228 rtnl_lock();
4229 set_bit(MTK_RESETTING, ð->state);
4230
4231 mtk_prepare_for_reset(eth);
4232 mtk_wed_fe_reset();
4233 /* Run again reset preliminary configuration in order to avoid any
4234 * possible race during FE reset since it can run releasing RTNL lock.
4235 */
4236 mtk_prepare_for_reset(eth);
4237
4238 /* stop all devices to make sure that dma is properly shut down */
4239 for (i = 0; i < MTK_MAX_DEVS; i++) {
4240 if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
4241 continue;
4242
4243 mtk_stop(eth->netdev[i]);
4244 __set_bit(i, &restart);
4245 }
4246
4247 usleep_range(15000, 16000);
4248
4249 if (eth->dev->pins)
4250 pinctrl_select_state(eth->dev->pins->p,
4251 eth->dev->pins->default_state);
4252 mtk_hw_init(eth, true);
4253
4254 /* restart DMA and enable IRQs */
4255 for (i = 0; i < MTK_MAX_DEVS; i++) {
4256 if (!eth->netdev[i] || !test_bit(i, &restart))
4257 continue;
4258
4259 if (mtk_open(eth->netdev[i])) {
4260 netif_alert(eth, ifup, eth->netdev[i],
4261 "Driver up/down cycle failed\n");
4262 dev_close(eth->netdev[i]);
4263 }
4264 }
4265
4266 /* set FE PPE ports link up */
4267 for (i = MTK_GMAC1_ID;
4268 i <= (mtk_is_netsys_v3_or_greater(eth) ? MTK_GMAC3_ID : MTK_GMAC2_ID);
4269 i += 2) {
4270 val = mtk_r32(eth, MTK_FE_GLO_CFG(i)) & ~MTK_FE_LINK_DOWN_P(PSE_PPE0_PORT);
4271 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
4272 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE1_PORT);
4273 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE2))
4274 val &= ~MTK_FE_LINK_DOWN_P(PSE_PPE2_PORT);
4275
4276 mtk_w32(eth, val, MTK_FE_GLO_CFG(i));
4277 }
4278
4279 clear_bit(MTK_RESETTING, ð->state);
4280
4281 mtk_wed_fe_reset_complete();
4282
4283 rtnl_unlock();
4284 }
4285
mtk_free_dev(struct mtk_eth * eth)4286 static int mtk_free_dev(struct mtk_eth *eth)
4287 {
4288 int i;
4289
4290 for (i = 0; i < MTK_MAX_DEVS; i++) {
4291 if (!eth->netdev[i])
4292 continue;
4293 free_netdev(eth->netdev[i]);
4294 }
4295
4296 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
4297 if (!eth->dsa_meta[i])
4298 break;
4299 metadata_dst_free(eth->dsa_meta[i]);
4300 }
4301
4302 return 0;
4303 }
4304
mtk_unreg_dev(struct mtk_eth * eth)4305 static int mtk_unreg_dev(struct mtk_eth *eth)
4306 {
4307 int i;
4308
4309 for (i = 0; i < MTK_MAX_DEVS; i++) {
4310 struct mtk_mac *mac;
4311 if (!eth->netdev[i])
4312 continue;
4313 mac = netdev_priv(eth->netdev[i]);
4314 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4315 unregister_netdevice_notifier(&mac->device_notifier);
4316 unregister_netdev(eth->netdev[i]);
4317 }
4318
4319 return 0;
4320 }
4321
mtk_sgmii_destroy(struct mtk_eth * eth)4322 static void mtk_sgmii_destroy(struct mtk_eth *eth)
4323 {
4324 int i;
4325
4326 for (i = 0; i < MTK_MAX_DEVS; i++)
4327 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]);
4328 }
4329
mtk_cleanup(struct mtk_eth * eth)4330 static int mtk_cleanup(struct mtk_eth *eth)
4331 {
4332 mtk_sgmii_destroy(eth);
4333 mtk_unreg_dev(eth);
4334 mtk_free_dev(eth);
4335 cancel_work_sync(ð->pending_work);
4336 cancel_delayed_work_sync(ð->reset.monitor_work);
4337
4338 return 0;
4339 }
4340
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)4341 static int mtk_get_link_ksettings(struct net_device *ndev,
4342 struct ethtool_link_ksettings *cmd)
4343 {
4344 struct mtk_mac *mac = netdev_priv(ndev);
4345
4346 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4347 return -EBUSY;
4348
4349 return phylink_ethtool_ksettings_get(mac->phylink, cmd);
4350 }
4351
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)4352 static int mtk_set_link_ksettings(struct net_device *ndev,
4353 const struct ethtool_link_ksettings *cmd)
4354 {
4355 struct mtk_mac *mac = netdev_priv(ndev);
4356
4357 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4358 return -EBUSY;
4359
4360 return phylink_ethtool_ksettings_set(mac->phylink, cmd);
4361 }
4362
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)4363 static void mtk_get_drvinfo(struct net_device *dev,
4364 struct ethtool_drvinfo *info)
4365 {
4366 struct mtk_mac *mac = netdev_priv(dev);
4367
4368 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
4369 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
4370 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
4371 }
4372
mtk_get_msglevel(struct net_device * dev)4373 static u32 mtk_get_msglevel(struct net_device *dev)
4374 {
4375 struct mtk_mac *mac = netdev_priv(dev);
4376
4377 return mac->hw->msg_enable;
4378 }
4379
mtk_set_msglevel(struct net_device * dev,u32 value)4380 static void mtk_set_msglevel(struct net_device *dev, u32 value)
4381 {
4382 struct mtk_mac *mac = netdev_priv(dev);
4383
4384 mac->hw->msg_enable = value;
4385 }
4386
mtk_nway_reset(struct net_device * dev)4387 static int mtk_nway_reset(struct net_device *dev)
4388 {
4389 struct mtk_mac *mac = netdev_priv(dev);
4390
4391 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4392 return -EBUSY;
4393
4394 if (!mac->phylink)
4395 return -ENOTSUPP;
4396
4397 return phylink_ethtool_nway_reset(mac->phylink);
4398 }
4399
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)4400 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4401 {
4402 int i;
4403
4404 switch (stringset) {
4405 case ETH_SS_STATS: {
4406 struct mtk_mac *mac = netdev_priv(dev);
4407
4408 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4409 ethtool_puts(&data, mtk_ethtool_stats[i].str);
4410 if (mtk_page_pool_enabled(mac->hw))
4411 page_pool_ethtool_stats_get_strings(data);
4412 break;
4413 }
4414 default:
4415 break;
4416 }
4417 }
4418
mtk_get_sset_count(struct net_device * dev,int sset)4419 static int mtk_get_sset_count(struct net_device *dev, int sset)
4420 {
4421 switch (sset) {
4422 case ETH_SS_STATS: {
4423 int count = ARRAY_SIZE(mtk_ethtool_stats);
4424 struct mtk_mac *mac = netdev_priv(dev);
4425
4426 if (mtk_page_pool_enabled(mac->hw))
4427 count += page_pool_ethtool_stats_get_count();
4428 return count;
4429 }
4430 default:
4431 return -EOPNOTSUPP;
4432 }
4433 }
4434
mtk_ethtool_pp_stats(struct mtk_eth * eth,u64 * data)4435 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data)
4436 {
4437 struct page_pool_stats stats = {};
4438 int i;
4439
4440 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) {
4441 struct mtk_rx_ring *ring = ð->rx_ring[i];
4442
4443 if (!ring->page_pool)
4444 continue;
4445
4446 page_pool_get_stats(ring->page_pool, &stats);
4447 }
4448 page_pool_ethtool_stats_get(data, &stats);
4449 }
4450
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)4451 static void mtk_get_ethtool_stats(struct net_device *dev,
4452 struct ethtool_stats *stats, u64 *data)
4453 {
4454 struct mtk_mac *mac = netdev_priv(dev);
4455 struct mtk_hw_stats *hwstats = mac->hw_stats;
4456 u64 *data_src, *data_dst;
4457 unsigned int start;
4458 int i;
4459
4460 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
4461 return;
4462
4463 if (netif_running(dev) && netif_device_present(dev)) {
4464 if (spin_trylock_bh(&hwstats->stats_lock)) {
4465 mtk_stats_update_mac(mac);
4466 spin_unlock_bh(&hwstats->stats_lock);
4467 }
4468 }
4469
4470 data_src = (u64 *)hwstats;
4471
4472 do {
4473 data_dst = data;
4474 start = u64_stats_fetch_begin(&hwstats->syncp);
4475
4476 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
4477 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
4478 if (mtk_page_pool_enabled(mac->hw))
4479 mtk_ethtool_pp_stats(mac->hw, data_dst);
4480 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
4481 }
4482
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)4483 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
4484 u32 *rule_locs)
4485 {
4486 int ret = -EOPNOTSUPP;
4487
4488 switch (cmd->cmd) {
4489 case ETHTOOL_GRXRINGS:
4490 if (dev->hw_features & NETIF_F_LRO) {
4491 cmd->data = MTK_MAX_RX_RING_NUM;
4492 ret = 0;
4493 }
4494 break;
4495 case ETHTOOL_GRXCLSRLCNT:
4496 if (dev->hw_features & NETIF_F_LRO) {
4497 struct mtk_mac *mac = netdev_priv(dev);
4498
4499 cmd->rule_cnt = mac->hwlro_ip_cnt;
4500 ret = 0;
4501 }
4502 break;
4503 case ETHTOOL_GRXCLSRULE:
4504 if (dev->hw_features & NETIF_F_LRO)
4505 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
4506 break;
4507 case ETHTOOL_GRXCLSRLALL:
4508 if (dev->hw_features & NETIF_F_LRO)
4509 ret = mtk_hwlro_get_fdir_all(dev, cmd,
4510 rule_locs);
4511 break;
4512 default:
4513 break;
4514 }
4515
4516 return ret;
4517 }
4518
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)4519 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
4520 {
4521 int ret = -EOPNOTSUPP;
4522
4523 switch (cmd->cmd) {
4524 case ETHTOOL_SRXCLSRLINS:
4525 if (dev->hw_features & NETIF_F_LRO)
4526 ret = mtk_hwlro_add_ipaddr(dev, cmd);
4527 break;
4528 case ETHTOOL_SRXCLSRLDEL:
4529 if (dev->hw_features & NETIF_F_LRO)
4530 ret = mtk_hwlro_del_ipaddr(dev, cmd);
4531 break;
4532 default:
4533 break;
4534 }
4535
4536 return ret;
4537 }
4538
mtk_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)4539 static void mtk_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4540 {
4541 struct mtk_mac *mac = netdev_priv(dev);
4542
4543 phylink_ethtool_get_pauseparam(mac->phylink, pause);
4544 }
4545
mtk_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)4546 static int mtk_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)
4547 {
4548 struct mtk_mac *mac = netdev_priv(dev);
4549
4550 return phylink_ethtool_set_pauseparam(mac->phylink, pause);
4551 }
4552
mtk_get_eee(struct net_device * dev,struct ethtool_keee * eee)4553 static int mtk_get_eee(struct net_device *dev, struct ethtool_keee *eee)
4554 {
4555 struct mtk_mac *mac = netdev_priv(dev);
4556
4557 return phylink_ethtool_get_eee(mac->phylink, eee);
4558 }
4559
mtk_set_eee(struct net_device * dev,struct ethtool_keee * eee)4560 static int mtk_set_eee(struct net_device *dev, struct ethtool_keee *eee)
4561 {
4562 struct mtk_mac *mac = netdev_priv(dev);
4563
4564 return phylink_ethtool_set_eee(mac->phylink, eee);
4565 }
4566
mtk_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)4567 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb,
4568 struct net_device *sb_dev)
4569 {
4570 struct mtk_mac *mac = netdev_priv(dev);
4571 unsigned int queue = 0;
4572
4573 if (netdev_uses_dsa(dev))
4574 queue = skb_get_queue_mapping(skb) + 3;
4575 else
4576 queue = mac->id;
4577
4578 if (queue >= dev->num_tx_queues)
4579 queue = 0;
4580
4581 return queue;
4582 }
4583
4584 static const struct ethtool_ops mtk_ethtool_ops = {
4585 .get_link_ksettings = mtk_get_link_ksettings,
4586 .set_link_ksettings = mtk_set_link_ksettings,
4587 .get_drvinfo = mtk_get_drvinfo,
4588 .get_msglevel = mtk_get_msglevel,
4589 .set_msglevel = mtk_set_msglevel,
4590 .nway_reset = mtk_nway_reset,
4591 .get_link = ethtool_op_get_link,
4592 .get_strings = mtk_get_strings,
4593 .get_sset_count = mtk_get_sset_count,
4594 .get_ethtool_stats = mtk_get_ethtool_stats,
4595 .get_pauseparam = mtk_get_pauseparam,
4596 .set_pauseparam = mtk_set_pauseparam,
4597 .get_rxnfc = mtk_get_rxnfc,
4598 .set_rxnfc = mtk_set_rxnfc,
4599 .get_eee = mtk_get_eee,
4600 .set_eee = mtk_set_eee,
4601 };
4602
4603 static const struct net_device_ops mtk_netdev_ops = {
4604 .ndo_uninit = mtk_uninit,
4605 .ndo_open = mtk_open,
4606 .ndo_stop = mtk_stop,
4607 .ndo_start_xmit = mtk_start_xmit,
4608 .ndo_set_mac_address = mtk_set_mac_address,
4609 .ndo_validate_addr = eth_validate_addr,
4610 .ndo_eth_ioctl = mtk_do_ioctl,
4611 .ndo_change_mtu = mtk_change_mtu,
4612 .ndo_tx_timeout = mtk_tx_timeout,
4613 .ndo_get_stats64 = mtk_get_stats64,
4614 .ndo_fix_features = mtk_fix_features,
4615 .ndo_set_features = mtk_set_features,
4616 #ifdef CONFIG_NET_POLL_CONTROLLER
4617 .ndo_poll_controller = mtk_poll_controller,
4618 #endif
4619 .ndo_setup_tc = mtk_eth_setup_tc,
4620 .ndo_bpf = mtk_xdp,
4621 .ndo_xdp_xmit = mtk_xdp_xmit,
4622 .ndo_select_queue = mtk_select_queue,
4623 };
4624
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)4625 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
4626 {
4627 const __be32 *_id = of_get_property(np, "reg", NULL);
4628 phy_interface_t phy_mode;
4629 struct phylink *phylink;
4630 struct mtk_mac *mac;
4631 int id, err;
4632 int txqs = 1;
4633 u32 val;
4634
4635 if (!_id) {
4636 dev_err(eth->dev, "missing mac id\n");
4637 return -EINVAL;
4638 }
4639
4640 id = be32_to_cpup(_id);
4641 if (id >= MTK_MAX_DEVS) {
4642 dev_err(eth->dev, "%d is not a valid mac id\n", id);
4643 return -EINVAL;
4644 }
4645
4646 if (eth->netdev[id]) {
4647 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
4648 return -EINVAL;
4649 }
4650
4651 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
4652 txqs = MTK_QDMA_NUM_QUEUES;
4653
4654 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1);
4655 if (!eth->netdev[id]) {
4656 dev_err(eth->dev, "alloc_etherdev failed\n");
4657 return -ENOMEM;
4658 }
4659 mac = netdev_priv(eth->netdev[id]);
4660 eth->mac[id] = mac;
4661 mac->id = id;
4662 mac->hw = eth;
4663 mac->of_node = np;
4664
4665 err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
4666 if (err == -EPROBE_DEFER)
4667 return err;
4668
4669 if (err) {
4670 /* If the mac address is invalid, use random mac address */
4671 eth_hw_addr_random(eth->netdev[id]);
4672 dev_err(eth->dev, "generated random MAC address %pM\n",
4673 eth->netdev[id]->dev_addr);
4674 }
4675
4676 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
4677 mac->hwlro_ip_cnt = 0;
4678
4679 mac->hw_stats = devm_kzalloc(eth->dev,
4680 sizeof(*mac->hw_stats),
4681 GFP_KERNEL);
4682 if (!mac->hw_stats) {
4683 dev_err(eth->dev, "failed to allocate counter memory\n");
4684 err = -ENOMEM;
4685 goto free_netdev;
4686 }
4687 spin_lock_init(&mac->hw_stats->stats_lock);
4688 u64_stats_init(&mac->hw_stats->syncp);
4689
4690 if (mtk_is_netsys_v3_or_greater(eth))
4691 mac->hw_stats->reg_offset = id * 0x80;
4692 else
4693 mac->hw_stats->reg_offset = id * 0x40;
4694
4695 /* phylink create */
4696 err = of_get_phy_mode(np, &phy_mode);
4697 if (err) {
4698 dev_err(eth->dev, "incorrect phy-mode\n");
4699 goto free_netdev;
4700 }
4701
4702 /* mac config is not set */
4703 mac->interface = PHY_INTERFACE_MODE_NA;
4704 mac->speed = SPEED_UNKNOWN;
4705
4706 mac->phylink_config.dev = ð->netdev[id]->dev;
4707 mac->phylink_config.type = PHYLINK_NETDEV;
4708 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
4709 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
4710 mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD |
4711 MAC_2500FD;
4712 mac->phylink_config.lpi_timer_default = 1000;
4713
4714 /* MT7623 gmac0 is now missing its speed-specific PLL configuration
4715 * in its .mac_config method (since state->speed is not valid there.
4716 * Disable support for MII, GMII and RGMII.
4717 */
4718 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
4719 __set_bit(PHY_INTERFACE_MODE_MII,
4720 mac->phylink_config.supported_interfaces);
4721 __set_bit(PHY_INTERFACE_MODE_GMII,
4722 mac->phylink_config.supported_interfaces);
4723
4724 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
4725 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
4726 }
4727
4728 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
4729 __set_bit(PHY_INTERFACE_MODE_TRGMII,
4730 mac->phylink_config.supported_interfaces);
4731
4732 /* TRGMII is not permitted on MT7621 if using DDR2 */
4733 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
4734 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
4735 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
4736 if (val & SYSCFG_DRAM_TYPE_DDR2)
4737 __clear_bit(PHY_INTERFACE_MODE_TRGMII,
4738 mac->phylink_config.supported_interfaces);
4739 }
4740
4741 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
4742 __set_bit(PHY_INTERFACE_MODE_SGMII,
4743 mac->phylink_config.supported_interfaces);
4744 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
4745 mac->phylink_config.supported_interfaces);
4746 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
4747 mac->phylink_config.supported_interfaces);
4748 }
4749
4750 if (mtk_is_netsys_v3_or_greater(mac->hw) &&
4751 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
4752 id == MTK_GMAC1_ID) {
4753 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
4754 MAC_SYM_PAUSE |
4755 MAC_10000FD;
4756 phy_interface_zero(mac->phylink_config.supported_interfaces);
4757 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
4758 mac->phylink_config.supported_interfaces);
4759 }
4760
4761 phylink = phylink_create(&mac->phylink_config,
4762 of_fwnode_handle(mac->of_node),
4763 phy_mode, &mtk_phylink_ops);
4764 if (IS_ERR(phylink)) {
4765 err = PTR_ERR(phylink);
4766 goto free_netdev;
4767 }
4768
4769 mac->phylink = phylink;
4770
4771 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
4772 eth->netdev[id]->watchdog_timeo = 5 * HZ;
4773 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
4774 eth->netdev[id]->base_addr = (unsigned long)eth->base;
4775
4776 eth->netdev[id]->hw_features = eth->soc->hw_features;
4777 if (eth->hwlro)
4778 eth->netdev[id]->hw_features |= NETIF_F_LRO;
4779
4780 eth->netdev[id]->vlan_features = eth->soc->hw_features &
4781 ~NETIF_F_HW_VLAN_CTAG_TX;
4782 eth->netdev[id]->features |= eth->soc->hw_features;
4783 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
4784
4785 eth->netdev[id]->irq = eth->irq[0];
4786 eth->netdev[id]->dev.of_node = np;
4787
4788 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4789 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
4790 else
4791 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
4792
4793 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
4794 mac->device_notifier.notifier_call = mtk_device_event;
4795 register_netdevice_notifier(&mac->device_notifier);
4796 }
4797
4798 if (mtk_page_pool_enabled(eth))
4799 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC |
4800 NETDEV_XDP_ACT_REDIRECT |
4801 NETDEV_XDP_ACT_NDO_XMIT |
4802 NETDEV_XDP_ACT_NDO_XMIT_SG;
4803
4804 return 0;
4805
4806 free_netdev:
4807 free_netdev(eth->netdev[id]);
4808 return err;
4809 }
4810
mtk_eth_set_dma_device(struct mtk_eth * eth,struct device * dma_dev)4811 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
4812 {
4813 struct net_device *dev, *tmp;
4814 LIST_HEAD(dev_list);
4815 int i;
4816
4817 rtnl_lock();
4818
4819 for (i = 0; i < MTK_MAX_DEVS; i++) {
4820 dev = eth->netdev[i];
4821
4822 if (!dev || !(dev->flags & IFF_UP))
4823 continue;
4824
4825 list_add_tail(&dev->close_list, &dev_list);
4826 }
4827
4828 dev_close_many(&dev_list, false);
4829
4830 eth->dma_dev = dma_dev;
4831
4832 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) {
4833 list_del_init(&dev->close_list);
4834 dev_open(dev, NULL);
4835 }
4836
4837 rtnl_unlock();
4838 }
4839
mtk_sgmii_init(struct mtk_eth * eth)4840 static int mtk_sgmii_init(struct mtk_eth *eth)
4841 {
4842 struct device_node *np;
4843 struct regmap *regmap;
4844 u32 flags;
4845 int i;
4846
4847 for (i = 0; i < MTK_MAX_DEVS; i++) {
4848 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i);
4849 if (!np)
4850 break;
4851
4852 regmap = syscon_node_to_regmap(np);
4853 flags = 0;
4854 if (of_property_read_bool(np, "mediatek,pnswap"))
4855 flags |= MTK_SGMII_FLAG_PN_SWAP;
4856
4857 of_node_put(np);
4858
4859 if (IS_ERR(regmap))
4860 return PTR_ERR(regmap);
4861
4862 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap,
4863 eth->soc->ana_rgc3,
4864 flags);
4865 }
4866
4867 return 0;
4868 }
4869
mtk_probe(struct platform_device * pdev)4870 static int mtk_probe(struct platform_device *pdev)
4871 {
4872 struct resource *res = NULL, *res_sram;
4873 struct device_node *mac_np;
4874 struct mtk_eth *eth;
4875 int err, i;
4876
4877 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
4878 if (!eth)
4879 return -ENOMEM;
4880
4881 eth->soc = of_device_get_match_data(&pdev->dev);
4882
4883 eth->dev = &pdev->dev;
4884 eth->dma_dev = &pdev->dev;
4885 eth->base = devm_platform_ioremap_resource(pdev, 0);
4886 if (IS_ERR(eth->base))
4887 return PTR_ERR(eth->base);
4888
4889 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
4890 eth->ip_align = NET_IP_ALIGN;
4891
4892 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4893 /* SRAM is actual memory and supports transparent access just like DRAM.
4894 * Hence we don't require __iomem being set and don't need to use accessor
4895 * functions to read from or write to SRAM.
4896 */
4897 if (mtk_is_netsys_v3_or_greater(eth)) {
4898 eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
4899 if (IS_ERR(eth->sram_base))
4900 return PTR_ERR(eth->sram_base);
4901 } else {
4902 eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
4903 }
4904 }
4905
4906 if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
4907 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
4908 if (!err)
4909 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4910
4911 if (err) {
4912 dev_err(&pdev->dev, "Wrong DMA config\n");
4913 return -EINVAL;
4914 }
4915 }
4916
4917 spin_lock_init(ð->page_lock);
4918 spin_lock_init(ð->tx_irq_lock);
4919 spin_lock_init(ð->rx_irq_lock);
4920 spin_lock_init(ð->dim_lock);
4921
4922 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4923 INIT_WORK(ð->rx_dim.work, mtk_dim_rx);
4924 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work);
4925
4926 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4927 INIT_WORK(ð->tx_dim.work, mtk_dim_tx);
4928
4929 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
4930 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4931 "mediatek,ethsys");
4932 if (IS_ERR(eth->ethsys)) {
4933 dev_err(&pdev->dev, "no ethsys regmap found\n");
4934 return PTR_ERR(eth->ethsys);
4935 }
4936 }
4937
4938 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
4939 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4940 "mediatek,infracfg");
4941 if (IS_ERR(eth->infra)) {
4942 dev_err(&pdev->dev, "no infracfg regmap found\n");
4943 return PTR_ERR(eth->infra);
4944 }
4945 }
4946
4947 if (of_dma_is_coherent(pdev->dev.of_node)) {
4948 struct regmap *cci;
4949
4950 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4951 "cci-control-port");
4952 /* enable CPU/bus coherency */
4953 if (!IS_ERR(cci))
4954 regmap_write(cci, 0, 3);
4955 }
4956
4957 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
4958 err = mtk_sgmii_init(eth);
4959
4960 if (err)
4961 return err;
4962 }
4963
4964 if (eth->soc->required_pctl) {
4965 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
4966 "mediatek,pctl");
4967 if (IS_ERR(eth->pctl)) {
4968 dev_err(&pdev->dev, "no pctl regmap found\n");
4969 err = PTR_ERR(eth->pctl);
4970 goto err_destroy_sgmii;
4971 }
4972 }
4973
4974 if (mtk_is_netsys_v2_or_greater(eth)) {
4975 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4976 if (!res) {
4977 err = -EINVAL;
4978 goto err_destroy_sgmii;
4979 }
4980 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
4981 if (mtk_is_netsys_v3_or_greater(eth)) {
4982 res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4983 if (!res_sram) {
4984 err = -EINVAL;
4985 goto err_destroy_sgmii;
4986 }
4987 eth->phy_scratch_ring = res_sram->start;
4988 } else {
4989 eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
4990 }
4991 }
4992 }
4993
4994 if (eth->soc->offload_version) {
4995 for (i = 0;; i++) {
4996 struct device_node *np;
4997 phys_addr_t wdma_phy;
4998 u32 wdma_base;
4999
5000 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))
5001 break;
5002
5003 np = of_parse_phandle(pdev->dev.of_node,
5004 "mediatek,wed", i);
5005 if (!np)
5006 break;
5007
5008 wdma_base = eth->soc->reg_map->wdma_base[i];
5009 wdma_phy = res ? res->start + wdma_base : 0;
5010 mtk_wed_add_hw(np, eth, eth->base + wdma_base,
5011 wdma_phy, i);
5012 }
5013 }
5014
5015 for (i = 0; i < 3; i++) {
5016 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
5017 eth->irq[i] = eth->irq[0];
5018 else
5019 eth->irq[i] = platform_get_irq(pdev, i);
5020 if (eth->irq[i] < 0) {
5021 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
5022 err = -ENXIO;
5023 goto err_wed_exit;
5024 }
5025 }
5026 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
5027 eth->clks[i] = devm_clk_get(eth->dev,
5028 mtk_clks_source_name[i]);
5029 if (IS_ERR(eth->clks[i])) {
5030 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) {
5031 err = -EPROBE_DEFER;
5032 goto err_wed_exit;
5033 }
5034 if (eth->soc->required_clks & BIT(i)) {
5035 dev_err(&pdev->dev, "clock %s not found\n",
5036 mtk_clks_source_name[i]);
5037 err = -EINVAL;
5038 goto err_wed_exit;
5039 }
5040 eth->clks[i] = NULL;
5041 }
5042 }
5043
5044 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
5045 INIT_WORK(ð->pending_work, mtk_pending_work);
5046
5047 err = mtk_hw_init(eth, false);
5048 if (err)
5049 goto err_wed_exit;
5050
5051 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
5052
5053 for_each_child_of_node(pdev->dev.of_node, mac_np) {
5054 if (!of_device_is_compatible(mac_np,
5055 "mediatek,eth-mac"))
5056 continue;
5057
5058 if (!of_device_is_available(mac_np))
5059 continue;
5060
5061 err = mtk_add_mac(eth, mac_np);
5062 if (err) {
5063 of_node_put(mac_np);
5064 goto err_deinit_hw;
5065 }
5066 }
5067
5068 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
5069 err = devm_request_irq(eth->dev, eth->irq[0],
5070 mtk_handle_irq, 0,
5071 dev_name(eth->dev), eth);
5072 } else {
5073 err = devm_request_irq(eth->dev, eth->irq[1],
5074 mtk_handle_irq_tx, 0,
5075 dev_name(eth->dev), eth);
5076 if (err)
5077 goto err_free_dev;
5078
5079 err = devm_request_irq(eth->dev, eth->irq[2],
5080 mtk_handle_irq_rx, 0,
5081 dev_name(eth->dev), eth);
5082 }
5083 if (err)
5084 goto err_free_dev;
5085
5086 /* No MT7628/88 support yet */
5087 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
5088 err = mtk_mdio_init(eth);
5089 if (err)
5090 goto err_free_dev;
5091 }
5092
5093 if (eth->soc->offload_version) {
5094 u8 ppe_num = eth->soc->ppe_num;
5095
5096 ppe_num = min_t(u8, ARRAY_SIZE(eth->ppe), ppe_num);
5097 for (i = 0; i < ppe_num; i++) {
5098 u32 ppe_addr = eth->soc->reg_map->ppe_base;
5099
5100 ppe_addr += (i == 2 ? 0xc00 : i * 0x400);
5101 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
5102
5103 if (!eth->ppe[i]) {
5104 err = -ENOMEM;
5105 goto err_deinit_ppe;
5106 }
5107 err = mtk_eth_offload_init(eth, i);
5108
5109 if (err)
5110 goto err_deinit_ppe;
5111 }
5112 }
5113
5114 for (i = 0; i < MTK_MAX_DEVS; i++) {
5115 if (!eth->netdev[i])
5116 continue;
5117
5118 err = register_netdev(eth->netdev[i]);
5119 if (err) {
5120 dev_err(eth->dev, "error bringing up device\n");
5121 goto err_deinit_ppe;
5122 } else
5123 netif_info(eth, probe, eth->netdev[i],
5124 "mediatek frame engine at 0x%08lx, irq %d\n",
5125 eth->netdev[i]->base_addr, eth->irq[0]);
5126 }
5127
5128 /* we run 2 devices on the same DMA ring so we need a dummy device
5129 * for NAPI to work
5130 */
5131 eth->dummy_dev = alloc_netdev_dummy(0);
5132 if (!eth->dummy_dev) {
5133 err = -ENOMEM;
5134 dev_err(eth->dev, "failed to allocated dummy device\n");
5135 goto err_unreg_netdev;
5136 }
5137 netif_napi_add(eth->dummy_dev, ð->tx_napi, mtk_napi_tx);
5138 netif_napi_add(eth->dummy_dev, ð->rx_napi, mtk_napi_rx);
5139
5140 platform_set_drvdata(pdev, eth);
5141 schedule_delayed_work(ð->reset.monitor_work,
5142 MTK_DMA_MONITOR_TIMEOUT);
5143
5144 return 0;
5145
5146 err_unreg_netdev:
5147 mtk_unreg_dev(eth);
5148 err_deinit_ppe:
5149 mtk_ppe_deinit(eth);
5150 mtk_mdio_cleanup(eth);
5151 err_free_dev:
5152 mtk_free_dev(eth);
5153 err_deinit_hw:
5154 mtk_hw_deinit(eth);
5155 err_wed_exit:
5156 mtk_wed_exit();
5157 err_destroy_sgmii:
5158 mtk_sgmii_destroy(eth);
5159
5160 return err;
5161 }
5162
mtk_remove(struct platform_device * pdev)5163 static void mtk_remove(struct platform_device *pdev)
5164 {
5165 struct mtk_eth *eth = platform_get_drvdata(pdev);
5166 struct mtk_mac *mac;
5167 int i;
5168
5169 /* stop all devices to make sure that dma is properly shut down */
5170 for (i = 0; i < MTK_MAX_DEVS; i++) {
5171 if (!eth->netdev[i])
5172 continue;
5173 mtk_stop(eth->netdev[i]);
5174 mac = netdev_priv(eth->netdev[i]);
5175 phylink_disconnect_phy(mac->phylink);
5176 }
5177
5178 mtk_wed_exit();
5179 mtk_hw_deinit(eth);
5180
5181 netif_napi_del(ð->tx_napi);
5182 netif_napi_del(ð->rx_napi);
5183 mtk_cleanup(eth);
5184 free_netdev(eth->dummy_dev);
5185 mtk_mdio_cleanup(eth);
5186 }
5187
5188 static const struct mtk_soc_data mt2701_data = {
5189 .reg_map = &mtk_reg_map,
5190 .caps = MT7623_CAPS | MTK_HWLRO,
5191 .hw_features = MTK_HW_FEATURES,
5192 .required_clks = MT7623_CLKS_BITMAP,
5193 .required_pctl = true,
5194 .version = 1,
5195 .tx = {
5196 .desc_size = sizeof(struct mtk_tx_dma),
5197 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5198 .dma_len_offset = 16,
5199 .dma_size = MTK_DMA_SIZE(2K),
5200 .fq_dma_size = MTK_DMA_SIZE(2K),
5201 },
5202 .rx = {
5203 .desc_size = sizeof(struct mtk_rx_dma),
5204 .irq_done_mask = MTK_RX_DONE_INT,
5205 .dma_l4_valid = RX_DMA_L4_VALID,
5206 .dma_size = MTK_DMA_SIZE(2K),
5207 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5208 .dma_len_offset = 16,
5209 },
5210 };
5211
5212 static const struct mtk_soc_data mt7621_data = {
5213 .reg_map = &mtk_reg_map,
5214 .caps = MT7621_CAPS,
5215 .hw_features = MTK_HW_FEATURES,
5216 .required_clks = MT7621_CLKS_BITMAP,
5217 .required_pctl = false,
5218 .version = 1,
5219 .offload_version = 1,
5220 .ppe_num = 1,
5221 .hash_offset = 2,
5222 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5223 .tx = {
5224 .desc_size = sizeof(struct mtk_tx_dma),
5225 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5226 .dma_len_offset = 16,
5227 .dma_size = MTK_DMA_SIZE(2K),
5228 .fq_dma_size = MTK_DMA_SIZE(2K),
5229 },
5230 .rx = {
5231 .desc_size = sizeof(struct mtk_rx_dma),
5232 .irq_done_mask = MTK_RX_DONE_INT,
5233 .dma_l4_valid = RX_DMA_L4_VALID,
5234 .dma_size = MTK_DMA_SIZE(2K),
5235 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5236 .dma_len_offset = 16,
5237 },
5238 };
5239
5240 static const struct mtk_soc_data mt7622_data = {
5241 .reg_map = &mtk_reg_map,
5242 .ana_rgc3 = 0x2028,
5243 .caps = MT7622_CAPS | MTK_HWLRO,
5244 .hw_features = MTK_HW_FEATURES,
5245 .required_clks = MT7622_CLKS_BITMAP,
5246 .required_pctl = false,
5247 .version = 1,
5248 .offload_version = 2,
5249 .ppe_num = 1,
5250 .hash_offset = 2,
5251 .has_accounting = true,
5252 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5253 .tx = {
5254 .desc_size = sizeof(struct mtk_tx_dma),
5255 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5256 .dma_len_offset = 16,
5257 .dma_size = MTK_DMA_SIZE(2K),
5258 .fq_dma_size = MTK_DMA_SIZE(2K),
5259 },
5260 .rx = {
5261 .desc_size = sizeof(struct mtk_rx_dma),
5262 .irq_done_mask = MTK_RX_DONE_INT,
5263 .dma_l4_valid = RX_DMA_L4_VALID,
5264 .dma_size = MTK_DMA_SIZE(2K),
5265 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5266 .dma_len_offset = 16,
5267 },
5268 };
5269
5270 static const struct mtk_soc_data mt7623_data = {
5271 .reg_map = &mtk_reg_map,
5272 .caps = MT7623_CAPS | MTK_HWLRO,
5273 .hw_features = MTK_HW_FEATURES,
5274 .required_clks = MT7623_CLKS_BITMAP,
5275 .required_pctl = true,
5276 .version = 1,
5277 .offload_version = 1,
5278 .ppe_num = 1,
5279 .hash_offset = 2,
5280 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
5281 .disable_pll_modes = true,
5282 .tx = {
5283 .desc_size = sizeof(struct mtk_tx_dma),
5284 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5285 .dma_len_offset = 16,
5286 .dma_size = MTK_DMA_SIZE(2K),
5287 .fq_dma_size = MTK_DMA_SIZE(2K),
5288 },
5289 .rx = {
5290 .desc_size = sizeof(struct mtk_rx_dma),
5291 .irq_done_mask = MTK_RX_DONE_INT,
5292 .dma_l4_valid = RX_DMA_L4_VALID,
5293 .dma_size = MTK_DMA_SIZE(2K),
5294 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5295 .dma_len_offset = 16,
5296 },
5297 };
5298
5299 static const struct mtk_soc_data mt7629_data = {
5300 .reg_map = &mtk_reg_map,
5301 .ana_rgc3 = 0x128,
5302 .caps = MT7629_CAPS | MTK_HWLRO,
5303 .hw_features = MTK_HW_FEATURES,
5304 .required_clks = MT7629_CLKS_BITMAP,
5305 .required_pctl = false,
5306 .has_accounting = true,
5307 .version = 1,
5308 .tx = {
5309 .desc_size = sizeof(struct mtk_tx_dma),
5310 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5311 .dma_len_offset = 16,
5312 .dma_size = MTK_DMA_SIZE(2K),
5313 .fq_dma_size = MTK_DMA_SIZE(2K),
5314 },
5315 .rx = {
5316 .desc_size = sizeof(struct mtk_rx_dma),
5317 .irq_done_mask = MTK_RX_DONE_INT,
5318 .dma_l4_valid = RX_DMA_L4_VALID,
5319 .dma_size = MTK_DMA_SIZE(2K),
5320 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5321 .dma_len_offset = 16,
5322 },
5323 };
5324
5325 static const struct mtk_soc_data mt7981_data = {
5326 .reg_map = &mt7986_reg_map,
5327 .ana_rgc3 = 0x128,
5328 .caps = MT7981_CAPS,
5329 .hw_features = MTK_HW_FEATURES,
5330 .required_clks = MT7981_CLKS_BITMAP,
5331 .required_pctl = false,
5332 .version = 2,
5333 .offload_version = 2,
5334 .ppe_num = 2,
5335 .hash_offset = 4,
5336 .has_accounting = true,
5337 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5338 .tx = {
5339 .desc_size = sizeof(struct mtk_tx_dma_v2),
5340 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5341 .dma_len_offset = 8,
5342 .dma_size = MTK_DMA_SIZE(2K),
5343 .fq_dma_size = MTK_DMA_SIZE(2K),
5344 },
5345 .rx = {
5346 .desc_size = sizeof(struct mtk_rx_dma),
5347 .irq_done_mask = MTK_RX_DONE_INT,
5348 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5349 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5350 .dma_len_offset = 16,
5351 .dma_size = MTK_DMA_SIZE(2K),
5352 },
5353 };
5354
5355 static const struct mtk_soc_data mt7986_data = {
5356 .reg_map = &mt7986_reg_map,
5357 .ana_rgc3 = 0x128,
5358 .caps = MT7986_CAPS,
5359 .hw_features = MTK_HW_FEATURES,
5360 .required_clks = MT7986_CLKS_BITMAP,
5361 .required_pctl = false,
5362 .version = 2,
5363 .offload_version = 2,
5364 .ppe_num = 2,
5365 .hash_offset = 4,
5366 .has_accounting = true,
5367 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
5368 .tx = {
5369 .desc_size = sizeof(struct mtk_tx_dma_v2),
5370 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5371 .dma_len_offset = 8,
5372 .dma_size = MTK_DMA_SIZE(2K),
5373 .fq_dma_size = MTK_DMA_SIZE(2K),
5374 },
5375 .rx = {
5376 .desc_size = sizeof(struct mtk_rx_dma),
5377 .irq_done_mask = MTK_RX_DONE_INT,
5378 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5379 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5380 .dma_len_offset = 16,
5381 .dma_size = MTK_DMA_SIZE(2K),
5382 },
5383 };
5384
5385 static const struct mtk_soc_data mt7988_data = {
5386 .reg_map = &mt7988_reg_map,
5387 .ana_rgc3 = 0x128,
5388 .caps = MT7988_CAPS,
5389 .hw_features = MTK_HW_FEATURES,
5390 .required_clks = MT7988_CLKS_BITMAP,
5391 .required_pctl = false,
5392 .version = 3,
5393 .offload_version = 2,
5394 .ppe_num = 3,
5395 .hash_offset = 4,
5396 .has_accounting = true,
5397 .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
5398 .tx = {
5399 .desc_size = sizeof(struct mtk_tx_dma_v2),
5400 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5401 .dma_len_offset = 8,
5402 .dma_size = MTK_DMA_SIZE(2K),
5403 .fq_dma_size = MTK_DMA_SIZE(4K),
5404 },
5405 .rx = {
5406 .desc_size = sizeof(struct mtk_rx_dma_v2),
5407 .irq_done_mask = MTK_RX_DONE_INT_V2,
5408 .dma_l4_valid = RX_DMA_L4_VALID_V2,
5409 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
5410 .dma_len_offset = 8,
5411 .dma_size = MTK_DMA_SIZE(2K),
5412 },
5413 };
5414
5415 static const struct mtk_soc_data rt5350_data = {
5416 .reg_map = &mt7628_reg_map,
5417 .caps = MT7628_CAPS,
5418 .hw_features = MTK_HW_FEATURES_MT7628,
5419 .required_clks = MT7628_CLKS_BITMAP,
5420 .required_pctl = false,
5421 .version = 1,
5422 .tx = {
5423 .desc_size = sizeof(struct mtk_tx_dma),
5424 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5425 .dma_len_offset = 16,
5426 .dma_size = MTK_DMA_SIZE(2K),
5427 },
5428 .rx = {
5429 .desc_size = sizeof(struct mtk_rx_dma),
5430 .irq_done_mask = MTK_RX_DONE_INT,
5431 .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
5432 .dma_max_len = MTK_TX_DMA_BUF_LEN,
5433 .dma_len_offset = 16,
5434 .dma_size = MTK_DMA_SIZE(2K),
5435 },
5436 };
5437
5438 const struct of_device_id of_mtk_match[] = {
5439 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
5440 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
5441 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
5442 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
5443 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
5444 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
5445 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
5446 { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
5447 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5448 {},
5449 };
5450 MODULE_DEVICE_TABLE(of, of_mtk_match);
5451
5452 static struct platform_driver mtk_driver = {
5453 .probe = mtk_probe,
5454 .remove = mtk_remove,
5455 .driver = {
5456 .name = "mtk_soc_eth",
5457 .of_match_table = of_mtk_match,
5458 },
5459 };
5460
5461 module_platform_driver(mtk_driver);
5462
5463 MODULE_LICENSE("GPL");
5464 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
5465 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
5466