1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2018-2021, Intel Corporation. */
3 
4 #ifndef _ICE_PTP_CONSTS_H_
5 #define _ICE_PTP_CONSTS_H_
6 
7 /* Constant definitions related to the hardware clock used for PTP 1588
8  * features and functionality.
9  */
10 /* Constants defined for the PTP 1588 clock hardware. */
11 
12 const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = {
13 	[ETH56G_PHY_REG_PTP] = {
14 		.base_addr = 0x092000,
15 		.step = 0x98,
16 	},
17 	[ETH56G_PHY_MEM_PTP] = {
18 		.base_addr = 0x093000,
19 		.step = 0x200,
20 	},
21 	[ETH56G_PHY_REG_XPCS] = {
22 		.base_addr = 0x000000,
23 		.step = 0x21000,
24 	},
25 	[ETH56G_PHY_REG_MAC] = {
26 		.base_addr = 0x085000,
27 		.step = 0x1000,
28 	},
29 	[ETH56G_PHY_REG_GPCS] = {
30 		.base_addr = 0x084000,
31 		.step = 0x400,
32 	},
33 };
34 
35 const
36 struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD] = {
37 	[ICE_ETH56G_LNK_SPD_1G] = {
38 		.tx_mode = { .def = 6, },
39 		.rx_mode = { .def = 6, },
40 		.blks_per_clk = 1,
41 		.blktime = 0x4000, /* 32 */
42 		.tx_offset = {
43 			.serdes = 0x6666, /* 51.2 */
44 			.no_fec = 0xd066, /* 104.2 */
45 			.sfd = 0x3000, /* 24 */
46 			.onestep = 0x30000 /* 384 */
47 		},
48 		.rx_offset = {
49 			.serdes = 0xffffc59a, /* -29.2 */
50 			.no_fec = 0xffff0a80, /* -122.75 */
51 			.sfd = 0x2c00, /* 22 */
52 			.bs_ds = 0x19a /* 0.8 */
53 			/* Dynamic bitslip 0 equals to 10 */
54 		}
55 	},
56 	[ICE_ETH56G_LNK_SPD_2_5G] = {
57 		.tx_mode = { .def = 6, },
58 		.rx_mode = { .def = 6, },
59 		.blks_per_clk = 1,
60 		.blktime = 0x199a, /* 12.8 */
61 		.tx_offset = {
62 			.serdes = 0x28f6, /* 20.48 */
63 			.no_fec = 0x53b8, /* 41.86 */
64 			.sfd = 0x1333, /* 9.6 */
65 			.onestep = 0x13333 /* 153.6 */
66 		},
67 		.rx_offset = {
68 			.serdes = 0xffffe8a4, /* -11.68 */
69 			.no_fec = 0xffff9a76, /* -50.77 */
70 			.sfd = 0xf33, /* 7.6 */
71 			.bs_ds = 0xa4 /* 0.32 */
72 		}
73 	},
74 	[ICE_ETH56G_LNK_SPD_10G] = {
75 		.tx_mode = { .def = 1, },
76 		.rx_mode = { .def = 1, },
77 		.blks_per_clk = 1,
78 		.blktime = 0x666, /* 3.2 */
79 		.tx_offset = {
80 			.serdes = 0x234c, /* 17.6484848 */
81 			.no_fec = 0x8e80, /* 71.25 */
82 			.fc = 0xb4a4, /* 90.32 */
83 			.sfd = 0x4a4, /* 2.32 */
84 			.onestep = 0x4ccd /* 38.4 */
85 		},
86 		.rx_offset = {
87 			.serdes = 0xffffeb27, /* -10.42424 */
88 			.no_fec = 0xffffcccd, /* -25.6 */
89 			.fc = 0xfffc557b, /* -469.26 */
90 			.sfd = 0x4a4, /* 2.32 */
91 			.bs_ds = 0x32 /* 0.0969697 */
92 		}
93 	},
94 	[ICE_ETH56G_LNK_SPD_25G] = {
95 		.tx_mode = {
96 			.def = 1,
97 			.rs = 4
98 		},
99 		.tx_mk_dly = 4,
100 		.tx_cw_dly = {
101 			.def = 1,
102 			.onestep = 6
103 		},
104 		.rx_mode = {
105 			.def = 1,
106 			.rs = 4
107 		},
108 		.rx_mk_dly = {
109 			.def = 1,
110 			.rs = 1
111 		},
112 		.rx_cw_dly = {
113 			.def = 1,
114 			.rs = 1
115 		},
116 		.blks_per_clk = 1,
117 		.blktime = 0x28f, /* 1.28 */
118 		.mktime = 0x147b, /* 10.24, only if RS-FEC enabled */
119 		.tx_offset = {
120 			.serdes = 0xe1e, /* 7.0593939 */
121 			.no_fec = 0x3857, /* 28.17 */
122 			.fc = 0x48c3, /* 36.38 */
123 			.rs = 0x8100, /* 64.5 */
124 			.sfd = 0x1dc, /* 0.93 */
125 			.onestep = 0x1eb8 /* 15.36 */
126 		},
127 		.rx_offset = {
128 			.serdes = 0xfffff7a9, /* -4.1697 */
129 			.no_fec = 0xffffe71a, /* -12.45 */
130 			.fc = 0xfffe894d, /* -187.35 */
131 			.rs = 0xfffff8cd, /* -3.6 */
132 			.sfd = 0x1dc, /* 0.93 */
133 			.bs_ds = 0x14 /* 0.0387879, RS-FEC 0 */
134 		}
135 	},
136 	[ICE_ETH56G_LNK_SPD_40G] = {
137 		.tx_mode = { .def = 3 },
138 		.tx_mk_dly = 4,
139 		.tx_cw_dly = {
140 			.def = 1,
141 			.onestep = 6
142 		},
143 		.rx_mode = { .def = 4 },
144 		.rx_mk_dly = { .def = 1 },
145 		.rx_cw_dly = { .def = 1 },
146 		.blktime = 0x333, /* 1.6 */
147 		.mktime = 0xccd, /* 6.4 */
148 		.tx_offset = {
149 			.serdes = 0x234c, /* 17.6484848 */
150 			.no_fec = 0x5a8a, /* 45.27 */
151 			.fc = 0x81b8, /* 64.86 */
152 			.sfd = 0x4a4, /* 2.32 */
153 			.onestep = 0x1333 /* 9.6 */
154 		},
155 		.rx_offset = {
156 			.serdes = 0xffffeb27, /* -10.42424 */
157 			.no_fec = 0xfffff594, /* -5.21 */
158 			.fc = 0xfffe3080, /* -231.75 */
159 			.sfd = 0x4a4, /* 2.32 */
160 			.bs_ds = 0xccd /* 6.4 */
161 		}
162 	},
163 	[ICE_ETH56G_LNK_SPD_50G] = {
164 		.tx_mode = { .def = 5 },
165 		.tx_mk_dly = 4,
166 		.tx_cw_dly = {
167 			.def = 1,
168 			.onestep = 6
169 		},
170 		.rx_mode = { .def = 5 },
171 		.rx_mk_dly = { .def = 1 },
172 		.rx_cw_dly = { .def = 1 },
173 		.blktime = 0x28f, /* 1.28 */
174 		.mktime = 0xa3d, /* 5.12 */
175 		.tx_offset = {
176 			.serdes = 0x13ba, /* 9.86353 */
177 			.rs = 0x5400, /* 42 */
178 			.sfd = 0xe6, /* 0.45 */
179 			.onestep = 0xf5c /* 7.68 */
180 		},
181 		.rx_offset = {
182 			.serdes = 0xfffff7e8, /* -4.04706 */
183 			.rs = 0xfffff994, /* -3.21 */
184 			.sfd = 0xe6 /* 0.45 */
185 		}
186 	},
187 	[ICE_ETH56G_LNK_SPD_50G2] = {
188 		.tx_mode = {
189 			.def = 3,
190 			.rs = 2
191 		},
192 		.tx_mk_dly = 4,
193 		.tx_cw_dly = {
194 			.def = 1,
195 			.onestep = 6
196 		},
197 		.rx_mode = {
198 			.def = 4,
199 			.rs = 1
200 		},
201 		.rx_mk_dly = { .def = 1 },
202 		.rx_cw_dly = { .def = 1 },
203 		.blktime = 0x28f, /* 1.28 */
204 		.mktime = 0xa3d, /* 5.12 */
205 		.tx_offset = {
206 			.serdes = 0xe1e, /* 7.0593939 */
207 			.no_fec = 0x3d33, /* 30.6 */
208 			.rs = 0x5057, /* 40.17 */
209 			.sfd = 0x1dc, /* 0.93 */
210 			.onestep = 0xf5c /* 7.68 */
211 		},
212 		.rx_offset = {
213 			.serdes = 0xfffff7a9, /* -4.1697 */
214 			.no_fec = 0xfffff8cd, /* -3.6 */
215 			.rs = 0xfffff21a, /* -6.95 */
216 			.sfd = 0x1dc, /* 0.93 */
217 			.bs_ds = 0xa3d /* 5.12, RS-FEC 0x633 (3.1) */
218 		}
219 	},
220 	[ICE_ETH56G_LNK_SPD_100G] = {
221 		.tx_mode = {
222 			.def = 3,
223 			.rs = 2
224 		},
225 		.tx_mk_dly = 10,
226 		.tx_cw_dly = {
227 			.def = 3,
228 			.onestep = 6
229 		},
230 		.rx_mode = {
231 			.def = 4,
232 			.rs = 1
233 		},
234 		.rx_mk_dly = { .def = 5 },
235 		.rx_cw_dly = { .def = 5 },
236 		.blks_per_clk = 1,
237 		.blktime = 0x148, /* 0.64 */
238 		.mktime = 0x199a, /* 12.8 */
239 		.tx_offset = {
240 			.serdes = 0xe1e, /* 7.0593939 */
241 			.no_fec = 0x67ec, /* 51.96 */
242 			.rs = 0x44fb, /* 34.49 */
243 			.sfd = 0x1dc, /* 0.93 */
244 			.onestep = 0xf5c /* 7.68 */
245 		},
246 		.rx_offset = {
247 			.serdes = 0xfffff7a9, /* -4.1697 */
248 			.no_fec = 0xfffff5a9, /* -5.17 */
249 			.rs = 0xfffff6e6, /* -4.55 */
250 			.sfd = 0x1dc, /* 0.93 */
251 			.bs_ds = 0x199a /* 12.8, RS-FEC 0x31b (1.552) */
252 		}
253 	},
254 	[ICE_ETH56G_LNK_SPD_100G2] = {
255 		.tx_mode = { .def = 5 },
256 		.tx_mk_dly = 10,
257 		.tx_cw_dly = {
258 			.def = 3,
259 			.onestep = 6
260 		},
261 		.rx_mode = { .def = 5 },
262 		.rx_mk_dly = { .def = 5 },
263 		.rx_cw_dly = { .def = 5 },
264 		.blks_per_clk = 1,
265 		.blktime = 0x148, /* 0.64 */
266 		.mktime = 0x199a, /* 12.8 */
267 		.tx_offset = {
268 			.serdes = 0x13ba, /* 9.86353 */
269 			.rs = 0x460a, /* 35.02 */
270 			.sfd = 0xe6, /* 0.45 */
271 			.onestep = 0xf5c /* 7.68 */
272 		},
273 		.rx_offset = {
274 			.serdes = 0xfffff7e8, /* -4.04706 */
275 			.rs = 0xfffff548, /* -5.36 */
276 			.sfd = 0xe6, /* 0.45 */
277 			.bs_ds = 0x303 /* 1.506 */
278 		}
279 	}
280 };
281 
282 /* struct ice_time_ref_info_e82x
283  *
284  * E822 hardware can use different sources as the reference for the PTP
285  * hardware clock. Each clock has different characteristics such as a slightly
286  * different frequency, etc.
287  *
288  * This lookup table defines several constants that depend on the current time
289  * reference. See the struct ice_time_ref_info_e82x for information about the
290  * meaning of each constant.
291  */
292 const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = {
293 	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
294 	{
295 		/* pll_freq */
296 		823437500, /* 823.4375 MHz PLL */
297 		/* nominal_incval */
298 		0x136e44fabULL,
299 	},
300 
301 	/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
302 	{
303 		/* pll_freq */
304 		783360000, /* 783.36 MHz */
305 		/* nominal_incval */
306 		0x146cc2177ULL,
307 	},
308 
309 	/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
310 	{
311 		/* pll_freq */
312 		796875000, /* 796.875 MHz */
313 		/* nominal_incval */
314 		0x141414141ULL,
315 	},
316 
317 	/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
318 	{
319 		/* pll_freq */
320 		816000000, /* 816 MHz */
321 		/* nominal_incval */
322 		0x139b9b9baULL,
323 	},
324 
325 	/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
326 	{
327 		/* pll_freq */
328 		830078125, /* 830.78125 MHz */
329 		/* nominal_incval */
330 		0x134679aceULL,
331 	},
332 
333 	/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
334 	{
335 		/* pll_freq */
336 		783360000, /* 783.36 MHz */
337 		/* nominal_incval */
338 		0x146cc2177ULL,
339 	},
340 };
341 
342 const struct ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
343 	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
344 	{
345 		/* refclk_pre_div */
346 		1,
347 		/* feedback_div */
348 		197,
349 		/* frac_n_div */
350 		2621440,
351 		/* post_pll_div */
352 		6,
353 	},
354 
355 	/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
356 	{
357 		/* refclk_pre_div */
358 		5,
359 		/* feedback_div */
360 		223,
361 		/* frac_n_div */
362 		524288,
363 		/* post_pll_div */
364 		7,
365 	},
366 
367 	/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
368 	{
369 		/* refclk_pre_div */
370 		5,
371 		/* feedback_div */
372 		223,
373 		/* frac_n_div */
374 		524288,
375 		/* post_pll_div */
376 		7,
377 	},
378 
379 	/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
380 	{
381 		/* refclk_pre_div */
382 		5,
383 		/* feedback_div */
384 		159,
385 		/* frac_n_div */
386 		1572864,
387 		/* post_pll_div */
388 		6,
389 	},
390 
391 	/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
392 	{
393 		/* refclk_pre_div */
394 		5,
395 		/* feedback_div */
396 		159,
397 		/* frac_n_div */
398 		1572864,
399 		/* post_pll_div */
400 		6,
401 	},
402 
403 	/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
404 	{
405 		/* refclk_pre_div */
406 		10,
407 		/* feedback_div */
408 		223,
409 		/* frac_n_div */
410 		524288,
411 		/* post_pll_div */
412 		7,
413 	},
414 };
415 
416 const
417 struct ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
418 	/* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
419 	{
420 		/* tspll_ck_refclkfreq */
421 		0x19,
422 		/* tspll_ndivratio */
423 		1,
424 		/* tspll_fbdiv_intgr */
425 		320,
426 		/* tspll_fbdiv_frac */
427 		0,
428 		/* ref1588_ck_div */
429 		0,
430 	},
431 
432 	/* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
433 	{
434 		/* tspll_ck_refclkfreq */
435 		0x29,
436 		/* tspll_ndivratio */
437 		3,
438 		/* tspll_fbdiv_intgr */
439 		195,
440 		/* tspll_fbdiv_frac */
441 		1342177280UL,
442 		/* ref1588_ck_div */
443 		0,
444 	},
445 
446 	/* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
447 	{
448 		/* tspll_ck_refclkfreq */
449 		0x3E,
450 		/* tspll_ndivratio */
451 		2,
452 		/* tspll_fbdiv_intgr */
453 		128,
454 		/* tspll_fbdiv_frac */
455 		0,
456 		/* ref1588_ck_div */
457 		0,
458 	},
459 
460 	/* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
461 	{
462 		/* tspll_ck_refclkfreq */
463 		0x33,
464 		/* tspll_ndivratio */
465 		3,
466 		/* tspll_fbdiv_intgr */
467 		156,
468 		/* tspll_fbdiv_frac */
469 		1073741824UL,
470 		/* ref1588_ck_div */
471 		0,
472 	},
473 
474 	/* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
475 	{
476 		/* tspll_ck_refclkfreq */
477 		0x1F,
478 		/* tspll_ndivratio */
479 		5,
480 		/* tspll_fbdiv_intgr */
481 		256,
482 		/* tspll_fbdiv_frac */
483 		0,
484 		/* ref1588_ck_div */
485 		0,
486 	},
487 
488 	/* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
489 	{
490 		/* tspll_ck_refclkfreq */
491 		0x52,
492 		/* tspll_ndivratio */
493 		3,
494 		/* tspll_fbdiv_intgr */
495 		97,
496 		/* tspll_fbdiv_frac */
497 		2818572288UL,
498 		/* ref1588_ck_div */
499 		0,
500 	},
501 };
502 
503 /* struct ice_vernier_info_e82x
504  *
505  * E822 hardware calibrates the delay of the timestamp indication from the
506  * actual packet transmission or reception during the initialization of the
507  * PHY. To do this, the hardware mechanism uses some conversions between the
508  * various clocks within the PHY block. This table defines constants used to
509  * calculate the correct conversion ratios in the PHY registers.
510  *
511  * Many of the values relate to the PAR/PCS clock conversion registers. For
512  * these registers, a value of 0 means that the associated register is not
513  * used by this link speed, and that the register should be cleared by writing
514  * 0. Other values specify the clock frequency in Hz.
515  */
516 const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
517 	/* ICE_PTP_LNK_SPD_1G */
518 	{
519 		/* tx_par_clk */
520 		31250000, /* 31.25 MHz */
521 		/* rx_par_clk */
522 		31250000, /* 31.25 MHz */
523 		/* tx_pcs_clk */
524 		125000000, /* 125 MHz */
525 		/* rx_pcs_clk */
526 		125000000, /* 125 MHz */
527 		/* tx_desk_rsgb_par */
528 		0, /* unused */
529 		/* rx_desk_rsgb_par */
530 		0, /* unused */
531 		/* tx_desk_rsgb_pcs */
532 		0, /* unused */
533 		/* rx_desk_rsgb_pcs */
534 		0, /* unused */
535 		/* tx_fixed_delay */
536 		25140,
537 		/* pmd_adj_divisor */
538 		10000000,
539 		/* rx_fixed_delay */
540 		17372,
541 	},
542 	/* ICE_PTP_LNK_SPD_10G */
543 	{
544 		/* tx_par_clk */
545 		257812500, /* 257.8125 MHz */
546 		/* rx_par_clk */
547 		257812500, /* 257.8125 MHz */
548 		/* tx_pcs_clk */
549 		156250000, /* 156.25 MHz */
550 		/* rx_pcs_clk */
551 		156250000, /* 156.25 MHz */
552 		/* tx_desk_rsgb_par */
553 		0, /* unused */
554 		/* rx_desk_rsgb_par */
555 		0, /* unused */
556 		/* tx_desk_rsgb_pcs */
557 		0, /* unused */
558 		/* rx_desk_rsgb_pcs */
559 		0, /* unused */
560 		/* tx_fixed_delay */
561 		6938,
562 		/* pmd_adj_divisor */
563 		82500000,
564 		/* rx_fixed_delay */
565 		6212,
566 	},
567 	/* ICE_PTP_LNK_SPD_25G */
568 	{
569 		/* tx_par_clk */
570 		644531250, /* 644.53125 MHZ */
571 		/* rx_par_clk */
572 		644531250, /* 644.53125 MHz */
573 		/* tx_pcs_clk */
574 		390625000, /* 390.625 MHz */
575 		/* rx_pcs_clk */
576 		390625000, /* 390.625 MHz */
577 		/* tx_desk_rsgb_par */
578 		0, /* unused */
579 		/* rx_desk_rsgb_par */
580 		0, /* unused */
581 		/* tx_desk_rsgb_pcs */
582 		0, /* unused */
583 		/* rx_desk_rsgb_pcs */
584 		0, /* unused */
585 		/* tx_fixed_delay */
586 		2778,
587 		/* pmd_adj_divisor */
588 		206250000,
589 		/* rx_fixed_delay */
590 		2491,
591 	},
592 	/* ICE_PTP_LNK_SPD_25G_RS */
593 	{
594 		/* tx_par_clk */
595 		0, /* unused */
596 		/* rx_par_clk */
597 		0, /* unused */
598 		/* tx_pcs_clk */
599 		0, /* unused */
600 		/* rx_pcs_clk */
601 		0, /* unused */
602 		/* tx_desk_rsgb_par */
603 		161132812, /* 162.1328125 MHz Reed Solomon gearbox */
604 		/* rx_desk_rsgb_par */
605 		161132812, /* 162.1328125 MHz Reed Solomon gearbox */
606 		/* tx_desk_rsgb_pcs */
607 		97656250, /* 97.62625 MHz Reed Solomon gearbox */
608 		/* rx_desk_rsgb_pcs */
609 		97656250, /* 97.62625 MHz Reed Solomon gearbox */
610 		/* tx_fixed_delay */
611 		3928,
612 		/* pmd_adj_divisor */
613 		206250000,
614 		/* rx_fixed_delay */
615 		29535,
616 	},
617 	/* ICE_PTP_LNK_SPD_40G */
618 	{
619 		/* tx_par_clk */
620 		257812500,
621 		/* rx_par_clk */
622 		257812500,
623 		/* tx_pcs_clk */
624 		156250000, /* 156.25 MHz */
625 		/* rx_pcs_clk */
626 		156250000, /* 156.25 MHz */
627 		/* tx_desk_rsgb_par */
628 		0, /* unused */
629 		/* rx_desk_rsgb_par */
630 		156250000, /* 156.25 MHz deskew clock */
631 		/* tx_desk_rsgb_pcs */
632 		0, /* unused */
633 		/* rx_desk_rsgb_pcs */
634 		156250000, /* 156.25 MHz deskew clock */
635 		/* tx_fixed_delay */
636 		5666,
637 		/* pmd_adj_divisor */
638 		82500000,
639 		/* rx_fixed_delay */
640 		4244,
641 	},
642 	/* ICE_PTP_LNK_SPD_50G */
643 	{
644 		/* tx_par_clk */
645 		644531250, /* 644.53125 MHZ */
646 		/* rx_par_clk */
647 		644531250, /* 644.53125 MHZ */
648 		/* tx_pcs_clk */
649 		390625000, /* 390.625 MHz */
650 		/* rx_pcs_clk */
651 		390625000, /* 390.625 MHz */
652 		/* tx_desk_rsgb_par */
653 		0, /* unused */
654 		/* rx_desk_rsgb_par */
655 		195312500, /* 193.3125 MHz deskew clock */
656 		/* tx_desk_rsgb_pcs */
657 		0, /* unused */
658 		/* rx_desk_rsgb_pcs */
659 		195312500, /* 193.3125 MHz deskew clock */
660 		/* tx_fixed_delay */
661 		2778,
662 		/* pmd_adj_divisor */
663 		206250000,
664 		/* rx_fixed_delay */
665 		2868,
666 	},
667 	/* ICE_PTP_LNK_SPD_50G_RS */
668 	{
669 		/* tx_par_clk */
670 		0, /* unused */
671 		/* rx_par_clk */
672 		644531250, /* 644.53125 MHz */
673 		/* tx_pcs_clk */
674 		0, /* unused */
675 		/* rx_pcs_clk */
676 		644531250, /* 644.53125 MHz */
677 		/* tx_desk_rsgb_par */
678 		322265625, /* 322.265625 MHz Reed Solomon gearbox */
679 		/* rx_desk_rsgb_par */
680 		322265625, /* 322.265625 MHz Reed Solomon gearbox */
681 		/* tx_desk_rsgb_pcs */
682 		644531250, /* 644.53125 MHz Reed Solomon gearbox */
683 		/* rx_desk_rsgb_pcs */
684 		644531250, /* 644.53125 MHz Reed Solomon gearbox */
685 		/* tx_fixed_delay */
686 		2095,
687 		/* pmd_adj_divisor */
688 		206250000,
689 		/* rx_fixed_delay */
690 		14524,
691 	},
692 	/* ICE_PTP_LNK_SPD_100G_RS */
693 	{
694 		/* tx_par_clk */
695 		0, /* unused */
696 		/* rx_par_clk */
697 		644531250, /* 644.53125 MHz */
698 		/* tx_pcs_clk */
699 		0, /* unused */
700 		/* rx_pcs_clk */
701 		644531250, /* 644.53125 MHz */
702 		/* tx_desk_rsgb_par */
703 		644531250, /* 644.53125 MHz Reed Solomon gearbox */
704 		/* rx_desk_rsgb_par */
705 		644531250, /* 644.53125 MHz Reed Solomon gearbox */
706 		/* tx_desk_rsgb_pcs */
707 		390625000, /* 390.625 MHz Reed Solomon gearbox */
708 		/* rx_desk_rsgb_pcs */
709 		390625000, /* 390.625 MHz Reed Solomon gearbox */
710 		/* tx_fixed_delay */
711 		1620,
712 		/* pmd_adj_divisor */
713 		206250000,
714 		/* rx_fixed_delay */
715 		7775,
716 	},
717 };
718 
719 #endif /* _ICE_PTP_CONSTS_H_ */
720