1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Driver for the MMC / SD / SDIO cell found in:
4 *
5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
6 *
7 * Copyright (C) 2015-19 Renesas Electronics Corporation
8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
10 * Copyright (C) 2007 Ian Molton
11 * Copyright (C) 2004 Ian Molton
12 */
13
14 #ifndef TMIO_MMC_H
15 #define TMIO_MMC_H
16
17 #include <linux/dmaengine.h>
18 #include <linux/highmem.h>
19 #include <linux/mutex.h>
20 #include <linux/pagemap.h>
21 #include <linux/scatterlist.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25
26 #define CTL_SD_CMD 0x00
27 #define CTL_ARG_REG 0x04
28 #define CTL_STOP_INTERNAL_ACTION 0x08
29 #define CTL_XFER_BLK_COUNT 0xa
30 #define CTL_RESPONSE 0x0c
31 /* driver merges STATUS and following STATUS2 */
32 #define CTL_STATUS 0x1c
33 /* driver merges IRQ_MASK and following IRQ_MASK2 */
34 #define CTL_IRQ_MASK 0x20
35 #define CTL_SD_CARD_CLK_CTL 0x24
36 #define CTL_SD_XFER_LEN 0x26
37 #define CTL_SD_MEM_CARD_OPT 0x28
38 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
39 #define CTL_SD_DATA_PORT 0x30
40 #define CTL_TRANSACTION_CTL 0x34
41 #define CTL_SDIO_STATUS 0x36
42 #define CTL_SDIO_IRQ_MASK 0x38
43 #define CTL_DMA_ENABLE 0xd8
44 #define CTL_RESET_SD 0xe0
45 #define CTL_VERSION 0xe2
46 #define CTL_SDIF_MODE 0xe6 /* only known on R-Car 2+ */
47 #define CTL_SD_STATUS 0xf2 /* only known on RZ/{G2L,G3E,V2H} */
48
49 /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
50 #define TMIO_STOP_STP BIT(0)
51 #define TMIO_STOP_SEC BIT(8)
52
53 /* Definitions for values the CTL_STATUS register can take */
54 #define TMIO_STAT_CMDRESPEND BIT(0)
55 #define TMIO_STAT_DATAEND BIT(2)
56 #define TMIO_STAT_CARD_REMOVE BIT(3)
57 #define TMIO_STAT_CARD_INSERT BIT(4)
58 #define TMIO_STAT_SIGSTATE BIT(5)
59 #define TMIO_STAT_WRPROTECT BIT(7)
60 #define TMIO_STAT_CARD_REMOVE_A BIT(8)
61 #define TMIO_STAT_CARD_INSERT_A BIT(9)
62 #define TMIO_STAT_SIGSTATE_A BIT(10)
63
64 /* These belong technically to CTL_STATUS2, but the driver merges them */
65 #define TMIO_STAT_CMD_IDX_ERR BIT(16)
66 #define TMIO_STAT_CRCFAIL BIT(17)
67 #define TMIO_STAT_STOPBIT_ERR BIT(18)
68 #define TMIO_STAT_DATATIMEOUT BIT(19)
69 #define TMIO_STAT_RXOVERFLOW BIT(20)
70 #define TMIO_STAT_TXUNDERRUN BIT(21)
71 #define TMIO_STAT_CMDTIMEOUT BIT(22)
72 #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
73 #define TMIO_STAT_RXRDY BIT(24)
74 #define TMIO_STAT_TXRQ BIT(25)
75 #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */
76 #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
77 #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
78 #define TMIO_STAT_CMD_BUSY BIT(30)
79 #define TMIO_STAT_ILL_ACCESS BIT(31)
80
81 /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
82 #define CLK_CTL_DIV_MASK 0xff
83 #define CLK_CTL_SCLKEN BIT(8)
84
85 /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
86 #define CARD_OPT_TOP_MASK 0xf0
87 #define CARD_OPT_TOP_SHIFT 4
88 #define CARD_OPT_EXTOP BIT(9) /* first appeared on R-Car Gen3 SDHI */
89 #define CARD_OPT_WIDTH8 BIT(13)
90 #define CARD_OPT_ALWAYS1 BIT(14)
91 #define CARD_OPT_WIDTH BIT(15)
92
93 /* Definitions for values the CTL_SDIO_STATUS register can take */
94 #define TMIO_SDIO_STAT_IOIRQ 0x0001
95 #define TMIO_SDIO_STAT_EXPUB52 0x4000
96 #define TMIO_SDIO_STAT_EXWT 0x8000
97 #define TMIO_SDIO_MASK_ALL 0xc007
98
99 #define TMIO_SDIO_SETBITS_MASK 0x0006
100
101 /* Definitions for values the CTL_DMA_ENABLE register can take */
102 #define DMA_ENABLE_DMASDRW BIT(1)
103
104 /* Definitions for values the CTL_SDIF_MODE register can take */
105 #define SDIF_MODE_HS400 BIT(0) /* only known on R-Car 2+ */
106
107 /* Definitions for values the CTL_SD_STATUS register can take */
108 #define SD_STATUS_PWEN BIT(0) /* only known on RZ/{G3E,V2H} */
109 #define SD_STATUS_IOVS BIT(16) /* only known on RZ/{G3E,V2H} */
110
111 /* Define some IRQ masks */
112 /* This is the mask used at reset by the chip */
113 #define TMIO_MASK_ALL 0x837f031d
114 #define TMIO_MASK_ALL_RCAR2 0x8b7f031d
115 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
116 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
117 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
118 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
119 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
120
121 #define TMIO_MAX_BLK_SIZE 512
122
123 struct tmio_mmc_data;
124 struct tmio_mmc_host;
125
126 struct tmio_mmc_dma_ops {
127 void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
128 void (*enable)(struct tmio_mmc_host *host, bool enable);
129 void (*request)(struct tmio_mmc_host *host,
130 struct tmio_mmc_data *pdata);
131 void (*release)(struct tmio_mmc_host *host);
132 void (*abort)(struct tmio_mmc_host *host);
133 void (*dataend)(struct tmio_mmc_host *host);
134
135 /* optional */
136 void (*end)(struct tmio_mmc_host *host); /* held host->lock */
137 bool (*dma_irq)(struct tmio_mmc_host *host);
138 };
139
140 struct tmio_mmc_host {
141 void __iomem *ctl;
142 struct mmc_command *cmd;
143 struct mmc_request *mrq;
144 struct mmc_data *data;
145 struct mmc_host *mmc;
146 struct mmc_host_ops ops;
147
148 /* pio related stuff */
149 struct scatterlist *sg_ptr;
150 struct scatterlist *sg_orig;
151 unsigned int sg_len;
152 unsigned int sg_off;
153 unsigned int bus_shift;
154
155 struct platform_device *pdev;
156 struct tmio_mmc_data *pdata;
157
158 /* DMA support */
159 bool dma_on;
160 struct dma_chan *chan_rx;
161 struct dma_chan *chan_tx;
162 struct work_struct dma_issue;
163 struct scatterlist bounce_sg;
164 u8 *bounce_buf;
165
166 /* Track lost interrupts */
167 struct delayed_work delayed_reset_work;
168 struct work_struct done;
169
170 /* Cache */
171 u32 sdcard_irq_mask;
172 u32 sdio_irq_mask;
173 unsigned int clk_cache;
174 u32 sdcard_irq_setbit_mask;
175 u32 sdcard_irq_mask_all;
176
177 spinlock_t lock; /* protect host private data */
178 unsigned long last_req_ts;
179 struct mutex ios_lock; /* protect set_ios() context */
180 bool native_hotplug;
181 bool sdio_irq_enabled;
182
183 /* Mandatory callback */
184 int (*clk_enable)(struct tmio_mmc_host *host);
185 void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
186
187 /* Optional callbacks */
188 void (*clk_disable)(struct tmio_mmc_host *host);
189 int (*multi_io_quirk)(struct mmc_card *card,
190 unsigned int direction, int blk_size);
191 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
192 void (*reset)(struct tmio_mmc_host *host, bool preserve);
193 bool (*check_retune)(struct tmio_mmc_host *host, struct mmc_request *mrq);
194 void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq);
195 unsigned int (*get_timeout_cycles)(struct tmio_mmc_host *host);
196
197 const struct tmio_mmc_dma_ops *dma_ops;
198 };
199
200 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
201 struct tmio_mmc_data *pdata);
202 void tmio_mmc_host_free(struct tmio_mmc_host *host);
203 int tmio_mmc_host_probe(struct tmio_mmc_host *host);
204 void tmio_mmc_host_remove(struct tmio_mmc_host *host);
205 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
206
207 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
208 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
209 irqreturn_t tmio_mmc_irq(int irq, void *devid);
210
211 #ifdef CONFIG_PM
212 int tmio_mmc_host_runtime_suspend(struct device *dev);
213 int tmio_mmc_host_runtime_resume(struct device *dev);
214 #endif
215
sd_ctrl_read16(struct tmio_mmc_host * host,int addr)216 static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
217 {
218 return ioread16(host->ctl + (addr << host->bus_shift));
219 }
220
sd_ctrl_read16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)221 static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
222 u16 *buf, int count)
223 {
224 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
225 }
226
sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host * host,int addr)227 static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
228 int addr)
229 {
230 return ioread16(host->ctl + (addr << host->bus_shift)) |
231 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
232 }
233
sd_ctrl_read32(struct tmio_mmc_host * host,int addr)234 static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
235 {
236 return ioread32(host->ctl + (addr << host->bus_shift));
237 }
238
sd_ctrl_read32_rep(struct tmio_mmc_host * host,int addr,u32 * buf,int count)239 static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
240 u32 *buf, int count)
241 {
242 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
243 }
244
sd_ctrl_write16(struct tmio_mmc_host * host,int addr,u16 val)245 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
246 u16 val)
247 {
248 /* If there is a hook and it returns non-zero then there
249 * is an error and the write should be skipped
250 */
251 if (host->write16_hook && host->write16_hook(host, addr))
252 return;
253 iowrite16(val, host->ctl + (addr << host->bus_shift));
254 }
255
sd_ctrl_write16_rep(struct tmio_mmc_host * host,int addr,u16 * buf,int count)256 static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
257 u16 *buf, int count)
258 {
259 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
260 }
261
sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host * host,int addr,u32 val)262 static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
263 int addr, u32 val)
264 {
265 if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
266 val |= host->sdcard_irq_setbit_mask;
267
268 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
269 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
270 }
271
sd_ctrl_write32(struct tmio_mmc_host * host,int addr,u32 val)272 static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
273 {
274 iowrite32(val, host->ctl + (addr << host->bus_shift));
275 }
276
sd_ctrl_write32_rep(struct tmio_mmc_host * host,int addr,const u32 * buf,int count)277 static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
278 const u32 *buf, int count)
279 {
280 iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
281 }
282
283 #endif
284