1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device access for Crystal Cove PMIC
4 *
5 * Copyright (C) 2012-2014, 2022 Intel Corporation. All rights reserved.
6 *
7 * Author: Yang, Bin <bin.yang@intel.com>
8 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
9 */
10
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mfd/core.h>
16 #include <linux/mfd/intel_soc_pmic.h>
17 #include <linux/platform_data/x86/soc.h>
18 #include <linux/pwm.h>
19 #include <linux/regmap.h>
20
21 #define CRYSTAL_COVE_MAX_REGISTER 0xC6
22
23 #define CRYSTAL_COVE_REG_IRQLVL1 0x02
24 #define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
25
26 #define CRYSTAL_COVE_IRQ_PWRSRC 0
27 #define CRYSTAL_COVE_IRQ_THRM 1
28 #define CRYSTAL_COVE_IRQ_BCU 2
29 #define CRYSTAL_COVE_IRQ_ADC 3
30 #define CRYSTAL_COVE_IRQ_CHGR 4
31 #define CRYSTAL_COVE_IRQ_GPIO 5
32 #define CRYSTAL_COVE_IRQ_VHDMIOCP 6
33
34 static const struct resource pwrsrc_resources[] = {
35 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
36 };
37
38 static const struct resource thermal_resources[] = {
39 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
40 };
41
42 static const struct resource bcu_resources[] = {
43 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
44 };
45
46 static const struct resource adc_resources[] = {
47 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
48 };
49
50 static const struct resource charger_resources[] = {
51 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
52 };
53
54 static const struct resource gpio_resources[] = {
55 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
56 };
57
58 static struct mfd_cell crystal_cove_byt_dev[] = {
59 {
60 .name = "crystal_cove_pwrsrc",
61 .num_resources = ARRAY_SIZE(pwrsrc_resources),
62 .resources = pwrsrc_resources,
63 },
64 {
65 .name = "crystal_cove_thermal",
66 .num_resources = ARRAY_SIZE(thermal_resources),
67 .resources = thermal_resources,
68 },
69 {
70 .name = "crystal_cove_bcu",
71 .num_resources = ARRAY_SIZE(bcu_resources),
72 .resources = bcu_resources,
73 },
74 {
75 .name = "crystal_cove_adc",
76 .num_resources = ARRAY_SIZE(adc_resources),
77 .resources = adc_resources,
78 },
79 {
80 .name = "crystal_cove_charger",
81 .num_resources = ARRAY_SIZE(charger_resources),
82 .resources = charger_resources,
83 },
84 {
85 .name = "crystal_cove_gpio",
86 .num_resources = ARRAY_SIZE(gpio_resources),
87 .resources = gpio_resources,
88 },
89 {
90 .name = "byt_crystal_cove_pmic",
91 },
92 {
93 .name = "crystal_cove_pwm",
94 },
95 };
96
97 static struct mfd_cell crystal_cove_cht_dev[] = {
98 {
99 .name = "crystal_cove_gpio",
100 .num_resources = ARRAY_SIZE(gpio_resources),
101 .resources = gpio_resources,
102 },
103 {
104 .name = "cht_crystal_cove_pmic",
105 },
106 {
107 .name = "crystal_cove_pwm",
108 },
109 };
110
111 static const struct regmap_config crystal_cove_regmap_config = {
112 .reg_bits = 8,
113 .val_bits = 8,
114
115 .max_register = CRYSTAL_COVE_MAX_REGISTER,
116 };
117
118 static const struct regmap_irq crystal_cove_irqs[] = {
119 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
120 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
121 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
122 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
123 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
124 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
125 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
126 };
127
128 static const struct regmap_irq_chip crystal_cove_irq_chip = {
129 .name = "Crystal Cove",
130 .irqs = crystal_cove_irqs,
131 .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
132 .num_regs = 1,
133 .status_base = CRYSTAL_COVE_REG_IRQLVL1,
134 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
135 };
136
137 /* PWM consumed by the Intel GFX */
138 static struct pwm_lookup crc_pwm_lookup[] = {
139 PWM_LOOKUP_WITH_MODULE("crystal_cove_pwm", 0, "0000:00:02.0",
140 "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL,
141 "pwm-crc"),
142 };
143
144 struct crystal_cove_config {
145 unsigned long irq_flags;
146 struct mfd_cell *cell_dev;
147 int n_cell_devs;
148 const struct regmap_config *regmap_config;
149 const struct regmap_irq_chip *irq_chip;
150 };
151
152 static const struct crystal_cove_config crystal_cove_config_byt_crc = {
153 .irq_flags = IRQF_TRIGGER_RISING,
154 .cell_dev = crystal_cove_byt_dev,
155 .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
156 .regmap_config = &crystal_cove_regmap_config,
157 .irq_chip = &crystal_cove_irq_chip,
158 };
159
160 static const struct crystal_cove_config crystal_cove_config_cht_crc = {
161 .irq_flags = IRQF_TRIGGER_RISING,
162 .cell_dev = crystal_cove_cht_dev,
163 .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
164 .regmap_config = &crystal_cove_regmap_config,
165 .irq_chip = &crystal_cove_irq_chip,
166 };
167
crystal_cove_i2c_probe(struct i2c_client * i2c)168 static int crystal_cove_i2c_probe(struct i2c_client *i2c)
169 {
170 const struct crystal_cove_config *config;
171 struct device *dev = &i2c->dev;
172 struct intel_soc_pmic *pmic;
173 int ret;
174
175 if (soc_intel_is_byt())
176 config = &crystal_cove_config_byt_crc;
177 else
178 config = &crystal_cove_config_cht_crc;
179
180 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
181 if (!pmic)
182 return -ENOMEM;
183
184 i2c_set_clientdata(i2c, pmic);
185
186 pmic->regmap = devm_regmap_init_i2c(i2c, config->regmap_config);
187 if (IS_ERR(pmic->regmap))
188 return PTR_ERR(pmic->regmap);
189
190 pmic->irq = i2c->irq;
191
192 ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
193 config->irq_flags | IRQF_ONESHOT,
194 0, config->irq_chip, &pmic->irq_chip_data);
195 if (ret)
196 return ret;
197
198 ret = enable_irq_wake(pmic->irq);
199 if (ret)
200 dev_warn(dev, "Can't enable IRQ as wake source: %d\n", ret);
201
202 /* Add lookup table for crc-pwm */
203 pwm_add_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
204
205 /* To distuingish this domain from the GPIO/charger's irqchip domains */
206 irq_domain_update_bus_token(regmap_irq_get_domain(pmic->irq_chip_data),
207 DOMAIN_BUS_NEXUS);
208
209 ret = mfd_add_devices(dev, PLATFORM_DEVID_NONE, config->cell_dev,
210 config->n_cell_devs, NULL, 0,
211 regmap_irq_get_domain(pmic->irq_chip_data));
212 if (ret)
213 pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
214
215 return ret;
216 }
217
crystal_cove_i2c_remove(struct i2c_client * i2c)218 static void crystal_cove_i2c_remove(struct i2c_client *i2c)
219 {
220 /* remove crc-pwm lookup table */
221 pwm_remove_table(crc_pwm_lookup, ARRAY_SIZE(crc_pwm_lookup));
222
223 mfd_remove_devices(&i2c->dev);
224 }
225
crystal_cove_shutdown(struct i2c_client * i2c)226 static void crystal_cove_shutdown(struct i2c_client *i2c)
227 {
228 struct intel_soc_pmic *pmic = i2c_get_clientdata(i2c);
229
230 disable_irq(pmic->irq);
231
232 return;
233 }
234
crystal_cove_suspend(struct device * dev)235 static int crystal_cove_suspend(struct device *dev)
236 {
237 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
238
239 disable_irq(pmic->irq);
240
241 return 0;
242 }
243
crystal_cove_resume(struct device * dev)244 static int crystal_cove_resume(struct device *dev)
245 {
246 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
247
248 enable_irq(pmic->irq);
249
250 return 0;
251 }
252
253 static DEFINE_SIMPLE_DEV_PM_OPS(crystal_cove_pm_ops, crystal_cove_suspend, crystal_cove_resume);
254
255 static const struct acpi_device_id crystal_cove_acpi_match[] = {
256 { "INT33FD" },
257 { },
258 };
259 MODULE_DEVICE_TABLE(acpi, crystal_cove_acpi_match);
260
261 static const struct i2c_device_id crystal_cove_i2c_match[] = {
262 { "intel_soc_pmic_crc" },
263 { }
264 };
265 MODULE_DEVICE_TABLE(i2c, crystal_cove_i2c_match);
266
267 static struct i2c_driver crystal_cove_i2c_driver = {
268 .driver = {
269 .name = "intel_soc_pmic_crc",
270 .pm = pm_sleep_ptr(&crystal_cove_pm_ops),
271 .acpi_match_table = crystal_cove_acpi_match,
272 },
273 .id_table = crystal_cove_i2c_match,
274 .probe = crystal_cove_i2c_probe,
275 .remove = crystal_cove_i2c_remove,
276 .shutdown = crystal_cove_shutdown,
277 };
278
279 module_i2c_driver(crystal_cove_i2c_driver);
280
281 MODULE_DESCRIPTION("I2C driver for Intel SoC PMIC");
282 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
283 MODULE_AUTHOR("Zhu, Lejun <lejun.zhu@linux.intel.com>");
284