1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4  *
5  * Author: Shunqing Chen <csq@rock-chips.com>
6  */
7 
8 #ifndef DW_HDMI_RX_CEC_H
9 #define DW_HDMI_RX_CEC_H
10 
11 struct snps_hdmirx_dev;
12 
13 struct hdmirx_cec_ops {
14 	void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val);
15 	u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg);
16 	void (*enable)(struct snps_hdmirx_dev *hdmirx);
17 	void (*disable)(struct snps_hdmirx_dev *hdmirx);
18 };
19 
20 struct hdmirx_cec_data {
21 	struct snps_hdmirx_dev *hdmirx;
22 	const struct hdmirx_cec_ops *ops;
23 	struct device *dev;
24 	int irq;
25 };
26 
27 struct hdmirx_cec {
28 	struct snps_hdmirx_dev *hdmirx;
29 	struct device *dev;
30 	const struct hdmirx_cec_ops *ops;
31 	u32 addresses;
32 	struct cec_adapter *adap;
33 	struct cec_msg rx_msg;
34 	unsigned int tx_status;
35 	bool tx_done;
36 	bool rx_done;
37 	int irq;
38 };
39 
40 struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data);
41 void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec);
42 
43 #endif /* DW_HDMI_RX_CEC_H */
44