1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <media/v4l2-event.h>
7 #include <media/v4l2-mem2mem.h>
8
9 #include "iris_buffer.h"
10 #include "iris_instance.h"
11 #include "iris_power.h"
12 #include "iris_vpu_buffer.h"
13
14 #define PIXELS_4K 4096
15 #define MAX_WIDTH 4096
16 #define MAX_HEIGHT 2304
17 #define Y_STRIDE_ALIGN 128
18 #define UV_STRIDE_ALIGN 128
19 #define Y_SCANLINE_ALIGN 32
20 #define UV_SCANLINE_ALIGN 16
21 #define UV_SCANLINE_ALIGN_QC08C 32
22 #define META_STRIDE_ALIGNED 64
23 #define META_SCANLINE_ALIGNED 16
24 #define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
25
26 /*
27 * NV12:
28 * YUV 4:2:0 image with a plane of 8 bit Y samples followed
29 * by an interleaved U/V plane containing 8 bit 2x2 subsampled
30 * colour difference samples.
31 *
32 * <-Y/UV_Stride (aligned to 128)->
33 * <------- Width ------->
34 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^
35 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
36 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height |
37 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | y_scanlines (aligned to 32)
38 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
39 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
40 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | |
41 * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V |
42 * . . . . . . . . . . . . . . . . |
43 * . . . . . . . . . . . . . . . . |
44 * . . . . . . . . . . . . . . . . |
45 * . . . . . . . . . . . . . . . . V
46 * U V U V U V U V U V U V . . . . ^
47 * U V U V U V U V U V U V . . . . |
48 * U V U V U V U V U V U V . . . . |
49 * U V U V U V U V U V U V . . . . uv_scanlines (aligned to 16)
50 * . . . . . . . . . . . . . . . . |
51 * . . . . . . . . . . . . . . . . V
52 * . . . . . . . . . . . . . . . . --> Buffer size aligned to 4K
53 *
54 * y_stride : Width aligned to 128
55 * uv_stride : Width aligned to 128
56 * y_scanlines: Height aligned to 32
57 * uv_scanlines: Height/2 aligned to 16
58 * Total size = align((y_stride * y_scanlines
59 * + uv_stride * uv_scanlines , 4096)
60 *
61 * Note: All the alignments are hardware requirements.
62 */
iris_yuv_buffer_size_nv12(struct iris_inst * inst)63 static u32 iris_yuv_buffer_size_nv12(struct iris_inst *inst)
64 {
65 u32 y_plane, uv_plane, y_stride, uv_stride, y_scanlines, uv_scanlines;
66 struct v4l2_format *f = inst->fmt_dst;
67
68 y_stride = ALIGN(f->fmt.pix_mp.width, Y_STRIDE_ALIGN);
69 uv_stride = ALIGN(f->fmt.pix_mp.width, UV_STRIDE_ALIGN);
70 y_scanlines = ALIGN(f->fmt.pix_mp.height, Y_SCANLINE_ALIGN);
71 uv_scanlines = ALIGN((f->fmt.pix_mp.height + 1) >> 1, UV_SCANLINE_ALIGN);
72 y_plane = y_stride * y_scanlines;
73 uv_plane = uv_stride * uv_scanlines;
74
75 return ALIGN(y_plane + uv_plane, PIXELS_4K);
76 }
77
78 /*
79 * QC08C:
80 * Compressed Macro-tile format for NV12.
81 * Contains 4 planes in the following order -
82 * (A) Y_Meta_Plane
83 * (B) Y_UBWC_Plane
84 * (C) UV_Meta_Plane
85 * (D) UV_UBWC_Plane
86 *
87 * Y_Meta_Plane consists of meta information to decode compressed
88 * tile data in Y_UBWC_Plane.
89 * Y_UBWC_Plane consists of Y data in compressed macro-tile format.
90 * UBWC decoder block will use the Y_Meta_Plane data together with
91 * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples.
92 *
93 * UV_Meta_Plane consists of meta information to decode compressed
94 * tile data in UV_UBWC_Plane.
95 * UV_UBWC_Plane consists of UV data in compressed macro-tile format.
96 * UBWC decoder block will use UV_Meta_Plane data together with
97 * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2
98 * subsampled color difference samples.
99 *
100 * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable
101 * and randomly accessible. There is no dependency between tiles.
102 *
103 * <----- y_meta_stride ----> (aligned to 64)
104 * <-------- Width ------>
105 * M M M M M M M M M M M M . . ^ ^
106 * M M M M M M M M M M M M . . | |
107 * M M M M M M M M M M M M . . Height |
108 * M M M M M M M M M M M M . . | y_meta_scanlines (aligned to 16)
109 * M M M M M M M M M M M M . . | |
110 * M M M M M M M M M M M M . . | |
111 * M M M M M M M M M M M M . . | |
112 * M M M M M M M M M M M M . . V |
113 * . . . . . . . . . . . . . . |
114 * . . . . . . . . . . . . . . |
115 * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
116 * . . . . . . . . . . . . . . V
117 * <--Compressed tile y_stride---> (aligned to 128)
118 * <------- Width ------->
119 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^
120 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
121 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height |
122 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile y_scanlines (aligned to 32)
123 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
124 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
125 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | |
126 * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V |
127 * . . . . . . . . . . . . . . . . |
128 * . . . . . . . . . . . . . . . . |
129 * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
130 * . . . . . . . . . . . . . . . . V
131 * <----- uv_meta_stride ----> (aligned to 64)
132 * M M M M M M M M M M M M . . ^
133 * M M M M M M M M M M M M . . |
134 * M M M M M M M M M M M M . . |
135 * M M M M M M M M M M M M . . uv_meta_scanlines (aligned to 16)
136 * . . . . . . . . . . . . . . |
137 * . . . . . . . . . . . . . . V
138 * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
139 * <--Compressed tile uv_stride---> (aligned to 128)
140 * U* V* U* V* U* V* U* V* . . . . ^
141 * U* V* U* V* U* V* U* V* . . . . |
142 * U* V* U* V* U* V* U* V* . . . . |
143 * U* V* U* V* U* V* U* V* . . . . uv_scanlines (aligned to 32)
144 * . . . . . . . . . . . . . . . . |
145 * . . . . . . . . . . . . . . . . V
146 * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k
147 *
148 * y_stride: width aligned to 128
149 * uv_stride: width aligned to 128
150 * y_scanlines: height aligned to 32
151 * uv_scanlines: height aligned to 32
152 * y_plane: buffer size aligned to 4096
153 * uv_plane: buffer size aligned to 4096
154 * y_meta_stride: width aligned to 64
155 * y_meta_scanlines: height aligned to 16
156 * y_meta_plane: buffer size aligned to 4096
157 * uv_meta_stride: width aligned to 64
158 * uv_meta_scanlines: height aligned to 16
159 * uv_meta_plane: buffer size aligned to 4096
160 *
161 * Total size = align( y_plane + uv_plane +
162 * y_meta_plane + uv_meta_plane, 4096)
163 *
164 * Note: All the alignments are hardware requirements.
165 */
iris_yuv_buffer_size_qc08c(struct iris_inst * inst)166 static u32 iris_yuv_buffer_size_qc08c(struct iris_inst *inst)
167 {
168 u32 y_plane, uv_plane, y_stride, uv_stride;
169 struct v4l2_format *f = inst->fmt_dst;
170 u32 uv_meta_stride, uv_meta_plane;
171 u32 y_meta_stride, y_meta_plane;
172
173 y_meta_stride = ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.width, META_STRIDE_ALIGNED >> 1),
174 META_STRIDE_ALIGNED);
175 y_meta_plane = y_meta_stride * ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.height,
176 META_SCANLINE_ALIGNED >> 1),
177 META_SCANLINE_ALIGNED);
178 y_meta_plane = ALIGN(y_meta_plane, PIXELS_4K);
179
180 y_stride = ALIGN(f->fmt.pix_mp.width, Y_STRIDE_ALIGN);
181 y_plane = ALIGN(y_stride * ALIGN(f->fmt.pix_mp.height, Y_SCANLINE_ALIGN), PIXELS_4K);
182
183 uv_meta_stride = ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.width / 2, META_STRIDE_ALIGNED >> 2),
184 META_STRIDE_ALIGNED);
185 uv_meta_plane = uv_meta_stride * ALIGN(DIV_ROUND_UP(f->fmt.pix_mp.height / 2,
186 META_SCANLINE_ALIGNED >> 1),
187 META_SCANLINE_ALIGNED);
188 uv_meta_plane = ALIGN(uv_meta_plane, PIXELS_4K);
189
190 uv_stride = ALIGN(f->fmt.pix_mp.width, UV_STRIDE_ALIGN);
191 uv_plane = ALIGN(uv_stride * ALIGN(f->fmt.pix_mp.height / 2, UV_SCANLINE_ALIGN_QC08C),
192 PIXELS_4K);
193
194 return ALIGN(y_meta_plane + y_plane + uv_meta_plane + uv_plane, PIXELS_4K);
195 }
196
iris_bitstream_buffer_size(struct iris_inst * inst)197 static u32 iris_bitstream_buffer_size(struct iris_inst *inst)
198 {
199 struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
200 u32 base_res_mbs = NUM_MBS_4K;
201 u32 frame_size, num_mbs;
202 u32 div_factor = 2;
203
204 num_mbs = iris_get_mbpf(inst);
205 if (num_mbs > NUM_MBS_4K) {
206 div_factor = 4;
207 base_res_mbs = caps->max_mbpf;
208 }
209
210 /*
211 * frame_size = YUVsize / div_factor
212 * where YUVsize = resolution_in_MBs * MBs_in_pixel * 3 / 2
213 */
214 frame_size = base_res_mbs * (16 * 16) * 3 / 2 / div_factor;
215
216 return ALIGN(frame_size, PIXELS_4K);
217 }
218
iris_get_buffer_size(struct iris_inst * inst,enum iris_buffer_type buffer_type)219 int iris_get_buffer_size(struct iris_inst *inst,
220 enum iris_buffer_type buffer_type)
221 {
222 switch (buffer_type) {
223 case BUF_INPUT:
224 return iris_bitstream_buffer_size(inst);
225 case BUF_OUTPUT:
226 return iris_yuv_buffer_size_nv12(inst);
227 case BUF_DPB:
228 return iris_yuv_buffer_size_qc08c(inst);
229 default:
230 return 0;
231 }
232 }
233
iris_fill_internal_buf_info(struct iris_inst * inst,enum iris_buffer_type buffer_type)234 static void iris_fill_internal_buf_info(struct iris_inst *inst,
235 enum iris_buffer_type buffer_type)
236 {
237 struct iris_buffers *buffers = &inst->buffers[buffer_type];
238
239 buffers->size = iris_vpu_buf_size(inst, buffer_type);
240 buffers->min_count = iris_vpu_buf_count(inst, buffer_type);
241 }
242
iris_get_internal_buffers(struct iris_inst * inst,u32 plane)243 void iris_get_internal_buffers(struct iris_inst *inst, u32 plane)
244 {
245 const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
246 const u32 *internal_buf_type;
247 u32 internal_buffer_count, i;
248
249 if (V4L2_TYPE_IS_OUTPUT(plane)) {
250 internal_buf_type = platform_data->dec_ip_int_buf_tbl;
251 internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
252 for (i = 0; i < internal_buffer_count; i++)
253 iris_fill_internal_buf_info(inst, internal_buf_type[i]);
254 } else {
255 internal_buf_type = platform_data->dec_op_int_buf_tbl;
256 internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
257 for (i = 0; i < internal_buffer_count; i++)
258 iris_fill_internal_buf_info(inst, internal_buf_type[i]);
259 }
260 }
261
iris_create_internal_buffer(struct iris_inst * inst,enum iris_buffer_type buffer_type,u32 index)262 static int iris_create_internal_buffer(struct iris_inst *inst,
263 enum iris_buffer_type buffer_type, u32 index)
264 {
265 struct iris_buffers *buffers = &inst->buffers[buffer_type];
266 struct iris_core *core = inst->core;
267 struct iris_buffer *buffer;
268
269 if (!buffers->size)
270 return 0;
271
272 buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
273 if (!buffer)
274 return -ENOMEM;
275
276 INIT_LIST_HEAD(&buffer->list);
277 buffer->type = buffer_type;
278 buffer->index = index;
279 buffer->buffer_size = buffers->size;
280 buffer->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_NO_KERNEL_MAPPING;
281 list_add_tail(&buffer->list, &buffers->list);
282
283 buffer->kvaddr = dma_alloc_attrs(core->dev, buffer->buffer_size,
284 &buffer->device_addr, GFP_KERNEL, buffer->dma_attrs);
285 if (!buffer->kvaddr)
286 return -ENOMEM;
287
288 return 0;
289 }
290
iris_create_internal_buffers(struct iris_inst * inst,u32 plane)291 int iris_create_internal_buffers(struct iris_inst *inst, u32 plane)
292 {
293 const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
294 u32 internal_buffer_count, i, j;
295 struct iris_buffers *buffers;
296 const u32 *internal_buf_type;
297 int ret;
298
299 if (V4L2_TYPE_IS_OUTPUT(plane)) {
300 internal_buf_type = platform_data->dec_ip_int_buf_tbl;
301 internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
302 } else {
303 internal_buf_type = platform_data->dec_op_int_buf_tbl;
304 internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
305 }
306
307 for (i = 0; i < internal_buffer_count; i++) {
308 buffers = &inst->buffers[internal_buf_type[i]];
309 for (j = 0; j < buffers->min_count; j++) {
310 ret = iris_create_internal_buffer(inst, internal_buf_type[i], j);
311 if (ret)
312 return ret;
313 }
314 }
315
316 return 0;
317 }
318
iris_queue_buffer(struct iris_inst * inst,struct iris_buffer * buf)319 int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf)
320 {
321 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
322 int ret;
323
324 ret = hfi_ops->session_queue_buf(inst, buf);
325 if (ret)
326 return ret;
327
328 buf->attr &= ~BUF_ATTR_DEFERRED;
329 buf->attr |= BUF_ATTR_QUEUED;
330
331 return 0;
332 }
333
iris_queue_internal_buffers(struct iris_inst * inst,u32 plane)334 int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane)
335 {
336 const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
337 struct iris_buffer *buffer, *next;
338 struct iris_buffers *buffers;
339 const u32 *internal_buf_type;
340 u32 internal_buffer_count, i;
341 int ret;
342
343 if (V4L2_TYPE_IS_OUTPUT(plane)) {
344 internal_buf_type = platform_data->dec_ip_int_buf_tbl;
345 internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
346 } else {
347 internal_buf_type = platform_data->dec_op_int_buf_tbl;
348 internal_buffer_count = platform_data->dec_op_int_buf_tbl_size;
349 }
350
351 for (i = 0; i < internal_buffer_count; i++) {
352 buffers = &inst->buffers[internal_buf_type[i]];
353 list_for_each_entry_safe(buffer, next, &buffers->list, list) {
354 if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
355 continue;
356 if (buffer->attr & BUF_ATTR_QUEUED)
357 continue;
358 ret = iris_queue_buffer(inst, buffer);
359 if (ret)
360 return ret;
361 }
362 }
363
364 return 0;
365 }
366
iris_destroy_internal_buffer(struct iris_inst * inst,struct iris_buffer * buffer)367 int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer)
368 {
369 struct iris_core *core = inst->core;
370
371 list_del(&buffer->list);
372 dma_free_attrs(core->dev, buffer->buffer_size, buffer->kvaddr,
373 buffer->device_addr, buffer->dma_attrs);
374 kfree(buffer);
375
376 return 0;
377 }
378
iris_destroy_internal_buffers(struct iris_inst * inst,u32 plane)379 int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane)
380 {
381 const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
382 struct iris_buffer *buf, *next;
383 struct iris_buffers *buffers;
384 const u32 *internal_buf_type;
385 u32 i, len;
386 int ret;
387
388 if (V4L2_TYPE_IS_OUTPUT(plane)) {
389 internal_buf_type = platform_data->dec_ip_int_buf_tbl;
390 len = platform_data->dec_ip_int_buf_tbl_size;
391 } else {
392 internal_buf_type = platform_data->dec_op_int_buf_tbl;
393 len = platform_data->dec_op_int_buf_tbl_size;
394 }
395
396 for (i = 0; i < len; i++) {
397 buffers = &inst->buffers[internal_buf_type[i]];
398 list_for_each_entry_safe(buf, next, &buffers->list, list) {
399 ret = iris_destroy_internal_buffer(inst, buf);
400 if (ret)
401 return ret;
402 }
403 }
404
405 return 0;
406 }
407
iris_release_internal_buffers(struct iris_inst * inst,enum iris_buffer_type buffer_type)408 static int iris_release_internal_buffers(struct iris_inst *inst,
409 enum iris_buffer_type buffer_type)
410 {
411 const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
412 struct iris_buffers *buffers = &inst->buffers[buffer_type];
413 struct iris_buffer *buffer, *next;
414 int ret;
415
416 list_for_each_entry_safe(buffer, next, &buffers->list, list) {
417 if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
418 continue;
419 if (!(buffer->attr & BUF_ATTR_QUEUED))
420 continue;
421 ret = hfi_ops->session_release_buf(inst, buffer);
422 if (ret)
423 return ret;
424 buffer->attr |= BUF_ATTR_PENDING_RELEASE;
425 }
426
427 return 0;
428 }
429
iris_release_input_internal_buffers(struct iris_inst * inst)430 static int iris_release_input_internal_buffers(struct iris_inst *inst)
431 {
432 const struct iris_platform_data *platform_data = inst->core->iris_platform_data;
433 const u32 *internal_buf_type;
434 u32 internal_buffer_count, i;
435 int ret;
436
437 internal_buf_type = platform_data->dec_ip_int_buf_tbl;
438 internal_buffer_count = platform_data->dec_ip_int_buf_tbl_size;
439
440 for (i = 0; i < internal_buffer_count; i++) {
441 ret = iris_release_internal_buffers(inst, internal_buf_type[i]);
442 if (ret)
443 return ret;
444 }
445
446 return 0;
447 }
448
iris_alloc_and_queue_persist_bufs(struct iris_inst * inst)449 int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst)
450 {
451 struct iris_buffers *buffers = &inst->buffers[BUF_PERSIST];
452 struct iris_buffer *buffer, *next;
453 int ret;
454 u32 i;
455
456 if (!list_empty(&buffers->list))
457 return 0;
458
459 iris_fill_internal_buf_info(inst, BUF_PERSIST);
460
461 for (i = 0; i < buffers->min_count; i++) {
462 ret = iris_create_internal_buffer(inst, BUF_PERSIST, i);
463 if (ret)
464 return ret;
465 }
466
467 list_for_each_entry_safe(buffer, next, &buffers->list, list) {
468 if (buffer->attr & BUF_ATTR_PENDING_RELEASE)
469 continue;
470 if (buffer->attr & BUF_ATTR_QUEUED)
471 continue;
472 ret = iris_queue_buffer(inst, buffer);
473 if (ret)
474 return ret;
475 }
476
477 return 0;
478 }
479
iris_alloc_and_queue_input_int_bufs(struct iris_inst * inst)480 int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst)
481 {
482 int ret;
483
484 iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
485
486 ret = iris_release_input_internal_buffers(inst);
487 if (ret)
488 return ret;
489
490 ret = iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
491 if (ret)
492 return ret;
493
494 return iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
495 }
496
iris_queue_deferred_buffers(struct iris_inst * inst,enum iris_buffer_type buf_type)497 int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type)
498 {
499 struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
500 struct v4l2_m2m_buffer *buffer, *n;
501 struct iris_buffer *buf;
502 int ret;
503
504 iris_scale_power(inst);
505
506 if (buf_type == BUF_INPUT) {
507 v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) {
508 buf = to_iris_buffer(&buffer->vb);
509 if (!(buf->attr & BUF_ATTR_DEFERRED))
510 continue;
511 ret = iris_queue_buffer(inst, buf);
512 if (ret)
513 return ret;
514 }
515 } else {
516 v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buffer, n) {
517 buf = to_iris_buffer(&buffer->vb);
518 if (!(buf->attr & BUF_ATTR_DEFERRED))
519 continue;
520 ret = iris_queue_buffer(inst, buf);
521 if (ret)
522 return ret;
523 }
524 }
525
526 return 0;
527 }
528
iris_vb2_queue_error(struct iris_inst * inst)529 void iris_vb2_queue_error(struct iris_inst *inst)
530 {
531 struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
532 struct vb2_queue *q;
533
534 q = v4l2_m2m_get_src_vq(m2m_ctx);
535 vb2_queue_error(q);
536 q = v4l2_m2m_get_dst_vq(m2m_ctx);
537 vb2_queue_error(q);
538 }
539
540 static struct vb2_v4l2_buffer *
iris_helper_find_buf(struct iris_inst * inst,u32 type,u32 idx)541 iris_helper_find_buf(struct iris_inst *inst, u32 type, u32 idx)
542 {
543 struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
544
545 if (V4L2_TYPE_IS_OUTPUT(type))
546 return v4l2_m2m_src_buf_remove_by_idx(m2m_ctx, idx);
547 else
548 return v4l2_m2m_dst_buf_remove_by_idx(m2m_ctx, idx);
549 }
550
iris_get_ts_metadata(struct iris_inst * inst,u64 timestamp_ns,struct vb2_v4l2_buffer * vbuf)551 static void iris_get_ts_metadata(struct iris_inst *inst, u64 timestamp_ns,
552 struct vb2_v4l2_buffer *vbuf)
553 {
554 u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
555 u32 i;
556
557 for (i = 0; i < ARRAY_SIZE(inst->tss); ++i) {
558 if (inst->tss[i].ts_ns != timestamp_ns)
559 continue;
560
561 vbuf->flags &= ~mask;
562 vbuf->flags |= inst->tss[i].flags;
563 vbuf->timecode = inst->tss[i].tc;
564 return;
565 }
566
567 vbuf->flags &= ~mask;
568 vbuf->flags |= inst->tss[inst->metadata_idx].flags;
569 vbuf->timecode = inst->tss[inst->metadata_idx].tc;
570 }
571
iris_vb2_buffer_done(struct iris_inst * inst,struct iris_buffer * buf)572 int iris_vb2_buffer_done(struct iris_inst *inst, struct iris_buffer *buf)
573 {
574 struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx;
575 struct vb2_v4l2_buffer *vbuf;
576 struct vb2_buffer *vb2;
577 u32 type, state;
578
579 switch (buf->type) {
580 case BUF_INPUT:
581 type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
582 break;
583 case BUF_OUTPUT:
584 type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
585 break;
586 default:
587 return 0; /* Internal DPB Buffers */
588 }
589
590 vbuf = iris_helper_find_buf(inst, type, buf->index);
591 if (!vbuf)
592 return -EINVAL;
593
594 vb2 = &vbuf->vb2_buf;
595
596 if (buf->flags & V4L2_BUF_FLAG_ERROR)
597 state = VB2_BUF_STATE_ERROR;
598 else
599 state = VB2_BUF_STATE_DONE;
600
601 vbuf->flags |= buf->flags;
602
603 if (V4L2_TYPE_IS_CAPTURE(type)) {
604 vb2_set_plane_payload(vb2, 0, buf->data_size);
605 vbuf->sequence = inst->sequence_cap++;
606 iris_get_ts_metadata(inst, buf->timestamp, vbuf);
607 } else {
608 vbuf->sequence = inst->sequence_out++;
609 }
610
611 if (vbuf->flags & V4L2_BUF_FLAG_LAST) {
612 if (!v4l2_m2m_has_stopped(m2m_ctx)) {
613 const struct v4l2_event ev = { .type = V4L2_EVENT_EOS };
614
615 v4l2_event_queue_fh(&inst->fh, &ev);
616 v4l2_m2m_mark_stopped(m2m_ctx);
617 }
618 }
619 vb2->timestamp = buf->timestamp;
620 v4l2_m2m_buf_done(vbuf, state);
621
622 return 0;
623 }
624