1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550)
4 *
5 * Copyright (c) 2024 Qualcomm Technologies, Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11
12 #include "camss.h"
13 #include "camss-vfe.h"
14
15 #define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00)
16
17 #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
18 #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
19
20 #define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC)
21
22 #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
23 #define WM_CFG_EN BIT(0)
24 #define WM_VIR_FRM_EN BIT(1)
25 #define WM_CFG_MODE BIT(16)
26 #define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100)
27 #define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100)
28 #define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100)
29 #define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF)
30 #define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100)
31 #define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF)
32 #define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100)
33
34 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100)
35 #define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100)
36 #define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100)
37 #define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100)
38
39 #define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
40 #define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
41
42 /*
43 * Bus client mapping:
44 *
45 * Full VFE:
46 * 23 = RDI0, 24 = RDI1, 25 = RDI2
47 *
48 * VFE LITE:
49 * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4
50 */
51 #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
52
vfe_wm_start(struct vfe_device * vfe,u8 wm,struct vfe_line * line)53 static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
54 {
55 struct v4l2_pix_format_mplane *pix =
56 &line->video_out.active_fmt.fmt.pix_mp;
57
58 wm = RDI_WM(wm);
59
60 /* no clock gating at bus input */
61 writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
62
63 writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
64
65 writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
66 vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
67 writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
68 vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
69 writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
70 vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
71 writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
72
73 /* no dropped frames, one irq per frame */
74 writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
75 writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
76 writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm));
77 writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm));
78
79 writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm));
80 writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm));
81
82 writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
83 }
84
vfe_wm_stop(struct vfe_device * vfe,u8 wm)85 static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
86 {
87 wm = RDI_WM(wm);
88 writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
89 }
90
vfe_wm_update(struct vfe_device * vfe,u8 wm,u32 addr,struct vfe_line * line)91 static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
92 struct vfe_line *line)
93 {
94 wm = RDI_WM(wm);
95 writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
96
97 dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n",
98 wm, addr);
99 }
100
vfe_reg_update(struct vfe_device * vfe,enum vfe_line_id line_id)101 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
102 {
103 int port_id = line_id;
104
105 camss_reg_update(vfe->camss, vfe->id, port_id, false);
106 }
107
vfe_reg_update_clear(struct vfe_device * vfe,enum vfe_line_id line_id)108 static inline void vfe_reg_update_clear(struct vfe_device *vfe,
109 enum vfe_line_id line_id)
110 {
111 int port_id = line_id;
112
113 camss_reg_update(vfe->camss, vfe->id, port_id, true);
114 }
115
116 static const struct camss_video_ops vfe_video_ops_780 = {
117 .queue_buffer = vfe_queue_buffer_v2,
118 .flush_buffers = vfe_flush_buffers,
119 };
120
vfe_subdev_init(struct device * dev,struct vfe_device * vfe)121 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
122 {
123 vfe->video_ops = vfe_video_ops_780;
124 }
125
vfe_global_reset(struct vfe_device * vfe)126 static void vfe_global_reset(struct vfe_device *vfe)
127 {
128 vfe_isr_reset_ack(vfe);
129 }
130
vfe_isr(int irq,void * dev)131 static irqreturn_t vfe_isr(int irq, void *dev)
132 {
133 /* nop */
134 return IRQ_HANDLED;
135 }
136
vfe_halt(struct vfe_device * vfe)137 static int vfe_halt(struct vfe_device *vfe)
138 {
139 /* rely on vfe_disable_output() to stop the VFE */
140 return 0;
141 }
142
143 const struct vfe_hw_ops vfe_ops_780 = {
144 .global_reset = vfe_global_reset,
145 .hw_version = vfe_hw_version,
146 .isr = vfe_isr,
147 .pm_domain_off = vfe_pm_domain_off,
148 .pm_domain_on = vfe_pm_domain_on,
149 .reg_update = vfe_reg_update,
150 .reg_update_clear = vfe_reg_update_clear,
151 .subdev_init = vfe_subdev_init,
152 .vfe_disable = vfe_disable,
153 .vfe_enable = vfe_enable_v2,
154 .vfe_halt = vfe_halt,
155 .vfe_wm_start = vfe_wm_start,
156 .vfe_wm_stop = vfe_wm_stop,
157 .vfe_buf_done = vfe_buf_done,
158 .vfe_wm_update = vfe_wm_update,
159 };
160