1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-csiphy-3ph-1-0.c
4 *
5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
6 *
7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2016-2018 Linaro Ltd.
9 */
10
11 #include "camss.h"
12 #include "camss-csiphy.h"
13
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17
18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
19 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6))
20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
21 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3)
22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
28 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50
29 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n))
30 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa
31 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n))
32 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2)
33 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n))
34 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0)
35 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n))
36 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2
37 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n))
38 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0)
39 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1)
40 #define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n))
41 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1
42 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n))
43 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8
44
45 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n))
46 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
47 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
48 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
49 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n))
50
51 #define CSIPHY_DEFAULT_PARAMS 0
52 #define CSIPHY_LANE_ENABLE 1
53 #define CSIPHY_SETTLE_CNT_LOWER_BYTE 2
54 #define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3
55 #define CSIPHY_DNP_PARAMS 4
56 #define CSIPHY_2PH_REGS 5
57 #define CSIPHY_3PH_REGS 6
58
59 struct csiphy_lane_regs {
60 s32 reg_addr;
61 s32 reg_data;
62 s32 delay;
63 u32 csiphy_param_type;
64 };
65
66 /* GEN2 1.0 2PH */
67 static const struct
68 csiphy_lane_regs lane_regs_sdm845[] = {
69 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
70 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
71 {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
72 {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
73 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
74 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
75 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
76 {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
77 {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
78 {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
79 {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
80 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
81 {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
82 {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
83 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
84 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
85 {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
86 {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
87 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
88 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
89 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
90 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
91 {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
92 {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
93 {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
94 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
95 {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
96 {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
97 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
98 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
99 {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
100 {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
101 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
102 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
103 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
104 {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
105 {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
106 {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
107 {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
108 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
109 {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
110 {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
111 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
112 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
113 {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
114 {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
115 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
116 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
117 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
118 {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
119 {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
120 {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
121 {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
122 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
123 {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
124 {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
125 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
126 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
127 {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
128 {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
129 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
130 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
131 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
132 {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
133 {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
134 {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
135 {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
136 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
137 {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
138 {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
139 };
140
141 /* GEN2 1.1 2PH */
142 static const struct
143 csiphy_lane_regs lane_regs_sc8280xp[] = {
144 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
145 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
146 {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
147 {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
148 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
149 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
150 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
151 {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
152 {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
153 {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
154 {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
155 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
156 {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
157 {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
158 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
159 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
160 {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
161 {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
162 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
163 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
164 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
165 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
166 {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
167 {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
168 {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
169 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
170 {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
171 {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
172 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
173 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
174 {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
175 {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
176 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
177 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
178 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
179 {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
180 {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
181 {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
182 {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
183 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
184 {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
185 {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
186 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
187 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
188 {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
189 {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
190 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
191 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
192 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
193 {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
194 {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
195 {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
196 {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
197 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
198 {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
199 {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
200 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
201 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
202 {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
203 {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
204 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
205 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
206 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
207 {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS},
208 {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
209 {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
210 {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
211 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
212 {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
213 {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
214 };
215
216 /* GEN2 1.2.1 2PH */
217 static const struct
218 csiphy_lane_regs lane_regs_sm8250[] = {
219 {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
220 {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
221 {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
222 {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
223 {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
224 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
225 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
226 {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
227 {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
228 {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
229 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
230 {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
231 {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
232 {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
233 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
234 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
235 {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
236 {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
237 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
238 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
239 {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
240 {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
241 {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
242 {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
243 {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
244 {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
245 {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
246 {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
247 {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
248 {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
249 {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
250 {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
251 {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
252 {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
253 {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
254 {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
255 {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
256 {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
257 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
258 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
259 {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
260 {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
261 {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
262 {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
263 {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
264 {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
265 {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
266 {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
267 {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
268 {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
269 {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
270 {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
271 {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
272 {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
273 {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
274 {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
275 {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
276 {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
277 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
278 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
279 {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
280 {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
281 {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
282 {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
283 {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
284 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
285 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
286 {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
287 {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
288 {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
289 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
290 {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
291 {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
292 {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
293 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
294 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
295 {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
296 {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
297 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
298 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
299 {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
300 {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
301 {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
302 {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
303 {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
304 {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
305 {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
306 {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
307 {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
308 {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
309 {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
310 {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
311 {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
312 {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
313 {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
314 {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
315 {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
316 {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS},
317 {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
318 {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
319 };
320
321 /* GEN2 2.1.2 2PH DPHY mode */
322 static const struct
323 csiphy_lane_regs lane_regs_sm8550[] = {
324 {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
325 {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
326 {0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
327 {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
328 {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
329 {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
330 {0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
331 {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
332 {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
333 {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
334 {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
335 {0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
336 {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
337 {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
338 {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
339 {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
340 {0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
341 {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
342 {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
343 {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
344 {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
345 {0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
346 {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
347 {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
348 {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
349 {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
350 {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
351 {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
352 {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
353 {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
354 {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
355 {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
356 {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
357 {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
358 {0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
359 {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
360 {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
361 {0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
362 {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
363 {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
364 {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
365 {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
366 {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
367 {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
368 {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
369 {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
370 {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
371 {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
372 {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
373 {0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
374 {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
375 {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
376 {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
377 {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
378 {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
379 {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
380 {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
381 {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
382 {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
383 {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
384 {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
385 {0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
386 {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
387 {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
388 {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
389 {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
390 {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
391 {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
392 {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
393 {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
394 {0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
395 {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
396 {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
397 {0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
398 {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
399 {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
400 {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
401 {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
402 {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
403 {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
404 {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
405 {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
406 {0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
407 {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
408 {0x0094, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
409 {0x005C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
410 {0x0060, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
411 {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
412 {0x0494, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
413 {0x045C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
414 {0x0460, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
415 {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
416 {0x0894, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
417 {0x085C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
418 {0x0860, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
419 {0x0864, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
420 {0x0C94, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS},
421 {0x0C5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
422 {0x0C60, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS},
423 {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
424 };
425
csiphy_hw_version_read(struct csiphy_device * csiphy,struct device * dev)426 static void csiphy_hw_version_read(struct csiphy_device *csiphy,
427 struct device *dev)
428 {
429 struct csiphy_device_regs *regs = csiphy->regs;
430 u32 hw_version;
431
432 writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csiphy->base +
433 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
434
435 hw_version = readl_relaxed(csiphy->base +
436 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12));
437 hw_version |= readl_relaxed(csiphy->base +
438 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8;
439 hw_version |= readl_relaxed(csiphy->base +
440 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16;
441 hw_version |= readl_relaxed(csiphy->base +
442 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24;
443
444 dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
445 }
446
447 /*
448 * csiphy_reset - Perform software reset on CSIPHY module
449 * @csiphy: CSIPHY device
450 */
csiphy_reset(struct csiphy_device * csiphy)451 static void csiphy_reset(struct csiphy_device *csiphy)
452 {
453 struct csiphy_device_regs *regs = csiphy->regs;
454
455 writel_relaxed(0x1, csiphy->base +
456 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0));
457 usleep_range(5000, 8000);
458 writel_relaxed(0x0, csiphy->base +
459 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0));
460 }
461
csiphy_isr(int irq,void * dev)462 static irqreturn_t csiphy_isr(int irq, void *dev)
463 {
464 struct csiphy_device *csiphy = dev;
465 struct csiphy_device_regs *regs = csiphy->regs;
466 int i;
467
468 for (i = 0; i < 11; i++) {
469 int c = i + 22;
470 u8 val = readl_relaxed(csiphy->base +
471 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i));
472
473 writel_relaxed(val, csiphy->base +
474 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c));
475 }
476
477 writel_relaxed(0x1, csiphy->base +
478 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10));
479 writel_relaxed(0x0, csiphy->base +
480 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10));
481
482 for (i = 22; i < 33; i++) {
483 writel_relaxed(0x0, csiphy->base +
484 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i));
485 }
486
487 return IRQ_HANDLED;
488 }
489
490 /*
491 * csiphy_settle_cnt_calc - Calculate settle count value
492 *
493 * Helper function to calculate settle count value. This is
494 * based on the CSI2 T_hs_settle parameter which in turn
495 * is calculated based on the CSI2 transmitter link frequency.
496 *
497 * Return settle count value or 0 if the CSI2 link frequency
498 * is not available
499 */
csiphy_settle_cnt_calc(s64 link_freq,u32 timer_clk_rate)500 static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
501 {
502 u32 ui; /* ps */
503 u32 timer_period; /* ps */
504 u32 t_hs_prepare_max; /* ps */
505 u32 t_hs_settle; /* ps */
506 u8 settle_cnt;
507
508 if (link_freq <= 0)
509 return 0;
510
511 ui = div_u64(1000000000000LL, link_freq);
512 ui /= 2;
513 t_hs_prepare_max = 85000 + 6 * ui;
514 t_hs_settle = t_hs_prepare_max;
515
516 timer_period = div_u64(1000000000000LL, timer_clk_rate);
517 settle_cnt = t_hs_settle / timer_period - 6;
518
519 return settle_cnt;
520 }
521
csiphy_gen1_config_lanes(struct csiphy_device * csiphy,struct csiphy_config * cfg,u8 settle_cnt)522 static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy,
523 struct csiphy_config *cfg,
524 u8 settle_cnt)
525 {
526 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
527 int i, l = 0;
528 u8 val;
529
530 for (i = 0; i <= c->num_data; i++) {
531 if (i == c->num_data)
532 l = 7;
533 else
534 l = c->data[i].pos * 2;
535
536 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
537 val |= 0x17;
538 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
539
540 val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT;
541 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
542
543 val = settle_cnt;
544 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
545
546 val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM |
547 CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT;
548 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
549
550 val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT;
551 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
552
553 val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT;
554 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
555
556 val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP |
557 CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE;
558 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
559
560 val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP;
561 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
562
563 val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP;
564 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
565
566 val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL;
567 writel_relaxed(val, csiphy->base +
568 CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l));
569 }
570
571 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
572 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
573
574 if (csiphy->camss->res->version == CAMSS_660)
575 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660;
576 else
577 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
578 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
579
580 val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
581 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
582 }
583
csiphy_gen2_config_lanes(struct csiphy_device * csiphy,u8 settle_cnt)584 static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
585 u8 settle_cnt)
586 {
587 const struct csiphy_lane_regs *r = csiphy->regs->lane_regs;
588 int i, array_size = csiphy->regs->lane_array_size;
589 u32 val;
590
591 for (i = 0; i < array_size; i++, r++) {
592 switch (r->csiphy_param_type) {
593 case CSIPHY_SETTLE_CNT_LOWER_BYTE:
594 val = settle_cnt & 0xff;
595 break;
596 case CSIPHY_DNP_PARAMS:
597 continue;
598 default:
599 val = r->reg_data;
600 break;
601 }
602 writel_relaxed(val, csiphy->base + r->reg_addr);
603 }
604 }
605
csiphy_get_lane_mask(struct csiphy_lanes_cfg * lane_cfg)606 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)
607 {
608 u8 lane_mask;
609 int i;
610
611 lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
612
613 for (i = 0; i < lane_cfg->num_data; i++)
614 lane_mask |= 1 << lane_cfg->data[i].pos;
615
616 return lane_mask;
617 }
618
csiphy_is_gen2(u32 version)619 static bool csiphy_is_gen2(u32 version)
620 {
621 bool ret = false;
622
623 switch (version) {
624 case CAMSS_7280:
625 case CAMSS_8250:
626 case CAMSS_8280XP:
627 case CAMSS_845:
628 case CAMSS_8550:
629 ret = true;
630 break;
631 }
632
633 return ret;
634 }
635
csiphy_lanes_enable(struct csiphy_device * csiphy,struct csiphy_config * cfg,s64 link_freq,u8 lane_mask)636 static void csiphy_lanes_enable(struct csiphy_device *csiphy,
637 struct csiphy_config *cfg,
638 s64 link_freq, u8 lane_mask)
639 {
640 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
641 struct csiphy_device_regs *regs = csiphy->regs;
642 u8 settle_cnt;
643 u8 val;
644 int i;
645
646 settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
647
648 val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
649 for (i = 0; i < c->num_data; i++)
650 val |= BIT(c->data[i].pos * 2);
651
652 writel_relaxed(val, csiphy->base +
653 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5));
654
655 val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
656 writel_relaxed(val, csiphy->base +
657 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
658
659 val = 0x02;
660 writel_relaxed(val, csiphy->base +
661 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 7));
662
663 val = 0x00;
664 writel_relaxed(val, csiphy->base +
665 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0));
666
667 if (csiphy_is_gen2(csiphy->camss->res->version))
668 csiphy_gen2_config_lanes(csiphy, settle_cnt);
669 else
670 csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
671
672 /* IRQ_MASK registers - disable all interrupts */
673 for (i = 11; i < 22; i++) {
674 writel_relaxed(0, csiphy->base +
675 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i));
676 }
677 }
678
csiphy_lanes_disable(struct csiphy_device * csiphy,struct csiphy_config * cfg)679 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
680 struct csiphy_config *cfg)
681 {
682 struct csiphy_device_regs *regs = csiphy->regs;
683
684 writel_relaxed(0, csiphy->base +
685 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5));
686
687 writel_relaxed(0, csiphy->base +
688 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6));
689 }
690
csiphy_init(struct csiphy_device * csiphy)691 static int csiphy_init(struct csiphy_device *csiphy)
692 {
693 struct device *dev = csiphy->camss->dev;
694 struct csiphy_device_regs *regs;
695
696 regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL);
697 if (!regs)
698 return -ENOMEM;
699
700 csiphy->regs = regs;
701 regs->offset = 0x800;
702
703 switch (csiphy->camss->res->version) {
704 case CAMSS_845:
705 regs->lane_regs = &lane_regs_sdm845[0];
706 regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
707 break;
708 case CAMSS_7280:
709 case CAMSS_8250:
710 regs->lane_regs = &lane_regs_sm8250[0];
711 regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
712 break;
713 case CAMSS_8280XP:
714 regs->lane_regs = &lane_regs_sc8280xp[0];
715 regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
716 break;
717 case CAMSS_8550:
718 regs->lane_regs = &lane_regs_sm8550[0];
719 regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
720 regs->offset = 0x1000;
721 break;
722 default:
723 WARN(1, "unknown csiphy version\n");
724 return -ENODEV;
725 }
726
727 return 0;
728 }
729
730 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
731 .get_lane_mask = csiphy_get_lane_mask,
732 .hw_version_read = csiphy_hw_version_read,
733 .reset = csiphy_reset,
734 .lanes_enable = csiphy_lanes_enable,
735 .lanes_disable = csiphy_lanes_disable,
736 .isr = csiphy_isr,
737 .init = csiphy_init,
738 };
739