1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
4 *
5 * Copyright (c) 2024 Qualcomm Technologies, Inc.
6 */
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/of.h>
13
14 #include "camss.h"
15 #include "camss-csid.h"
16 #include "camss-csid-780.h"
17
18 #define CSID_IO_PATH_CFG0(csid) (0x4 * (csid))
19 #define OUTPUT_IFE_EN 0x100
20 #define INTERNAL_CSID 1
21
22 #define CSID_RST_CFG 0xC
23 #define RST_MODE BIT(0)
24 #define RST_LOCATION BIT(4)
25
26 #define CSID_RST_CMD 0x10
27 #define SELECT_HW_RST BIT(0)
28 #define SELECT_IRQ_RST BIT(2)
29
30 #define CSID_IRQ_CMD 0x14
31 #define IRQ_CMD_CLEAR BIT(0)
32
33 #define CSID_RUP_AUP_CMD 0x18
34 #define CSID_RUP_AUP_RDI(rdi) ((BIT(4) | BIT(20)) << (rdi))
35
36 #define CSID_TOP_IRQ_STATUS 0x7C
37 #define TOP_IRQ_STATUS_RESET_DONE BIT(0)
38
39 #define CSID_TOP_IRQ_MASK 0x80
40 #define CSID_TOP_IRQ_CLEAR 0x84
41 #define CSID_TOP_IRQ_SET 0x88
42
43 #define CSID_CSI2_RX_IRQ_STATUS 0x9C
44 #define CSID_CSI2_RX_IRQ_MASK 0xA0
45 #define CSID_CSI2_RX_IRQ_CLEAR 0xA4
46 #define CSID_CSI2_RX_IRQ_SET 0xA8
47
48 #define CSID_BUF_DONE_IRQ_STATUS 0x8C
49 #define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14)
50 #define CSID_BUF_DONE_IRQ_MASK 0x90
51 #define CSID_BUF_DONE_IRQ_CLEAR 0x94
52 #define CSID_BUF_DONE_IRQ_SET 0x98
53
54 #define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0xEC + 0x10 * (rdi))
55 #define RUP_DONE_IRQ_STATUS BIT(23)
56
57 #define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0xF4 + 0x10 * (rdi))
58 #define CSID_CSI2_RDIN_IRQ_SET(rdi) (0xF8 + 0x10 * (rdi))
59
60 #define CSID_CSI2_RX_CFG0 0x200
61 #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
62 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4
63 #define CSI2_RX_CFG0_PHY_NUM_SEL 20
64
65 #define CSID_CSI2_RX_CFG1 0x204
66 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
67 #define CSI2_RX_CFG1_VC_MODE BIT(2)
68
69 #define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi))
70 #define RDI_CFG0_TIMESTAMP_EN BIT(6)
71 #define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
72 #define RDI_CFG0_DECODE_FORMAT 12
73 #define RDI_CFG0_DT 16
74 #define RDI_CFG0_VC 22
75 #define RDI_CFG0_DT_ID 27
76 #define RDI_CFG0_EN BIT(31)
77
78 #define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi))
79 #define RDI_CTRL_START_CMD BIT(0)
80
81 #define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi))
82 #define RDI_CFG1_DROP_H_EN BIT(5)
83 #define RDI_CFG1_DROP_V_EN BIT(6)
84 #define RDI_CFG1_CROP_H_EN BIT(7)
85 #define RDI_CFG1_CROP_V_EN BIT(8)
86 #define RDI_CFG1_PIX_STORE BIT(10)
87 #define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
88
89 #define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi))
90 #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi))
91
92 #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
93
__csid_configure_rx(struct csid_device * csid,struct csid_phy_config * phy,int vc)94 static void __csid_configure_rx(struct csid_device *csid,
95 struct csid_phy_config *phy, int vc)
96 {
97 int val;
98
99 val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
100 val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
101 val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL;
102
103 writel(val, csid->base + CSID_CSI2_RX_CFG0);
104
105 val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
106 if (vc > 3)
107 val |= CSI2_RX_CFG1_VC_MODE;
108
109 writel(val, csid->base + CSID_CSI2_RX_CFG1);
110 }
111
__csid_ctrl_rdi(struct csid_device * csid,int enable,u8 rdi)112 static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
113 {
114 int val = 0;
115
116 if (enable)
117 val = RDI_CTRL_START_CMD;
118
119 writel(val, csid->base + CSID_RDI_CTRL(rdi));
120 }
121
__csid_configure_wrapper(struct csid_device * csid)122 static void __csid_configure_wrapper(struct csid_device *csid)
123 {
124 u32 val;
125
126 /* csid lite doesn't need to configure top register */
127 if (csid->res->is_lite)
128 return;
129
130 val = OUTPUT_IFE_EN | INTERNAL_CSID;
131 writel(val, csid->camss->csid_wrapper_base + CSID_IO_PATH_CFG0(csid->id));
132 }
133
__csid_configure_rdi_stream(struct csid_device * csid,u8 enable,u8 vc)134 static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
135 {
136 u32 val;
137 u8 lane_cnt = csid->phy.lane_cnt;
138 /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
139 struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
140 const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
141 csid->res->formats->nformats,
142 input_format->code);
143
144 if (!lane_cnt)
145 lane_cnt = 4;
146
147 /*
148 * DT_ID is a two bit bitfield that is concatenated with
149 * the four least significant bits of the five bit VC
150 * bitfield to generate an internal CID value.
151 *
152 * CSID_RDI_CFG0(vc)
153 * DT_ID : 28:27
154 * VC : 26:22
155 * DT : 21:16
156 *
157 * CID : VC 3:0 << 2 | DT_ID 1:0
158 */
159 u8 dt_id = vc & 0x03;
160
161 val = RDI_CFG0_TIMESTAMP_EN;
162 val |= RDI_CFG0_TIMESTAMP_STB_SEL;
163 /* note: for non-RDI path, this should be format->decode_format */
164 val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
165 val |= vc << RDI_CFG0_VC;
166 val |= format->data_type << RDI_CFG0_DT;
167 val |= dt_id << RDI_CFG0_DT_ID;
168
169 writel(val, csid->base + CSID_RDI_CFG0(vc));
170
171 val = RDI_CFG1_PACKING_FORMAT_MIPI;
172 val |= RDI_CFG1_PIX_STORE;
173 val |= RDI_CFG1_DROP_H_EN;
174 val |= RDI_CFG1_DROP_V_EN;
175 val |= RDI_CFG1_CROP_H_EN;
176 val |= RDI_CFG1_CROP_V_EN;
177
178 writel(val, csid->base + CSID_RDI_CFG1(vc));
179
180 val = 0;
181 writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
182
183 val = 1;
184 writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
185
186 val = 0;
187 writel(val, csid->base + CSID_RDI_CTRL(vc));
188
189 val = readl(csid->base + CSID_RDI_CFG0(vc));
190
191 if (enable)
192 val |= RDI_CFG0_EN;
193 writel(val, csid->base + CSID_RDI_CFG0(vc));
194 }
195
csid_configure_stream(struct csid_device * csid,u8 enable)196 static void csid_configure_stream(struct csid_device *csid, u8 enable)
197 {
198 u8 i;
199
200 __csid_configure_wrapper(csid);
201
202 /* Loop through all enabled VCs and configure stream for each */
203 for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
204 if (csid->phy.en_vc & BIT(i)) {
205 __csid_configure_rdi_stream(csid, enable, i);
206 __csid_configure_rx(csid, &csid->phy, i);
207 __csid_ctrl_rdi(csid, enable, i);
208 }
209 }
210
csid_configure_testgen_pattern(struct csid_device * csid,s32 val)211 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
212 {
213 return 0;
214 }
215
csid_subdev_reg_update(struct csid_device * csid,int port_id,bool clear)216 static void csid_subdev_reg_update(struct csid_device *csid, int port_id, bool clear)
217 {
218 if (clear) {
219 csid->reg_update &= ~CSID_RUP_AUP_RDI(port_id);
220 } else {
221 csid->reg_update |= CSID_RUP_AUP_RDI(port_id);
222 writel(csid->reg_update, csid->base + CSID_RUP_AUP_CMD);
223 }
224 }
225
226 /*
227 * csid_isr - CSID module interrupt service routine
228 * @irq: Interrupt line
229 * @dev: CSID device
230 *
231 * Return IRQ_HANDLED on success
232 */
csid_isr(int irq,void * dev)233 static irqreturn_t csid_isr(int irq, void *dev)
234 {
235 struct csid_device *csid = dev;
236 u32 val, buf_done_val;
237 u8 reset_done;
238 int i;
239
240 val = readl(csid->base + CSID_TOP_IRQ_STATUS);
241 writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
242 reset_done = val & TOP_IRQ_STATUS_RESET_DONE;
243
244 val = readl(csid->base + CSID_CSI2_RX_IRQ_STATUS);
245 writel(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
246
247 buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
248 writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
249
250 /* Read and clear IRQ status for each enabled RDI channel */
251 for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
252 if (csid->phy.en_vc & BIT(i)) {
253 val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
254 writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
255
256 if (val & RUP_DONE_IRQ_STATUS)
257 /* clear the reg update bit */
258 csid_subdev_reg_update(csid, i, true);
259
260 if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
261 /*
262 * For Titan 780, bus done and RUP IRQ have been moved to
263 * CSID from VFE. Once CSID received bus done, need notify
264 * VFE of this event. Trigger VFE to handle bus done process.
265 */
266 camss_buf_done(csid->camss, csid->id, i);
267 }
268 }
269
270 val = IRQ_CMD_CLEAR;
271 writel(val, csid->base + CSID_IRQ_CMD);
272
273 if (reset_done)
274 complete(&csid->reset_complete);
275
276 return IRQ_HANDLED;
277 }
278
279 /*
280 * csid_reset - Trigger reset on CSID module and wait to complete
281 * @csid: CSID device
282 *
283 * Return 0 on success or a negative error code otherwise
284 */
csid_reset(struct csid_device * csid)285 static int csid_reset(struct csid_device *csid)
286 {
287 unsigned long time;
288 u32 val;
289 int i;
290
291 reinit_completion(&csid->reset_complete);
292
293 writel(1, csid->base + CSID_TOP_IRQ_CLEAR);
294 writel(1, csid->base + CSID_IRQ_CMD);
295 writel(1, csid->base + CSID_TOP_IRQ_MASK);
296
297 for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
298 if (csid->phy.en_vc & BIT(i)) {
299 writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i),
300 csid->base + CSID_BUF_DONE_IRQ_CLEAR);
301 writel(IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
302 writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i),
303 csid->base + CSID_BUF_DONE_IRQ_MASK);
304 }
305
306 /* preserve registers */
307 val = RST_LOCATION | RST_MODE;
308 writel(val, csid->base + CSID_RST_CFG);
309
310 val = SELECT_HW_RST | SELECT_IRQ_RST;
311 writel(val, csid->base + CSID_RST_CMD);
312
313 time = wait_for_completion_timeout(&csid->reset_complete,
314 msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
315 if (!time) {
316 dev_err(csid->camss->dev, "CSID reset timeout\n");
317 return -EIO;
318 }
319
320 return 0;
321 }
322
csid_subdev_init(struct csid_device * csid)323 static void csid_subdev_init(struct csid_device *csid)
324 {
325 csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
326 }
327
328 const struct csid_hw_ops csid_ops_780 = {
329 .configure_stream = csid_configure_stream,
330 .configure_testgen_pattern = csid_configure_testgen_pattern,
331 .hw_version = csid_hw_version,
332 .isr = csid_isr,
333 .reset = csid_reset,
334 .src_pad_code = csid_src_pad_code,
335 .subdev_init = csid_subdev_init,
336 .reg_update = csid_subdev_reg_update,
337 };
338