1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
4 *
5 * Copyright (C) STMicroelectronics SA 2019
6 * Authors: Mickael Guene <mickael.guene@st.com>
7 * for STMicroelectronics.
8 *
9 *
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/of_graph.h>
19 #include <linux/regulator/consumer.h>
20 #include <media/mipi-csi2.h>
21 #include <media/v4l2-async.h>
22 #include <media/v4l2-cci.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-fwnode.h>
26 #include <media/v4l2-subdev.h>
27
28 #define MIPID02_CLK_LANE_WR_REG1 CCI_REG8(0x01)
29 #define MIPID02_CLK_LANE_REG1 CCI_REG8(0x02)
30 #define MIPID02_CLK_LANE_REG3 CCI_REG8(0x04)
31 #define MIPID02_DATA_LANE0_REG1 CCI_REG8(0x05)
32 #define MIPID02_DATA_LANE0_REG2 CCI_REG8(0x06)
33 #define MIPID02_DATA_LANE1_REG1 CCI_REG8(0x09)
34 #define MIPID02_DATA_LANE1_REG2 CCI_REG8(0x0a)
35 #define MIPID02_MODE_REG1 CCI_REG8(0x14)
36 #define MIPID02_MODE_REG2 CCI_REG8(0x15)
37 #define MIPID02_DATA_ID_RREG CCI_REG8(0x17)
38 #define MIPID02_DATA_SELECTION_CTRL CCI_REG8(0x19)
39 #define MIPID02_PIX_WIDTH_CTRL CCI_REG8(0x1e)
40 #define MIPID02_PIX_WIDTH_CTRL_EMB CCI_REG8(0x1f)
41
42 /* Bits definition for MIPID02_CLK_LANE_REG1 */
43 #define CLK_ENABLE BIT(0)
44 /* Bits definition for MIPID02_CLK_LANE_REG3 */
45 #define CLK_MIPI_CSI BIT(1)
46 /* Bits definition for MIPID02_DATA_LANE0_REG1 */
47 #define DATA_ENABLE BIT(0)
48 /* Bits definition for MIPID02_DATA_LANEx_REG2 */
49 #define DATA_MIPI_CSI BIT(0)
50 /* Bits definition for MIPID02_MODE_REG1 */
51 #define MODE_DATA_SWAP BIT(2)
52 #define MODE_NO_BYPASS BIT(6)
53 /* Bits definition for MIPID02_MODE_REG2 */
54 #define MODE_HSYNC_ACTIVE_HIGH BIT(1)
55 #define MODE_VSYNC_ACTIVE_HIGH BIT(2)
56 #define MODE_PCLK_SAMPLE_RISING BIT(3)
57 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
58 #define SELECTION_MANUAL_DATA BIT(2)
59 #define SELECTION_MANUAL_WIDTH BIT(3)
60
61 static const u32 mipid02_supported_fmt_codes[] = {
62 MEDIA_BUS_FMT_SBGGR8_1X8, MEDIA_BUS_FMT_SGBRG8_1X8,
63 MEDIA_BUS_FMT_SGRBG8_1X8, MEDIA_BUS_FMT_SRGGB8_1X8,
64 MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10,
65 MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10,
66 MEDIA_BUS_FMT_SBGGR12_1X12, MEDIA_BUS_FMT_SGBRG12_1X12,
67 MEDIA_BUS_FMT_SGRBG12_1X12, MEDIA_BUS_FMT_SRGGB12_1X12,
68 MEDIA_BUS_FMT_YUYV8_1X16, MEDIA_BUS_FMT_YVYU8_1X16,
69 MEDIA_BUS_FMT_UYVY8_1X16, MEDIA_BUS_FMT_VYUY8_1X16,
70 MEDIA_BUS_FMT_RGB565_1X16, MEDIA_BUS_FMT_BGR888_1X24,
71 MEDIA_BUS_FMT_Y8_1X8, MEDIA_BUS_FMT_JPEG_1X8
72 };
73
74 /* regulator supplies */
75 static const char * const mipid02_supply_name[] = {
76 "VDDE", /* 1.8V digital I/O supply */
77 "VDDIN", /* 1V8 voltage regulator supply */
78 };
79
80 #define MIPID02_NUM_SUPPLIES ARRAY_SIZE(mipid02_supply_name)
81
82 #define MIPID02_SINK_0 0
83 #define MIPID02_SINK_1 1
84 #define MIPID02_SOURCE 2
85 #define MIPID02_PAD_NB 3
86
87 struct mipid02_dev {
88 struct i2c_client *i2c_client;
89 struct regulator_bulk_data supplies[MIPID02_NUM_SUPPLIES];
90 struct v4l2_subdev sd;
91 struct regmap *regmap;
92 struct media_pad pad[MIPID02_PAD_NB];
93 struct clk *xclk;
94 struct gpio_desc *reset_gpio;
95 /* endpoints info */
96 struct v4l2_fwnode_endpoint rx;
97 struct v4l2_fwnode_endpoint tx;
98 /* remote source */
99 struct v4l2_async_notifier notifier;
100 struct v4l2_subdev *s_subdev;
101 u16 s_subdev_pad_id;
102 /* registers */
103 struct {
104 u8 clk_lane_reg1;
105 u8 data_lane0_reg1;
106 u8 data_lane1_reg1;
107 u8 mode_reg1;
108 u8 mode_reg2;
109 u8 data_selection_ctrl;
110 u8 data_id_rreg;
111 u8 pix_width_ctrl;
112 u8 pix_width_ctrl_emb;
113 } r;
114 };
115
bpp_from_code(__u32 code)116 static int bpp_from_code(__u32 code)
117 {
118 switch (code) {
119 case MEDIA_BUS_FMT_SBGGR8_1X8:
120 case MEDIA_BUS_FMT_SGBRG8_1X8:
121 case MEDIA_BUS_FMT_SGRBG8_1X8:
122 case MEDIA_BUS_FMT_SRGGB8_1X8:
123 case MEDIA_BUS_FMT_Y8_1X8:
124 return 8;
125 case MEDIA_BUS_FMT_SBGGR10_1X10:
126 case MEDIA_BUS_FMT_SGBRG10_1X10:
127 case MEDIA_BUS_FMT_SGRBG10_1X10:
128 case MEDIA_BUS_FMT_SRGGB10_1X10:
129 return 10;
130 case MEDIA_BUS_FMT_SBGGR12_1X12:
131 case MEDIA_BUS_FMT_SGBRG12_1X12:
132 case MEDIA_BUS_FMT_SGRBG12_1X12:
133 case MEDIA_BUS_FMT_SRGGB12_1X12:
134 return 12;
135 case MEDIA_BUS_FMT_YUYV8_1X16:
136 case MEDIA_BUS_FMT_YVYU8_1X16:
137 case MEDIA_BUS_FMT_UYVY8_1X16:
138 case MEDIA_BUS_FMT_VYUY8_1X16:
139 case MEDIA_BUS_FMT_RGB565_1X16:
140 return 16;
141 case MEDIA_BUS_FMT_BGR888_1X24:
142 return 24;
143 default:
144 return 0;
145 }
146 }
147
data_type_from_code(__u32 code)148 static u8 data_type_from_code(__u32 code)
149 {
150 switch (code) {
151 case MEDIA_BUS_FMT_SBGGR8_1X8:
152 case MEDIA_BUS_FMT_SGBRG8_1X8:
153 case MEDIA_BUS_FMT_SGRBG8_1X8:
154 case MEDIA_BUS_FMT_SRGGB8_1X8:
155 case MEDIA_BUS_FMT_Y8_1X8:
156 return MIPI_CSI2_DT_RAW8;
157 case MEDIA_BUS_FMT_SBGGR10_1X10:
158 case MEDIA_BUS_FMT_SGBRG10_1X10:
159 case MEDIA_BUS_FMT_SGRBG10_1X10:
160 case MEDIA_BUS_FMT_SRGGB10_1X10:
161 return MIPI_CSI2_DT_RAW10;
162 case MEDIA_BUS_FMT_SBGGR12_1X12:
163 case MEDIA_BUS_FMT_SGBRG12_1X12:
164 case MEDIA_BUS_FMT_SGRBG12_1X12:
165 case MEDIA_BUS_FMT_SRGGB12_1X12:
166 return MIPI_CSI2_DT_RAW12;
167 case MEDIA_BUS_FMT_YUYV8_1X16:
168 case MEDIA_BUS_FMT_YVYU8_1X16:
169 case MEDIA_BUS_FMT_UYVY8_1X16:
170 case MEDIA_BUS_FMT_VYUY8_1X16:
171 return MIPI_CSI2_DT_YUV422_8B;
172 case MEDIA_BUS_FMT_BGR888_1X24:
173 return MIPI_CSI2_DT_RGB888;
174 case MEDIA_BUS_FMT_RGB565_1X16:
175 return MIPI_CSI2_DT_RGB565;
176 default:
177 return 0;
178 }
179 }
180
get_fmt_code(__u32 code)181 static __u32 get_fmt_code(__u32 code)
182 {
183 unsigned int i;
184
185 for (i = 0; i < ARRAY_SIZE(mipid02_supported_fmt_codes); i++) {
186 if (code == mipid02_supported_fmt_codes[i])
187 return code;
188 }
189
190 return mipid02_supported_fmt_codes[0];
191 }
192
serial_to_parallel_code(__u32 serial)193 static __u32 serial_to_parallel_code(__u32 serial)
194 {
195 if (serial == MEDIA_BUS_FMT_RGB565_1X16)
196 return MEDIA_BUS_FMT_RGB565_2X8_LE;
197 if (serial == MEDIA_BUS_FMT_YUYV8_1X16)
198 return MEDIA_BUS_FMT_YUYV8_2X8;
199 if (serial == MEDIA_BUS_FMT_YVYU8_1X16)
200 return MEDIA_BUS_FMT_YVYU8_2X8;
201 if (serial == MEDIA_BUS_FMT_UYVY8_1X16)
202 return MEDIA_BUS_FMT_UYVY8_2X8;
203 if (serial == MEDIA_BUS_FMT_VYUY8_1X16)
204 return MEDIA_BUS_FMT_VYUY8_2X8;
205 if (serial == MEDIA_BUS_FMT_BGR888_1X24)
206 return MEDIA_BUS_FMT_BGR888_3X8;
207
208 return serial;
209 }
210
to_mipid02_dev(struct v4l2_subdev * sd)211 static inline struct mipid02_dev *to_mipid02_dev(struct v4l2_subdev *sd)
212 {
213 return container_of(sd, struct mipid02_dev, sd);
214 }
215
mipid02_get_regulators(struct mipid02_dev * bridge)216 static int mipid02_get_regulators(struct mipid02_dev *bridge)
217 {
218 unsigned int i;
219
220 for (i = 0; i < MIPID02_NUM_SUPPLIES; i++)
221 bridge->supplies[i].supply = mipid02_supply_name[i];
222
223 return devm_regulator_bulk_get(&bridge->i2c_client->dev,
224 MIPID02_NUM_SUPPLIES,
225 bridge->supplies);
226 }
227
mipid02_apply_reset(struct mipid02_dev * bridge)228 static void mipid02_apply_reset(struct mipid02_dev *bridge)
229 {
230 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
231 usleep_range(5000, 10000);
232 gpiod_set_value_cansleep(bridge->reset_gpio, 1);
233 usleep_range(5000, 10000);
234 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
235 usleep_range(5000, 10000);
236 }
237
mipid02_set_power_on(struct device * dev)238 static int mipid02_set_power_on(struct device *dev)
239 {
240 struct v4l2_subdev *sd = dev_get_drvdata(dev);
241 struct mipid02_dev *bridge = to_mipid02_dev(sd);
242 struct i2c_client *client = bridge->i2c_client;
243 int ret;
244
245 ret = clk_prepare_enable(bridge->xclk);
246 if (ret) {
247 dev_err(&client->dev, "%s: failed to enable clock\n", __func__);
248 return ret;
249 }
250
251 ret = regulator_bulk_enable(MIPID02_NUM_SUPPLIES,
252 bridge->supplies);
253 if (ret) {
254 dev_err(&client->dev, "%s: failed to enable regulators\n",
255 __func__);
256 goto xclk_off;
257 }
258
259 if (bridge->reset_gpio) {
260 dev_dbg(&client->dev, "apply reset");
261 mipid02_apply_reset(bridge);
262 } else {
263 dev_dbg(&client->dev, "don't apply reset");
264 usleep_range(5000, 10000);
265 }
266
267 return 0;
268
269 xclk_off:
270 clk_disable_unprepare(bridge->xclk);
271 return ret;
272 }
273
mipid02_set_power_off(struct device * dev)274 static int mipid02_set_power_off(struct device *dev)
275 {
276 struct v4l2_subdev *sd = dev_get_drvdata(dev);
277 struct mipid02_dev *bridge = to_mipid02_dev(sd);
278
279 regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
280 clk_disable_unprepare(bridge->xclk);
281
282 return 0;
283 }
284
mipid02_detect(struct mipid02_dev * bridge)285 static int mipid02_detect(struct mipid02_dev *bridge)
286 {
287 u64 reg;
288
289 /*
290 * There is no version registers. Just try to read register
291 * MIPID02_CLK_LANE_WR_REG1.
292 */
293 return cci_read(bridge->regmap, MIPID02_CLK_LANE_WR_REG1, ®, NULL);
294 }
295
296 /*
297 * We need to know link frequency to setup clk_lane_reg1 timings. Link frequency
298 * will be retrieve from connected device via v4l2_get_link_freq, bit per pixel
299 * and number of lanes.
300 */
mipid02_configure_from_rx_speed(struct mipid02_dev * bridge,struct v4l2_mbus_framefmt * fmt)301 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge,
302 struct v4l2_mbus_framefmt *fmt)
303 {
304 struct media_pad *remote =
305 &bridge->s_subdev->entity.pads[bridge->s_subdev_pad_id];
306 struct i2c_client *client = bridge->i2c_client;
307 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
308 u32 bpp = bpp_from_code(fmt->code);
309 /*
310 * clk_lane_reg1 requires 4 times the unit interval time, and bitrate
311 * is twice the link frequency, hence ui_4 = 1000000000 * 4 / 2
312 */
313 u64 ui_4 = 2000000000;
314 s64 link_freq;
315
316 link_freq = v4l2_get_link_freq(remote, bpp,
317 2 * ep->bus.mipi_csi2.num_data_lanes);
318 if (link_freq < 0) {
319 dev_err(&client->dev, "Failed to get link frequency");
320 return -EINVAL;
321 }
322
323 dev_dbg(&client->dev, "detect link_freq = %lld Hz", link_freq);
324 ui_4 = div64_u64(ui_4, link_freq);
325 bridge->r.clk_lane_reg1 |= ui_4 << 2;
326
327 return 0;
328 }
329
mipid02_configure_clk_lane(struct mipid02_dev * bridge)330 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
331 {
332 struct i2c_client *client = bridge->i2c_client;
333 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
334 bool *polarities = ep->bus.mipi_csi2.lane_polarities;
335
336 /* midid02 doesn't support clock lane remapping */
337 if (ep->bus.mipi_csi2.clock_lane != 0) {
338 dev_err(&client->dev, "clk lane must be map to lane 0\n");
339 return -EINVAL;
340 }
341 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
342
343 return 0;
344 }
345
mipid02_configure_data0_lane(struct mipid02_dev * bridge,int nb,bool are_lanes_swap,bool * polarities)346 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
347 bool are_lanes_swap, bool *polarities)
348 {
349 bool are_pin_swap = are_lanes_swap ? polarities[2] : polarities[1];
350
351 if (nb == 1 && are_lanes_swap)
352 return 0;
353
354 /*
355 * data lane 0 as pin swap polarity reversed compared to clock and
356 * data lane 1
357 */
358 if (!are_pin_swap)
359 bridge->r.data_lane0_reg1 = 1 << 1;
360 bridge->r.data_lane0_reg1 |= DATA_ENABLE;
361
362 return 0;
363 }
364
mipid02_configure_data1_lane(struct mipid02_dev * bridge,int nb,bool are_lanes_swap,bool * polarities)365 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
366 bool are_lanes_swap, bool *polarities)
367 {
368 bool are_pin_swap = are_lanes_swap ? polarities[1] : polarities[2];
369
370 if (nb == 1 && !are_lanes_swap)
371 return 0;
372
373 if (are_pin_swap)
374 bridge->r.data_lane1_reg1 = 1 << 1;
375 bridge->r.data_lane1_reg1 |= DATA_ENABLE;
376
377 return 0;
378 }
379
mipid02_configure_from_rx(struct mipid02_dev * bridge,struct v4l2_mbus_framefmt * fmt)380 static int mipid02_configure_from_rx(struct mipid02_dev *bridge,
381 struct v4l2_mbus_framefmt *fmt)
382 {
383 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
384 bool are_lanes_swap = ep->bus.mipi_csi2.data_lanes[0] == 2;
385 bool *polarities = ep->bus.mipi_csi2.lane_polarities;
386 int nb = ep->bus.mipi_csi2.num_data_lanes;
387 int ret;
388
389 ret = mipid02_configure_clk_lane(bridge);
390 if (ret)
391 return ret;
392
393 ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
394 polarities);
395 if (ret)
396 return ret;
397
398 ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
399 polarities);
400 if (ret)
401 return ret;
402
403 bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
404 bridge->r.mode_reg1 |= (nb - 1) << 1;
405
406 return mipid02_configure_from_rx_speed(bridge, fmt);
407 }
408
mipid02_configure_from_tx(struct mipid02_dev * bridge)409 static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
410 {
411 struct v4l2_fwnode_endpoint *ep = &bridge->tx;
412
413 bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
414 bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
415 bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
416 if (ep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
417 bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
418 if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
419 bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
420 if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
421 bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
422
423 return 0;
424 }
425
mipid02_configure_from_code(struct mipid02_dev * bridge,struct v4l2_mbus_framefmt * fmt)426 static int mipid02_configure_from_code(struct mipid02_dev *bridge,
427 struct v4l2_mbus_framefmt *fmt)
428 {
429 u8 data_type;
430
431 bridge->r.data_id_rreg = 0;
432
433 if (fmt->code != MEDIA_BUS_FMT_JPEG_1X8) {
434 bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
435
436 data_type = data_type_from_code(fmt->code);
437 if (!data_type)
438 return -EINVAL;
439 bridge->r.data_id_rreg = data_type;
440 }
441
442 return 0;
443 }
444
mipid02_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)445 static int mipid02_disable_streams(struct v4l2_subdev *sd,
446 struct v4l2_subdev_state *state, u32 pad,
447 u64 streams_mask)
448 {
449 struct mipid02_dev *bridge = to_mipid02_dev(sd);
450 struct i2c_client *client = bridge->i2c_client;
451 int ret = -EINVAL;
452
453 if (!bridge->s_subdev)
454 goto error;
455
456 ret = v4l2_subdev_disable_streams(bridge->s_subdev,
457 bridge->s_subdev_pad_id, BIT(0));
458 if (ret)
459 goto error;
460
461 /* Disable all lanes */
462 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret);
463 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret);
464 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret);
465 if (ret)
466 goto error;
467
468 pm_runtime_mark_last_busy(&client->dev);
469 pm_runtime_put_autosuspend(&client->dev);
470
471 error:
472 if (ret)
473 dev_err(&client->dev, "failed to stream off %d", ret);
474
475 return ret;
476 }
477
mipid02_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)478 static int mipid02_enable_streams(struct v4l2_subdev *sd,
479 struct v4l2_subdev_state *state, u32 pad,
480 u64 streams_mask)
481 {
482 struct mipid02_dev *bridge = to_mipid02_dev(sd);
483 struct i2c_client *client = bridge->i2c_client;
484 struct v4l2_mbus_framefmt *fmt;
485 int ret = -EINVAL;
486
487 if (!bridge->s_subdev)
488 return ret;
489
490 memset(&bridge->r, 0, sizeof(bridge->r));
491
492 fmt = v4l2_subdev_state_get_format(state, MIPID02_SINK_0);
493
494 /* build registers content */
495 ret = mipid02_configure_from_rx(bridge, fmt);
496 if (ret)
497 return ret;
498 ret = mipid02_configure_from_tx(bridge);
499 if (ret)
500 return ret;
501 ret = mipid02_configure_from_code(bridge, fmt);
502 if (ret)
503 return ret;
504
505 ret = pm_runtime_resume_and_get(&client->dev);
506 if (ret < 0)
507 return ret;
508
509 /* write mipi registers */
510 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1,
511 bridge->r.clk_lane_reg1, &ret);
512 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI, &ret);
513 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1,
514 bridge->r.data_lane0_reg1, &ret);
515 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG2, DATA_MIPI_CSI, &ret);
516 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1,
517 bridge->r.data_lane1_reg1, &ret);
518 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG2, DATA_MIPI_CSI, &ret);
519 cci_write(bridge->regmap, MIPID02_MODE_REG1,
520 MODE_NO_BYPASS | bridge->r.mode_reg1, &ret);
521 cci_write(bridge->regmap, MIPID02_MODE_REG2, bridge->r.mode_reg2, &ret);
522 cci_write(bridge->regmap, MIPID02_DATA_ID_RREG, bridge->r.data_id_rreg,
523 &ret);
524 cci_write(bridge->regmap, MIPID02_DATA_SELECTION_CTRL,
525 bridge->r.data_selection_ctrl, &ret);
526 cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL,
527 bridge->r.pix_width_ctrl, &ret);
528 cci_write(bridge->regmap, MIPID02_PIX_WIDTH_CTRL_EMB,
529 bridge->r.pix_width_ctrl_emb, &ret);
530 if (ret)
531 goto error;
532
533 ret = v4l2_subdev_enable_streams(bridge->s_subdev,
534 bridge->s_subdev_pad_id, BIT(0));
535 if (ret)
536 goto error;
537
538 return 0;
539
540 error:
541 cci_write(bridge->regmap, MIPID02_CLK_LANE_REG1, 0, &ret);
542 cci_write(bridge->regmap, MIPID02_DATA_LANE0_REG1, 0, &ret);
543 cci_write(bridge->regmap, MIPID02_DATA_LANE1_REG1, 0, &ret);
544
545 pm_runtime_mark_last_busy(&client->dev);
546 pm_runtime_put_autosuspend(&client->dev);
547 return ret;
548 }
549
550 static const struct v4l2_mbus_framefmt default_fmt = {
551 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
552 .field = V4L2_FIELD_NONE,
553 .colorspace = V4L2_COLORSPACE_SRGB,
554 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
555 .quantization = V4L2_QUANTIZATION_FULL_RANGE,
556 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
557 .width = 640,
558 .height = 480,
559 };
560
mipid02_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)561 static int mipid02_init_state(struct v4l2_subdev *sd,
562 struct v4l2_subdev_state *state)
563 {
564 *v4l2_subdev_state_get_format(state, MIPID02_SINK_0) = default_fmt;
565 /* MIPID02_SINK_1 isn't supported yet */
566 *v4l2_subdev_state_get_format(state, MIPID02_SOURCE) = default_fmt;
567
568 return 0;
569 }
570
mipid02_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)571 static int mipid02_enum_mbus_code(struct v4l2_subdev *sd,
572 struct v4l2_subdev_state *sd_state,
573 struct v4l2_subdev_mbus_code_enum *code)
574 {
575 struct v4l2_mbus_framefmt *sink_fmt;
576 int ret = 0;
577
578 switch (code->pad) {
579 case MIPID02_SINK_0:
580 if (code->index >= ARRAY_SIZE(mipid02_supported_fmt_codes))
581 ret = -EINVAL;
582 else
583 code->code = mipid02_supported_fmt_codes[code->index];
584 break;
585 case MIPID02_SOURCE:
586 if (code->index == 0) {
587 sink_fmt = v4l2_subdev_state_get_format(sd_state,
588 MIPID02_SINK_0);
589 code->code = serial_to_parallel_code(sink_fmt->code);
590 } else {
591 ret = -EINVAL;
592 }
593 break;
594 default:
595 ret = -EINVAL;
596 }
597
598 return ret;
599 }
600
mipid02_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)601 static int mipid02_set_fmt(struct v4l2_subdev *sd,
602 struct v4l2_subdev_state *sd_state,
603 struct v4l2_subdev_format *fmt)
604 {
605 struct mipid02_dev *bridge = to_mipid02_dev(sd);
606 struct i2c_client *client = bridge->i2c_client;
607 struct v4l2_mbus_framefmt *pad_fmt;
608
609 dev_dbg(&client->dev, "%s for %d", __func__, fmt->pad);
610
611 /* second CSI-2 pad not yet supported */
612 if (fmt->pad == MIPID02_SINK_1)
613 return -EINVAL;
614
615 pad_fmt = v4l2_subdev_state_get_format(sd_state, fmt->pad);
616 fmt->format.code = get_fmt_code(fmt->format.code);
617
618 /* code may need to be converted */
619 if (fmt->pad == MIPID02_SOURCE)
620 fmt->format.code = serial_to_parallel_code(fmt->format.code);
621
622 *pad_fmt = fmt->format;
623
624 /* Propagate the format to the source pad in case of sink pad update */
625 if (fmt->pad == MIPID02_SINK_0) {
626 pad_fmt = v4l2_subdev_state_get_format(sd_state,
627 MIPID02_SOURCE);
628 *pad_fmt = fmt->format;
629 pad_fmt->code = serial_to_parallel_code(fmt->format.code);
630 }
631
632 return 0;
633 }
634
635 static const struct v4l2_subdev_video_ops mipid02_video_ops = {
636 .s_stream = v4l2_subdev_s_stream_helper,
637 };
638
639 static const struct v4l2_subdev_pad_ops mipid02_pad_ops = {
640 .enum_mbus_code = mipid02_enum_mbus_code,
641 .get_fmt = v4l2_subdev_get_fmt,
642 .set_fmt = mipid02_set_fmt,
643 .enable_streams = mipid02_enable_streams,
644 .disable_streams = mipid02_disable_streams,
645 };
646
647 static const struct v4l2_subdev_ops mipid02_subdev_ops = {
648 .video = &mipid02_video_ops,
649 .pad = &mipid02_pad_ops,
650 };
651
652 static const struct v4l2_subdev_internal_ops mipid02_subdev_internal_ops = {
653 .init_state = mipid02_init_state,
654 };
655
656 static const struct media_entity_operations mipid02_subdev_entity_ops = {
657 .link_validate = v4l2_subdev_link_validate,
658 };
659
mipid02_async_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * s_subdev,struct v4l2_async_connection * asd)660 static int mipid02_async_bound(struct v4l2_async_notifier *notifier,
661 struct v4l2_subdev *s_subdev,
662 struct v4l2_async_connection *asd)
663 {
664 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
665 struct i2c_client *client = bridge->i2c_client;
666 int source_pad;
667 int ret;
668
669 dev_dbg(&client->dev, "sensor_async_bound call %p", s_subdev);
670
671 source_pad = media_entity_get_fwnode_pad(&s_subdev->entity,
672 s_subdev->fwnode,
673 MEDIA_PAD_FL_SOURCE);
674 if (source_pad < 0) {
675 dev_err(&client->dev, "Couldn't find output pad for subdev %s\n",
676 s_subdev->name);
677 return source_pad;
678 }
679
680 ret = media_create_pad_link(&s_subdev->entity, source_pad,
681 &bridge->sd.entity, 0,
682 MEDIA_LNK_FL_ENABLED |
683 MEDIA_LNK_FL_IMMUTABLE);
684 if (ret) {
685 dev_err(&client->dev, "Couldn't create media link %d", ret);
686 return ret;
687 }
688
689 bridge->s_subdev = s_subdev;
690 bridge->s_subdev_pad_id = source_pad;
691
692 return 0;
693 }
694
mipid02_async_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * s_subdev,struct v4l2_async_connection * asd)695 static void mipid02_async_unbind(struct v4l2_async_notifier *notifier,
696 struct v4l2_subdev *s_subdev,
697 struct v4l2_async_connection *asd)
698 {
699 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
700
701 bridge->s_subdev = NULL;
702 }
703
704 static const struct v4l2_async_notifier_operations mipid02_notifier_ops = {
705 .bound = mipid02_async_bound,
706 .unbind = mipid02_async_unbind,
707 };
708
mipid02_parse_rx_ep(struct mipid02_dev * bridge)709 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
710 {
711 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY };
712 struct i2c_client *client = bridge->i2c_client;
713 struct v4l2_async_connection *asd;
714 struct device_node *ep_node;
715 int ret;
716
717 /* parse rx (endpoint 0) */
718 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
719 0, 0);
720 if (!ep_node) {
721 dev_err(&client->dev, "unable to find port0 ep");
722 ret = -EINVAL;
723 goto error;
724 }
725
726 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
727 if (ret) {
728 dev_err(&client->dev, "Could not parse v4l2 endpoint %d\n",
729 ret);
730 goto error_of_node_put;
731 }
732
733 /* do some sanity checks */
734 if (ep.bus.mipi_csi2.num_data_lanes > 2) {
735 dev_err(&client->dev, "max supported data lanes is 2 / got %d",
736 ep.bus.mipi_csi2.num_data_lanes);
737 ret = -EINVAL;
738 goto error_of_node_put;
739 }
740
741 /* register it for later use */
742 bridge->rx = ep;
743
744 /* register async notifier so we get noticed when sensor is connected */
745 v4l2_async_subdev_nf_init(&bridge->notifier, &bridge->sd);
746 asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier,
747 of_fwnode_handle(ep_node),
748 struct v4l2_async_connection);
749 of_node_put(ep_node);
750
751 if (IS_ERR(asd)) {
752 dev_err(&client->dev, "fail to register asd to notifier %ld",
753 PTR_ERR(asd));
754 return PTR_ERR(asd);
755 }
756 bridge->notifier.ops = &mipid02_notifier_ops;
757
758 ret = v4l2_async_nf_register(&bridge->notifier);
759 if (ret)
760 v4l2_async_nf_cleanup(&bridge->notifier);
761
762 return ret;
763
764 error_of_node_put:
765 of_node_put(ep_node);
766 error:
767
768 return ret;
769 }
770
mipid02_parse_tx_ep(struct mipid02_dev * bridge)771 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
772 {
773 struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_PARALLEL };
774 struct i2c_client *client = bridge->i2c_client;
775 struct device_node *ep_node;
776 int ret;
777
778 /* parse tx (endpoint 2) */
779 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
780 2, 0);
781 if (!ep_node) {
782 dev_err(&client->dev, "unable to find port1 ep");
783 ret = -EINVAL;
784 goto error;
785 }
786
787 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);
788 if (ret) {
789 dev_err(&client->dev, "Could not parse v4l2 endpoint\n");
790 goto error_of_node_put;
791 }
792
793 of_node_put(ep_node);
794 bridge->tx = ep;
795
796 return 0;
797
798 error_of_node_put:
799 of_node_put(ep_node);
800 error:
801
802 return -EINVAL;
803 }
804
mipid02_probe(struct i2c_client * client)805 static int mipid02_probe(struct i2c_client *client)
806 {
807 struct device *dev = &client->dev;
808 struct mipid02_dev *bridge;
809 u32 clk_freq;
810 int ret;
811
812 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
813 if (!bridge)
814 return -ENOMEM;
815
816 bridge->i2c_client = client;
817 v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
818
819 /* got and check clock */
820 bridge->xclk = devm_clk_get(dev, "xclk");
821 if (IS_ERR(bridge->xclk)) {
822 dev_err(dev, "failed to get xclk\n");
823 return PTR_ERR(bridge->xclk);
824 }
825
826 clk_freq = clk_get_rate(bridge->xclk);
827 if (clk_freq < 6000000 || clk_freq > 27000000) {
828 dev_err(dev, "xclk freq must be in 6-27 Mhz range. got %d Hz\n",
829 clk_freq);
830 return -EINVAL;
831 }
832
833 bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
834 GPIOD_OUT_HIGH);
835
836 if (IS_ERR(bridge->reset_gpio)) {
837 dev_err(dev, "failed to get reset GPIO\n");
838 return PTR_ERR(bridge->reset_gpio);
839 }
840
841 ret = mipid02_get_regulators(bridge);
842 if (ret) {
843 dev_err(dev, "failed to get regulators %d", ret);
844 return ret;
845 }
846
847 /* Initialise the regmap for further cci access */
848 bridge->regmap = devm_cci_regmap_init_i2c(client, 16);
849 if (IS_ERR(bridge->regmap))
850 return dev_err_probe(dev, PTR_ERR(bridge->regmap),
851 "failed to get cci regmap\n");
852
853 bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
854 bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
855 bridge->sd.internal_ops = &mipid02_subdev_internal_ops;
856 bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
857 bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
858 bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
859 bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
860 ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
861 bridge->pad);
862 if (ret) {
863 dev_err(&client->dev, "pads init failed %d", ret);
864 return ret;
865 }
866
867 ret = v4l2_subdev_init_finalize(&bridge->sd);
868 if (ret < 0) {
869 dev_err(dev, "subdev init error: %d\n", ret);
870 goto entity_cleanup;
871 }
872
873 /* enable clock, power and reset device if available */
874 ret = mipid02_set_power_on(&client->dev);
875 if (ret)
876 goto entity_cleanup;
877
878 ret = mipid02_detect(bridge);
879 if (ret) {
880 dev_err(&client->dev, "failed to detect mipid02 %d", ret);
881 goto power_off;
882 }
883
884 ret = mipid02_parse_tx_ep(bridge);
885 if (ret) {
886 dev_err(&client->dev, "failed to parse tx %d", ret);
887 goto power_off;
888 }
889
890 ret = mipid02_parse_rx_ep(bridge);
891 if (ret) {
892 dev_err(&client->dev, "failed to parse rx %d", ret);
893 goto power_off;
894 }
895
896 /* Enable runtime PM and turn off the device */
897 pm_runtime_set_active(dev);
898 pm_runtime_get_noresume(&client->dev);
899 pm_runtime_enable(dev);
900
901 pm_runtime_set_autosuspend_delay(&client->dev, 1000);
902 pm_runtime_use_autosuspend(&client->dev);
903 pm_runtime_put_autosuspend(&client->dev);
904
905 ret = v4l2_async_register_subdev(&bridge->sd);
906 if (ret < 0) {
907 dev_err(&client->dev, "v4l2_async_register_subdev failed %d",
908 ret);
909 goto unregister_notifier;
910 }
911
912 dev_info(&client->dev, "mipid02 device probe successfully");
913
914 return 0;
915
916 unregister_notifier:
917 v4l2_async_nf_unregister(&bridge->notifier);
918 v4l2_async_nf_cleanup(&bridge->notifier);
919 pm_runtime_disable(&client->dev);
920 pm_runtime_set_suspended(&client->dev);
921 power_off:
922 mipid02_set_power_off(&client->dev);
923 entity_cleanup:
924 media_entity_cleanup(&bridge->sd.entity);
925
926 return ret;
927 }
928
mipid02_remove(struct i2c_client * client)929 static void mipid02_remove(struct i2c_client *client)
930 {
931 struct v4l2_subdev *sd = i2c_get_clientdata(client);
932 struct mipid02_dev *bridge = to_mipid02_dev(sd);
933
934 v4l2_async_nf_unregister(&bridge->notifier);
935 v4l2_async_nf_cleanup(&bridge->notifier);
936 v4l2_async_unregister_subdev(&bridge->sd);
937
938 pm_runtime_disable(&client->dev);
939 if (!pm_runtime_status_suspended(&client->dev))
940 mipid02_set_power_off(&client->dev);
941 pm_runtime_set_suspended(&client->dev);
942 media_entity_cleanup(&bridge->sd.entity);
943 }
944
945 static const struct of_device_id mipid02_dt_ids[] = {
946 { .compatible = "st,st-mipid02" },
947 { /* sentinel */ }
948 };
949 MODULE_DEVICE_TABLE(of, mipid02_dt_ids);
950
951 static const struct dev_pm_ops mipid02_pm_ops = {
952 RUNTIME_PM_OPS(mipid02_set_power_off, mipid02_set_power_on, NULL)
953 };
954
955 static struct i2c_driver mipid02_i2c_driver = {
956 .driver = {
957 .name = "st-mipid02",
958 .of_match_table = mipid02_dt_ids,
959 .pm = pm_ptr(&mipid02_pm_ops),
960 },
961 .probe = mipid02_probe,
962 .remove = mipid02_remove,
963 };
964
965 module_i2c_driver(mipid02_i2c_driver);
966
967 MODULE_AUTHOR("Mickael Guene <mickael.guene@st.com>");
968 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");
969 MODULE_LICENSE("GPL v2");
970