1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2H(P) ICU Driver
4 *
5 * Based on irq-renesas-rzg2l.c
6 *
7 * Copyright (C) 2024 Renesas Electronics Corporation.
8 *
9 * Author: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/cleanup.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/irqchip.h>
18 #include <linux/irqdomain.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
24 #include <linux/syscore_ops.h>
25
26 /* DT "interrupts" indexes */
27 #define ICU_IRQ_START 1
28 #define ICU_IRQ_COUNT 16
29 #define ICU_TINT_START (ICU_IRQ_START + ICU_IRQ_COUNT)
30 #define ICU_TINT_COUNT 32
31 #define ICU_NUM_IRQ (ICU_TINT_START + ICU_TINT_COUNT)
32
33 /* Registers */
34 #define ICU_NSCNT 0x00
35 #define ICU_NSCLR 0x04
36 #define ICU_NITSR 0x08
37 #define ICU_ISCTR 0x10
38 #define ICU_ISCLR 0x14
39 #define ICU_IITSR 0x18
40 #define ICU_TSCTR 0x20
41 #define ICU_TSCLR 0x24
42 #define ICU_TITSR(k) (0x28 + (k) * 4)
43 #define ICU_TSSR(k) (0x30 + (k) * 4)
44
45 /* NMI */
46 #define ICU_NMI_EDGE_FALLING 0
47 #define ICU_NMI_EDGE_RISING 1
48
49 #define ICU_NSCLR_NCLR BIT(0)
50
51 /* IRQ */
52 #define ICU_IRQ_LEVEL_LOW 0
53 #define ICU_IRQ_EDGE_FALLING 1
54 #define ICU_IRQ_EDGE_RISING 2
55 #define ICU_IRQ_EDGE_BOTH 3
56
57 #define ICU_IITSR_IITSEL_PREP(iitsel, n) ((iitsel) << ((n) * 2))
58 #define ICU_IITSR_IITSEL_GET(iitsr, n) (((iitsr) >> ((n) * 2)) & 0x03)
59 #define ICU_IITSR_IITSEL_MASK(n) ICU_IITSR_IITSEL_PREP(0x03, n)
60
61 /* TINT */
62 #define ICU_TINT_EDGE_RISING 0
63 #define ICU_TINT_EDGE_FALLING 1
64 #define ICU_TINT_LEVEL_HIGH 2
65 #define ICU_TINT_LEVEL_LOW 3
66
67 #define ICU_TSSR_TSSEL_PREP(tssel, n, field_width) ((tssel) << ((n) * (field_width)))
68 #define ICU_TSSR_TSSEL_MASK(n, field_width) \
69 ({\
70 typeof(field_width) (_field_width) = (field_width); \
71 ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
72 })
73
74 #define ICU_TSSR_TIEN(n, field_width) \
75 ({\
76 typeof(field_width) (_field_width) = (field_width); \
77 BIT((_field_width) - 1) << ((n) * (_field_width)); \
78 })
79
80 #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16)
81 #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16)
82 #define ICU_TITSR_TITSEL_PREP(titsel, n) ICU_IITSR_IITSEL_PREP(titsel, n)
83 #define ICU_TITSR_TITSEL_MASK(n) ICU_IITSR_IITSEL_MASK(n)
84 #define ICU_TITSR_TITSEL_GET(titsr, n) ICU_IITSR_IITSEL_GET(titsr, n)
85
86 #define ICU_TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
87 #define ICU_TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
88 #define ICU_RZG3E_TINT_OFFSET 0x800
89 #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c
90 #define ICU_RZV2H_TSSEL_MAX_VAL 0x55
91
92 /**
93 * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
94 * @tssel_lut: TINT lookup table
95 * @t_offs: TINT offset
96 * @max_tssel: TSSEL max value
97 * @field_width: TSSR field width
98 */
99 struct rzv2h_hw_info {
100 const u8 *tssel_lut;
101 u16 t_offs;
102 u8 max_tssel;
103 u8 field_width;
104 };
105
106 /**
107 * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
108 * @base: Controller's base address
109 * @fwspec: IRQ firmware specific data
110 * @lock: Lock to serialize access to hardware registers
111 * @info: Pointer to struct rzv2h_hw_info
112 */
113 struct rzv2h_icu_priv {
114 void __iomem *base;
115 struct irq_fwspec fwspec[ICU_NUM_IRQ];
116 raw_spinlock_t lock;
117 const struct rzv2h_hw_info *info;
118 };
119
irq_data_to_priv(struct irq_data * data)120 static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *data)
121 {
122 return data->domain->host_data;
123 }
124
rzv2h_icu_eoi(struct irq_data * d)125 static void rzv2h_icu_eoi(struct irq_data *d)
126 {
127 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
128 unsigned int hw_irq = irqd_to_hwirq(d);
129 unsigned int tintirq_nr;
130 u32 bit;
131
132 scoped_guard(raw_spinlock, &priv->lock) {
133 if (hw_irq >= ICU_TINT_START) {
134 tintirq_nr = hw_irq - ICU_TINT_START;
135 bit = BIT(tintirq_nr);
136 if (!irqd_is_level_type(d))
137 writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
138 } else if (hw_irq >= ICU_IRQ_START) {
139 tintirq_nr = hw_irq - ICU_IRQ_START;
140 bit = BIT(tintirq_nr);
141 if (!irqd_is_level_type(d))
142 writel_relaxed(bit, priv->base + ICU_ISCLR);
143 } else {
144 writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR);
145 }
146 }
147
148 irq_chip_eoi_parent(d);
149 }
150
rzv2h_tint_irq_endisable(struct irq_data * d,bool enable)151 static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable)
152 {
153 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
154 unsigned int hw_irq = irqd_to_hwirq(d);
155 u32 tint_nr, tssel_n, k, tssr;
156 u8 nr_tint;
157
158 if (hw_irq < ICU_TINT_START)
159 return;
160
161 tint_nr = hw_irq - ICU_TINT_START;
162 nr_tint = 32 / priv->info->field_width;
163 k = tint_nr / nr_tint;
164 tssel_n = tint_nr % nr_tint;
165
166 guard(raw_spinlock)(&priv->lock);
167 tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k));
168 if (enable)
169 tssr |= ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
170 else
171 tssr &= ~ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
172 writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k));
173
174 /*
175 * A glitch in the edge detection circuit can cause a spurious
176 * interrupt. Clear the status flag after setting the ICU_TSSRk
177 * registers, which is recommended by the hardware manual as a
178 * countermeasure.
179 */
180 writel_relaxed(BIT(tint_nr), priv->base + priv->info->t_offs + ICU_TSCLR);
181 }
182
rzv2h_icu_irq_disable(struct irq_data * d)183 static void rzv2h_icu_irq_disable(struct irq_data *d)
184 {
185 irq_chip_disable_parent(d);
186 rzv2h_tint_irq_endisable(d, false);
187 }
188
rzv2h_icu_irq_enable(struct irq_data * d)189 static void rzv2h_icu_irq_enable(struct irq_data *d)
190 {
191 rzv2h_tint_irq_endisable(d, true);
192 irq_chip_enable_parent(d);
193 }
194
rzv2h_nmi_set_type(struct irq_data * d,unsigned int type)195 static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type)
196 {
197 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
198 u32 sense;
199
200 switch (type & IRQ_TYPE_SENSE_MASK) {
201 case IRQ_TYPE_EDGE_FALLING:
202 sense = ICU_NMI_EDGE_FALLING;
203 break;
204
205 case IRQ_TYPE_EDGE_RISING:
206 sense = ICU_NMI_EDGE_RISING;
207 break;
208
209 default:
210 return -EINVAL;
211 }
212
213 writel_relaxed(sense, priv->base + ICU_NITSR);
214
215 return 0;
216 }
217
rzv2h_clear_irq_int(struct rzv2h_icu_priv * priv,unsigned int hwirq)218 static void rzv2h_clear_irq_int(struct rzv2h_icu_priv *priv, unsigned int hwirq)
219 {
220 unsigned int irq_nr = hwirq - ICU_IRQ_START;
221 u32 isctr, iitsr, iitsel;
222 u32 bit = BIT(irq_nr);
223
224 isctr = readl_relaxed(priv->base + ICU_ISCTR);
225 iitsr = readl_relaxed(priv->base + ICU_IITSR);
226 iitsel = ICU_IITSR_IITSEL_GET(iitsr, irq_nr);
227
228 /*
229 * When level sensing is used, the interrupt flag gets automatically cleared when the
230 * interrupt signal is de-asserted by the source of the interrupt request, therefore clear
231 * the interrupt only for edge triggered interrupts.
232 */
233 if ((isctr & bit) && (iitsel != ICU_IRQ_LEVEL_LOW))
234 writel_relaxed(bit, priv->base + ICU_ISCLR);
235 }
236
rzv2h_irq_set_type(struct irq_data * d,unsigned int type)237 static int rzv2h_irq_set_type(struct irq_data *d, unsigned int type)
238 {
239 struct rzv2h_icu_priv *priv = irq_data_to_priv(d);
240 unsigned int hwirq = irqd_to_hwirq(d);
241 u32 irq_nr = hwirq - ICU_IRQ_START;
242 u32 iitsr, sense;
243
244 switch (type & IRQ_TYPE_SENSE_MASK) {
245 case IRQ_TYPE_LEVEL_LOW:
246 sense = ICU_IRQ_LEVEL_LOW;
247 break;
248
249 case IRQ_TYPE_EDGE_FALLING:
250 sense = ICU_IRQ_EDGE_FALLING;
251 break;
252
253 case IRQ_TYPE_EDGE_RISING:
254 sense = ICU_IRQ_EDGE_RISING;
255 break;
256
257 case IRQ_TYPE_EDGE_BOTH:
258 sense = ICU_IRQ_EDGE_BOTH;
259 break;
260
261 default:
262 return -EINVAL;
263 }
264
265 guard(raw_spinlock)(&priv->lock);
266 iitsr = readl_relaxed(priv->base + ICU_IITSR);
267 iitsr &= ~ICU_IITSR_IITSEL_MASK(irq_nr);
268 iitsr |= ICU_IITSR_IITSEL_PREP(sense, irq_nr);
269 rzv2h_clear_irq_int(priv, hwirq);
270 writel_relaxed(iitsr, priv->base + ICU_IITSR);
271
272 return 0;
273 }
274
rzv2h_clear_tint_int(struct rzv2h_icu_priv * priv,unsigned int hwirq)275 static void rzv2h_clear_tint_int(struct rzv2h_icu_priv *priv, unsigned int hwirq)
276 {
277 unsigned int tint_nr = hwirq - ICU_TINT_START;
278 int titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
279 u32 tsctr, titsr, titsel;
280 u32 bit = BIT(tint_nr);
281 int k = tint_nr / 16;
282
283 tsctr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSCTR);
284 titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(k));
285 titsel = ICU_TITSR_TITSEL_GET(titsr, titsel_n);
286
287 /*
288 * Writing 1 to the corresponding flag from register ICU_TSCTR only has effect if
289 * TSTATn = 1b and if it's a rising edge or a falling edge interrupt.
290 */
291 if ((tsctr & bit) && ((titsel == ICU_TINT_EDGE_RISING) ||
292 (titsel == ICU_TINT_EDGE_FALLING)))
293 writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR);
294 }
295
rzv2h_tint_set_type(struct irq_data * d,unsigned int type)296 static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
297 {
298 u32 titsr, titsr_k, titsel_n, tien;
299 struct rzv2h_icu_priv *priv;
300 u32 tssr, tssr_k, tssel_n;
301 unsigned int hwirq;
302 u32 tint, sense;
303 int tint_nr;
304 u8 nr_tint;
305
306 switch (type & IRQ_TYPE_SENSE_MASK) {
307 case IRQ_TYPE_LEVEL_LOW:
308 sense = ICU_TINT_LEVEL_LOW;
309 break;
310
311 case IRQ_TYPE_LEVEL_HIGH:
312 sense = ICU_TINT_LEVEL_HIGH;
313 break;
314
315 case IRQ_TYPE_EDGE_RISING:
316 sense = ICU_TINT_EDGE_RISING;
317 break;
318
319 case IRQ_TYPE_EDGE_FALLING:
320 sense = ICU_TINT_EDGE_FALLING;
321 break;
322
323 default:
324 return -EINVAL;
325 }
326
327 priv = irq_data_to_priv(d);
328 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
329 if (tint > priv->info->max_tssel)
330 return -EINVAL;
331
332 if (priv->info->tssel_lut)
333 tint = priv->info->tssel_lut[tint];
334
335 hwirq = irqd_to_hwirq(d);
336 tint_nr = hwirq - ICU_TINT_START;
337
338 nr_tint = 32 / priv->info->field_width;
339 tssr_k = tint_nr / nr_tint;
340 tssel_n = tint_nr % nr_tint;
341 tien = ICU_TSSR_TIEN(tssel_n, priv->info->field_width);
342
343 titsr_k = ICU_TITSR_K(tint_nr);
344 titsel_n = ICU_TITSR_TITSEL_N(tint_nr);
345
346 guard(raw_spinlock)(&priv->lock);
347
348 tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
349 tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n, priv->info->field_width) | tien);
350 tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n, priv->info->field_width);
351
352 writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
353
354 titsr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
355 titsr &= ~ICU_TITSR_TITSEL_MASK(titsel_n);
356 titsr |= ICU_TITSR_TITSEL_PREP(sense, titsel_n);
357
358 writel_relaxed(titsr, priv->base + priv->info->t_offs + ICU_TITSR(titsr_k));
359
360 rzv2h_clear_tint_int(priv, hwirq);
361
362 writel_relaxed(tssr | tien, priv->base + priv->info->t_offs + ICU_TSSR(tssr_k));
363
364 return 0;
365 }
366
rzv2h_icu_set_type(struct irq_data * d,unsigned int type)367 static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type)
368 {
369 unsigned int hw_irq = irqd_to_hwirq(d);
370 int ret;
371
372 if (hw_irq >= ICU_TINT_START)
373 ret = rzv2h_tint_set_type(d, type);
374 else if (hw_irq >= ICU_IRQ_START)
375 ret = rzv2h_irq_set_type(d, type);
376 else
377 ret = rzv2h_nmi_set_type(d, type);
378
379 if (ret)
380 return ret;
381
382 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
383 }
384
385 static const struct irq_chip rzv2h_icu_chip = {
386 .name = "rzv2h-icu",
387 .irq_eoi = rzv2h_icu_eoi,
388 .irq_mask = irq_chip_mask_parent,
389 .irq_unmask = irq_chip_unmask_parent,
390 .irq_disable = rzv2h_icu_irq_disable,
391 .irq_enable = rzv2h_icu_irq_enable,
392 .irq_get_irqchip_state = irq_chip_get_parent_state,
393 .irq_set_irqchip_state = irq_chip_set_parent_state,
394 .irq_retrigger = irq_chip_retrigger_hierarchy,
395 .irq_set_type = rzv2h_icu_set_type,
396 .irq_set_affinity = irq_chip_set_affinity_parent,
397 .flags = IRQCHIP_SET_TYPE_MASKED,
398 };
399
rzv2h_icu_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)400 static int rzv2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
401 void *arg)
402 {
403 struct rzv2h_icu_priv *priv = domain->host_data;
404 unsigned long tint = 0;
405 irq_hw_number_t hwirq;
406 unsigned int type;
407 int ret;
408
409 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
410 if (ret)
411 return ret;
412
413 /*
414 * For TINT interrupts the hwirq and TINT are encoded in
415 * fwspec->param[0].
416 * hwirq is embedded in bits 0-15.
417 * TINT is embedded in bits 16-31.
418 */
419 if (hwirq >= ICU_TINT_START) {
420 tint = ICU_TINT_EXTRACT_GPIOINT(hwirq);
421 hwirq = ICU_TINT_EXTRACT_HWIRQ(hwirq);
422
423 if (hwirq < ICU_TINT_START)
424 return -EINVAL;
425 }
426
427 if (hwirq > (ICU_NUM_IRQ - 1))
428 return -EINVAL;
429
430 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzv2h_icu_chip,
431 (void *)(uintptr_t)tint);
432 if (ret)
433 return ret;
434
435 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
436 }
437
438 static const struct irq_domain_ops rzv2h_icu_domain_ops = {
439 .alloc = rzv2h_icu_alloc,
440 .free = irq_domain_free_irqs_common,
441 .translate = irq_domain_translate_twocell,
442 };
443
rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv * priv,struct device_node * np)444 static int rzv2h_icu_parse_interrupts(struct rzv2h_icu_priv *priv, struct device_node *np)
445 {
446 struct of_phandle_args map;
447 unsigned int i;
448 int ret;
449
450 for (i = 0; i < ICU_NUM_IRQ; i++) {
451 ret = of_irq_parse_one(np, i, &map);
452 if (ret)
453 return ret;
454
455 of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);
456 }
457
458 return 0;
459 }
460
rzv2h_icu_put_device(void * data)461 static void rzv2h_icu_put_device(void *data)
462 {
463 put_device(data);
464 }
465
rzv2h_icu_init_common(struct device_node * node,struct device_node * parent,const struct rzv2h_hw_info * hw_info)466 static int rzv2h_icu_init_common(struct device_node *node, struct device_node *parent,
467 const struct rzv2h_hw_info *hw_info)
468 {
469 struct irq_domain *irq_domain, *parent_domain;
470 struct rzv2h_icu_priv *rzv2h_icu_data;
471 struct platform_device *pdev;
472 struct reset_control *resetn;
473 int ret;
474
475 pdev = of_find_device_by_node(node);
476 if (!pdev)
477 return -ENODEV;
478
479 ret = devm_add_action_or_reset(&pdev->dev, rzv2h_icu_put_device,
480 &pdev->dev);
481 if (ret < 0)
482 return ret;
483
484 parent_domain = irq_find_host(parent);
485 if (!parent_domain) {
486 dev_err(&pdev->dev, "cannot find parent domain\n");
487 return -ENODEV;
488 }
489
490 rzv2h_icu_data = devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_KERNEL);
491 if (!rzv2h_icu_data)
492 return -ENOMEM;
493
494 rzv2h_icu_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
495 if (IS_ERR(rzv2h_icu_data->base))
496 return PTR_ERR(rzv2h_icu_data->base);
497
498 ret = rzv2h_icu_parse_interrupts(rzv2h_icu_data, node);
499 if (ret) {
500 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
501 return ret;
502 }
503
504 resetn = devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL);
505 if (IS_ERR(resetn)) {
506 ret = PTR_ERR(resetn);
507 dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret);
508 return ret;
509 }
510
511 ret = devm_pm_runtime_enable(&pdev->dev);
512 if (ret < 0) {
513 dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret);
514 return ret;
515 }
516
517 ret = pm_runtime_resume_and_get(&pdev->dev);
518 if (ret < 0) {
519 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
520 return ret;
521 }
522
523 raw_spin_lock_init(&rzv2h_icu_data->lock);
524
525 irq_domain = irq_domain_add_hierarchy(parent_domain, 0, ICU_NUM_IRQ, node,
526 &rzv2h_icu_domain_ops, rzv2h_icu_data);
527 if (!irq_domain) {
528 dev_err(&pdev->dev, "failed to add irq domain\n");
529 ret = -ENOMEM;
530 goto pm_put;
531 }
532
533 rzv2h_icu_data->info = hw_info;
534
535 /*
536 * coccicheck complains about a missing put_device call before returning, but it's a false
537 * positive. We still need &pdev->dev after successfully returning from this function.
538 */
539 return 0;
540
541 pm_put:
542 pm_runtime_put(&pdev->dev);
543
544 return ret;
545 }
546
547 /* Mapping based on port index on Table 4.2-6 and TSSEL bits on Table 4.6-4 */
548 static const u8 rzg3e_tssel_lut[] = {
549 81, 82, 83, 84, 85, 86, 87, 88, /* P00-P07 */
550 89, 90, 91, 92, 93, 94, 95, 96, /* P10-P17 */
551 111, 112, /* P20-P21 */
552 97, 98, 99, 100, 101, 102, 103, 104, /* P30-P37 */
553 105, 106, 107, 108, 109, 110, /* P40-P45 */
554 113, 114, 115, 116, 117, 118, 119, /* P50-P56 */
555 120, 121, 122, 123, 124, 125, 126, /* P60-P66 */
556 127, 128, 129, 130, 131, 132, 133, 134, /* P70-P77 */
557 135, 136, 137, 138, 139, 140, /* P80-P85 */
558 43, 44, 45, 46, 47, 48, 49, 50, /* PA0-PA7 */
559 51, 52, 53, 54, 55, 56, 57, 58, /* PB0-PB7 */
560 59, 60, 61, /* PC0-PC2 */
561 62, 63, 64, 65, 66, 67, 68, 69, /* PD0-PD7 */
562 70, 71, 72, 73, 74, 75, 76, 77, /* PE0-PE7 */
563 78, 79, 80, /* PF0-PF2 */
564 25, 26, 27, 28, 29, 30, 31, 32, /* PG0-PG7 */
565 33, 34, 35, 36, 37, 38, /* PH0-PH5 */
566 4, 5, 6, 7, 8, /* PJ0-PJ4 */
567 39, 40, 41, 42, /* PK0-PK3 */
568 9, 10, 11, 12, 21, 22, 23, 24, /* PL0-PL7 */
569 13, 14, 15, 16, 17, 18, 19, 20, /* PM0-PM7 */
570 0, 1, 2, 3 /* PS0-PS3 */
571 };
572
573 static const struct rzv2h_hw_info rzg3e_hw_params = {
574 .tssel_lut = rzg3e_tssel_lut,
575 .t_offs = ICU_RZG3E_TINT_OFFSET,
576 .max_tssel = ICU_RZG3E_TSSEL_MAX_VAL,
577 .field_width = 16,
578 };
579
580 static const struct rzv2h_hw_info rzv2h_hw_params = {
581 .t_offs = 0,
582 .max_tssel = ICU_RZV2H_TSSEL_MAX_VAL,
583 .field_width = 8,
584 };
585
rzg3e_icu_init(struct device_node * node,struct device_node * parent)586 static int rzg3e_icu_init(struct device_node *node, struct device_node *parent)
587 {
588 return rzv2h_icu_init_common(node, parent, &rzg3e_hw_params);
589 }
590
rzv2h_icu_init(struct device_node * node,struct device_node * parent)591 static int rzv2h_icu_init(struct device_node *node, struct device_node *parent)
592 {
593 return rzv2h_icu_init_common(node, parent, &rzv2h_hw_params);
594 }
595
596 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu)
597 IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_init)
598 IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_init)
599 IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu)
600 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
601 MODULE_DESCRIPTION("Renesas RZ/V2H(P) ICU Driver");
602