1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Analog Devices AD3552R
4  * Digital to Analog converter driver, High Speed version
5  *
6  * Copyright 2024 Analog Devices Inc.
7  */
8 
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/iio/backend.h>
13 #include <linux/iio/buffer.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/units.h>
18 
19 #include "ad3552r.h"
20 #include "ad3552r-hs.h"
21 
22 /*
23  * Important notes for register map access:
24  * ========================================
25  *
26  * Register address space is divided in 2 regions, primary (config) and
27  * secondary (DAC). Primary region can only be accessed in simple SPI mode,
28  * with exception for ad355x models where setting QSPI pin high allows QSPI
29  * access to both the regions.
30  *
31  * Due to the fact that ad3541/2r do not implement QSPI, for proper device
32  * detection, HDL keeps "QSPI" pin level low at boot (see ad3552r manual, rev B
33  * table 7, pin 31, digital input). For this reason, actually the working mode
34  * between SPI, DSPI and QSPI must be set via software, configuring the target
35  * DAC appropriately, together with the backend API to configure the bus mode
36  * accordingly.
37  *
38  * Also, important to note that none of the three modes allow to read in DDR.
39  *
40  * In non-buffering operations, mode is set to simple SPI SDR for all primary
41  * and secondary region r/w accesses, to avoid to switch the mode each time DAC
42  * register is accessed (raw accesses, r/w), and to be able to dump registers
43  * content (possible as non DDR only).
44  * In buffering mode, driver sets best possible mode, D/QSPI and DDR.
45  */
46 
47 struct ad3552r_hs_state {
48 	const struct ad3552r_model_data *model_data;
49 	struct gpio_desc *reset_gpio;
50 	struct device *dev;
51 	struct iio_backend *back;
52 	bool single_channel;
53 	struct ad3552r_ch_data ch_data[AD3552R_MAX_CH];
54 	struct ad3552r_hs_platform_data *data;
55 	/* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */
56 	u32 config_d;
57 };
58 
ad3552r_hs_reg_read(struct ad3552r_hs_state * st,u32 reg,u32 * val,size_t xfer_size)59 static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val,
60 			       size_t xfer_size)
61 {
62 	/* No chip in the family supports DDR read. Informing of this. */
63 	WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR);
64 
65 	return st->data->bus_reg_read(st->back, reg, val, xfer_size);
66 }
67 
ad3552r_hs_update_reg_bits(struct ad3552r_hs_state * st,u32 reg,u32 mask,u32 val,size_t xfer_size)68 static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg,
69 				      u32 mask, u32 val, size_t xfer_size)
70 {
71 	u32 rval;
72 	int ret;
73 
74 	ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size);
75 	if (ret)
76 		return ret;
77 
78 	rval = (rval & ~mask) | val;
79 
80 	return st->data->bus_reg_write(st->back, reg, rval, xfer_size);
81 }
82 
ad3552r_hs_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)83 static int ad3552r_hs_read_raw(struct iio_dev *indio_dev,
84 			       struct iio_chan_spec const *chan,
85 			       int *val, int *val2, long mask)
86 {
87 	struct ad3552r_hs_state *st = iio_priv(indio_dev);
88 	int ret;
89 	int ch = chan->channel;
90 
91 	switch (mask) {
92 	case IIO_CHAN_INFO_SAMP_FREQ:
93 		/*
94 		 * Using a "num_spi_data_lanes" variable since ad3541/2 have
95 		 * only DSPI interface, while ad355x is QSPI. Then using 2 as
96 		 * DDR mode is considered always on (considering buffering
97 		 * mode always).
98 		 */
99 		*val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz *
100 					 st->model_data->num_spi_data_lanes * 2,
101 					 chan->scan_type.realbits);
102 
103 		return IIO_VAL_INT;
104 
105 	case IIO_CHAN_INFO_RAW:
106 		/* For RAW accesses, stay always in simple-spi. */
107 		ret = ad3552r_hs_reg_read(st,
108 				AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
109 				val, 2);
110 		if (ret)
111 			return ret;
112 
113 		return IIO_VAL_INT;
114 	case IIO_CHAN_INFO_SCALE:
115 		*val = st->ch_data[ch].scale_int;
116 		*val2 = st->ch_data[ch].scale_dec;
117 		return IIO_VAL_INT_PLUS_MICRO;
118 	case IIO_CHAN_INFO_OFFSET:
119 		*val = st->ch_data[ch].offset_int;
120 		*val2 = st->ch_data[ch].offset_dec;
121 		return IIO_VAL_INT_PLUS_MICRO;
122 	default:
123 		return -EINVAL;
124 	}
125 }
126 
ad3552r_hs_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)127 static int ad3552r_hs_write_raw(struct iio_dev *indio_dev,
128 				struct iio_chan_spec const *chan,
129 				int val, int val2, long mask)
130 {
131 	struct ad3552r_hs_state *st = iio_priv(indio_dev);
132 	int ret;
133 
134 	switch (mask) {
135 	case IIO_CHAN_INFO_RAW:
136 		if (!iio_device_claim_direct(indio_dev))
137 			return -EBUSY;
138 		/* For RAW accesses, stay always in simple-spi. */
139 		ret = st->data->bus_reg_write(st->back,
140 			AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
141 			val, 2);
142 
143 		iio_device_release_direct(indio_dev);
144 		return ret;
145 	default:
146 		return -EINVAL;
147 	}
148 }
149 
ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state * st)150 static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st)
151 {
152 	int bus_mode;
153 
154 	if (st->model_data->num_spi_data_lanes == 4)
155 		bus_mode = AD3552R_IO_MODE_QSPI;
156 	else
157 		bus_mode = AD3552R_IO_MODE_DSPI;
158 
159 	return st->data->bus_set_io_mode(st->back, bus_mode);
160 }
161 
ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state * st)162 static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st)
163 {
164 	u32 mode_target;
165 
166 	/*
167 	 * Best access for secondary reg area, QSPI where possible,
168 	 * else as DSPI.
169 	 */
170 	if (st->model_data->num_spi_data_lanes == 4)
171 		mode_target = AD3552R_QUAD_SPI;
172 	else
173 		mode_target = AD3552R_DUAL_SPI;
174 
175 	/*
176 	 * Better to not use update here, since generally it is already
177 	 * set as DDR mode, and it's not possible to read in DDR mode.
178 	 */
179 	return st->data->bus_reg_write(st->back,
180 				AD3552R_REG_ADDR_TRANSFER_REGISTER,
181 				FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
182 					   mode_target) |
183 				AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
184 }
185 
ad3552r_hs_buffer_postenable(struct iio_dev * indio_dev)186 static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
187 {
188 	struct ad3552r_hs_state *st = iio_priv(indio_dev);
189 	struct iio_backend_data_fmt fmt = {
190 		.type = IIO_BACKEND_DATA_UNSIGNED
191 	};
192 	int loop_len, val, ret;
193 
194 	switch (*indio_dev->active_scan_mask) {
195 	case AD3552R_CH0_ACTIVE:
196 		st->single_channel = true;
197 		loop_len = 2;
198 		val = AD3552R_REG_ADDR_CH_DAC_16B(0);
199 		break;
200 	case AD3552R_CH1_ACTIVE:
201 		st->single_channel = true;
202 		loop_len = 2;
203 		val = AD3552R_REG_ADDR_CH_DAC_16B(1);
204 		break;
205 	case AD3552R_CH0_ACTIVE | AD3552R_CH1_ACTIVE:
206 		st->single_channel = false;
207 		loop_len = 4;
208 		val = AD3552R_REG_ADDR_CH_DAC_16B(1);
209 		break;
210 	default:
211 		return -EINVAL;
212 	}
213 
214 	/*
215 	 * With ad3541/2r support, QSPI pin is held low at reset from HDL,
216 	 * streaming start sequence must respect strictly the order below.
217 	 */
218 
219 	/* Primary region access, set streaming mode (now in SPI + SDR). */
220 	ret = ad3552r_hs_update_reg_bits(st,
221 					 AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
222 					 AD3552R_MASK_SINGLE_INST, 0, 1);
223 	if (ret)
224 		return ret;
225 
226 	/*
227 	 * Set target loop len, keeping the value: streaming writes at address
228 	 * 0x2c or 0x2a, in descending loop (2 or 4 bytes), keeping loop len
229 	 * value so that it's not cleared hereafter when _CS is deasserted.
230 	 */
231 	ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
232 					 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
233 					 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
234 					 1);
235 	if (ret)
236 		goto exit_err_streaming;
237 
238 	ret = st->data->bus_reg_write(st->back,
239 				      AD3552R_REG_ADDR_STREAM_MODE,
240 				      loop_len, 1);
241 	if (ret)
242 		goto exit_err_streaming;
243 
244 	st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR;
245 	ret = st->data->bus_reg_write(st->back,
246 				      AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
247 				      st->config_d, 1);
248 	if (ret)
249 		goto exit_err_streaming;
250 
251 	ret = iio_backend_ddr_enable(st->back);
252 	if (ret)
253 		goto exit_err_ddr_mode_target;
254 
255 	/*
256 	 * From here onward mode is DDR, so reading any register is not possible
257 	 * anymore, including calling "ad3552r_hs_update_reg_bits" function.
258 	 */
259 
260 	/* Set target to best high speed mode (D or QSPI). */
261 	ret = ad3552r_hs_set_target_io_mode_hs(st);
262 	if (ret)
263 		goto exit_err_ddr_mode;
264 
265 	/* Set bus to best high speed mode (D or QSPI). */
266 	ret = ad3552r_hs_set_bus_io_mode_hs(st);
267 	if (ret)
268 		goto exit_err_bus_mode_target;
269 
270 	/*
271 	 * Backend setup must be done now only, or related register values will
272 	 * be disrupted by previous bus accesses.
273 	 */
274 	ret = iio_backend_data_transfer_addr(st->back, val);
275 	if (ret)
276 		goto exit_err_bus_mode_target;
277 
278 	ret = iio_backend_data_format_set(st->back, 0, &fmt);
279 	if (ret)
280 		goto exit_err_bus_mode_target;
281 
282 	ret = iio_backend_data_stream_enable(st->back);
283 	if (ret)
284 		goto exit_err_bus_mode_target;
285 
286 	return 0;
287 
288 exit_err_bus_mode_target:
289 	/* Back to simple SPI, not using update to avoid read. */
290 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER,
291 				FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
292 					   AD3552R_SPI) |
293 				AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
294 
295 	/*
296 	 * Back bus to simple SPI, this must be executed together with above
297 	 * target mode unwind, and can be done only after it.
298 	 */
299 	st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
300 
301 exit_err_ddr_mode:
302 	iio_backend_ddr_disable(st->back);
303 
304 exit_err_ddr_mode_target:
305 	/*
306 	 * Back to SDR. In DDR we cannot read, whatever the mode is, so not
307 	 * using update.
308 	 */
309 	st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
310 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
311 				st->config_d, 1);
312 
313 exit_err_streaming:
314 	/* Back to single instruction mode, disabling loop. */
315 	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
316 				AD3552R_MASK_SINGLE_INST |
317 				AD3552R_MASK_SHORT_INSTRUCTION, 1);
318 
319 	return ret;
320 }
321 
ad3552r_hs_buffer_predisable(struct iio_dev * indio_dev)322 static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev)
323 {
324 	struct ad3552r_hs_state *st = iio_priv(indio_dev);
325 	int ret;
326 
327 	ret = iio_backend_data_stream_disable(st->back);
328 	if (ret)
329 		return ret;
330 
331 	/*
332 	 * Set us to simple SPI, even if still in ddr, so to be able to write
333 	 * in primary region.
334 	 */
335 	ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
336 	if (ret)
337 		return ret;
338 
339 	/*
340 	 * Back to SDR (in DDR we cannot read, whatever the mode is, so not
341 	 * using update).
342 	 */
343 	st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
344 	ret = st->data->bus_reg_write(st->back,
345 				      AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
346 				      st->config_d, 1);
347 	if (ret)
348 		return ret;
349 
350 	ret = iio_backend_ddr_disable(st->back);
351 	if (ret)
352 		return ret;
353 
354 	/*
355 	 * Back to simple SPI for secondary region too now, so to be able to
356 	 * dump/read registers there too if needed.
357 	 */
358 	ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
359 					 AD3552R_MASK_MULTI_IO_MODE,
360 					 AD3552R_SPI, 1);
361 	if (ret)
362 		return ret;
363 
364 	/* Back to single instruction mode, disabling loop. */
365 	ret = ad3552r_hs_update_reg_bits(st,
366 					 AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
367 					 AD3552R_MASK_SINGLE_INST,
368 					 AD3552R_MASK_SINGLE_INST, 1);
369 	if (ret)
370 		return ret;
371 
372 	return 0;
373 }
374 
ad3552r_hs_set_output_range(struct ad3552r_hs_state * st,int ch,unsigned int mode)375 static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st,
376 					      int ch, unsigned int mode)
377 {
378 	int val;
379 
380 	if (ch == 0)
381 		val = FIELD_PREP(AD3552R_MASK_CH0_RANGE, mode);
382 	else
383 		val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode);
384 
385 	return ad3552r_hs_update_reg_bits(st,
386 					  AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
387 					  AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
388 					  val, 1);
389 }
390 
ad3552r_hs_reset(struct ad3552r_hs_state * st)391 static int ad3552r_hs_reset(struct ad3552r_hs_state *st)
392 {
393 	int ret;
394 
395 	st->reset_gpio = devm_gpiod_get_optional(st->dev,
396 						 "reset", GPIOD_OUT_HIGH);
397 	if (IS_ERR(st->reset_gpio))
398 		return PTR_ERR(st->reset_gpio);
399 
400 	if (st->reset_gpio) {
401 		fsleep(10);
402 		gpiod_set_value_cansleep(st->reset_gpio, 0);
403 	} else {
404 		ret = ad3552r_hs_update_reg_bits(st,
405 			AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
406 			AD3552R_MASK_SOFTWARE_RESET,
407 			AD3552R_MASK_SOFTWARE_RESET, 1);
408 		if (ret)
409 			return ret;
410 	}
411 	msleep(100);
412 
413 	return 0;
414 }
415 
ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state * st)416 static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st)
417 {
418 	int ret, val;
419 
420 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
421 				      AD3552R_SCRATCH_PAD_TEST_VAL1, 1);
422 	if (ret)
423 		return ret;
424 
425 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
426 				     &val, 1);
427 	if (ret)
428 		return ret;
429 
430 	if (val != AD3552R_SCRATCH_PAD_TEST_VAL1)
431 		return dev_err_probe(st->dev, -EIO,
432 			"SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n",
433 			AD3552R_SCRATCH_PAD_TEST_VAL1, val);
434 
435 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
436 				      AD3552R_SCRATCH_PAD_TEST_VAL2, 1);
437 	if (ret)
438 		return ret;
439 
440 	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
441 				     &val, 1);
442 	if (ret)
443 		return ret;
444 
445 	if (val != AD3552R_SCRATCH_PAD_TEST_VAL2)
446 		return dev_err_probe(st->dev, -EIO,
447 			"SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n",
448 			AD3552R_SCRATCH_PAD_TEST_VAL2, val);
449 
450 	return 0;
451 }
452 
ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state * st,int ch,u16 gain,u16 offset)453 static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st,
454 					int ch, u16 gain, u16 offset)
455 {
456 	int ret;
457 
458 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch),
459 				      offset, 1);
460 	if (ret)
461 		return ret;
462 
463 	return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch),
464 				      gain, 1);
465 }
466 
ad3552r_hs_setup(struct ad3552r_hs_state * st)467 static int ad3552r_hs_setup(struct ad3552r_hs_state *st)
468 {
469 	u16 id;
470 	u16 gain = 0, offset = 0;
471 	u32 ch, val, range;
472 	int ret;
473 
474 	ret = ad3552r_hs_reset(st);
475 	if (ret)
476 		return ret;
477 
478 	/* HDL starts with DDR enabled, disabling it. */
479 	ret = iio_backend_ddr_disable(st->back);
480 	if (ret)
481 		return ret;
482 
483 	ret = st->data->bus_reg_write(st->back,
484 				      AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
485 				      AD3552R_MASK_SINGLE_INST |
486 				      AD3552R_MASK_SHORT_INSTRUCTION, 1);
487 	if (ret)
488 		return ret;
489 
490 	ret = ad3552r_hs_scratch_pad_test(st);
491 	if (ret)
492 		return ret;
493 
494 	/*
495 	 * Caching config_d, needed to restore it after streaming,
496 	 * and also, to detect possible DDR read, that's not allowed.
497 	 */
498 	ret = st->data->bus_reg_read(st->back,
499 				     AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
500 				     &st->config_d, 1);
501 	if (ret)
502 		return ret;
503 
504 	ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1);
505 	if (ret)
506 		return ret;
507 
508 	id = val;
509 
510 	ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1);
511 	if (ret)
512 		return ret;
513 
514 	id |= val << 8;
515 	if (id != st->model_data->chip_id)
516 		dev_warn(st->dev,
517 			 "chip ID mismatch, detected 0x%x but expected 0x%x\n",
518 			 id, st->model_data->chip_id);
519 
520 	dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name);
521 
522 	/* Clear reset error flag, see ad3552r manual, rev B table 38. */
523 	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS,
524 				      AD3552R_MASK_RESET_STATUS, 1);
525 	if (ret)
526 		return ret;
527 
528 	ret = st->data->bus_reg_write(st->back,
529 				      AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
530 				      0, 1);
531 	if (ret)
532 		return ret;
533 
534 	ret = iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL);
535 	if (ret)
536 		return ret;
537 
538 	ret = iio_backend_data_source_set(st->back, 1, IIO_BACKEND_EXTERNAL);
539 	if (ret)
540 		return ret;
541 
542 	ret = ad3552r_get_ref_voltage(st->dev, &val);
543 	if (ret < 0)
544 		return ret;
545 
546 	val = ret;
547 
548 	ret = ad3552r_hs_update_reg_bits(st,
549 					 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
550 					 AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
551 					 val, 1);
552 	if (ret)
553 		return ret;
554 
555 	ret = ad3552r_get_drive_strength(st->dev, &val);
556 	if (!ret) {
557 		st->config_d |=
558 			FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val);
559 
560 		ret = st->data->bus_reg_write(st->back,
561 					AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
562 					st->config_d, 1);
563 		if (ret)
564 			return ret;
565 	}
566 
567 	device_for_each_child_node_scoped(st->dev, child) {
568 		ret = fwnode_property_read_u32(child, "reg", &ch);
569 		if (ret)
570 			return dev_err_probe(st->dev, ret,
571 					     "reg property missing\n");
572 
573 		ret = ad3552r_get_output_range(st->dev, st->model_data, child,
574 					       &range);
575 		if (ret && ret != -ENOENT)
576 			return ret;
577 		if (ret == -ENOENT) {
578 			ret = ad3552r_get_custom_gain(st->dev, child,
579 						&st->ch_data[ch].p,
580 						&st->ch_data[ch].n,
581 						&st->ch_data[ch].rfb,
582 						&st->ch_data[ch].gain_offset);
583 			if (ret)
584 				return ret;
585 
586 			gain = ad3552r_calc_custom_gain(st->ch_data[ch].p,
587 						st->ch_data[ch].n,
588 						st->ch_data[ch].gain_offset);
589 			offset = abs(st->ch_data[ch].gain_offset);
590 
591 			st->ch_data[ch].range_override = 1;
592 
593 			ret = ad3552r_hs_setup_custom_gain(st, ch, gain,
594 							   offset);
595 			if (ret)
596 				return ret;
597 		} else {
598 			st->ch_data[ch].range = range;
599 
600 			ret = ad3552r_hs_set_output_range(st, ch, range);
601 			if (ret)
602 				return ret;
603 		}
604 
605 		ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data);
606 	}
607 
608 	return 0;
609 }
610 
611 static const struct iio_buffer_setup_ops ad3552r_hs_buffer_setup_ops = {
612 	.postenable = ad3552r_hs_buffer_postenable,
613 	.predisable = ad3552r_hs_buffer_predisable,
614 };
615 
616 #define AD3552R_CHANNEL(ch) { \
617 	.type = IIO_VOLTAGE, \
618 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
619 			      BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
620 			      BIT(IIO_CHAN_INFO_SCALE) | \
621 			      BIT(IIO_CHAN_INFO_OFFSET), \
622 	.output = 1, \
623 	.indexed = 1, \
624 	.channel = (ch), \
625 	.scan_index = (ch), \
626 	.scan_type = { \
627 		.sign = 'u', \
628 		.realbits = 16, \
629 		.storagebits = 16, \
630 		.endianness = IIO_BE, \
631 	} \
632 }
633 
634 static const struct iio_chan_spec ad3552r_hs_channels[] = {
635 	AD3552R_CHANNEL(0),
636 	AD3552R_CHANNEL(1),
637 };
638 
639 static const struct iio_info ad3552r_hs_info = {
640 	.read_raw = &ad3552r_hs_read_raw,
641 	.write_raw = &ad3552r_hs_write_raw,
642 };
643 
ad3552r_hs_probe(struct platform_device * pdev)644 static int ad3552r_hs_probe(struct platform_device *pdev)
645 {
646 	struct ad3552r_hs_state *st;
647 	struct iio_dev *indio_dev;
648 	int ret;
649 
650 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
651 	if (!indio_dev)
652 		return -ENOMEM;
653 
654 	st = iio_priv(indio_dev);
655 	st->dev = &pdev->dev;
656 
657 	st->data = dev_get_platdata(st->dev);
658 	if (!st->data)
659 		return dev_err_probe(st->dev, -ENODEV, "No platform data !");
660 
661 	st->back = devm_iio_backend_get(&pdev->dev, NULL);
662 	if (IS_ERR(st->back))
663 		return PTR_ERR(st->back);
664 
665 	ret = devm_iio_backend_enable(&pdev->dev, st->back);
666 	if (ret)
667 		return ret;
668 
669 	st->model_data = device_get_match_data(&pdev->dev);
670 	if (!st->model_data)
671 		return -ENODEV;
672 
673 	indio_dev->name = "ad3552r";
674 	indio_dev->modes = INDIO_DIRECT_MODE;
675 	indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops;
676 	indio_dev->channels = ad3552r_hs_channels;
677 	indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels);
678 	indio_dev->info = &ad3552r_hs_info;
679 
680 	ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev);
681 	if (ret)
682 		return ret;
683 
684 	ret = ad3552r_hs_setup(st);
685 	if (ret)
686 		return ret;
687 
688 	return devm_iio_device_register(&pdev->dev, indio_dev);
689 }
690 
691 static const struct of_device_id ad3552r_hs_of_id[] = {
692 	{ .compatible = "adi,ad3541r", .data = &ad3541r_model_data },
693 	{ .compatible = "adi,ad3542r", .data = &ad3542r_model_data },
694 	{ .compatible = "adi,ad3551r", .data = &ad3551r_model_data },
695 	{ .compatible = "adi,ad3552r", .data = &ad3552r_model_data },
696 	{ }
697 };
698 MODULE_DEVICE_TABLE(of, ad3552r_hs_of_id);
699 
700 static struct platform_driver ad3552r_hs_driver = {
701 	.driver = {
702 		.name = "ad3552r-hs",
703 		.of_match_table = ad3552r_hs_of_id,
704 	},
705 	.probe = ad3552r_hs_probe,
706 };
707 module_platform_driver(ad3552r_hs_driver);
708 
709 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
710 MODULE_AUTHOR("Angelo Dureghello <adueghello@baylibre.com>");
711 MODULE_DESCRIPTION("AD3552R Driver - High Speed version");
712 MODULE_LICENSE("GPL");
713 MODULE_IMPORT_NS("IIO_BACKEND");
714 MODULE_IMPORT_NS("IIO_AD3552R");
715