1 // SPDX-License-Identifier: (GPL-2.0-only)
2 /*
3 * Analog Devices Inc. AD7625 ADC driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 * Copyright 2024 BayLibre, SAS
7 *
8 * Note that this driver requires the AXI ADC IP block configured for
9 * LVDS to function. See Documentation/iio/ad7625.rst for more
10 * information.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iio/backend.h>
18 #include <linux/iio/iio.h>
19 #include <linux/kernel.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/pwm.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/units.h>
26
27 #define AD7625_INTERNAL_REF_MV 4096
28 #define AD7960_MAX_NBW_FREQ (2 * MEGA)
29
30 struct ad7625_timing_spec {
31 /* Max conversion high time (t_{CNVH}). */
32 unsigned int conv_high_ns;
33 /* Max conversion to MSB delay (t_{MSB}). */
34 unsigned int conv_msb_ns;
35 };
36
37 struct ad7625_chip_info {
38 const char *name;
39 const unsigned int max_sample_freq_hz;
40 const struct ad7625_timing_spec *timing_spec;
41 const struct iio_chan_spec chan_spec;
42 const bool has_power_down_state;
43 const bool has_bandwidth_control;
44 const bool has_internal_vref;
45 };
46
47 /* AD7625_CHAN_SPEC - Define a chan spec structure for a specific chip */
48 #define AD7625_CHAN_SPEC(_bits) { \
49 .type = IIO_VOLTAGE, \
50 .indexed = 1, \
51 .differential = 1, \
52 .channel = 0, \
53 .channel2 = 1, \
54 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \
55 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
56 .scan_index = 0, \
57 .scan_type.sign = 's', \
58 .scan_type.storagebits = (_bits) > 16 ? 32 : 16, \
59 .scan_type.realbits = (_bits), \
60 }
61
62 struct ad7625_state {
63 const struct ad7625_chip_info *info;
64 struct iio_backend *back;
65 /* rate of the clock gated by the "clk_gate" PWM */
66 u32 ref_clk_rate_hz;
67 /* PWM burst signal for transferring acquired data to the host */
68 struct pwm_device *clk_gate_pwm;
69 /*
70 * PWM control signal for initiating data conversion. Analog
71 * inputs are sampled beginning on this signal's rising edge.
72 */
73 struct pwm_device *cnv_pwm;
74 /*
75 * Waveforms containing the last-requested and rounded
76 * properties for the clk_gate and cnv PWMs
77 */
78 struct pwm_waveform clk_gate_wf;
79 struct pwm_waveform cnv_wf;
80 unsigned int vref_mv;
81 u32 sampling_freq_hz;
82 /*
83 * Optional GPIOs for controlling device state. EN0 and EN1
84 * determine voltage reference configuration and on/off state.
85 * EN2 controls the device -3dB bandwidth (and by extension, max
86 * sample rate). EN3 controls the VCM reference output. EN2 and
87 * EN3 are only present for the AD796x devices.
88 */
89 struct gpio_desc *en_gpios[4];
90 bool can_power_down;
91 bool can_refin;
92 bool can_ref_4v096;
93 /*
94 * Indicate whether the bandwidth can be narrow (9MHz).
95 * When true, device sample rate must also be < 2MSPS.
96 */
97 bool can_narrow_bandwidth;
98 /* Indicate whether the bandwidth can be wide (28MHz). */
99 bool can_wide_bandwidth;
100 bool can_ref_5v;
101 bool can_snooze;
102 bool can_test_pattern;
103 /* Indicate whether there is a REFIN supply connected */
104 bool have_refin;
105 };
106
107 static const struct ad7625_timing_spec ad7625_timing_spec = {
108 .conv_high_ns = 40,
109 .conv_msb_ns = 145,
110 };
111
112 static const struct ad7625_timing_spec ad7626_timing_spec = {
113 .conv_high_ns = 40,
114 .conv_msb_ns = 80,
115 };
116
117 /*
118 * conv_msb_ns is set to 0 instead of the datasheet maximum of 200ns to
119 * avoid exceeding the minimum conversion time, i.e. it is effectively
120 * modulo 200 and offset by a full period. Values greater than or equal
121 * to the period would be rejected by the PWM API.
122 */
123 static const struct ad7625_timing_spec ad7960_timing_spec = {
124 .conv_high_ns = 80,
125 .conv_msb_ns = 0,
126 };
127
128 static const struct ad7625_chip_info ad7625_chip_info = {
129 .name = "ad7625",
130 .max_sample_freq_hz = 6 * MEGA,
131 .timing_spec = &ad7625_timing_spec,
132 .chan_spec = AD7625_CHAN_SPEC(16),
133 .has_power_down_state = false,
134 .has_bandwidth_control = false,
135 .has_internal_vref = true,
136 };
137
138 static const struct ad7625_chip_info ad7626_chip_info = {
139 .name = "ad7626",
140 .max_sample_freq_hz = 10 * MEGA,
141 .timing_spec = &ad7626_timing_spec,
142 .chan_spec = AD7625_CHAN_SPEC(16),
143 .has_power_down_state = true,
144 .has_bandwidth_control = false,
145 .has_internal_vref = true,
146 };
147
148 static const struct ad7625_chip_info ad7960_chip_info = {
149 .name = "ad7960",
150 .max_sample_freq_hz = 5 * MEGA,
151 .timing_spec = &ad7960_timing_spec,
152 .chan_spec = AD7625_CHAN_SPEC(18),
153 .has_power_down_state = true,
154 .has_bandwidth_control = true,
155 .has_internal_vref = false,
156 };
157
158 static const struct ad7625_chip_info ad7961_chip_info = {
159 .name = "ad7961",
160 .max_sample_freq_hz = 5 * MEGA,
161 .timing_spec = &ad7960_timing_spec,
162 .chan_spec = AD7625_CHAN_SPEC(16),
163 .has_power_down_state = true,
164 .has_bandwidth_control = true,
165 .has_internal_vref = false,
166 };
167
168 enum ad7960_mode {
169 AD7960_MODE_POWER_DOWN,
170 AD7960_MODE_SNOOZE,
171 AD7960_MODE_NARROW_BANDWIDTH,
172 AD7960_MODE_WIDE_BANDWIDTH,
173 AD7960_MODE_TEST_PATTERN,
174 };
175
ad7625_set_sampling_freq(struct ad7625_state * st,u32 freq)176 static int ad7625_set_sampling_freq(struct ad7625_state *st, u32 freq)
177 {
178 u32 target;
179 struct pwm_waveform clk_gate_wf = { }, cnv_wf = { };
180 int ret;
181
182 target = DIV_ROUND_UP(NSEC_PER_SEC, freq);
183 cnv_wf.period_length_ns = clamp(target, 100, 10 * KILO);
184
185 /*
186 * Use the maximum conversion time t_CNVH from the datasheet as
187 * the duty_cycle for ref_clk, cnv, and clk_gate
188 */
189 cnv_wf.duty_length_ns = st->info->timing_spec->conv_high_ns;
190
191 ret = pwm_round_waveform_might_sleep(st->cnv_pwm, &cnv_wf);
192 if (ret)
193 return ret;
194
195 /*
196 * Set up the burst signal for transferring data. period and
197 * offset should mirror the CNV signal
198 */
199 clk_gate_wf.period_length_ns = cnv_wf.period_length_ns;
200
201 clk_gate_wf.duty_length_ns = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC *
202 st->info->chan_spec.scan_type.realbits,
203 st->ref_clk_rate_hz);
204
205 /* max t_MSB from datasheet */
206 clk_gate_wf.duty_offset_ns = st->info->timing_spec->conv_msb_ns;
207
208 ret = pwm_round_waveform_might_sleep(st->clk_gate_pwm, &clk_gate_wf);
209 if (ret)
210 return ret;
211
212 st->cnv_wf = cnv_wf;
213 st->clk_gate_wf = clk_gate_wf;
214
215 /* TODO: Add a rounding API for PWMs that can simplify this */
216 target = DIV_ROUND_CLOSEST(st->ref_clk_rate_hz, freq);
217 st->sampling_freq_hz = DIV_ROUND_CLOSEST(st->ref_clk_rate_hz,
218 target);
219
220 return 0;
221 }
222
ad7625_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)223 static int ad7625_read_raw(struct iio_dev *indio_dev,
224 const struct iio_chan_spec *chan,
225 int *val, int *val2, long info)
226 {
227 struct ad7625_state *st = iio_priv(indio_dev);
228
229 switch (info) {
230 case IIO_CHAN_INFO_SAMP_FREQ:
231 *val = st->sampling_freq_hz;
232
233 return IIO_VAL_INT;
234
235 case IIO_CHAN_INFO_SCALE:
236 *val = st->vref_mv;
237 *val2 = chan->scan_type.realbits - 1;
238
239 return IIO_VAL_FRACTIONAL_LOG2;
240
241 default:
242 return -EINVAL;
243 }
244 }
245
ad7625_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)246 static int ad7625_write_raw(struct iio_dev *indio_dev,
247 struct iio_chan_spec const *chan,
248 int val, int val2, long info)
249 {
250 struct ad7625_state *st = iio_priv(indio_dev);
251 int ret;
252
253 switch (info) {
254 case IIO_CHAN_INFO_SAMP_FREQ:
255 if (!iio_device_claim_direct(indio_dev))
256 return -EBUSY;
257 ret = ad7625_set_sampling_freq(st, val);
258 iio_device_release_direct(indio_dev);
259 return ret;
260 default:
261 return -EINVAL;
262 }
263 }
264
ad7625_parse_mode(struct device * dev,struct ad7625_state * st,int num_gpios)265 static int ad7625_parse_mode(struct device *dev, struct ad7625_state *st,
266 int num_gpios)
267 {
268 bool en_always_on[4], en_always_off[4];
269 bool en_may_be_on[4], en_may_be_off[4];
270 char en_gpio_buf[4];
271 char always_on_buf[18];
272 int i;
273
274 for (i = 0; i < num_gpios; i++) {
275 snprintf(en_gpio_buf, sizeof(en_gpio_buf), "en%d", i);
276 snprintf(always_on_buf, sizeof(always_on_buf),
277 "adi,en%d-always-on", i);
278 /* Set the device to 0b0000 (power-down mode) by default */
279 st->en_gpios[i] = devm_gpiod_get_optional(dev, en_gpio_buf,
280 GPIOD_OUT_LOW);
281 if (IS_ERR(st->en_gpios[i]))
282 return dev_err_probe(dev, PTR_ERR(st->en_gpios[i]),
283 "failed to get EN%d GPIO\n", i);
284
285 en_always_on[i] = device_property_read_bool(dev, always_on_buf);
286 if (st->en_gpios[i] && en_always_on[i])
287 return dev_err_probe(dev, -EINVAL,
288 "cannot have adi,en%d-always-on and en%d-gpios\n", i, i);
289
290 en_may_be_off[i] = !en_always_on[i];
291 en_may_be_on[i] = en_always_on[i] || st->en_gpios[i];
292 en_always_off[i] = !en_always_on[i] && !st->en_gpios[i];
293 }
294
295 /*
296 * Power down is mode 0bXX00, but not all devices have a valid
297 * power down state.
298 */
299 st->can_power_down = en_may_be_off[1] && en_may_be_off[0] &&
300 st->info->has_power_down_state;
301 /*
302 * The REFIN pin can take a 1.2V (AD762x) or 2.048V (AD796x)
303 * external reference when the mode is 0bXX01.
304 */
305 st->can_refin = en_may_be_off[1] && en_may_be_on[0];
306 /* 4.096V can be applied to REF when the EN mode is 0bXX10. */
307 st->can_ref_4v096 = en_may_be_on[1] && en_may_be_off[0];
308
309 /* Avoid AD796x-specific setup if the part is an AD762x */
310 if (num_gpios == 2)
311 return 0;
312
313 /* mode 0b1100 (AD796x) is invalid */
314 if (en_always_on[3] && en_always_on[2] &&
315 en_always_off[1] && en_always_off[0])
316 return dev_err_probe(dev, -EINVAL,
317 "EN GPIOs set to invalid mode 0b1100\n");
318 /*
319 * 5V can be applied to the AD796x REF pin when the EN mode is
320 * the same (0bX001 or 0bX101) as for can_refin, and REFIN is
321 * 0V.
322 */
323 st->can_ref_5v = st->can_refin;
324 /*
325 * Bandwidth (AD796x) is controlled solely by EN2. If it's
326 * specified and not hard-wired, then we can configure it to
327 * change the bandwidth between 28MHz and 9MHz.
328 */
329 st->can_narrow_bandwidth = en_may_be_on[2];
330 /* Wide bandwidth mode is possible if EN2 can be 0. */
331 st->can_wide_bandwidth = en_may_be_off[2];
332 /* Snooze mode (AD796x) is 0bXX11 when REFIN = 0V. */
333 st->can_snooze = en_may_be_on[1] && en_may_be_on[0];
334 /* Test pattern mode (AD796x) is 0b0100. */
335 st->can_test_pattern = en_may_be_off[3] && en_may_be_on[2] &&
336 en_may_be_off[1] && en_may_be_off[0];
337
338 return 0;
339 }
340
341 /* Set EN1 and EN0 based on reference voltage source */
ad7625_set_en_gpios_for_vref(struct ad7625_state * st,bool have_refin,int ref_mv)342 static void ad7625_set_en_gpios_for_vref(struct ad7625_state *st,
343 bool have_refin, int ref_mv)
344 {
345 if (have_refin || ref_mv == 5000) {
346 gpiod_set_value_cansleep(st->en_gpios[1], 0);
347 gpiod_set_value_cansleep(st->en_gpios[0], 1);
348 } else if (ref_mv == 4096) {
349 gpiod_set_value_cansleep(st->en_gpios[1], 1);
350 gpiod_set_value_cansleep(st->en_gpios[0], 0);
351 } else {
352 /*
353 * Unreachable by AD796x, since the driver will error if
354 * neither REF nor REFIN is provided
355 */
356 gpiod_set_value_cansleep(st->en_gpios[1], 1);
357 gpiod_set_value_cansleep(st->en_gpios[0], 1);
358 }
359 }
360
ad7960_set_mode(struct ad7625_state * st,enum ad7960_mode mode,bool have_refin,int ref_mv)361 static int ad7960_set_mode(struct ad7625_state *st, enum ad7960_mode mode,
362 bool have_refin, int ref_mv)
363 {
364 switch (mode) {
365 case AD7960_MODE_POWER_DOWN:
366 if (!st->can_power_down)
367 return -EINVAL;
368
369 gpiod_set_value_cansleep(st->en_gpios[2], 0);
370 gpiod_set_value_cansleep(st->en_gpios[1], 0);
371 gpiod_set_value_cansleep(st->en_gpios[0], 0);
372
373 return 0;
374
375 case AD7960_MODE_SNOOZE:
376 if (!st->can_snooze)
377 return -EINVAL;
378
379 gpiod_set_value_cansleep(st->en_gpios[1], 1);
380 gpiod_set_value_cansleep(st->en_gpios[0], 1);
381
382 return 0;
383
384 case AD7960_MODE_NARROW_BANDWIDTH:
385 if (!st->can_narrow_bandwidth)
386 return -EINVAL;
387
388 gpiod_set_value_cansleep(st->en_gpios[2], 1);
389 ad7625_set_en_gpios_for_vref(st, have_refin, ref_mv);
390
391 return 0;
392
393 case AD7960_MODE_WIDE_BANDWIDTH:
394 if (!st->can_wide_bandwidth)
395 return -EINVAL;
396
397 gpiod_set_value_cansleep(st->en_gpios[2], 0);
398 ad7625_set_en_gpios_for_vref(st, have_refin, ref_mv);
399
400 return 0;
401
402 case AD7960_MODE_TEST_PATTERN:
403 if (!st->can_test_pattern)
404 return -EINVAL;
405
406 gpiod_set_value_cansleep(st->en_gpios[3], 0);
407 gpiod_set_value_cansleep(st->en_gpios[2], 1);
408 gpiod_set_value_cansleep(st->en_gpios[1], 0);
409 gpiod_set_value_cansleep(st->en_gpios[0], 0);
410
411 return 0;
412
413 default:
414 return -EINVAL;
415 }
416 }
417
ad7625_buffer_preenable(struct iio_dev * indio_dev)418 static int ad7625_buffer_preenable(struct iio_dev *indio_dev)
419 {
420 struct ad7625_state *st = iio_priv(indio_dev);
421 int ret;
422
423 ret = pwm_set_waveform_might_sleep(st->cnv_pwm, &st->cnv_wf, false);
424 if (ret)
425 return ret;
426
427 ret = pwm_set_waveform_might_sleep(st->clk_gate_pwm,
428 &st->clk_gate_wf, false);
429 if (ret) {
430 /* Disable cnv PWM if clk_gate setup failed */
431 pwm_disable(st->cnv_pwm);
432 return ret;
433 }
434
435 return 0;
436 }
437
ad7625_buffer_postdisable(struct iio_dev * indio_dev)438 static int ad7625_buffer_postdisable(struct iio_dev *indio_dev)
439 {
440 struct ad7625_state *st = iio_priv(indio_dev);
441
442 pwm_disable(st->clk_gate_pwm);
443 pwm_disable(st->cnv_pwm);
444
445 return 0;
446 }
447
448 static const struct iio_info ad7625_info = {
449 .read_raw = ad7625_read_raw,
450 .write_raw = ad7625_write_raw,
451 };
452
453 static const struct iio_buffer_setup_ops ad7625_buffer_setup_ops = {
454 .preenable = &ad7625_buffer_preenable,
455 .postdisable = &ad7625_buffer_postdisable,
456 };
457
devm_ad7625_pwm_get(struct device * dev,struct ad7625_state * st)458 static int devm_ad7625_pwm_get(struct device *dev,
459 struct ad7625_state *st)
460 {
461 struct clk *ref_clk;
462 u32 ref_clk_rate_hz;
463
464 st->cnv_pwm = devm_pwm_get(dev, "cnv");
465 if (IS_ERR(st->cnv_pwm))
466 return dev_err_probe(dev, PTR_ERR(st->cnv_pwm),
467 "failed to get cnv pwm\n");
468
469 /* Preemptively disable the PWM in case it was enabled at boot */
470 pwm_disable(st->cnv_pwm);
471
472 st->clk_gate_pwm = devm_pwm_get(dev, "clk_gate");
473 if (IS_ERR(st->clk_gate_pwm))
474 return dev_err_probe(dev, PTR_ERR(st->clk_gate_pwm),
475 "failed to get clk_gate pwm\n");
476
477 /* Preemptively disable the PWM in case it was enabled at boot */
478 pwm_disable(st->clk_gate_pwm);
479
480 ref_clk = devm_clk_get_enabled(dev, NULL);
481 if (IS_ERR(ref_clk))
482 return dev_err_probe(dev, PTR_ERR(ref_clk),
483 "failed to get ref_clk\n");
484
485 ref_clk_rate_hz = clk_get_rate(ref_clk);
486 if (!ref_clk_rate_hz)
487 return dev_err_probe(dev, -EINVAL,
488 "failed to get ref_clk rate\n");
489
490 st->ref_clk_rate_hz = ref_clk_rate_hz;
491
492 return 0;
493 }
494
495 /*
496 * There are three required input voltages for each device, plus two
497 * conditionally-optional (depending on part) REF and REFIN voltages
498 * where their validity depends upon the EN pin configuration.
499 *
500 * Power-up info for the device says to bring up vio, then vdd2, then
501 * vdd1, so list them in that order in the regulator_names array.
502 *
503 * The reference voltage source is determined like so:
504 * - internal reference: neither REF or REFIN is connected (invalid for
505 * AD796x)
506 * - internal buffer, external reference: REF not connected, REFIN
507 * connected
508 * - external reference: REF connected, REFIN not connected
509 */
devm_ad7625_regulator_setup(struct device * dev,struct ad7625_state * st)510 static int devm_ad7625_regulator_setup(struct device *dev,
511 struct ad7625_state *st)
512 {
513 static const char * const regulator_names[] = { "vio", "vdd2", "vdd1" };
514 int ret, ref_mv;
515
516 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
517 regulator_names);
518 if (ret)
519 return ret;
520
521 ret = devm_regulator_get_enable_read_voltage(dev, "ref");
522 if (ret < 0 && ret != -ENODEV)
523 return dev_err_probe(dev, ret, "failed to get REF voltage\n");
524
525 ref_mv = ret == -ENODEV ? 0 : ret / 1000;
526
527 ret = devm_regulator_get_enable_optional(dev, "refin");
528 if (ret < 0 && ret != -ENODEV)
529 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n");
530
531 st->have_refin = ret != -ENODEV;
532
533 if (st->have_refin && !st->can_refin)
534 return dev_err_probe(dev, -EINVAL,
535 "REFIN provided in unsupported mode\n");
536
537 if (!st->info->has_internal_vref && !st->have_refin && !ref_mv)
538 return dev_err_probe(dev, -EINVAL,
539 "Need either REFIN or REF\n");
540
541 if (st->have_refin && ref_mv)
542 return dev_err_probe(dev, -EINVAL,
543 "cannot have both REFIN and REF supplies\n");
544
545 if (ref_mv == 4096 && !st->can_ref_4v096)
546 return dev_err_probe(dev, -EINVAL,
547 "REF is 4.096V in unsupported mode\n");
548
549 if (ref_mv == 5000 && !st->can_ref_5v)
550 return dev_err_probe(dev, -EINVAL,
551 "REF is 5V in unsupported mode\n");
552
553 st->vref_mv = ref_mv ?: AD7625_INTERNAL_REF_MV;
554
555 return 0;
556 }
557
ad7625_probe(struct platform_device * pdev)558 static int ad7625_probe(struct platform_device *pdev)
559 {
560 struct device *dev = &pdev->dev;
561 struct iio_dev *indio_dev;
562 struct ad7625_state *st;
563 int ret;
564 u32 default_sample_freq;
565
566 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
567 if (!indio_dev)
568 return -ENOMEM;
569
570 st = iio_priv(indio_dev);
571
572 st->info = device_get_match_data(dev);
573 if (!st->info)
574 return dev_err_probe(dev, -EINVAL, "no chip info\n");
575
576 if (device_property_read_bool(dev, "adi,no-dco"))
577 return dev_err_probe(dev, -EINVAL,
578 "self-clocked mode not supported\n");
579
580 if (st->info->has_bandwidth_control)
581 ret = ad7625_parse_mode(dev, st, 4);
582 else
583 ret = ad7625_parse_mode(dev, st, 2);
584
585 if (ret)
586 return ret;
587
588 ret = devm_ad7625_regulator_setup(dev, st);
589 if (ret)
590 return ret;
591
592 /* Set the device mode based on detected EN configuration. */
593 if (!st->info->has_bandwidth_control) {
594 ad7625_set_en_gpios_for_vref(st, st->have_refin, st->vref_mv);
595 } else {
596 /*
597 * If neither sampling mode is available, then report an error,
598 * since the other modes are not useful defaults.
599 */
600 if (st->can_wide_bandwidth) {
601 ret = ad7960_set_mode(st, AD7960_MODE_WIDE_BANDWIDTH,
602 st->have_refin, st->vref_mv);
603 } else if (st->can_narrow_bandwidth) {
604 ret = ad7960_set_mode(st, AD7960_MODE_NARROW_BANDWIDTH,
605 st->have_refin, st->vref_mv);
606 } else {
607 return dev_err_probe(dev, -EINVAL,
608 "couldn't set device to wide or narrow bandwidth modes\n");
609 }
610
611 if (ret)
612 return dev_err_probe(dev, -EINVAL,
613 "failed to set EN pins\n");
614 }
615
616 ret = devm_ad7625_pwm_get(dev, st);
617 if (ret)
618 return ret;
619
620 indio_dev->channels = &st->info->chan_spec;
621 indio_dev->num_channels = 1;
622 indio_dev->name = st->info->name;
623 indio_dev->info = &ad7625_info;
624 indio_dev->setup_ops = &ad7625_buffer_setup_ops;
625
626 st->back = devm_iio_backend_get(dev, NULL);
627 if (IS_ERR(st->back))
628 return dev_err_probe(dev, PTR_ERR(st->back),
629 "failed to get IIO backend\n");
630
631 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
632 if (ret)
633 return ret;
634
635 ret = devm_iio_backend_enable(dev, st->back);
636 if (ret)
637 return ret;
638
639 /*
640 * Set the initial sampling frequency to the maximum, unless the
641 * AD796x device is limited to narrow bandwidth by EN2 == 1, in
642 * which case the sampling frequency should be limited to 2MSPS
643 */
644 default_sample_freq = st->info->max_sample_freq_hz;
645 if (st->info->has_bandwidth_control && !st->can_wide_bandwidth)
646 default_sample_freq = AD7960_MAX_NBW_FREQ;
647
648 ret = ad7625_set_sampling_freq(st, default_sample_freq);
649 if (ret)
650 dev_err_probe(dev, ret,
651 "failed to set valid sampling frequency\n");
652
653 return devm_iio_device_register(dev, indio_dev);
654 }
655
656 static const struct of_device_id ad7625_of_match[] = {
657 { .compatible = "adi,ad7625", .data = &ad7625_chip_info },
658 { .compatible = "adi,ad7626", .data = &ad7626_chip_info },
659 { .compatible = "adi,ad7960", .data = &ad7960_chip_info },
660 { .compatible = "adi,ad7961", .data = &ad7961_chip_info },
661 { }
662 };
663 MODULE_DEVICE_TABLE(of, ad7625_of_match);
664
665 static const struct platform_device_id ad7625_device_ids[] = {
666 { .name = "ad7625", .driver_data = (kernel_ulong_t)&ad7625_chip_info },
667 { .name = "ad7626", .driver_data = (kernel_ulong_t)&ad7626_chip_info },
668 { .name = "ad7960", .driver_data = (kernel_ulong_t)&ad7960_chip_info },
669 { .name = "ad7961", .driver_data = (kernel_ulong_t)&ad7961_chip_info },
670 { }
671 };
672 MODULE_DEVICE_TABLE(platform, ad7625_device_ids);
673
674 static struct platform_driver ad7625_driver = {
675 .probe = ad7625_probe,
676 .driver = {
677 .name = "ad7625",
678 .of_match_table = ad7625_of_match,
679 },
680 .id_table = ad7625_device_ids,
681 };
682 module_platform_driver(ad7625_driver);
683
684 MODULE_AUTHOR("Trevor Gamblin <tgamblin@baylibre.com>");
685 MODULE_DESCRIPTION("Analog Devices AD7625 ADC");
686 MODULE_LICENSE("GPL");
687 MODULE_IMPORT_NS("IIO_BACKEND");
688