1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD4030 and AD4630 ADC family driver.
4 *
5 * Copyright 2024 Analog Devices, Inc.
6 * Copyright 2024 BayLibre, SAS
7 *
8 * based on code from:
9 * Analog Devices, Inc.
10 * Sergiu Cuciurean <sergiu.cuciurean@analog.com>
11 * Nuno Sa <nuno.sa@analog.com>
12 * Marcelo Schmitt <marcelo.schmitt@analog.com>
13 * Liviu Adace <liviu.adace@analog.com>
14 */
15
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spi/spi.h>
24 #include <linux/unaligned.h>
25 #include <linux/units.h>
26
27 #define AD4030_REG_INTERFACE_CONFIG_A 0x00
28 #define AD4030_REG_INTERFACE_CONFIG_A_SW_RESET (BIT(0) | BIT(7))
29 #define AD4030_REG_INTERFACE_CONFIG_B 0x01
30 #define AD4030_REG_DEVICE_CONFIG 0x02
31 #define AD4030_REG_CHIP_TYPE 0x03
32 #define AD4030_REG_PRODUCT_ID_L 0x04
33 #define AD4030_REG_PRODUCT_ID_H 0x05
34 #define AD4030_REG_CHIP_GRADE 0x06
35 #define AD4030_REG_CHIP_GRADE_AD4030_24_GRADE 0x10
36 #define AD4030_REG_CHIP_GRADE_AD4630_16_GRADE 0x03
37 #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00
38 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05
39 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02
40 #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3)
41 #define AD4030_REG_SCRATCH_PAD 0x0A
42 #define AD4030_REG_SPI_REVISION 0x0B
43 #define AD4030_REG_VENDOR_L 0x0C
44 #define AD4030_REG_VENDOR_H 0x0D
45 #define AD4030_REG_STREAM_MODE 0x0E
46 #define AD4030_REG_INTERFACE_CONFIG_C 0x10
47 #define AD4030_REG_INTERFACE_STATUS_A 0x11
48 #define AD4030_REG_EXIT_CFG_MODE 0x14
49 #define AD4030_REG_EXIT_CFG_MODE_EXIT_MSK BIT(0)
50 #define AD4030_REG_AVG 0x15
51 #define AD4030_REG_AVG_MASK_AVG_SYNC BIT(7)
52 #define AD4030_REG_AVG_MASK_AVG_VAL GENMASK(4, 0)
53 #define AD4030_REG_OFFSET_X0_0 0x16
54 #define AD4030_REG_OFFSET_X0_1 0x17
55 #define AD4030_REG_OFFSET_X0_2 0x18
56 #define AD4030_REG_OFFSET_X1_0 0x19
57 #define AD4030_REG_OFFSET_X1_1 0x1A
58 #define AD4030_REG_OFFSET_X1_2 0x1B
59 #define AD4030_REG_OFFSET_BYTES_NB 3
60 #define AD4030_REG_OFFSET_CHAN(ch) \
61 (AD4030_REG_OFFSET_X0_2 + (AD4030_REG_OFFSET_BYTES_NB * (ch)))
62 #define AD4030_REG_GAIN_X0_LSB 0x1C
63 #define AD4030_REG_GAIN_X0_MSB 0x1D
64 #define AD4030_REG_GAIN_X1_LSB 0x1E
65 #define AD4030_REG_GAIN_X1_MSB 0x1F
66 #define AD4030_REG_GAIN_MAX_GAIN 1999970
67 #define AD4030_REG_GAIN_BYTES_NB 2
68 #define AD4030_REG_GAIN_CHAN(ch) \
69 (AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch)))
70 #define AD4030_REG_MODES 0x20
71 #define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0)
72 #define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6)
73 #define AD4030_REG_OSCILATOR 0x21
74 #define AD4030_REG_IO 0x22
75 #define AD4030_REG_IO_MASK_IO2X BIT(1)
76 #define AD4030_REG_PAT0 0x23
77 #define AD4030_REG_PAT1 0x24
78 #define AD4030_REG_PAT2 0x25
79 #define AD4030_REG_PAT3 0x26
80 #define AD4030_REG_DIG_DIAG 0x34
81 #define AD4030_REG_DIG_ERR 0x35
82
83 /* Sequence starting with "1 0 1" to enable reg access */
84 #define AD4030_REG_ACCESS 0xA0
85
86 #define AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED BITS_TO_BYTES(64)
87 #define AD4030_MAX_HARDWARE_CHANNEL_NB 2
88 #define AD4030_MAX_IIO_CHANNEL_NB 5
89 #define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK 0b10
90 #define AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK 0b1100
91 #define AD4030_GAIN_MIDLE_POINT 0x8000
92 /*
93 * This accounts for 1 sample per channel plus one s64 for the timestamp,
94 * aligned on a s64 boundary
95 */
96 #define AD4030_MAXIMUM_RX_BUFFER_SIZE \
97 (ALIGN(AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED * \
98 AD4030_MAX_HARDWARE_CHANNEL_NB, \
99 sizeof(s64)) + sizeof(s64))
100
101 #define AD4030_VREF_MIN_UV (4096 * MILLI)
102 #define AD4030_VREF_MAX_UV (5000 * MILLI)
103 #define AD4030_VIO_THRESHOLD_UV (1400 * MILLI)
104 #define AD4030_SPI_MAX_XFER_LEN 8
105 #define AD4030_SPI_MAX_REG_XFER_SPEED (80 * MEGA)
106 #define AD4030_TCNVH_NS 10
107 #define AD4030_TCNVL_NS 20
108 #define AD4030_TCYC_NS 500
109 #define AD4030_TCYC_ADJUSTED_NS (AD4030_TCYC_NS - AD4030_TCNVL_NS)
110 #define AD4030_TRESET_PW_NS 50
111 #define AD4632_TCYC_NS 2000
112 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS)
113 #define AD4030_TRESET_COM_DELAY_MS 750
114
115 enum ad4030_out_mode {
116 AD4030_OUT_DATA_MD_DIFF,
117 AD4030_OUT_DATA_MD_16_DIFF_8_COM,
118 AD4030_OUT_DATA_MD_24_DIFF_8_COM,
119 AD4030_OUT_DATA_MD_30_AVERAGED_DIFF,
120 AD4030_OUT_DATA_MD_32_PATTERN,
121 };
122
123 enum {
124 AD4030_LANE_MD_1_PER_CH,
125 AD4030_LANE_MD_2_PER_CH,
126 AD4030_LANE_MD_4_PER_CH,
127 AD4030_LANE_MD_INTERLEAVED,
128 };
129
130 enum {
131 AD4030_SCAN_TYPE_NORMAL,
132 AD4030_SCAN_TYPE_AVG,
133 };
134
135 struct ad4030_chip_info {
136 const char *name;
137 const unsigned long *available_masks;
138 const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB];
139 u8 grade;
140 u8 precision_bits;
141 /* Number of hardware channels */
142 int num_voltage_inputs;
143 unsigned int tcyc_ns;
144 };
145
146 struct ad4030_state {
147 struct spi_device *spi;
148 struct regmap *regmap;
149 const struct ad4030_chip_info *chip;
150 const struct iio_scan_type *current_scan_type;
151 struct gpio_desc *cnv_gpio;
152 int vref_uv;
153 int vio_uv;
154 int offset_avail[3];
155 unsigned int avg_log2;
156 enum ad4030_out_mode mode;
157
158 /*
159 * DMA (thus cache coherency maintenance) requires the transfer buffers
160 * to live in their own cache lines.
161 */
162 u8 tx_data[AD4030_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
163 union {
164 u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE];
165 struct {
166 s32 diff;
167 u8 common;
168 } single;
169 struct {
170 s32 diff[2];
171 u8 common[2];
172 } dual;
173 } rx_data;
174 };
175
176 /*
177 * For a chip with 2 hardware channel this will be used to create 2 common-mode
178 * channels:
179 * - voltage4
180 * - voltage5
181 * As the common-mode channels are after the differential ones, we compute the
182 * channel number like this:
183 * - _idx is the scan_index (the order in the output buffer)
184 * - _ch is the hardware channel number this common-mode channel is related
185 * - _idx - _ch gives us the number of channel in the chip
186 * - _idx - _ch * 2 is the starting number of the common-mode channels, since
187 * for each differential channel there is a common-mode channel
188 * - _idx - _ch * 2 + _ch gives the channel number for this specific common-mode
189 * channel
190 */
191 #define AD4030_CHAN_CMO(_idx, _ch) { \
192 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
193 BIT(IIO_CHAN_INFO_SCALE), \
194 .type = IIO_VOLTAGE, \
195 .indexed = 1, \
196 .address = (_ch), \
197 .channel = ((_idx) - (_ch)) * 2 + (_ch), \
198 .scan_index = (_idx), \
199 .scan_type = { \
200 .sign = 'u', \
201 .storagebits = 8, \
202 .realbits = 8, \
203 .endianness = IIO_BE, \
204 }, \
205 }
206
207 /*
208 * For a chip with 2 hardware channel this will be used to create 2 differential
209 * channels:
210 * - voltage0-voltage1
211 * - voltage2-voltage3
212 */
213 #define AD4030_CHAN_DIFF(_idx, _scan_type) { \
214 .info_mask_shared_by_all = \
215 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
216 .info_mask_shared_by_all_available = \
217 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
218 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
219 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
220 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
221 BIT(IIO_CHAN_INFO_RAW), \
222 .info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
223 BIT(IIO_CHAN_INFO_CALIBSCALE), \
224 .type = IIO_VOLTAGE, \
225 .indexed = 1, \
226 .address = (_idx), \
227 .channel = (_idx) * 2, \
228 .channel2 = (_idx) * 2 + 1, \
229 .scan_index = (_idx), \
230 .differential = true, \
231 .has_ext_scan_type = 1, \
232 .ext_scan_type = _scan_type, \
233 .num_ext_scan_type = ARRAY_SIZE(_scan_type), \
234 }
235
236 static const int ad4030_average_modes[] = {
237 1, 2, 4, 8, 16, 32, 64, 128,
238 256, 512, 1024, 2048, 4096, 8192, 16384, 32768,
239 65536,
240 };
241
ad4030_enter_config_mode(struct ad4030_state * st)242 static int ad4030_enter_config_mode(struct ad4030_state *st)
243 {
244 st->tx_data[0] = AD4030_REG_ACCESS;
245
246 struct spi_transfer xfer = {
247 .tx_buf = st->tx_data,
248 .bits_per_word = 8,
249 .len = 1,
250 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
251 };
252
253 return spi_sync_transfer(st->spi, &xfer, 1);
254 }
255
ad4030_exit_config_mode(struct ad4030_state * st)256 static int ad4030_exit_config_mode(struct ad4030_state *st)
257 {
258 st->tx_data[0] = 0;
259 st->tx_data[1] = AD4030_REG_EXIT_CFG_MODE;
260 st->tx_data[2] = AD4030_REG_EXIT_CFG_MODE_EXIT_MSK;
261
262 struct spi_transfer xfer = {
263 .tx_buf = st->tx_data,
264 .bits_per_word = 8,
265 .len = 3,
266 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
267 };
268
269 return spi_sync_transfer(st->spi, &xfer, 1);
270 }
271
ad4030_spi_read(void * context,const void * reg,size_t reg_size,void * val,size_t val_size)272 static int ad4030_spi_read(void *context, const void *reg, size_t reg_size,
273 void *val, size_t val_size)
274 {
275 int ret;
276 struct ad4030_state *st = context;
277 struct spi_transfer xfer = {
278 .tx_buf = st->tx_data,
279 .rx_buf = st->rx_data.raw,
280 .bits_per_word = 8,
281 .len = reg_size + val_size,
282 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
283 };
284
285 if (xfer.len > sizeof(st->tx_data) ||
286 xfer.len > sizeof(st->rx_data.raw))
287 return -EINVAL;
288
289 ret = ad4030_enter_config_mode(st);
290 if (ret)
291 return ret;
292
293 memset(st->tx_data, 0, sizeof(st->tx_data));
294 memcpy(st->tx_data, reg, reg_size);
295
296 ret = spi_sync_transfer(st->spi, &xfer, 1);
297 if (ret)
298 return ret;
299
300 memcpy(val, &st->rx_data.raw[reg_size], val_size);
301
302 return ad4030_exit_config_mode(st);
303 }
304
ad4030_spi_write(void * context,const void * data,size_t count)305 static int ad4030_spi_write(void *context, const void *data, size_t count)
306 {
307 int ret;
308 struct ad4030_state *st = context;
309 bool is_reset = count >= 3 &&
310 ((u8 *)data)[0] == 0 &&
311 ((u8 *)data)[1] == 0 &&
312 ((u8 *)data)[2] == 0x81;
313 struct spi_transfer xfer = {
314 .tx_buf = st->tx_data,
315 .bits_per_word = 8,
316 .len = count,
317 .speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
318 };
319
320 if (count > sizeof(st->tx_data))
321 return -EINVAL;
322
323 ret = ad4030_enter_config_mode(st);
324 if (ret)
325 return ret;
326
327 memcpy(st->tx_data, data, count);
328
329 ret = spi_sync_transfer(st->spi, &xfer, 1);
330 if (ret)
331 return ret;
332
333 /*
334 * From datasheet: "After a [...] reset, no SPI commands or conversions
335 * can be started for 750us"
336 * After a reset we are in conversion mode, no need to exit config mode
337 */
338 if (is_reset) {
339 fsleep(750);
340 return 0;
341 }
342
343 return ad4030_exit_config_mode(st);
344 }
345
346 static const struct regmap_bus ad4030_regmap_bus = {
347 .read = ad4030_spi_read,
348 .write = ad4030_spi_write,
349 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
350 };
351
352 static const struct regmap_range ad4030_regmap_rd_range[] = {
353 regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_A, AD4030_REG_CHIP_GRADE),
354 regmap_reg_range(AD4030_REG_SCRATCH_PAD, AD4030_REG_STREAM_MODE),
355 regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_C,
356 AD4030_REG_INTERFACE_STATUS_A),
357 regmap_reg_range(AD4030_REG_EXIT_CFG_MODE, AD4030_REG_PAT3),
358 regmap_reg_range(AD4030_REG_DIG_DIAG, AD4030_REG_DIG_ERR),
359 };
360
361 static const struct regmap_range ad4030_regmap_wr_range[] = {
362 regmap_reg_range(AD4030_REG_CHIP_TYPE, AD4030_REG_CHIP_GRADE),
363 regmap_reg_range(AD4030_REG_SPI_REVISION, AD4030_REG_VENDOR_H),
364 };
365
366 static const struct regmap_access_table ad4030_regmap_rd_table = {
367 .yes_ranges = ad4030_regmap_rd_range,
368 .n_yes_ranges = ARRAY_SIZE(ad4030_regmap_rd_range),
369 };
370
371 static const struct regmap_access_table ad4030_regmap_wr_table = {
372 .no_ranges = ad4030_regmap_wr_range,
373 .n_no_ranges = ARRAY_SIZE(ad4030_regmap_wr_range),
374 };
375
376 static const struct regmap_config ad4030_regmap_config = {
377 .reg_bits = 16,
378 .val_bits = 8,
379 .read_flag_mask = 0x80,
380 .rd_table = &ad4030_regmap_rd_table,
381 .wr_table = &ad4030_regmap_wr_table,
382 .max_register = AD4030_REG_DIG_ERR,
383 };
384
ad4030_get_chan_scale(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2)385 static int ad4030_get_chan_scale(struct iio_dev *indio_dev,
386 struct iio_chan_spec const *chan,
387 int *val,
388 int *val2)
389 {
390 struct ad4030_state *st = iio_priv(indio_dev);
391 const struct iio_scan_type *scan_type;
392
393 if (chan->differential) {
394 scan_type = iio_get_current_scan_type(indio_dev,
395 st->chip->channels);
396 *val = (st->vref_uv * 2) / MILLI;
397 *val2 = scan_type->realbits;
398 return IIO_VAL_FRACTIONAL_LOG2;
399 }
400
401 *val = st->vref_uv / MILLI;
402 *val2 = chan->scan_type.realbits;
403 return IIO_VAL_FRACTIONAL_LOG2;
404 }
405
ad4030_get_chan_calibscale(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2)406 static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev,
407 struct iio_chan_spec const *chan,
408 int *val,
409 int *val2)
410 {
411 struct ad4030_state *st = iio_priv(indio_dev);
412 u16 gain;
413 int ret;
414
415 ret = regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address),
416 st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB);
417 if (ret)
418 return ret;
419
420 gain = get_unaligned_be16(st->rx_data.raw);
421
422 /* From datasheet: multiplied output = input × gain word/0x8000 */
423 *val = gain / AD4030_GAIN_MIDLE_POINT;
424 *val2 = mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO,
425 AD4030_GAIN_MIDLE_POINT);
426
427 return IIO_VAL_INT_PLUS_NANO;
428 }
429
430 /* Returns the offset where 1 LSB = (VREF/2^precision_bits - 1)/gain */
ad4030_get_chan_calibbias(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)431 static int ad4030_get_chan_calibbias(struct iio_dev *indio_dev,
432 struct iio_chan_spec const *chan,
433 int *val)
434 {
435 struct ad4030_state *st = iio_priv(indio_dev);
436 int ret;
437
438 ret = regmap_bulk_read(st->regmap,
439 AD4030_REG_OFFSET_CHAN(chan->address),
440 st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB);
441 if (ret)
442 return ret;
443
444 switch (st->chip->precision_bits) {
445 case 16:
446 *val = sign_extend32(get_unaligned_be16(st->rx_data.raw), 15);
447 return IIO_VAL_INT;
448
449 case 24:
450 *val = sign_extend32(get_unaligned_be24(st->rx_data.raw), 23);
451 return IIO_VAL_INT;
452
453 default:
454 return -EINVAL;
455 }
456 }
457
ad4030_set_chan_calibscale(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int gain_int,int gain_frac)458 static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev,
459 struct iio_chan_spec const *chan,
460 int gain_int,
461 int gain_frac)
462 {
463 struct ad4030_state *st = iio_priv(indio_dev);
464 u64 gain;
465
466 if (gain_int < 0 || gain_frac < 0)
467 return -EINVAL;
468
469 gain = mul_u32_u32(gain_int, MICRO) + gain_frac;
470
471 if (gain > AD4030_REG_GAIN_MAX_GAIN)
472 return -EINVAL;
473
474 put_unaligned_be16(DIV_ROUND_CLOSEST_ULL(gain * AD4030_GAIN_MIDLE_POINT,
475 MICRO),
476 st->tx_data);
477
478 return regmap_bulk_write(st->regmap,
479 AD4030_REG_GAIN_CHAN(chan->address),
480 st->tx_data, AD4030_REG_GAIN_BYTES_NB);
481 }
482
ad4030_set_chan_calibbias(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int offset)483 static int ad4030_set_chan_calibbias(struct iio_dev *indio_dev,
484 struct iio_chan_spec const *chan,
485 int offset)
486 {
487 struct ad4030_state *st = iio_priv(indio_dev);
488
489 if (offset < st->offset_avail[0] || offset > st->offset_avail[2])
490 return -EINVAL;
491
492 st->tx_data[2] = 0;
493
494 switch (st->chip->precision_bits) {
495 case 16:
496 put_unaligned_be16(offset, st->tx_data);
497 break;
498
499 case 24:
500 put_unaligned_be24(offset, st->tx_data);
501 break;
502
503 default:
504 return -EINVAL;
505 }
506
507 return regmap_bulk_write(st->regmap,
508 AD4030_REG_OFFSET_CHAN(chan->address),
509 st->tx_data, AD4030_REG_OFFSET_BYTES_NB);
510 }
511
ad4030_set_avg_frame_len(struct iio_dev * dev,int avg_val)512 static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val)
513 {
514 struct ad4030_state *st = iio_priv(dev);
515 unsigned int avg_log2 = ilog2(avg_val);
516 unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1;
517 int ret;
518
519 if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx])
520 return -EINVAL;
521
522 ret = regmap_write(st->regmap, AD4030_REG_AVG,
523 AD4030_REG_AVG_MASK_AVG_SYNC |
524 FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2));
525 if (ret)
526 return ret;
527
528 st->avg_log2 = avg_log2;
529
530 return 0;
531 }
532
ad4030_is_common_byte_asked(struct ad4030_state * st,unsigned int mask)533 static bool ad4030_is_common_byte_asked(struct ad4030_state *st,
534 unsigned int mask)
535 {
536 return mask & (st->chip->num_voltage_inputs == 1 ?
537 AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK :
538 AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK);
539 }
540
ad4030_set_mode(struct iio_dev * indio_dev,unsigned long mask)541 static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask)
542 {
543 struct ad4030_state *st = iio_priv(indio_dev);
544
545 if (st->avg_log2 > 0) {
546 st->mode = AD4030_OUT_DATA_MD_30_AVERAGED_DIFF;
547 } else if (ad4030_is_common_byte_asked(st, mask)) {
548 switch (st->chip->precision_bits) {
549 case 16:
550 st->mode = AD4030_OUT_DATA_MD_16_DIFF_8_COM;
551 break;
552
553 case 24:
554 st->mode = AD4030_OUT_DATA_MD_24_DIFF_8_COM;
555 break;
556
557 default:
558 return -EINVAL;
559 }
560 } else {
561 st->mode = AD4030_OUT_DATA_MD_DIFF;
562 }
563
564 st->current_scan_type = iio_get_current_scan_type(indio_dev,
565 st->chip->channels);
566 if (IS_ERR(st->current_scan_type))
567 return PTR_ERR(st->current_scan_type);
568
569 return regmap_update_bits(st->regmap, AD4030_REG_MODES,
570 AD4030_REG_MODES_MASK_OUT_DATA_MODE,
571 st->mode);
572 }
573
574 /*
575 * Descramble 2 32bits numbers out of a 64bits. The bits are interleaved:
576 * 1 bit for first number, 1 bit for the second, and so on...
577 */
ad4030_extract_interleaved(u8 * src,u32 * ch0,u32 * ch1)578 static void ad4030_extract_interleaved(u8 *src, u32 *ch0, u32 *ch1)
579 {
580 u8 h0, h1, l0, l1;
581 u32 out0, out1;
582 u8 *out0_raw = (u8 *)&out0;
583 u8 *out1_raw = (u8 *)&out1;
584
585 for (int i = 0; i < 4; i++) {
586 h0 = src[i * 2];
587 l1 = src[i * 2 + 1];
588 h1 = h0 << 1;
589 l0 = l1 >> 1;
590
591 h0 &= 0xAA;
592 l0 &= 0x55;
593 h1 &= 0xAA;
594 l1 &= 0x55;
595
596 h0 = (h0 | h0 << 001) & 0xCC;
597 h1 = (h1 | h1 << 001) & 0xCC;
598 l0 = (l0 | l0 >> 001) & 0x33;
599 l1 = (l1 | l1 >> 001) & 0x33;
600 h0 = (h0 | h0 << 002) & 0xF0;
601 h1 = (h1 | h1 << 002) & 0xF0;
602 l0 = (l0 | l0 >> 002) & 0x0F;
603 l1 = (l1 | l1 >> 002) & 0x0F;
604
605 out0_raw[i] = h0 | l0;
606 out1_raw[i] = h1 | l1;
607 }
608
609 *ch0 = out0;
610 *ch1 = out1;
611 }
612
ad4030_conversion(struct iio_dev * indio_dev)613 static int ad4030_conversion(struct iio_dev *indio_dev)
614 {
615 struct ad4030_state *st = iio_priv(indio_dev);
616 unsigned char diff_realbytes =
617 BITS_TO_BYTES(st->current_scan_type->realbits);
618 unsigned char diff_storagebytes =
619 BITS_TO_BYTES(st->current_scan_type->storagebits);
620 unsigned int bytes_to_read;
621 unsigned long cnv_nb = BIT(st->avg_log2);
622 unsigned int i;
623 int ret;
624
625 /* Number of bytes for one differential channel */
626 bytes_to_read = diff_realbytes;
627 /* Add one byte if we are using a differential + common byte mode */
628 bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM ||
629 st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0;
630 /* Mulitiply by the number of hardware channels */
631 bytes_to_read *= st->chip->num_voltage_inputs;
632
633 for (i = 0; i < cnv_nb; i++) {
634 gpiod_set_value_cansleep(st->cnv_gpio, 1);
635 ndelay(AD4030_TCNVH_NS);
636 gpiod_set_value_cansleep(st->cnv_gpio, 0);
637 ndelay(st->chip->tcyc_ns);
638 }
639
640 ret = spi_read(st->spi, st->rx_data.raw, bytes_to_read);
641 if (ret)
642 return ret;
643
644 if (st->chip->num_voltage_inputs == 2)
645 ad4030_extract_interleaved(st->rx_data.raw,
646 &st->rx_data.dual.diff[0],
647 &st->rx_data.dual.diff[1]);
648
649 if (st->mode != AD4030_OUT_DATA_MD_16_DIFF_8_COM &&
650 st->mode != AD4030_OUT_DATA_MD_24_DIFF_8_COM)
651 return 0;
652
653 if (st->chip->num_voltage_inputs == 1) {
654 st->rx_data.single.common = st->rx_data.raw[diff_realbytes];
655 return 0;
656 }
657
658 for (i = 0; i < st->chip->num_voltage_inputs; i++)
659 st->rx_data.dual.common[i] =
660 st->rx_data.raw[diff_storagebytes * i + diff_realbytes];
661
662 return 0;
663 }
664
ad4030_single_conversion(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val)665 static int ad4030_single_conversion(struct iio_dev *indio_dev,
666 const struct iio_chan_spec *chan, int *val)
667 {
668 struct ad4030_state *st = iio_priv(indio_dev);
669 int ret;
670
671 ret = ad4030_set_mode(indio_dev, BIT(chan->scan_index));
672 if (ret)
673 return ret;
674
675 st->current_scan_type = iio_get_current_scan_type(indio_dev,
676 st->chip->channels);
677 if (IS_ERR(st->current_scan_type))
678 return PTR_ERR(st->current_scan_type);
679
680 ret = ad4030_conversion(indio_dev);
681 if (ret)
682 return ret;
683
684 if (chan->differential)
685 if (st->chip->num_voltage_inputs == 1)
686 *val = st->rx_data.single.diff;
687 else
688 *val = st->rx_data.dual.diff[chan->address];
689 else
690 if (st->chip->num_voltage_inputs == 1)
691 *val = st->rx_data.single.common;
692 else
693 *val = st->rx_data.dual.common[chan->address];
694
695 return IIO_VAL_INT;
696 }
697
ad4030_trigger_handler(int irq,void * p)698 static irqreturn_t ad4030_trigger_handler(int irq, void *p)
699 {
700 struct iio_poll_func *pf = p;
701 struct iio_dev *indio_dev = pf->indio_dev;
702 struct ad4030_state *st = iio_priv(indio_dev);
703 int ret;
704
705 ret = ad4030_conversion(indio_dev);
706 if (ret)
707 goto out;
708
709 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_data.raw,
710 pf->timestamp);
711
712 out:
713 iio_trigger_notify_done(indio_dev->trig);
714
715 return IRQ_HANDLED;
716 }
717
718 static const int ad4030_gain_avail[3][2] = {
719 { 0, 0 },
720 { 0, 30518 },
721 { 1, 999969482 },
722 };
723
ad4030_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,const int ** vals,int * type,int * length,long mask)724 static int ad4030_read_avail(struct iio_dev *indio_dev,
725 struct iio_chan_spec const *channel,
726 const int **vals, int *type,
727 int *length, long mask)
728 {
729 struct ad4030_state *st = iio_priv(indio_dev);
730
731 switch (mask) {
732 case IIO_CHAN_INFO_CALIBBIAS:
733 *vals = st->offset_avail;
734 *type = IIO_VAL_INT;
735 return IIO_AVAIL_RANGE;
736
737 case IIO_CHAN_INFO_CALIBSCALE:
738 *vals = (void *)ad4030_gain_avail;
739 *type = IIO_VAL_INT_PLUS_NANO;
740 return IIO_AVAIL_RANGE;
741
742 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
743 *vals = ad4030_average_modes;
744 *type = IIO_VAL_INT;
745 *length = ARRAY_SIZE(ad4030_average_modes);
746 return IIO_AVAIL_LIST;
747
748 default:
749 return -EINVAL;
750 }
751 }
752
ad4030_read_raw_dispatch(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)753 static int ad4030_read_raw_dispatch(struct iio_dev *indio_dev,
754 struct iio_chan_spec const *chan, int *val,
755 int *val2, long info)
756 {
757 struct ad4030_state *st = iio_priv(indio_dev);
758
759 switch (info) {
760 case IIO_CHAN_INFO_RAW:
761 return ad4030_single_conversion(indio_dev, chan, val);
762
763 case IIO_CHAN_INFO_CALIBSCALE:
764 return ad4030_get_chan_calibscale(indio_dev, chan, val, val2);
765
766 case IIO_CHAN_INFO_CALIBBIAS:
767 return ad4030_get_chan_calibbias(indio_dev, chan, val);
768
769 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
770 *val = BIT(st->avg_log2);
771 return IIO_VAL_INT;
772
773 default:
774 return -EINVAL;
775 }
776 }
777
ad4030_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)778 static int ad4030_read_raw(struct iio_dev *indio_dev,
779 struct iio_chan_spec const *chan, int *val,
780 int *val2, long info)
781 {
782 int ret;
783
784 if (info == IIO_CHAN_INFO_SCALE)
785 return ad4030_get_chan_scale(indio_dev, chan, val, val2);
786
787 if (!iio_device_claim_direct(indio_dev))
788 return -EBUSY;
789
790 ret = ad4030_read_raw_dispatch(indio_dev, chan, val, val2, info);
791
792 iio_device_release_direct(indio_dev);
793
794 return ret;
795 }
796
ad4030_write_raw_dispatch(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)797 static int ad4030_write_raw_dispatch(struct iio_dev *indio_dev,
798 struct iio_chan_spec const *chan, int val,
799 int val2, long info)
800 {
801 switch (info) {
802 case IIO_CHAN_INFO_CALIBSCALE:
803 return ad4030_set_chan_calibscale(indio_dev, chan, val, val2);
804
805 case IIO_CHAN_INFO_CALIBBIAS:
806 if (val2 != 0)
807 return -EINVAL;
808 return ad4030_set_chan_calibbias(indio_dev, chan, val);
809
810 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
811 return ad4030_set_avg_frame_len(indio_dev, val);
812
813 default:
814 return -EINVAL;
815 }
816 }
817
ad4030_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)818 static int ad4030_write_raw(struct iio_dev *indio_dev,
819 struct iio_chan_spec const *chan, int val,
820 int val2, long info)
821 {
822 int ret;
823
824 if (!iio_device_claim_direct(indio_dev))
825 return -EBUSY;
826
827 ret = ad4030_write_raw_dispatch(indio_dev, chan, val, val2, info);
828
829 iio_device_release_direct(indio_dev);
830
831 return ret;
832 }
833
ad4030_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)834 static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg,
835 unsigned int writeval, unsigned int *readval)
836 {
837 const struct ad4030_state *st = iio_priv(indio_dev);
838 int ret;
839
840 if (!iio_device_claim_direct(indio_dev))
841 return -EBUSY;
842
843 if (readval)
844 ret = regmap_read(st->regmap, reg, readval);
845 else
846 ret = regmap_write(st->regmap, reg, writeval);
847
848 iio_device_release_direct(indio_dev);
849
850 return ret;
851 }
852
ad4030_read_label(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,char * label)853 static int ad4030_read_label(struct iio_dev *indio_dev,
854 struct iio_chan_spec const *chan,
855 char *label)
856 {
857 if (chan->differential)
858 return sprintf(label, "differential%lu\n", chan->address);
859 return sprintf(label, "common-mode%lu\n", chan->address);
860 }
861
ad4030_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)862 static int ad4030_get_current_scan_type(const struct iio_dev *indio_dev,
863 const struct iio_chan_spec *chan)
864 {
865 struct ad4030_state *st = iio_priv(indio_dev);
866
867 return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL;
868 }
869
870 static const struct iio_info ad4030_iio_info = {
871 .read_avail = ad4030_read_avail,
872 .read_raw = ad4030_read_raw,
873 .write_raw = ad4030_write_raw,
874 .debugfs_reg_access = ad4030_reg_access,
875 .read_label = ad4030_read_label,
876 .get_current_scan_type = ad4030_get_current_scan_type,
877 };
878
ad4030_buffer_preenable(struct iio_dev * indio_dev)879 static int ad4030_buffer_preenable(struct iio_dev *indio_dev)
880 {
881 return ad4030_set_mode(indio_dev, *indio_dev->active_scan_mask);
882 }
883
ad4030_validate_scan_mask(struct iio_dev * indio_dev,const unsigned long * scan_mask)884 static bool ad4030_validate_scan_mask(struct iio_dev *indio_dev,
885 const unsigned long *scan_mask)
886 {
887 struct ad4030_state *st = iio_priv(indio_dev);
888
889 /* Asking for both common channels and averaging */
890 if (st->avg_log2 && ad4030_is_common_byte_asked(st, *scan_mask))
891 return false;
892
893 return true;
894 }
895
896 static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops = {
897 .preenable = ad4030_buffer_preenable,
898 .validate_scan_mask = ad4030_validate_scan_mask,
899 };
900
ad4030_regulators_get(struct ad4030_state * st)901 static int ad4030_regulators_get(struct ad4030_state *st)
902 {
903 struct device *dev = &st->spi->dev;
904 static const char * const ids[] = { "vdd-5v", "vdd-1v8" };
905 int ret;
906
907 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ids), ids);
908 if (ret)
909 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
910
911 st->vio_uv = devm_regulator_get_enable_read_voltage(dev, "vio");
912 if (st->vio_uv < 0)
913 return dev_err_probe(dev, st->vio_uv,
914 "Failed to enable and read vio voltage\n");
915
916 st->vref_uv = devm_regulator_get_enable_read_voltage(dev, "ref");
917 if (st->vref_uv < 0) {
918 if (st->vref_uv != -ENODEV)
919 return dev_err_probe(dev, st->vref_uv,
920 "Failed to read ref voltage\n");
921
922 /* if not using optional REF, the REFIN must be used */
923 st->vref_uv = devm_regulator_get_enable_read_voltage(dev,
924 "refin");
925 if (st->vref_uv < 0)
926 return dev_err_probe(dev, st->vref_uv,
927 "Failed to read refin voltage\n");
928 }
929
930 return 0;
931 }
932
ad4030_reset(struct ad4030_state * st)933 static int ad4030_reset(struct ad4030_state *st)
934 {
935 struct device *dev = &st->spi->dev;
936 struct gpio_desc *reset;
937
938 reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
939 if (IS_ERR(reset))
940 return dev_err_probe(dev, PTR_ERR(reset),
941 "Failed to get reset GPIO\n");
942
943 if (reset) {
944 ndelay(50);
945 gpiod_set_value_cansleep(reset, 0);
946 return 0;
947 }
948
949 return regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A,
950 AD4030_REG_INTERFACE_CONFIG_A_SW_RESET);
951 }
952
ad4030_detect_chip_info(const struct ad4030_state * st)953 static int ad4030_detect_chip_info(const struct ad4030_state *st)
954 {
955 unsigned int grade;
956 int ret;
957
958 ret = regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade);
959 if (ret)
960 return ret;
961
962 grade = FIELD_GET(AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE, grade);
963 if (grade != st->chip->grade)
964 dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade,
965 st->chip->name);
966
967 return 0;
968 }
969
ad4030_config(struct ad4030_state * st)970 static int ad4030_config(struct ad4030_state *st)
971 {
972 int ret;
973 u8 reg_modes;
974
975 st->offset_avail[0] = (int)BIT(st->chip->precision_bits - 1) * -1;
976 st->offset_avail[1] = 1;
977 st->offset_avail[2] = BIT(st->chip->precision_bits - 1) - 1;
978
979 if (st->chip->num_voltage_inputs > 1)
980 reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE,
981 AD4030_LANE_MD_INTERLEAVED);
982 else
983 reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE,
984 AD4030_LANE_MD_1_PER_CH);
985
986 ret = regmap_write(st->regmap, AD4030_REG_MODES, reg_modes);
987 if (ret)
988 return ret;
989
990 if (st->vio_uv < AD4030_VIO_THRESHOLD_UV)
991 return regmap_write(st->regmap, AD4030_REG_IO,
992 AD4030_REG_IO_MASK_IO2X);
993
994 return 0;
995 }
996
ad4030_probe(struct spi_device * spi)997 static int ad4030_probe(struct spi_device *spi)
998 {
999 struct device *dev = &spi->dev;
1000 struct iio_dev *indio_dev;
1001 struct ad4030_state *st;
1002 int ret;
1003
1004 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1005 if (!indio_dev)
1006 return -ENOMEM;
1007
1008 st = iio_priv(indio_dev);
1009 st->spi = spi;
1010
1011 st->regmap = devm_regmap_init(dev, &ad4030_regmap_bus, st,
1012 &ad4030_regmap_config);
1013 if (IS_ERR(st->regmap))
1014 return dev_err_probe(dev, PTR_ERR(st->regmap),
1015 "Failed to initialize regmap\n");
1016
1017 st->chip = spi_get_device_match_data(spi);
1018 if (!st->chip)
1019 return -EINVAL;
1020
1021 ret = ad4030_regulators_get(st);
1022 if (ret)
1023 return ret;
1024
1025 /*
1026 * From datasheet: "Perform a reset no sooner than 3ms after the power
1027 * supplies are valid and stable"
1028 */
1029 fsleep(3000);
1030
1031 ret = ad4030_reset(st);
1032 if (ret)
1033 return ret;
1034
1035 ret = ad4030_detect_chip_info(st);
1036 if (ret)
1037 return ret;
1038
1039 ret = ad4030_config(st);
1040 if (ret)
1041 return ret;
1042
1043 st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW);
1044 if (IS_ERR(st->cnv_gpio))
1045 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio),
1046 "Failed to get cnv gpio\n");
1047
1048 /*
1049 * One hardware channel is split in two software channels when using
1050 * common byte mode. Add one more channel for the timestamp.
1051 */
1052 indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1;
1053 indio_dev->name = st->chip->name;
1054 indio_dev->modes = INDIO_DIRECT_MODE;
1055 indio_dev->info = &ad4030_iio_info;
1056 indio_dev->channels = st->chip->channels;
1057 indio_dev->available_scan_masks = st->chip->available_masks;
1058
1059 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1060 iio_pollfunc_store_time,
1061 ad4030_trigger_handler,
1062 &ad4030_buffer_setup_ops);
1063 if (ret)
1064 return dev_err_probe(dev, ret,
1065 "Failed to setup triggered buffer\n");
1066
1067 return devm_iio_device_register(dev, indio_dev);
1068 }
1069
1070 static const unsigned long ad4030_channel_masks[] = {
1071 /* Differential only */
1072 BIT(0),
1073 /* Differential and common-mode voltage */
1074 GENMASK(1, 0),
1075 0,
1076 };
1077
1078 static const unsigned long ad4630_channel_masks[] = {
1079 /* Differential only */
1080 BIT(1) | BIT(0),
1081 /* Differential with common byte */
1082 GENMASK(3, 0),
1083 0,
1084 };
1085
1086 static const struct iio_scan_type ad4030_24_scan_types[] = {
1087 [AD4030_SCAN_TYPE_NORMAL] = {
1088 .sign = 's',
1089 .storagebits = 32,
1090 .realbits = 24,
1091 .shift = 8,
1092 .endianness = IIO_BE,
1093 },
1094 [AD4030_SCAN_TYPE_AVG] = {
1095 .sign = 's',
1096 .storagebits = 32,
1097 .realbits = 30,
1098 .shift = 2,
1099 .endianness = IIO_BE,
1100 },
1101 };
1102
1103 static const struct iio_scan_type ad4030_16_scan_types[] = {
1104 [AD4030_SCAN_TYPE_NORMAL] = {
1105 .sign = 's',
1106 .storagebits = 32,
1107 .realbits = 16,
1108 .shift = 16,
1109 .endianness = IIO_BE,
1110 },
1111 [AD4030_SCAN_TYPE_AVG] = {
1112 .sign = 's',
1113 .storagebits = 32,
1114 .realbits = 30,
1115 .shift = 2,
1116 .endianness = IIO_BE,
1117 }
1118 };
1119
1120 static const struct ad4030_chip_info ad4030_24_chip_info = {
1121 .name = "ad4030-24",
1122 .available_masks = ad4030_channel_masks,
1123 .channels = {
1124 AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1125 AD4030_CHAN_CMO(1, 0),
1126 IIO_CHAN_SOFT_TIMESTAMP(2),
1127 },
1128 .grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE,
1129 .precision_bits = 24,
1130 .num_voltage_inputs = 1,
1131 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1132 };
1133
1134 static const struct ad4030_chip_info ad4630_16_chip_info = {
1135 .name = "ad4630-16",
1136 .available_masks = ad4630_channel_masks,
1137 .channels = {
1138 AD4030_CHAN_DIFF(0, ad4030_16_scan_types),
1139 AD4030_CHAN_DIFF(1, ad4030_16_scan_types),
1140 AD4030_CHAN_CMO(2, 0),
1141 AD4030_CHAN_CMO(3, 1),
1142 IIO_CHAN_SOFT_TIMESTAMP(4),
1143 },
1144 .grade = AD4030_REG_CHIP_GRADE_AD4630_16_GRADE,
1145 .precision_bits = 16,
1146 .num_voltage_inputs = 2,
1147 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1148 };
1149
1150 static const struct ad4030_chip_info ad4630_24_chip_info = {
1151 .name = "ad4630-24",
1152 .available_masks = ad4630_channel_masks,
1153 .channels = {
1154 AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1155 AD4030_CHAN_DIFF(1, ad4030_24_scan_types),
1156 AD4030_CHAN_CMO(2, 0),
1157 AD4030_CHAN_CMO(3, 1),
1158 IIO_CHAN_SOFT_TIMESTAMP(4),
1159 },
1160 .grade = AD4030_REG_CHIP_GRADE_AD4630_24_GRADE,
1161 .precision_bits = 24,
1162 .num_voltage_inputs = 2,
1163 .tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1164 };
1165
1166 static const struct ad4030_chip_info ad4632_16_chip_info = {
1167 .name = "ad4632-16",
1168 .available_masks = ad4630_channel_masks,
1169 .channels = {
1170 AD4030_CHAN_DIFF(0, ad4030_16_scan_types),
1171 AD4030_CHAN_DIFF(1, ad4030_16_scan_types),
1172 AD4030_CHAN_CMO(2, 0),
1173 AD4030_CHAN_CMO(3, 1),
1174 IIO_CHAN_SOFT_TIMESTAMP(4),
1175 },
1176 .grade = AD4030_REG_CHIP_GRADE_AD4632_16_GRADE,
1177 .precision_bits = 16,
1178 .num_voltage_inputs = 2,
1179 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS,
1180 };
1181
1182 static const struct ad4030_chip_info ad4632_24_chip_info = {
1183 .name = "ad4632-24",
1184 .available_masks = ad4630_channel_masks,
1185 .channels = {
1186 AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1187 AD4030_CHAN_DIFF(1, ad4030_24_scan_types),
1188 AD4030_CHAN_CMO(2, 0),
1189 AD4030_CHAN_CMO(3, 1),
1190 IIO_CHAN_SOFT_TIMESTAMP(4),
1191 },
1192 .grade = AD4030_REG_CHIP_GRADE_AD4632_24_GRADE,
1193 .precision_bits = 24,
1194 .num_voltage_inputs = 2,
1195 .tcyc_ns = AD4632_TCYC_ADJUSTED_NS,
1196 };
1197
1198 static const struct spi_device_id ad4030_id_table[] = {
1199 { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info },
1200 { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info },
1201 { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info },
1202 { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info },
1203 { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info },
1204 { }
1205 };
1206 MODULE_DEVICE_TABLE(spi, ad4030_id_table);
1207
1208 static const struct of_device_id ad4030_of_match[] = {
1209 { .compatible = "adi,ad4030-24", .data = &ad4030_24_chip_info },
1210 { .compatible = "adi,ad4630-16", .data = &ad4630_16_chip_info },
1211 { .compatible = "adi,ad4630-24", .data = &ad4630_24_chip_info },
1212 { .compatible = "adi,ad4632-16", .data = &ad4632_16_chip_info },
1213 { .compatible = "adi,ad4632-24", .data = &ad4632_24_chip_info },
1214 { }
1215 };
1216 MODULE_DEVICE_TABLE(of, ad4030_of_match);
1217
1218 static struct spi_driver ad4030_driver = {
1219 .driver = {
1220 .name = "ad4030",
1221 .of_match_table = ad4030_of_match,
1222 },
1223 .probe = ad4030_probe,
1224 .id_table = ad4030_id_table,
1225 };
1226 module_spi_driver(ad4030_driver);
1227
1228 MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");
1229 MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver");
1230 MODULE_LICENSE("GPL");
1231