1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2022 ROHM Semiconductors
4 *
5 * ROHM/KIONIX accelerometer driver
6 */
7
8 #include <linux/cleanup.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/mutex.h>
15 #include <linux/property.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <linux/string_choices.h>
20 #include <linux/types.h>
21 #include <linux/units.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/trigger_consumer.h>
27 #include <linux/iio/triggered_buffer.h>
28
29 #include "kionix-kx022a.h"
30
31 /*
32 * The KX022A has FIFO which can store 43 samples of HiRes data from 2
33 * channels. This equals to 43 (samples) * 3 (channels) * 2 (bytes/sample) to
34 * 258 bytes of sample data. The quirk to know is that the amount of bytes in
35 * the FIFO is advertised via 8 bit register (max value 255). The thing to note
36 * is that full 258 bytes of data is indicated using the max value 255.
37 */
38 #define KX022A_FIFO_LENGTH 43
39 #define KX022A_FIFO_FULL_VALUE 255
40 #define KX022A_SOFT_RESET_WAIT_TIME_US (5 * USEC_PER_MSEC)
41 #define KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US (500 * USEC_PER_MSEC)
42
43 /* 3 axis, 2 bytes of data for each of the axis */
44 #define KX022A_FIFO_SAMPLES_SIZE_BYTES 6
45 #define KX022A_FIFO_MAX_BYTES \
46 (KX022A_FIFO_LENGTH * KX022A_FIFO_SAMPLES_SIZE_BYTES)
47
48 enum {
49 KX022A_STATE_SAMPLE,
50 KX022A_STATE_FIFO,
51 };
52
53 /* kx022a Regmap configs */
54 static const struct regmap_range kx022a_volatile_ranges[] = {
55 {
56 .range_min = KX022A_REG_XHP_L,
57 .range_max = KX022A_REG_COTR,
58 }, {
59 .range_min = KX022A_REG_TSCP,
60 .range_max = KX022A_REG_INT_REL,
61 }, {
62 /* The reset bit will be cleared by sensor */
63 .range_min = KX022A_REG_CNTL2,
64 .range_max = KX022A_REG_CNTL2,
65 }, {
66 .range_min = KX022A_REG_BUF_STATUS_1,
67 .range_max = KX022A_REG_BUF_READ,
68 },
69 };
70
71 static const struct regmap_access_table kx022a_volatile_regs = {
72 .yes_ranges = &kx022a_volatile_ranges[0],
73 .n_yes_ranges = ARRAY_SIZE(kx022a_volatile_ranges),
74 };
75
76 static const struct regmap_range kx022a_precious_ranges[] = {
77 {
78 .range_min = KX022A_REG_INT_REL,
79 .range_max = KX022A_REG_INT_REL,
80 },
81 };
82
83 static const struct regmap_access_table kx022a_precious_regs = {
84 .yes_ranges = &kx022a_precious_ranges[0],
85 .n_yes_ranges = ARRAY_SIZE(kx022a_precious_ranges),
86 };
87
88 /*
89 * The HW does not set WHO_AM_I reg as read-only but we don't want to write it
90 * so we still include it in the read-only ranges.
91 */
92 static const struct regmap_range kx022a_read_only_ranges[] = {
93 {
94 .range_min = KX022A_REG_XHP_L,
95 .range_max = KX022A_REG_INT_REL,
96 }, {
97 .range_min = KX022A_REG_BUF_STATUS_1,
98 .range_max = KX022A_REG_BUF_STATUS_2,
99 }, {
100 .range_min = KX022A_REG_BUF_READ,
101 .range_max = KX022A_REG_BUF_READ,
102 },
103 };
104
105 static const struct regmap_access_table kx022a_ro_regs = {
106 .no_ranges = &kx022a_read_only_ranges[0],
107 .n_no_ranges = ARRAY_SIZE(kx022a_read_only_ranges),
108 };
109
110 static const struct regmap_range kx022a_write_only_ranges[] = {
111 {
112 .range_min = KX022A_REG_BTS_WUF_TH,
113 .range_max = KX022A_REG_BTS_WUF_TH,
114 }, {
115 .range_min = KX022A_REG_MAN_WAKE,
116 .range_max = KX022A_REG_MAN_WAKE,
117 }, {
118 .range_min = KX022A_REG_SELF_TEST,
119 .range_max = KX022A_REG_SELF_TEST,
120 }, {
121 .range_min = KX022A_REG_BUF_CLEAR,
122 .range_max = KX022A_REG_BUF_CLEAR,
123 },
124 };
125
126 static const struct regmap_access_table kx022a_wo_regs = {
127 .no_ranges = &kx022a_write_only_ranges[0],
128 .n_no_ranges = ARRAY_SIZE(kx022a_write_only_ranges),
129 };
130
131 static const struct regmap_range kx022a_noinc_read_ranges[] = {
132 {
133 .range_min = KX022A_REG_BUF_READ,
134 .range_max = KX022A_REG_BUF_READ,
135 },
136 };
137
138 static const struct regmap_access_table kx022a_nir_regs = {
139 .yes_ranges = &kx022a_noinc_read_ranges[0],
140 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges),
141 };
142
143 static const struct regmap_config kx022a_regmap_config = {
144 .reg_bits = 8,
145 .val_bits = 8,
146 .volatile_table = &kx022a_volatile_regs,
147 .rd_table = &kx022a_wo_regs,
148 .wr_table = &kx022a_ro_regs,
149 .rd_noinc_table = &kx022a_nir_regs,
150 .precious_table = &kx022a_precious_regs,
151 .max_register = KX022A_MAX_REGISTER,
152 .cache_type = REGCACHE_MAPLE,
153 };
154
155 /* Regmap configs kx132 */
156 static const struct regmap_range kx132_volatile_ranges[] = {
157 {
158 .range_min = KX132_REG_XADP_L,
159 .range_max = KX132_REG_COTR,
160 }, {
161 .range_min = KX132_REG_TSCP,
162 .range_max = KX132_REG_INT_REL,
163 }, {
164 /* The reset bit will be cleared by sensor */
165 .range_min = KX132_REG_CNTL2,
166 .range_max = KX132_REG_CNTL2,
167 }, {
168 .range_min = KX132_REG_CNTL5,
169 .range_max = KX132_REG_CNTL5,
170 }, {
171 .range_min = KX132_REG_BUF_STATUS_1,
172 .range_max = KX132_REG_BUF_READ,
173 },
174 };
175
176 static const struct regmap_access_table kx132_volatile_regs = {
177 .yes_ranges = &kx132_volatile_ranges[0],
178 .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges),
179 };
180
181 static const struct regmap_range kx132_precious_ranges[] = {
182 {
183 .range_min = KX132_REG_INT_REL,
184 .range_max = KX132_REG_INT_REL,
185 },
186 };
187
188 static const struct regmap_access_table kx132_precious_regs = {
189 .yes_ranges = &kx132_precious_ranges[0],
190 .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges),
191 };
192
193 static const struct regmap_range kx132_read_only_ranges[] = {
194 {
195 .range_min = KX132_REG_XADP_L,
196 .range_max = KX132_REG_INT_REL,
197 }, {
198 .range_min = KX132_REG_BUF_STATUS_1,
199 .range_max = KX132_REG_BUF_STATUS_2,
200 }, {
201 .range_min = KX132_REG_BUF_READ,
202 .range_max = KX132_REG_BUF_READ,
203 }, {
204 /* Kionix reserved registers: should not be written */
205 .range_min = 0x28,
206 .range_max = 0x28,
207 }, {
208 .range_min = 0x35,
209 .range_max = 0x36,
210 }, {
211 .range_min = 0x3c,
212 .range_max = 0x48,
213 }, {
214 .range_min = 0x4e,
215 .range_max = 0x5c,
216 }, {
217 .range_min = 0x77,
218 .range_max = 0x7f,
219 },
220 };
221
222 static const struct regmap_access_table kx132_ro_regs = {
223 .no_ranges = &kx132_read_only_ranges[0],
224 .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges),
225 };
226
227 static const struct regmap_range kx132_write_only_ranges[] = {
228 {
229 .range_min = KX132_REG_SELF_TEST,
230 .range_max = KX132_REG_SELF_TEST,
231 }, {
232 .range_min = KX132_REG_BUF_CLEAR,
233 .range_max = KX132_REG_BUF_CLEAR,
234 },
235 };
236
237 static const struct regmap_access_table kx132_wo_regs = {
238 .no_ranges = &kx132_write_only_ranges[0],
239 .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges),
240 };
241
242 static const struct regmap_range kx132_noinc_read_ranges[] = {
243 {
244 .range_min = KX132_REG_BUF_READ,
245 .range_max = KX132_REG_BUF_READ,
246 },
247 };
248
249 static const struct regmap_access_table kx132_nir_regs = {
250 .yes_ranges = &kx132_noinc_read_ranges[0],
251 .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges),
252 };
253
254 static const struct regmap_config kx132_regmap_config = {
255 .reg_bits = 8,
256 .val_bits = 8,
257 .volatile_table = &kx132_volatile_regs,
258 .rd_table = &kx132_wo_regs,
259 .wr_table = &kx132_ro_regs,
260 .rd_noinc_table = &kx132_nir_regs,
261 .precious_table = &kx132_precious_regs,
262 .max_register = KX132_MAX_REGISTER,
263 .cache_type = REGCACHE_MAPLE,
264 };
265
266 struct kx022a_data {
267 struct regmap *regmap;
268 const struct kx022a_chip_info *chip_info;
269 struct iio_trigger *trig;
270 struct device *dev;
271 struct iio_mount_matrix orientation;
272 int64_t timestamp, old_timestamp;
273
274 int irq;
275 int inc_reg;
276 int ien_reg;
277
278 unsigned int state;
279 unsigned int odr_ns;
280
281 bool trigger_enabled;
282 /*
283 * Prevent toggling the sensor stby/active state (PC1 bit) in the
284 * middle of a configuration, or when the fifo is enabled. Also,
285 * protect the data stored/retrieved from this structure from
286 * concurrent accesses.
287 */
288 struct mutex mutex;
289 u8 watermark;
290
291 __le16 *fifo_buffer;
292
293 /* 3 x 16bit accel data + timestamp */
294 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN);
295 struct {
296 __le16 channels[3];
297 aligned_s64 ts;
298 } scan;
299 };
300
301 static const struct iio_mount_matrix *
kx022a_get_mount_matrix(const struct iio_dev * idev,const struct iio_chan_spec * chan)302 kx022a_get_mount_matrix(const struct iio_dev *idev,
303 const struct iio_chan_spec *chan)
304 {
305 struct kx022a_data *data = iio_priv(idev);
306
307 return &data->orientation;
308 }
309
310 enum {
311 AXIS_X,
312 AXIS_Y,
313 AXIS_Z,
314 AXIS_MAX
315 };
316
317 static const unsigned long kx022a_scan_masks[] = {
318 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0
319 };
320
321 static const struct iio_chan_spec_ext_info kx022a_ext_info[] = {
322 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix),
323 { }
324 };
325
326 #define KX022A_ACCEL_CHAN(axis, reg, index) \
327 { \
328 .type = IIO_ACCEL, \
329 .modified = 1, \
330 .channel2 = IIO_MOD_##axis, \
331 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
332 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
333 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
334 .info_mask_shared_by_type_available = \
335 BIT(IIO_CHAN_INFO_SCALE) | \
336 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
337 .ext_info = kx022a_ext_info, \
338 .address = reg, \
339 .scan_index = index, \
340 .scan_type = { \
341 .sign = 's', \
342 .realbits = 16, \
343 .storagebits = 16, \
344 .endianness = IIO_LE, \
345 }, \
346 }
347
348 static const struct iio_chan_spec kx022a_channels[] = {
349 KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0),
350 KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1),
351 KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2),
352 IIO_CHAN_SOFT_TIMESTAMP(3),
353 };
354
355 static const struct iio_chan_spec kx132_channels[] = {
356 KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0),
357 KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1),
358 KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2),
359 IIO_CHAN_SOFT_TIMESTAMP(3),
360 };
361
362 /*
363 * The sensor HW can support ODR up to 1600 Hz, which is beyond what most of the
364 * Linux CPUs can handle without dropping samples. Also, the low power mode is
365 * not available for higher sample rates. Thus, the driver only supports 200 Hz
366 * and slower ODRs. The slowest is 0.78 Hz.
367 */
368 static const int kx022a_accel_samp_freq_table[][2] = {
369 { 0, 780000 },
370 { 1, 563000 },
371 { 3, 125000 },
372 { 6, 250000 },
373 { 12, 500000 },
374 { 25, 0 },
375 { 50, 0 },
376 { 100, 0 },
377 { 200, 0 },
378 };
379
380 static const unsigned int kx022a_odrs[] = {
381 1282051282,
382 639795266,
383 320 * MEGA,
384 160 * MEGA,
385 80 * MEGA,
386 40 * MEGA,
387 20 * MEGA,
388 10 * MEGA,
389 5 * MEGA,
390 };
391
392 /*
393 * range is typically +-2G/4G/8G/16G, distributed over the amount of bits.
394 * The scale table can be calculated using
395 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2
396 * => KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed
397 * in low-power mode(?) )
398 * => +/-2G => 4 / 2^16 * 9,80665
399 * => +/-2G - 0.000598550415
400 * +/-4G - 0.00119710083
401 * +/-8G - 0.00239420166
402 * +/-16G - 0.00478840332
403 */
404 static const int kx022a_scale_table[][2] = {
405 { 0, 598550 },
406 { 0, 1197101 },
407 { 0, 2394202 },
408 { 0, 4788403 },
409 };
410
411 /* KX134ACR-LBZ ranges are (+/-) 8, 16, 32, 64 G */
412 static const int kx134acr_lbz_scale_table[][2] = {
413 { 0, 2394202 },
414 { 0, 4788403 },
415 { 0, 9576807 },
416 { 0, 19153613 },
417 };
418
kx022a_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)419 static int kx022a_read_avail(struct iio_dev *indio_dev,
420 struct iio_chan_spec const *chan,
421 const int **vals, int *type, int *length,
422 long mask)
423 {
424 struct kx022a_data *data = iio_priv(indio_dev);
425
426 switch (mask) {
427 case IIO_CHAN_INFO_SAMP_FREQ:
428 *vals = (const int *)kx022a_accel_samp_freq_table;
429 *length = ARRAY_SIZE(kx022a_accel_samp_freq_table) *
430 ARRAY_SIZE(kx022a_accel_samp_freq_table[0]);
431 *type = IIO_VAL_INT_PLUS_MICRO;
432 return IIO_AVAIL_LIST;
433 case IIO_CHAN_INFO_SCALE:
434 *vals = (const int *)data->chip_info->scale_table;
435 *length = data->chip_info->scale_table_size;
436 *type = IIO_VAL_INT_PLUS_NANO;
437 return IIO_AVAIL_LIST;
438 default:
439 return -EINVAL;
440 }
441 }
442
443 #define KX022A_DEFAULT_PERIOD_NS (20 * NSEC_PER_MSEC)
444
kx022a_reg2freq(unsigned int val,int * val1,int * val2)445 static void kx022a_reg2freq(unsigned int val, int *val1, int *val2)
446 {
447 *val1 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][0];
448 *val2 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][1];
449 }
450
kx022a_reg2scale(struct kx022a_data * data,unsigned int val,unsigned int * val1,unsigned int * val2)451 static void kx022a_reg2scale(struct kx022a_data *data, unsigned int val,
452 unsigned int *val1, unsigned int *val2)
453 {
454 val &= KX022A_MASK_GSEL;
455 val >>= KX022A_GSEL_SHIFT;
456
457 *val1 = data->chip_info->scale_table[val][0];
458 *val2 = data->chip_info->scale_table[val][1];
459 }
460
__kx022a_turn_on_off(struct kx022a_data * data,bool on)461 static int __kx022a_turn_on_off(struct kx022a_data *data, bool on)
462 {
463 int ret;
464
465 if (on)
466 ret = regmap_set_bits(data->regmap, data->chip_info->cntl,
467 KX022A_MASK_PC1);
468 else
469 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl,
470 KX022A_MASK_PC1);
471 if (ret)
472 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret);
473
474 return ret;
475 }
476
kx022a_turn_off_lock(struct kx022a_data * data)477 static int kx022a_turn_off_lock(struct kx022a_data *data)
478 {
479 int ret;
480
481 mutex_lock(&data->mutex);
482 ret = __kx022a_turn_on_off(data, false);
483 if (ret)
484 mutex_unlock(&data->mutex);
485
486 return ret;
487 }
488
kx022a_turn_on_unlock(struct kx022a_data * data)489 static int kx022a_turn_on_unlock(struct kx022a_data *data)
490 {
491 int ret;
492
493 ret = __kx022a_turn_on_off(data, true);
494 mutex_unlock(&data->mutex);
495
496 return ret;
497 }
498
kx022a_write_raw_get_fmt(struct iio_dev * idev,struct iio_chan_spec const * chan,long mask)499 static int kx022a_write_raw_get_fmt(struct iio_dev *idev,
500 struct iio_chan_spec const *chan,
501 long mask)
502 {
503 switch (mask) {
504 case IIO_CHAN_INFO_SCALE:
505 return IIO_VAL_INT_PLUS_NANO;
506 case IIO_CHAN_INFO_SAMP_FREQ:
507 return IIO_VAL_INT_PLUS_MICRO;
508 default:
509 return -EINVAL;
510 }
511 }
512
__kx022a_write_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int val,int val2,long mask)513 static int __kx022a_write_raw(struct iio_dev *idev,
514 struct iio_chan_spec const *chan,
515 int val, int val2, long mask)
516 {
517 struct kx022a_data *data = iio_priv(idev);
518 int ret, n;
519
520 switch (mask) {
521 case IIO_CHAN_INFO_SAMP_FREQ:
522 n = ARRAY_SIZE(kx022a_accel_samp_freq_table);
523
524 while (n--)
525 if (val == kx022a_accel_samp_freq_table[n][0] &&
526 val2 == kx022a_accel_samp_freq_table[n][1])
527 break;
528 if (n < 0)
529 return -EINVAL;
530
531 ret = kx022a_turn_off_lock(data);
532 if (ret)
533 return ret;
534
535 ret = regmap_update_bits(data->regmap,
536 data->chip_info->odcntl,
537 KX022A_MASK_ODR, n);
538 data->odr_ns = kx022a_odrs[n];
539 kx022a_turn_on_unlock(data);
540 return ret;
541 case IIO_CHAN_INFO_SCALE:
542 n = data->chip_info->scale_table_size / 2;
543
544 while (n-- > 0)
545 if (val == data->chip_info->scale_table[n][0] &&
546 val2 == data->chip_info->scale_table[n][1])
547 break;
548 if (n < 0)
549 return -EINVAL;
550
551 ret = kx022a_turn_off_lock(data);
552 if (ret)
553 return ret;
554
555 ret = regmap_update_bits(data->regmap, data->chip_info->cntl,
556 KX022A_MASK_GSEL,
557 n << KX022A_GSEL_SHIFT);
558 kx022a_turn_on_unlock(data);
559 return ret;
560 default:
561 return -EINVAL;
562 }
563 }
564
kx022a_write_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int val,int val2,long mask)565 static int kx022a_write_raw(struct iio_dev *idev,
566 struct iio_chan_spec const *chan,
567 int val, int val2, long mask)
568 {
569 int ret;
570
571 /*
572 * We should not allow changing scale or frequency when FIFO is running
573 * as it will mess the timestamp/scale for samples existing in the
574 * buffer. If this turns out to be an issue we can later change logic
575 * to internally flush the fifo before reconfiguring so the samples in
576 * fifo keep matching the freq/scale settings. (Such setup could cause
577 * issues if users trust the watermark to be reached within known
578 * time-limit).
579 */
580 if (!iio_device_claim_direct(idev))
581 return -EBUSY;
582
583 ret = __kx022a_write_raw(idev, chan, val, val2, mask);
584
585 iio_device_release_direct(idev);
586
587 return ret;
588 }
589
kx022a_fifo_set_wmi(struct kx022a_data * data)590 static int kx022a_fifo_set_wmi(struct kx022a_data *data)
591 {
592 u8 threshold;
593
594 threshold = data->watermark;
595
596 return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1,
597 KX022A_MASK_WM_TH, threshold);
598 }
599
kx022a_get_axis(struct kx022a_data * data,struct iio_chan_spec const * chan,int * val)600 static int kx022a_get_axis(struct kx022a_data *data,
601 struct iio_chan_spec const *chan,
602 int *val)
603 {
604 int ret;
605
606 ret = regmap_bulk_read(data->regmap, chan->address, &data->buffer[0],
607 sizeof(__le16));
608 if (ret)
609 return ret;
610
611 *val = (s16)le16_to_cpu(data->buffer[0]);
612
613 return IIO_VAL_INT;
614 }
615
kx022a_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)616 static int kx022a_read_raw(struct iio_dev *idev,
617 struct iio_chan_spec const *chan,
618 int *val, int *val2, long mask)
619 {
620 struct kx022a_data *data = iio_priv(idev);
621 unsigned int regval;
622 int ret;
623
624 switch (mask) {
625 case IIO_CHAN_INFO_RAW:
626 if (!iio_device_claim_direct(idev))
627 return -EBUSY;
628
629 mutex_lock(&data->mutex);
630 ret = kx022a_get_axis(data, chan, val);
631 mutex_unlock(&data->mutex);
632
633 iio_device_release_direct(idev);
634
635 return ret;
636
637 case IIO_CHAN_INFO_SAMP_FREQ:
638 ret = regmap_read(data->regmap, data->chip_info->odcntl, ®val);
639 if (ret)
640 return ret;
641
642 if ((regval & KX022A_MASK_ODR) >
643 ARRAY_SIZE(kx022a_accel_samp_freq_table)) {
644 dev_err(data->dev, "Invalid ODR\n");
645 return -EINVAL;
646 }
647
648 kx022a_reg2freq(regval, val, val2);
649
650 return IIO_VAL_INT_PLUS_MICRO;
651
652 case IIO_CHAN_INFO_SCALE:
653 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val);
654 if (ret < 0)
655 return ret;
656
657 kx022a_reg2scale(data, regval, val, val2);
658
659 return IIO_VAL_INT_PLUS_NANO;
660 }
661
662 return -EINVAL;
663 };
664
kx022a_set_watermark(struct iio_dev * idev,unsigned int val)665 static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val)
666 {
667 struct kx022a_data *data = iio_priv(idev);
668
669 val = min(data->chip_info->fifo_length, val);
670
671 mutex_lock(&data->mutex);
672 data->watermark = val;
673 mutex_unlock(&data->mutex);
674
675 return 0;
676 }
677
hwfifo_enabled_show(struct device * dev,struct device_attribute * attr,char * buf)678 static ssize_t hwfifo_enabled_show(struct device *dev,
679 struct device_attribute *attr,
680 char *buf)
681 {
682 struct iio_dev *idev = dev_to_iio_dev(dev);
683 struct kx022a_data *data = iio_priv(idev);
684 bool state;
685
686 mutex_lock(&data->mutex);
687 state = data->state;
688 mutex_unlock(&data->mutex);
689
690 return sysfs_emit(buf, "%d\n", state);
691 }
692
hwfifo_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)693 static ssize_t hwfifo_watermark_show(struct device *dev,
694 struct device_attribute *attr,
695 char *buf)
696 {
697 struct iio_dev *idev = dev_to_iio_dev(dev);
698 struct kx022a_data *data = iio_priv(idev);
699 int wm;
700
701 mutex_lock(&data->mutex);
702 wm = data->watermark;
703 mutex_unlock(&data->mutex);
704
705 return sysfs_emit(buf, "%d\n", wm);
706 }
707
708 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
709 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
710
711 static const struct iio_dev_attr *kx022a_fifo_attributes[] = {
712 &iio_dev_attr_hwfifo_watermark,
713 &iio_dev_attr_hwfifo_enabled,
714 NULL
715 };
716
kx022a_drop_fifo_contents(struct kx022a_data * data)717 static int kx022a_drop_fifo_contents(struct kx022a_data *data)
718 {
719 /*
720 * We must clear the old time-stamp to avoid computing the timestamps
721 * based on samples acquired when buffer was last enabled.
722 *
723 * We don't need to protect the timestamp as long as we are only
724 * called from fifo-disable where we can guarantee the sensor is not
725 * triggering interrupts and where the mutex is locked to prevent the
726 * user-space access.
727 */
728 data->timestamp = 0;
729
730 return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0);
731 }
732
kx022a_get_fifo_bytes_available(struct kx022a_data * data)733 static int kx022a_get_fifo_bytes_available(struct kx022a_data *data)
734 {
735 int ret, fifo_bytes;
736
737 ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes);
738 if (ret) {
739 dev_err(data->dev, "Error reading buffer status\n");
740 return ret;
741 }
742
743 if (fifo_bytes == KX022A_FIFO_FULL_VALUE)
744 return KX022A_FIFO_MAX_BYTES;
745
746 return fifo_bytes;
747 }
748
kx132_get_fifo_bytes_available(struct kx022a_data * data)749 static int kx132_get_fifo_bytes_available(struct kx022a_data *data)
750 {
751 __le16 buf_status;
752 int ret, fifo_bytes;
753
754 ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1,
755 &buf_status, sizeof(buf_status));
756 if (ret) {
757 dev_err(data->dev, "Error reading buffer status\n");
758 return ret;
759 }
760
761 fifo_bytes = le16_to_cpu(buf_status);
762 fifo_bytes &= data->chip_info->buf_smp_lvl_mask;
763 fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length *
764 KX022A_FIFO_SAMPLES_SIZE_BYTES);
765
766 return fifo_bytes;
767 }
768
__kx022a_fifo_flush(struct iio_dev * idev,unsigned int samples,bool irq)769 static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples,
770 bool irq)
771 {
772 struct kx022a_data *data = iio_priv(idev);
773 uint64_t sample_period;
774 int count, fifo_bytes;
775 bool renable = false;
776 int64_t tstamp;
777 int ret, i;
778
779 fifo_bytes = data->chip_info->get_fifo_bytes_available(data);
780
781 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES)
782 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n");
783
784 count = fifo_bytes / KX022A_FIFO_SAMPLES_SIZE_BYTES;
785 if (!count)
786 return 0;
787
788 /*
789 * If we are being called from IRQ handler we know the stored timestamp
790 * is fairly accurate for the last stored sample. Otherwise, if we are
791 * called as a result of a read operation from userspace and hence
792 * before the watermark interrupt was triggered, take a timestamp
793 * now. We can fall anywhere in between two samples so the error in this
794 * case is at most one sample period.
795 */
796 if (!irq) {
797 /*
798 * We need to have the IRQ disabled or we risk of messing-up
799 * the timestamps. If we are ran from IRQ, then the
800 * IRQF_ONESHOT has us covered - but if we are ran by the
801 * user-space read we need to disable the IRQ to be on a safe
802 * side. We do this usng synchronous disable so that if the
803 * IRQ thread is being ran on other CPU we wait for it to be
804 * finished.
805 */
806 disable_irq(data->irq);
807 renable = true;
808
809 data->old_timestamp = data->timestamp;
810 data->timestamp = iio_get_time_ns(idev);
811 }
812
813 /*
814 * Approximate timestamps for each of the sample based on the sampling
815 * frequency, timestamp for last sample and number of samples.
816 *
817 * We'd better not use the current bandwidth settings to compute the
818 * sample period. The real sample rate varies with the device and
819 * small variation adds when we store a large number of samples.
820 *
821 * To avoid this issue we compute the actual sample period ourselves
822 * based on the timestamp delta between the last two flush operations.
823 */
824 if (data->old_timestamp) {
825 sample_period = data->timestamp - data->old_timestamp;
826 do_div(sample_period, count);
827 } else {
828 sample_period = data->odr_ns;
829 }
830 tstamp = data->timestamp - (count - 1) * sample_period;
831
832 if (samples && count > samples) {
833 /*
834 * Here we leave some old samples to the buffer. We need to
835 * adjust the timestamp to match the first sample in the buffer
836 * or we will miscalculate the sample_period at next round.
837 */
838 data->timestamp -= (count - samples) * sample_period;
839 count = samples;
840 }
841
842 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES;
843 ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read,
844 data->fifo_buffer, fifo_bytes);
845 if (ret)
846 goto renable_out;
847
848 for (i = 0; i < count; i++) {
849 __le16 *sam = &data->fifo_buffer[i * 3];
850 __le16 *chs;
851 int bit;
852
853 chs = &data->scan.channels[0];
854 for_each_set_bit(bit, idev->active_scan_mask, AXIS_MAX)
855 chs[bit] = sam[bit];
856
857 iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp);
858
859 tstamp += sample_period;
860 }
861
862 ret = count;
863
864 renable_out:
865 if (renable)
866 enable_irq(data->irq);
867
868 return ret;
869 }
870
kx022a_fifo_flush(struct iio_dev * idev,unsigned int samples)871 static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples)
872 {
873 struct kx022a_data *data = iio_priv(idev);
874 int ret;
875
876 mutex_lock(&data->mutex);
877 ret = __kx022a_fifo_flush(idev, samples, false);
878 mutex_unlock(&data->mutex);
879
880 return ret;
881 }
882
883 static const struct iio_info kx022a_info = {
884 .read_raw = &kx022a_read_raw,
885 .write_raw = &kx022a_write_raw,
886 .write_raw_get_fmt = &kx022a_write_raw_get_fmt,
887 .read_avail = &kx022a_read_avail,
888
889 .validate_trigger = iio_validate_own_trigger,
890 .hwfifo_set_watermark = kx022a_set_watermark,
891 .hwfifo_flush_to_buffer = kx022a_fifo_flush,
892 };
893
kx022a_set_drdy_irq(struct kx022a_data * data,bool en)894 static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en)
895 {
896 if (en)
897 return regmap_set_bits(data->regmap, data->chip_info->cntl,
898 KX022A_MASK_DRDY);
899
900 return regmap_clear_bits(data->regmap, data->chip_info->cntl,
901 KX022A_MASK_DRDY);
902 }
903
kx022a_prepare_irq_pin(struct kx022a_data * data)904 static int kx022a_prepare_irq_pin(struct kx022a_data *data)
905 {
906 /* Enable IRQ1 pin. Set polarity to active low */
907 int mask = KX022A_MASK_IEN | KX022A_MASK_IPOL |
908 KX022A_MASK_ITYP;
909 int val = KX022A_MASK_IEN | KX022A_IPOL_LOW |
910 KX022A_ITYP_LEVEL;
911 int ret;
912
913 ret = regmap_update_bits(data->regmap, data->inc_reg, mask, val);
914 if (ret)
915 return ret;
916
917 /* We enable WMI to IRQ pin only at buffer_enable */
918 mask = KX022A_MASK_INS2_DRDY;
919
920 return regmap_set_bits(data->regmap, data->ien_reg, mask);
921 }
922
kx022a_fifo_disable(struct kx022a_data * data)923 static int kx022a_fifo_disable(struct kx022a_data *data)
924 {
925 int ret = 0;
926
927 guard(mutex)(&data->mutex);
928 ret = __kx022a_turn_on_off(data, false);
929 if (ret)
930 return ret;
931
932 ret = regmap_clear_bits(data->regmap, data->ien_reg, KX022A_MASK_WMI);
933 if (ret)
934 return ret;
935
936 ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2,
937 KX022A_MASK_BUF_EN);
938 if (ret)
939 return ret;
940
941 data->state &= ~KX022A_STATE_FIFO;
942
943 kx022a_drop_fifo_contents(data);
944
945 kfree(data->fifo_buffer);
946
947 return __kx022a_turn_on_off(data, true);
948 }
949
kx022a_buffer_predisable(struct iio_dev * idev)950 static int kx022a_buffer_predisable(struct iio_dev *idev)
951 {
952 struct kx022a_data *data = iio_priv(idev);
953
954 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)
955 return 0;
956
957 return kx022a_fifo_disable(data);
958 }
959
kx022a_fifo_enable(struct kx022a_data * data)960 static int kx022a_fifo_enable(struct kx022a_data *data)
961 {
962 int ret;
963
964 data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length,
965 KX022A_FIFO_SAMPLES_SIZE_BYTES,
966 GFP_KERNEL);
967 if (!data->fifo_buffer)
968 return -ENOMEM;
969
970 guard(mutex)(&data->mutex);
971 ret = __kx022a_turn_on_off(data, false);
972 if (ret)
973 return ret;
974
975 /* Update watermark to HW */
976 ret = kx022a_fifo_set_wmi(data);
977 if (ret)
978 return ret;
979
980 /* Enable buffer */
981 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,
982 KX022A_MASK_BUF_EN);
983 if (ret)
984 return ret;
985
986 data->state |= KX022A_STATE_FIFO;
987 ret = regmap_set_bits(data->regmap, data->ien_reg,
988 KX022A_MASK_WMI);
989 if (ret)
990 return ret;
991
992 return __kx022a_turn_on_off(data, true);
993 }
994
kx022a_buffer_postenable(struct iio_dev * idev)995 static int kx022a_buffer_postenable(struct iio_dev *idev)
996 {
997 struct kx022a_data *data = iio_priv(idev);
998
999 /*
1000 * If we use data-ready trigger, then the IRQ masks should be handled by
1001 * trigger enable and the hardware buffer is not used but we just update
1002 * results to the IIO fifo when data-ready triggers.
1003 */
1004 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)
1005 return 0;
1006
1007 return kx022a_fifo_enable(data);
1008 }
1009
1010 static const struct iio_buffer_setup_ops kx022a_buffer_ops = {
1011 .postenable = kx022a_buffer_postenable,
1012 .predisable = kx022a_buffer_predisable,
1013 };
1014
kx022a_trigger_handler(int irq,void * p)1015 static irqreturn_t kx022a_trigger_handler(int irq, void *p)
1016 {
1017 struct iio_poll_func *pf = p;
1018 struct iio_dev *idev = pf->indio_dev;
1019 struct kx022a_data *data = iio_priv(idev);
1020 int ret;
1021
1022 ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer,
1023 KX022A_FIFO_SAMPLES_SIZE_BYTES);
1024 if (ret < 0)
1025 goto err_read;
1026
1027 iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp);
1028 err_read:
1029 iio_trigger_notify_done(idev->trig);
1030
1031 return IRQ_HANDLED;
1032 }
1033
1034 /* Get timestamps and wake the thread if we need to read data */
kx022a_irq_handler(int irq,void * private)1035 static irqreturn_t kx022a_irq_handler(int irq, void *private)
1036 {
1037 struct iio_dev *idev = private;
1038 struct kx022a_data *data = iio_priv(idev);
1039
1040 data->old_timestamp = data->timestamp;
1041 data->timestamp = iio_get_time_ns(idev);
1042
1043 if (data->state & KX022A_STATE_FIFO || data->trigger_enabled)
1044 return IRQ_WAKE_THREAD;
1045
1046 return IRQ_NONE;
1047 }
1048
1049 /*
1050 * WMI and data-ready IRQs are acked when results are read. If we add
1051 * TILT/WAKE or other IRQs - then we may need to implement the acking
1052 * (which is racy).
1053 */
kx022a_irq_thread_handler(int irq,void * private)1054 static irqreturn_t kx022a_irq_thread_handler(int irq, void *private)
1055 {
1056 struct iio_dev *idev = private;
1057 struct kx022a_data *data = iio_priv(idev);
1058 irqreturn_t ret = IRQ_NONE;
1059
1060 guard(mutex)(&data->mutex);
1061
1062 if (data->trigger_enabled) {
1063 iio_trigger_poll_nested(data->trig);
1064 ret = IRQ_HANDLED;
1065 }
1066
1067 if (data->state & KX022A_STATE_FIFO) {
1068 int ok;
1069
1070 ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true);
1071 if (ok > 0)
1072 ret = IRQ_HANDLED;
1073 }
1074
1075 return ret;
1076 }
1077
kx022a_trigger_set_state(struct iio_trigger * trig,bool state)1078 static int kx022a_trigger_set_state(struct iio_trigger *trig,
1079 bool state)
1080 {
1081 struct kx022a_data *data = iio_trigger_get_drvdata(trig);
1082 int ret = 0;
1083
1084 guard(mutex)(&data->mutex);
1085
1086 if (data->trigger_enabled == state)
1087 return 0;
1088
1089 if (data->state & KX022A_STATE_FIFO) {
1090 dev_warn(data->dev, "Can't set trigger when FIFO enabled\n");
1091 return -EBUSY;
1092 }
1093
1094 ret = __kx022a_turn_on_off(data, false);
1095 if (ret)
1096 return ret;
1097
1098 data->trigger_enabled = state;
1099 ret = kx022a_set_drdy_irq(data, state);
1100 if (ret)
1101 return ret;
1102
1103 return __kx022a_turn_on_off(data, true);
1104 }
1105
1106 static const struct iio_trigger_ops kx022a_trigger_ops = {
1107 .set_trigger_state = kx022a_trigger_set_state,
1108 };
1109
kx022a_chip_init(struct kx022a_data * data)1110 static int kx022a_chip_init(struct kx022a_data *data)
1111 {
1112 int ret, val;
1113
1114 /* Reset the senor */
1115 ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST);
1116 if (ret)
1117 return ret;
1118
1119 /*
1120 * According to the power-on procedure documents, there is (at least)
1121 * 2ms delay required after the software reset. This should be same for
1122 * all, KX022ACR-Z, KX132-1211, KX132ACR-LBZ and KX134ACR-LBZ.
1123 *
1124 * https://fscdn.rohm.com/kionix/en/document/AN010_KX022ACR-Z_Power-on_Procedure_E.pdf
1125 * https://fscdn.rohm.com/kionix/en/document/TN027-Power-On-Procedure.pdf
1126 * https://fscdn.rohm.com/kionix/en/document/AN011_KX134ACR-LBZ_Power-on_Procedure_E.pdf
1127 */
1128 msleep(2);
1129
1130 ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val,
1131 !(val & KX022A_MASK_SRST),
1132 KX022A_SOFT_RESET_WAIT_TIME_US,
1133 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US);
1134 if (ret) {
1135 dev_err(data->dev, "Sensor reset %s\n",
1136 val & KX022A_MASK_SRST ? "timeout" : "fail#");
1137 return ret;
1138 }
1139
1140 ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config);
1141 if (ret) {
1142 dev_err(data->dev, "Failed to reinit reg cache\n");
1143 return ret;
1144 }
1145
1146 /* set data res 16bit */
1147 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,
1148 KX022A_MASK_BRES16);
1149 if (ret) {
1150 dev_err(data->dev, "Failed to set data resolution\n");
1151 return ret;
1152 }
1153
1154 return kx022a_prepare_irq_pin(data);
1155 }
1156
1157 const struct kx022a_chip_info kx022a_chip_info = {
1158 .name = "kx022-accel",
1159 .regmap_config = &kx022a_regmap_config,
1160 .channels = kx022a_channels,
1161 .num_channels = ARRAY_SIZE(kx022a_channels),
1162 .scale_table = kx022a_scale_table,
1163 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1164 ARRAY_SIZE(kx022a_scale_table[0]),
1165 .fifo_length = KX022A_FIFO_LENGTH,
1166 .who = KX022A_REG_WHO,
1167 .id = KX022A_ID,
1168 .cntl = KX022A_REG_CNTL,
1169 .cntl2 = KX022A_REG_CNTL2,
1170 .odcntl = KX022A_REG_ODCNTL,
1171 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1172 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1173 .buf_clear = KX022A_REG_BUF_CLEAR,
1174 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1175 .buf_read = KX022A_REG_BUF_READ,
1176 .inc1 = KX022A_REG_INC1,
1177 .inc4 = KX022A_REG_INC4,
1178 .inc5 = KX022A_REG_INC5,
1179 .inc6 = KX022A_REG_INC6,
1180 .xout_l = KX022A_REG_XOUT_L,
1181 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1182 };
1183 EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, "IIO_KX022A");
1184
1185 const struct kx022a_chip_info kx132_chip_info = {
1186 .name = "kx132-1211",
1187 .regmap_config = &kx132_regmap_config,
1188 .channels = kx132_channels,
1189 .num_channels = ARRAY_SIZE(kx132_channels),
1190 .scale_table = kx022a_scale_table,
1191 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1192 ARRAY_SIZE(kx022a_scale_table[0]),
1193 .fifo_length = KX132_FIFO_LENGTH,
1194 .who = KX132_REG_WHO,
1195 .id = KX132_ID,
1196 .cntl = KX132_REG_CNTL,
1197 .cntl2 = KX132_REG_CNTL2,
1198 .odcntl = KX132_REG_ODCNTL,
1199 .buf_cntl1 = KX132_REG_BUF_CNTL1,
1200 .buf_cntl2 = KX132_REG_BUF_CNTL2,
1201 .buf_clear = KX132_REG_BUF_CLEAR,
1202 .buf_status1 = KX132_REG_BUF_STATUS_1,
1203 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL,
1204 .buf_read = KX132_REG_BUF_READ,
1205 .inc1 = KX132_REG_INC1,
1206 .inc4 = KX132_REG_INC4,
1207 .inc5 = KX132_REG_INC5,
1208 .inc6 = KX132_REG_INC6,
1209 .xout_l = KX132_REG_XOUT_L,
1210 .get_fifo_bytes_available = kx132_get_fifo_bytes_available,
1211 };
1212 EXPORT_SYMBOL_NS_GPL(kx132_chip_info, "IIO_KX022A");
1213
1214 const struct kx022a_chip_info kx134_chip_info = {
1215 .name = "kx134-1211",
1216 .regmap_config = &kx132_regmap_config,
1217 .channels = kx132_channels,
1218 .num_channels = ARRAY_SIZE(kx132_channels),
1219 .scale_table = kx134acr_lbz_scale_table,
1220 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) *
1221 ARRAY_SIZE(kx134acr_lbz_scale_table[0]),
1222 .fifo_length = KX132_FIFO_LENGTH,
1223 .who = KX132_REG_WHO,
1224 .id = KX134_1211_ID,
1225 .cntl = KX132_REG_CNTL,
1226 .cntl2 = KX132_REG_CNTL2,
1227 .odcntl = KX132_REG_ODCNTL,
1228 .buf_cntl1 = KX132_REG_BUF_CNTL1,
1229 .buf_cntl2 = KX132_REG_BUF_CNTL2,
1230 .buf_clear = KX132_REG_BUF_CLEAR,
1231 .buf_status1 = KX132_REG_BUF_STATUS_1,
1232 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL,
1233 .buf_read = KX132_REG_BUF_READ,
1234 .inc1 = KX132_REG_INC1,
1235 .inc4 = KX132_REG_INC4,
1236 .inc5 = KX132_REG_INC5,
1237 .inc6 = KX132_REG_INC6,
1238 .xout_l = KX132_REG_XOUT_L,
1239 .get_fifo_bytes_available = kx132_get_fifo_bytes_available,
1240 };
1241 EXPORT_SYMBOL_NS_GPL(kx134_chip_info, "IIO_KX022A");
1242
1243 /*
1244 * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is
1245 * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial
1246 * applications and the tap/double tap, free fall and tilt engines were
1247 * removed. Rest of the registers and functionalities (excluding the ID
1248 * register) are exact match to what is found in KX022.
1249 */
1250 const struct kx022a_chip_info kx132acr_chip_info = {
1251 .name = "kx132acr-lbz",
1252 .regmap_config = &kx022a_regmap_config,
1253 .channels = kx022a_channels,
1254 .num_channels = ARRAY_SIZE(kx022a_channels),
1255 .scale_table = kx022a_scale_table,
1256 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1257 ARRAY_SIZE(kx022a_scale_table[0]),
1258 .fifo_length = KX022A_FIFO_LENGTH,
1259 .who = KX022A_REG_WHO,
1260 .id = KX132ACR_LBZ_ID,
1261 .cntl = KX022A_REG_CNTL,
1262 .cntl2 = KX022A_REG_CNTL2,
1263 .odcntl = KX022A_REG_ODCNTL,
1264 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1265 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1266 .buf_clear = KX022A_REG_BUF_CLEAR,
1267 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1268 .buf_read = KX022A_REG_BUF_READ,
1269 .inc1 = KX022A_REG_INC1,
1270 .inc4 = KX022A_REG_INC4,
1271 .inc5 = KX022A_REG_INC5,
1272 .inc6 = KX022A_REG_INC6,
1273 .xout_l = KX022A_REG_XOUT_L,
1274 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1275 };
1276 EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, "IIO_KX022A");
1277
1278 const struct kx022a_chip_info kx134acr_chip_info = {
1279 .name = "kx134acr-lbz",
1280 .regmap_config = &kx022a_regmap_config,
1281 .channels = kx022a_channels,
1282 .num_channels = ARRAY_SIZE(kx022a_channels),
1283 .scale_table = kx134acr_lbz_scale_table,
1284 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) *
1285 ARRAY_SIZE(kx134acr_lbz_scale_table[0]),
1286 .fifo_length = KX022A_FIFO_LENGTH,
1287 .who = KX022A_REG_WHO,
1288 .id = KX134ACR_LBZ_ID,
1289 .cntl = KX022A_REG_CNTL,
1290 .cntl2 = KX022A_REG_CNTL2,
1291 .odcntl = KX022A_REG_ODCNTL,
1292 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1293 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1294 .buf_clear = KX022A_REG_BUF_CLEAR,
1295 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1296 .buf_read = KX022A_REG_BUF_READ,
1297 .inc1 = KX022A_REG_INC1,
1298 .inc4 = KX022A_REG_INC4,
1299 .inc5 = KX022A_REG_INC5,
1300 .inc6 = KX022A_REG_INC6,
1301 .xout_l = KX022A_REG_XOUT_L,
1302 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1303 };
1304 EXPORT_SYMBOL_NS_GPL(kx134acr_chip_info, "IIO_KX022A");
1305
kx022a_probe_internal(struct device * dev,const struct kx022a_chip_info * chip_info)1306 int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info)
1307 {
1308 static const char * const regulator_names[] = {"io-vdd", "vdd"};
1309 struct iio_trigger *indio_trig;
1310 struct fwnode_handle *fwnode;
1311 struct kx022a_data *data;
1312 struct regmap *regmap;
1313 unsigned int chip_id;
1314 struct iio_dev *idev;
1315 int ret, irq;
1316 char *name;
1317
1318 regmap = dev_get_regmap(dev, NULL);
1319 if (!regmap) {
1320 dev_err(dev, "no regmap\n");
1321 return -EINVAL;
1322 }
1323
1324 fwnode = dev_fwnode(dev);
1325 if (!fwnode)
1326 return -ENODEV;
1327
1328 idev = devm_iio_device_alloc(dev, sizeof(*data));
1329 if (!idev)
1330 return -ENOMEM;
1331
1332 data = iio_priv(idev);
1333 data->chip_info = chip_info;
1334
1335 /*
1336 * VDD is the analog and digital domain voltage supply and
1337 * IO_VDD is the digital I/O voltage supply.
1338 */
1339 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
1340 regulator_names);
1341 if (ret && ret != -ENODEV)
1342 return dev_err_probe(dev, ret, "failed to enable regulator\n");
1343
1344 ret = regmap_read(regmap, chip_info->who, &chip_id);
1345 if (ret)
1346 return dev_err_probe(dev, ret, "Failed to access sensor\n");
1347
1348 if (chip_id != chip_info->id)
1349 dev_warn(dev, "unknown device 0x%x\n", chip_id);
1350
1351 irq = fwnode_irq_get_byname(fwnode, "INT1");
1352 if (irq > 0) {
1353 data->inc_reg = chip_info->inc1;
1354 data->ien_reg = chip_info->inc4;
1355 } else {
1356 irq = fwnode_irq_get_byname(fwnode, "INT2");
1357 if (irq < 0)
1358 return dev_err_probe(dev, irq, "No suitable IRQ\n");
1359
1360 data->inc_reg = chip_info->inc5;
1361 data->ien_reg = chip_info->inc6;
1362 }
1363
1364 data->regmap = regmap;
1365 data->dev = dev;
1366 data->irq = irq;
1367 data->odr_ns = KX022A_DEFAULT_PERIOD_NS;
1368 mutex_init(&data->mutex);
1369
1370 idev->channels = chip_info->channels;
1371 idev->num_channels = chip_info->num_channels;
1372 idev->name = chip_info->name;
1373 idev->info = &kx022a_info;
1374 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1375 idev->available_scan_masks = kx022a_scan_masks;
1376
1377 /* Read the mounting matrix, if present */
1378 ret = iio_read_mount_matrix(dev, &data->orientation);
1379 if (ret)
1380 return ret;
1381
1382 /* The sensor must be turned off for configuration */
1383 ret = kx022a_turn_off_lock(data);
1384 if (ret)
1385 return ret;
1386
1387 ret = kx022a_chip_init(data);
1388 if (ret) {
1389 mutex_unlock(&data->mutex);
1390 return ret;
1391 }
1392
1393 ret = kx022a_turn_on_unlock(data);
1394 if (ret)
1395 return ret;
1396
1397 ret = devm_iio_triggered_buffer_setup_ext(dev, idev,
1398 &iio_pollfunc_store_time,
1399 kx022a_trigger_handler,
1400 IIO_BUFFER_DIRECTION_IN,
1401 &kx022a_buffer_ops,
1402 kx022a_fifo_attributes);
1403
1404 if (ret)
1405 return dev_err_probe(data->dev, ret,
1406 "iio_triggered_buffer_setup_ext FAIL\n");
1407 indio_trig = devm_iio_trigger_alloc(dev, "%sdata-rdy-dev%d", idev->name,
1408 iio_device_id(idev));
1409 if (!indio_trig)
1410 return -ENOMEM;
1411
1412 data->trig = indio_trig;
1413
1414 indio_trig->ops = &kx022a_trigger_ops;
1415 iio_trigger_set_drvdata(indio_trig, data);
1416
1417 /*
1418 * No need to check for NULL. request_threaded_irq() defaults to
1419 * dev_name() should the alloc fail.
1420 */
1421 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-kx022a",
1422 dev_name(data->dev));
1423
1424 ret = devm_request_threaded_irq(data->dev, irq, kx022a_irq_handler,
1425 &kx022a_irq_thread_handler,
1426 IRQF_ONESHOT, name, idev);
1427 if (ret)
1428 return dev_err_probe(data->dev, ret, "Could not request IRQ\n");
1429
1430 ret = devm_iio_trigger_register(dev, indio_trig);
1431 if (ret)
1432 return dev_err_probe(data->dev, ret,
1433 "Trigger registration failed\n");
1434
1435 ret = devm_iio_device_register(data->dev, idev);
1436 if (ret < 0)
1437 return dev_err_probe(dev, ret,
1438 "Unable to register iio device\n");
1439
1440 return ret;
1441 }
1442 EXPORT_SYMBOL_NS_GPL(kx022a_probe_internal, "IIO_KX022A");
1443
1444 MODULE_DESCRIPTION("ROHM/Kionix KX022A accelerometer driver");
1445 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
1446 MODULE_LICENSE("GPL");
1447