1 /*
2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23 #include <linux/reset.h>
24 #include <linux/io.h>
25 #include <linux/of.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
29
30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32
33 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
39
40 /* Ctlr status values */
41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42 #define MV64XXX_I2C_STATUS_MAST_START 0x08
43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
58
59 /* Register defines (I2C bridge) */
60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
69
70 /* Bridge Control values */
71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
79
80 /* Bridge Status values */
81 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
82
83 /* Driver states */
84 enum {
85 MV64XXX_I2C_STATE_INVALID,
86 MV64XXX_I2C_STATE_IDLE,
87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA,
93 };
94
95 /* Driver actions */
96 enum {
97 MV64XXX_I2C_ACTION_INVALID,
98 MV64XXX_I2C_ACTION_CONTINUE,
99 MV64XXX_I2C_ACTION_SEND_RESTART,
100 MV64XXX_I2C_ACTION_SEND_ADDR_1,
101 MV64XXX_I2C_ACTION_SEND_ADDR_2,
102 MV64XXX_I2C_ACTION_SEND_DATA,
103 MV64XXX_I2C_ACTION_RCV_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
105 MV64XXX_I2C_ACTION_SEND_STOP,
106 };
107
108 struct mv64xxx_i2c_regs {
109 u8 addr;
110 u8 ext_addr;
111 u8 data;
112 u8 control;
113 u8 status;
114 u8 clock;
115 u8 soft_reset;
116 };
117
118 struct mv64xxx_i2c_data {
119 struct i2c_msg *msgs;
120 int num_msgs;
121 int irq;
122 u32 state;
123 u32 action;
124 u32 aborting;
125 u32 cntl_bits;
126 void __iomem *reg_base;
127 struct mv64xxx_i2c_regs reg_offsets;
128 u32 addr1;
129 u32 addr2;
130 u32 bytes_left;
131 u32 byte_posn;
132 u32 send_stop;
133 u32 block;
134 int rc;
135 u32 freq_m;
136 u32 freq_n;
137 struct clk *clk;
138 struct clk *reg_clk;
139 wait_queue_head_t waitq;
140 spinlock_t lock;
141 struct i2c_msg *msg;
142 struct i2c_adapter adapter;
143 bool offload_enabled;
144 /* 5us delay in order to avoid repeated start timing violation */
145 bool errata_delay;
146 struct reset_control *rstc;
147 bool irq_clear_inverted;
148 /* Clk div is 2 to the power n, not 2 to the power n + 1 */
149 bool clk_n_base_0;
150 struct i2c_bus_recovery_info rinfo;
151 bool atomic;
152 };
153
154 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
155 .addr = 0x00,
156 .ext_addr = 0x10,
157 .data = 0x04,
158 .control = 0x08,
159 .status = 0x0c,
160 .clock = 0x0c,
161 .soft_reset = 0x1c,
162 };
163
164 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
165 .addr = 0x00,
166 .ext_addr = 0x04,
167 .data = 0x08,
168 .control = 0x0c,
169 .status = 0x10,
170 .clock = 0x14,
171 .soft_reset = 0x18,
172 };
173
174 static void
mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data * drv_data,struct i2c_msg * msg)175 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
176 struct i2c_msg *msg)
177 {
178 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
179 MV64XXX_I2C_REG_CONTROL_TWSIEN;
180
181 if (!drv_data->atomic)
182 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
183
184 if (msg->flags & I2C_M_TEN) {
185 drv_data->addr1 = i2c_10bit_addr_hi_from_msg(msg);
186 drv_data->addr2 = i2c_10bit_addr_lo_from_msg(msg);
187 } else {
188 drv_data->addr1 = i2c_8bit_addr_from_msg(msg);
189 drv_data->addr2 = 0;
190 }
191 }
192
193 /*
194 *****************************************************************************
195 *
196 * Finite State Machine & Interrupt Routines
197 *
198 *****************************************************************************
199 */
200
201 /* Reset hardware and initialize FSM */
202 static void
mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data * drv_data)203 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
204 {
205 if (drv_data->offload_enabled) {
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
208 writel(0, drv_data->reg_base +
209 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
210 writel(0, drv_data->reg_base +
211 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
212 }
213
214 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
215 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
216 drv_data->reg_base + drv_data->reg_offsets.clock);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
219 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
220 drv_data->reg_base + drv_data->reg_offsets.control);
221
222 if (drv_data->errata_delay)
223 udelay(5);
224
225 drv_data->state = MV64XXX_I2C_STATE_IDLE;
226 }
227
228 static void
mv64xxx_i2c_fsm(struct mv64xxx_i2c_data * drv_data,u32 status)229 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
230 {
231 /*
232 * If state is idle, then this is likely the remnants of an old
233 * operation that driver has given up on or the user has killed.
234 * If so, issue the stop condition and go to idle.
235 */
236 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
237 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
238 return;
239 }
240
241 /* The status from the ctlr [mostly] tells us what to do next */
242 switch (status) {
243 /* Start condition interrupt */
244 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
245 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
246 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
247 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
248 break;
249
250 /* Performing a write */
251 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
252 if (drv_data->msg->flags & I2C_M_TEN) {
253 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
254 drv_data->state =
255 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
256 break;
257 }
258 fallthrough;
259 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
260 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
261 if ((drv_data->bytes_left == 0)
262 || (drv_data->aborting
263 && (drv_data->byte_posn != 0))) {
264 if (drv_data->send_stop || drv_data->aborting) {
265 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
266 drv_data->state = MV64XXX_I2C_STATE_IDLE;
267 } else {
268 drv_data->action =
269 MV64XXX_I2C_ACTION_SEND_RESTART;
270 drv_data->state =
271 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
272 }
273 } else {
274 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
275 drv_data->state =
276 MV64XXX_I2C_STATE_WAITING_FOR_TARGET_ACK;
277 drv_data->bytes_left--;
278 }
279 break;
280
281 /* Performing a read */
282 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
283 if (drv_data->msg->flags & I2C_M_TEN) {
284 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
285 drv_data->state =
286 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
287 break;
288 }
289 fallthrough;
290 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
291 if (drv_data->bytes_left == 0) {
292 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
293 drv_data->state = MV64XXX_I2C_STATE_IDLE;
294 break;
295 }
296 fallthrough;
297 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
298 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
299 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
300 else {
301 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
302 drv_data->bytes_left--;
303 }
304 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_TARGET_DATA;
305
306 if ((drv_data->bytes_left == 1) || drv_data->aborting)
307 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
308 break;
309
310 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
311 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
312 drv_data->state = MV64XXX_I2C_STATE_IDLE;
313 break;
314
315 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
316 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
317 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
318 /* Doesn't seem to be a device at other end */
319 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
320 drv_data->state = MV64XXX_I2C_STATE_IDLE;
321 drv_data->rc = -ENXIO;
322 break;
323
324 default:
325 dev_err(&drv_data->adapter.dev,
326 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
327 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
328 drv_data->state, status, drv_data->msg->addr,
329 drv_data->msg->flags);
330 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
331 mv64xxx_i2c_hw_init(drv_data);
332 i2c_recover_bus(&drv_data->adapter);
333 drv_data->rc = -EAGAIN;
334 }
335 }
336
mv64xxx_i2c_send_start(struct mv64xxx_i2c_data * drv_data)337 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
338 {
339 drv_data->msg = drv_data->msgs;
340 drv_data->byte_posn = 0;
341 drv_data->bytes_left = drv_data->msg->len;
342 drv_data->aborting = 0;
343 drv_data->rc = 0;
344
345 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
346 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
347 drv_data->reg_base + drv_data->reg_offsets.control);
348 }
349
350 static void
mv64xxx_i2c_do_action(struct mv64xxx_i2c_data * drv_data)351 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
352 {
353 switch(drv_data->action) {
354 case MV64XXX_I2C_ACTION_SEND_RESTART:
355 /* We should only get here if we have further messages */
356 BUG_ON(drv_data->num_msgs == 0);
357
358 drv_data->msgs++;
359 drv_data->num_msgs--;
360 mv64xxx_i2c_send_start(drv_data);
361
362 if (drv_data->errata_delay)
363 udelay(5);
364
365 /*
366 * We're never at the start of the message here, and by this
367 * time it's already too late to do any protocol mangling.
368 * Thankfully, do not advertise support for that feature.
369 */
370 drv_data->send_stop = drv_data->num_msgs == 1;
371 break;
372
373 case MV64XXX_I2C_ACTION_CONTINUE:
374 writel(drv_data->cntl_bits,
375 drv_data->reg_base + drv_data->reg_offsets.control);
376 break;
377
378 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
379 writel(drv_data->addr1,
380 drv_data->reg_base + drv_data->reg_offsets.data);
381 writel(drv_data->cntl_bits,
382 drv_data->reg_base + drv_data->reg_offsets.control);
383 break;
384
385 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
386 writel(drv_data->addr2,
387 drv_data->reg_base + drv_data->reg_offsets.data);
388 writel(drv_data->cntl_bits,
389 drv_data->reg_base + drv_data->reg_offsets.control);
390 break;
391
392 case MV64XXX_I2C_ACTION_SEND_DATA:
393 writel(drv_data->msg->buf[drv_data->byte_posn++],
394 drv_data->reg_base + drv_data->reg_offsets.data);
395 writel(drv_data->cntl_bits,
396 drv_data->reg_base + drv_data->reg_offsets.control);
397 break;
398
399 case MV64XXX_I2C_ACTION_RCV_DATA:
400 drv_data->msg->buf[drv_data->byte_posn++] =
401 readl(drv_data->reg_base + drv_data->reg_offsets.data);
402 writel(drv_data->cntl_bits,
403 drv_data->reg_base + drv_data->reg_offsets.control);
404 break;
405
406 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
407 drv_data->msg->buf[drv_data->byte_posn++] =
408 readl(drv_data->reg_base + drv_data->reg_offsets.data);
409 if (!drv_data->atomic)
410 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
411 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
412 drv_data->reg_base + drv_data->reg_offsets.control);
413 drv_data->block = 0;
414 if (drv_data->errata_delay)
415 udelay(5);
416
417 wake_up(&drv_data->waitq);
418 break;
419
420 case MV64XXX_I2C_ACTION_INVALID:
421 default:
422 dev_err(&drv_data->adapter.dev,
423 "mv64xxx_i2c_do_action: Invalid action: %d\n",
424 drv_data->action);
425 drv_data->rc = -EIO;
426 fallthrough;
427 case MV64XXX_I2C_ACTION_SEND_STOP:
428 if (!drv_data->atomic)
429 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
430 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
431 drv_data->reg_base + drv_data->reg_offsets.control);
432 drv_data->block = 0;
433 wake_up(&drv_data->waitq);
434 break;
435 }
436 }
437
438 static void
mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data * drv_data,struct i2c_msg * msg)439 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
440 struct i2c_msg *msg)
441 {
442 u32 buf[2];
443
444 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
445 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
446
447 memcpy(msg->buf, buf, msg->len);
448 }
449
450 static int
mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data * drv_data)451 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
452 {
453 u32 cause, status;
454
455 cause = readl(drv_data->reg_base +
456 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
457 if (!cause)
458 return IRQ_NONE;
459
460 status = readl(drv_data->reg_base +
461 MV64XXX_I2C_REG_BRIDGE_STATUS);
462
463 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
464 drv_data->rc = -EIO;
465 goto out;
466 }
467
468 drv_data->rc = 0;
469
470 /*
471 * Transaction is a one message read transaction, read data
472 * for this message.
473 */
474 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
475 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
476 drv_data->msgs++;
477 drv_data->num_msgs--;
478 }
479 /*
480 * Transaction is a two messages write/read transaction, read
481 * data for the second (read) message.
482 */
483 else if (drv_data->num_msgs == 2 &&
484 !(drv_data->msgs[0].flags & I2C_M_RD) &&
485 drv_data->msgs[1].flags & I2C_M_RD) {
486 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
487 drv_data->msgs += 2;
488 drv_data->num_msgs -= 2;
489 }
490
491 out:
492 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
493 writel(0, drv_data->reg_base +
494 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
495 drv_data->block = 0;
496
497 wake_up(&drv_data->waitq);
498
499 return IRQ_HANDLED;
500 }
501
502 static irqreturn_t
mv64xxx_i2c_intr(int irq,void * dev_id)503 mv64xxx_i2c_intr(int irq, void *dev_id)
504 {
505 struct mv64xxx_i2c_data *drv_data = dev_id;
506 u32 status;
507 irqreturn_t rc = IRQ_NONE;
508
509 spin_lock(&drv_data->lock);
510
511 if (drv_data->offload_enabled)
512 rc = mv64xxx_i2c_intr_offload(drv_data);
513
514 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
515 MV64XXX_I2C_REG_CONTROL_IFLG) {
516 /*
517 * It seems that sometime the controller updates the status
518 * register only after it asserts IFLG in control register.
519 * This may result in weird bugs when in atomic mode. A delay
520 * of 100 ns before reading the status register solves this
521 * issue. This bug does not seem to appear when using
522 * interrupts.
523 */
524 if (drv_data->atomic)
525 ndelay(100);
526
527 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
528 mv64xxx_i2c_fsm(drv_data, status);
529 mv64xxx_i2c_do_action(drv_data);
530
531 if (drv_data->irq_clear_inverted)
532 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
533 drv_data->reg_base + drv_data->reg_offsets.control);
534
535 rc = IRQ_HANDLED;
536 }
537 spin_unlock(&drv_data->lock);
538
539 return rc;
540 }
541
542 /*
543 *****************************************************************************
544 *
545 * I2C Msg Execution Routines
546 *
547 *****************************************************************************
548 */
549 static void
mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data * drv_data)550 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
551 {
552 long time_left;
553 unsigned long flags;
554 char abort = 0;
555
556 time_left = wait_event_timeout(drv_data->waitq,
557 !drv_data->block, drv_data->adapter.timeout);
558
559 spin_lock_irqsave(&drv_data->lock, flags);
560 if (!time_left) { /* Timed out */
561 drv_data->rc = -ETIMEDOUT;
562 abort = 1;
563 } else if (time_left < 0) { /* Interrupted/Error */
564 drv_data->rc = time_left; /* errno value */
565 abort = 1;
566 }
567
568 if (abort && drv_data->block) {
569 drv_data->aborting = 1;
570 spin_unlock_irqrestore(&drv_data->lock, flags);
571
572 time_left = wait_event_timeout(drv_data->waitq,
573 !drv_data->block, drv_data->adapter.timeout);
574
575 if ((time_left <= 0) && drv_data->block) {
576 drv_data->state = MV64XXX_I2C_STATE_IDLE;
577 dev_err(&drv_data->adapter.dev,
578 "mv64xxx: I2C bus locked, block: %d, "
579 "time_left: %d\n", drv_data->block,
580 (int)time_left);
581 mv64xxx_i2c_hw_init(drv_data);
582 i2c_recover_bus(&drv_data->adapter);
583 }
584 } else
585 spin_unlock_irqrestore(&drv_data->lock, flags);
586 }
587
mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data * drv_data)588 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
589 {
590 ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
591
592 while (READ_ONCE(drv_data->block) &&
593 ktime_compare(ktime_get(), timeout) < 0) {
594 udelay(5);
595 mv64xxx_i2c_intr(0, drv_data);
596 }
597 }
598
599 static int
mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data * drv_data,struct i2c_msg * msg,int is_last)600 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
601 int is_last)
602 {
603 unsigned long flags;
604
605 spin_lock_irqsave(&drv_data->lock, flags);
606
607 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
608
609 drv_data->send_stop = is_last;
610 drv_data->block = 1;
611 mv64xxx_i2c_send_start(drv_data);
612 spin_unlock_irqrestore(&drv_data->lock, flags);
613
614 if (!drv_data->atomic)
615 mv64xxx_i2c_wait_for_completion(drv_data);
616 else
617 mv64xxx_i2c_wait_polling(drv_data);
618
619 return drv_data->rc;
620 }
621
622 static void
mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data * drv_data)623 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
624 {
625 struct i2c_msg *msg = drv_data->msgs;
626 u32 buf[2];
627
628 memcpy(buf, msg->buf, msg->len);
629
630 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
631 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
632 }
633
634 static int
mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data * drv_data)635 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
636 {
637 struct i2c_msg *msgs = drv_data->msgs;
638 int num = drv_data->num_msgs;
639 unsigned long ctrl_reg;
640 unsigned long flags;
641
642 spin_lock_irqsave(&drv_data->lock, flags);
643
644 /* Build transaction */
645 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
646 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
647
648 if (msgs[0].flags & I2C_M_TEN)
649 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
650
651 /* Single write message transaction */
652 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
653 size_t len = msgs[0].len - 1;
654
655 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
656 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
657 mv64xxx_i2c_prepare_tx(drv_data);
658 }
659 /* Single read message transaction */
660 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
661 size_t len = msgs[0].len - 1;
662
663 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
664 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
665 }
666 /*
667 * Transaction with one write and one read message. This is
668 * guaranteed by the mv64xx_i2c_can_offload() checks.
669 */
670 else if (num == 2) {
671 size_t lentx = msgs[0].len - 1;
672 size_t lenrx = msgs[1].len - 1;
673
674 ctrl_reg |=
675 MV64XXX_I2C_BRIDGE_CONTROL_RD |
676 MV64XXX_I2C_BRIDGE_CONTROL_WR |
677 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
678 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
679 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
680 mv64xxx_i2c_prepare_tx(drv_data);
681 }
682
683 /* Execute transaction */
684 drv_data->block = 1;
685 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
686 spin_unlock_irqrestore(&drv_data->lock, flags);
687
688 mv64xxx_i2c_wait_for_completion(drv_data);
689
690 return drv_data->rc;
691 }
692
693 static bool
mv64xxx_i2c_valid_offload_sz(struct i2c_msg * msg)694 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
695 {
696 return msg->len <= 8 && msg->len >= 1;
697 }
698
699 static bool
mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data * drv_data)700 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
701 {
702 struct i2c_msg *msgs = drv_data->msgs;
703 int num = drv_data->num_msgs;
704
705 if (!drv_data->offload_enabled)
706 return false;
707
708 /*
709 * We can offload a transaction consisting of a single
710 * message, as long as the message has a length between 1 and
711 * 8 bytes.
712 */
713 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
714 return true;
715
716 /*
717 * We can offload a transaction consisting of two messages, if
718 * the first is a write and a second is a read, and both have
719 * a length between 1 and 8 bytes.
720 */
721 if (num == 2 &&
722 mv64xxx_i2c_valid_offload_sz(msgs) &&
723 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
724 !(msgs[0].flags & I2C_M_RD) &&
725 msgs[1].flags & I2C_M_RD)
726 return true;
727
728 return false;
729 }
730
731 /*
732 *****************************************************************************
733 *
734 * I2C Core Support Routines (Interface to higher level I2C code)
735 *
736 *****************************************************************************
737 */
738 static u32
mv64xxx_i2c_functionality(struct i2c_adapter * adap)739 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
740 {
741 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
742 }
743
744 static int
mv64xxx_i2c_xfer_core(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)745 mv64xxx_i2c_xfer_core(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
746 {
747 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
748 int rc, ret = num;
749
750 rc = pm_runtime_resume_and_get(&adap->dev);
751 if (rc)
752 return rc;
753
754 BUG_ON(drv_data->msgs != NULL);
755 drv_data->msgs = msgs;
756 drv_data->num_msgs = num;
757
758 if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
759 rc = mv64xxx_i2c_offload_xfer(drv_data);
760 else
761 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
762
763 if (rc < 0)
764 ret = rc;
765
766 drv_data->num_msgs = 0;
767 drv_data->msgs = NULL;
768
769 pm_runtime_mark_last_busy(&adap->dev);
770 pm_runtime_put_autosuspend(&adap->dev);
771
772 return ret;
773 }
774
775 static int
mv64xxx_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)776 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
777 {
778 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
779
780 drv_data->atomic = 0;
781 return mv64xxx_i2c_xfer_core(adap, msgs, num);
782 }
783
mv64xxx_i2c_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)784 static int mv64xxx_i2c_xfer_atomic(struct i2c_adapter *adap,
785 struct i2c_msg msgs[], int num)
786 {
787 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
788
789 drv_data->atomic = 1;
790 return mv64xxx_i2c_xfer_core(adap, msgs, num);
791 }
792
793 static const struct i2c_algorithm mv64xxx_i2c_algo = {
794 .xfer = mv64xxx_i2c_xfer,
795 .xfer_atomic = mv64xxx_i2c_xfer_atomic,
796 .functionality = mv64xxx_i2c_functionality,
797 };
798
799 /*
800 *****************************************************************************
801 *
802 * Driver Interface & Early Init Routines
803 *
804 *****************************************************************************
805 */
806 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
807 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
808 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
809 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
810 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
811 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
812 {}
813 };
814 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
815
816 #ifdef CONFIG_OF
817 static int
mv64xxx_calc_freq(struct mv64xxx_i2c_data * drv_data,const int tclk,const int n,const int m)818 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
819 const int tclk, const int n, const int m)
820 {
821 if (drv_data->clk_n_base_0)
822 return tclk / (10 * (m + 1) * (1 << n));
823 else
824 return tclk / (10 * (m + 1) * (2 << n));
825 }
826
827 static bool
mv64xxx_find_baud_factors(struct mv64xxx_i2c_data * drv_data,const u32 req_freq,const u32 tclk)828 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
829 const u32 req_freq, const u32 tclk)
830 {
831 int freq, delta, best_delta = INT_MAX;
832 int m, n;
833
834 for (n = 0; n <= 7; n++)
835 for (m = 0; m <= 15; m++) {
836 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
837 delta = req_freq - freq;
838 if (delta >= 0 && delta < best_delta) {
839 drv_data->freq_m = m;
840 drv_data->freq_n = n;
841 best_delta = delta;
842 }
843 if (best_delta == 0)
844 return true;
845 }
846 if (best_delta == INT_MAX)
847 return false;
848 return true;
849 }
850
851 static int
mv64xxx_of_config(struct mv64xxx_i2c_data * drv_data,struct device * dev)852 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
853 struct device *dev)
854 {
855 const struct mv64xxx_i2c_regs *data;
856 struct device_node *np = dev->of_node;
857 u32 bus_freq, tclk;
858 int rc = 0;
859
860 /* CLK is mandatory when using DT to describe the i2c bus. We
861 * need to know tclk in order to calculate bus clock
862 * factors.
863 */
864 if (!drv_data->clk) {
865 rc = -ENODEV;
866 goto out;
867 }
868 tclk = clk_get_rate(drv_data->clk);
869
870 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
871 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
872
873 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
874 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
875 drv_data->clk_n_base_0 = true;
876
877 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
878 rc = -EINVAL;
879 goto out;
880 }
881
882 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
883 if (IS_ERR(drv_data->rstc)) {
884 rc = PTR_ERR(drv_data->rstc);
885 goto out;
886 }
887
888 /* Its not yet defined how timeouts will be specified in device tree.
889 * So hard code the value to 1 second.
890 */
891 drv_data->adapter.timeout = HZ;
892
893 data = device_get_match_data(dev);
894 if (!data)
895 return -ENODEV;
896
897 memcpy(&drv_data->reg_offsets, data, sizeof(drv_data->reg_offsets));
898
899 /*
900 * For controllers embedded in new SoCs activate the
901 * Transaction Generator support and the errata fix.
902 */
903 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
904 drv_data->offload_enabled = true;
905 /* The delay is only needed in standard mode (100kHz) */
906 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
907 drv_data->errata_delay = true;
908 }
909
910 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
911 drv_data->offload_enabled = false;
912 /* The delay is only needed in standard mode (100kHz) */
913 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
914 drv_data->errata_delay = true;
915 }
916
917 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
918 drv_data->irq_clear_inverted = true;
919
920 out:
921 return rc;
922 }
923 #else /* CONFIG_OF */
924 static int
mv64xxx_of_config(struct mv64xxx_i2c_data * drv_data,struct device * dev)925 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
926 struct device *dev)
927 {
928 return -ENODEV;
929 }
930 #endif /* CONFIG_OF */
931
mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data * drv_data,struct device * dev)932 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
933 struct device *dev)
934 {
935 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
936
937 rinfo->pinctrl = devm_pinctrl_get(dev);
938 if (IS_ERR(rinfo->pinctrl)) {
939 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
940 return -EPROBE_DEFER;
941 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
942 return PTR_ERR(rinfo->pinctrl);
943 } else if (!rinfo->pinctrl) {
944 return -ENODEV;
945 }
946
947 drv_data->adapter.bus_recovery_info = rinfo;
948 return 0;
949 }
950
951 static int
mv64xxx_i2c_runtime_suspend(struct device * dev)952 mv64xxx_i2c_runtime_suspend(struct device *dev)
953 {
954 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
955
956 reset_control_assert(drv_data->rstc);
957 clk_disable_unprepare(drv_data->reg_clk);
958 clk_disable_unprepare(drv_data->clk);
959
960 return 0;
961 }
962
963 static int
mv64xxx_i2c_runtime_resume(struct device * dev)964 mv64xxx_i2c_runtime_resume(struct device *dev)
965 {
966 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
967
968 clk_prepare_enable(drv_data->clk);
969 clk_prepare_enable(drv_data->reg_clk);
970 reset_control_reset(drv_data->rstc);
971
972 mv64xxx_i2c_hw_init(drv_data);
973
974 return 0;
975 }
976
977 static int
mv64xxx_i2c_probe(struct platform_device * pd)978 mv64xxx_i2c_probe(struct platform_device *pd)
979 {
980 struct mv64xxx_i2c_data *drv_data;
981 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
982 int rc;
983
984 if ((!pdata && !pd->dev.of_node))
985 return -ENODEV;
986
987 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
988 GFP_KERNEL);
989 if (!drv_data)
990 return -ENOMEM;
991
992 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
993 if (IS_ERR(drv_data->reg_base))
994 return PTR_ERR(drv_data->reg_base);
995
996 strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
997 sizeof(drv_data->adapter.name));
998
999 init_waitqueue_head(&drv_data->waitq);
1000 spin_lock_init(&drv_data->lock);
1001
1002 /* Not all platforms have clocks */
1003 drv_data->clk = devm_clk_get(&pd->dev, NULL);
1004 if (IS_ERR(drv_data->clk)) {
1005 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1006 return -EPROBE_DEFER;
1007 drv_data->clk = NULL;
1008 }
1009
1010 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1011 if (IS_ERR(drv_data->reg_clk)) {
1012 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1013 return -EPROBE_DEFER;
1014 drv_data->reg_clk = NULL;
1015 }
1016
1017 drv_data->irq = platform_get_irq(pd, 0);
1018 if (drv_data->irq < 0)
1019 return drv_data->irq;
1020
1021 if (pdata) {
1022 drv_data->freq_m = pdata->freq_m;
1023 drv_data->freq_n = pdata->freq_n;
1024 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1025 drv_data->offload_enabled = false;
1026 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1027 } else if (pd->dev.of_node) {
1028 rc = mv64xxx_of_config(drv_data, &pd->dev);
1029 if (rc)
1030 return rc;
1031 }
1032
1033 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1034 if (rc == -EPROBE_DEFER)
1035 return rc;
1036
1037 drv_data->adapter.dev.parent = &pd->dev;
1038 drv_data->adapter.algo = &mv64xxx_i2c_algo;
1039 drv_data->adapter.owner = THIS_MODULE;
1040 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1041 drv_data->adapter.nr = pd->id;
1042 drv_data->adapter.dev.of_node = pd->dev.of_node;
1043 platform_set_drvdata(pd, drv_data);
1044 i2c_set_adapdata(&drv_data->adapter, drv_data);
1045
1046 pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
1047 pm_runtime_use_autosuspend(&pd->dev);
1048 pm_runtime_enable(&pd->dev);
1049 if (!pm_runtime_enabled(&pd->dev)) {
1050 rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1051 if (rc)
1052 goto exit_disable_pm;
1053 }
1054
1055 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1056 MV64XXX_I2C_CTLR_NAME, drv_data);
1057 if (rc) {
1058 dev_err(&drv_data->adapter.dev,
1059 "mv64xxx: Can't register intr handler irq%d: %d\n",
1060 drv_data->irq, rc);
1061 goto exit_disable_pm;
1062 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1063 dev_err(&drv_data->adapter.dev,
1064 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1065 goto exit_free_irq;
1066 }
1067
1068 return 0;
1069
1070 exit_free_irq:
1071 free_irq(drv_data->irq, drv_data);
1072 exit_disable_pm:
1073 pm_runtime_disable(&pd->dev);
1074 if (!pm_runtime_status_suspended(&pd->dev))
1075 mv64xxx_i2c_runtime_suspend(&pd->dev);
1076
1077 return rc;
1078 }
1079
1080 static void
mv64xxx_i2c_remove(struct platform_device * pd)1081 mv64xxx_i2c_remove(struct platform_device *pd)
1082 {
1083 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1084
1085 i2c_del_adapter(&drv_data->adapter);
1086 free_irq(drv_data->irq, drv_data);
1087 pm_runtime_disable(&pd->dev);
1088 if (!pm_runtime_status_suspended(&pd->dev))
1089 mv64xxx_i2c_runtime_suspend(&pd->dev);
1090 }
1091
1092 static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1093 SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1094 mv64xxx_i2c_runtime_resume, NULL)
1095 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1096 pm_runtime_force_resume)
1097 };
1098
1099 static struct platform_driver mv64xxx_i2c_driver = {
1100 .probe = mv64xxx_i2c_probe,
1101 .remove = mv64xxx_i2c_remove,
1102 .driver = {
1103 .name = MV64XXX_I2C_CTLR_NAME,
1104 .pm = &mv64xxx_i2c_pm_ops,
1105 .of_match_table = mv64xxx_i2c_of_match_table,
1106 },
1107 };
1108
1109 module_platform_driver(mv64xxx_i2c_driver);
1110
1111 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1112 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1113 MODULE_LICENSE("GPL");
1114