1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/acpi.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/kvm_host.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/err.h>
16 #include <linux/fs.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/smp.h>
20 #include <linux/sysfs.h>
21 #include <linux/stat.h>
22 #include <linux/clk.h>
23 #include <linux/cpu.h>
24 #include <linux/cpu_pm.h>
25 #include <linux/coresight.h>
26 #include <linux/coresight-pmu.h>
27 #include <linux/amba/bus.h>
28 #include <linux/seq_file.h>
29 #include <linux/uaccess.h>
30 #include <linux/perf_event.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/property.h>
34 #include <linux/clk/clk-conf.h>
35 
36 #include <asm/barrier.h>
37 #include <asm/sections.h>
38 #include <asm/sysreg.h>
39 #include <asm/local.h>
40 #include <asm/virt.h>
41 
42 #include "coresight-etm4x.h"
43 #include "coresight-etm-perf.h"
44 #include "coresight-etm4x-cfg.h"
45 #include "coresight-self-hosted-trace.h"
46 #include "coresight-syscfg.h"
47 #include "coresight-trace-id.h"
48 
49 static int boot_enable;
50 module_param(boot_enable, int, 0444);
51 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
52 
53 #define PARAM_PM_SAVE_FIRMWARE	  0 /* save self-hosted state as per firmware */
54 #define PARAM_PM_SAVE_NEVER	  1 /* never save any state */
55 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
56 
57 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
58 module_param(pm_save_enable, int, 0444);
59 MODULE_PARM_DESC(pm_save_enable,
60 	"Save/restore state on power down: 1 = never, 2 = self-hosted");
61 
62 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
63 static void etm4_set_default_config(struct etmv4_config *config);
64 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
65 				  struct perf_event *event);
66 static u64 etm4_get_access_type(struct etmv4_config *config);
67 
68 static enum cpuhp_state hp_online;
69 
70 struct etm4_init_arg {
71 	struct device		*dev;
72 	struct csdev_access	*csa;
73 };
74 
75 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
76 static int etm4_probe_cpu(unsigned int cpu);
77 
78 /*
79  * Check if TRCSSPCICRn(i) is implemented for a given instance.
80  *
81  * TRCSSPCICRn is implemented only if :
82  *	TRCSSPCICR<n> is present only if all of the following are true:
83  *		TRCIDR4.NUMSSCC > n.
84  *		TRCIDR4.NUMPC > 0b0000 .
85  *		TRCSSCSR<n>.PC == 0b1
86  */
etm4x_sspcicrn_present(struct etmv4_drvdata * drvdata,int n)87 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
88 {
89 	return (n < drvdata->nr_ss_cmp) &&
90 	       drvdata->nr_pe &&
91 	       (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
92 }
93 
etm4x_sysreg_read(u32 offset,bool _relaxed,bool _64bit)94 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
95 {
96 	u64 res = 0;
97 
98 	switch (offset) {
99 	ETM4x_READ_SYSREG_CASES(res)
100 	default :
101 		pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
102 			 offset);
103 	}
104 
105 	if (!_relaxed)
106 		__io_ar(res);	/* Imitate the !relaxed I/O helpers */
107 
108 	return res;
109 }
110 
etm4x_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)111 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
112 {
113 	if (!_relaxed)
114 		__io_bw();	/* Imitate the !relaxed I/O helpers */
115 	if (!_64bit)
116 		val &= GENMASK(31, 0);
117 
118 	switch (offset) {
119 	ETM4x_WRITE_SYSREG_CASES(val)
120 	default :
121 		pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
122 			offset);
123 	}
124 }
125 
ete_sysreg_read(u32 offset,bool _relaxed,bool _64bit)126 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
127 {
128 	u64 res = 0;
129 
130 	switch (offset) {
131 	ETE_READ_CASES(res)
132 	default :
133 		pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
134 				    offset);
135 	}
136 
137 	if (!_relaxed)
138 		__io_ar(res);	/* Imitate the !relaxed I/O helpers */
139 
140 	return res;
141 }
142 
ete_sysreg_write(u64 val,u32 offset,bool _relaxed,bool _64bit)143 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
144 {
145 	if (!_relaxed)
146 		__io_bw();	/* Imitate the !relaxed I/O helpers */
147 	if (!_64bit)
148 		val &= GENMASK(31, 0);
149 
150 	switch (offset) {
151 	ETE_WRITE_CASES(val)
152 	default :
153 		pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
154 				    offset);
155 	}
156 }
157 
etm_detect_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)158 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
159 			       struct csdev_access *csa)
160 {
161 	u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
162 
163 	drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
164 }
165 
etm_write_os_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa,u32 val)166 static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
167 			      struct csdev_access *csa, u32 val)
168 {
169 	val = !!val;
170 
171 	switch (drvdata->os_lock_model) {
172 	case ETM_OSLOCK_PRESENT:
173 		etm4x_relaxed_write32(csa, val, TRCOSLAR);
174 		break;
175 	case ETM_OSLOCK_PE:
176 		write_sysreg_s(val, SYS_OSLAR_EL1);
177 		break;
178 	default:
179 		pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
180 			     smp_processor_id(), drvdata->os_lock_model);
181 		fallthrough;
182 	case ETM_OSLOCK_NI:
183 		return;
184 	}
185 	isb();
186 }
187 
etm4_os_unlock_csa(struct etmv4_drvdata * drvdata,struct csdev_access * csa)188 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
189 				      struct csdev_access *csa)
190 {
191 	WARN_ON(drvdata->cpu != smp_processor_id());
192 
193 	/* Writing 0 to OS Lock unlocks the trace unit registers */
194 	etm_write_os_lock(drvdata, csa, 0x0);
195 	drvdata->os_unlock = true;
196 }
197 
etm4_os_unlock(struct etmv4_drvdata * drvdata)198 static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
199 {
200 	if (!WARN_ON(!drvdata->csdev))
201 		etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
202 }
203 
etm4_os_lock(struct etmv4_drvdata * drvdata)204 static void etm4_os_lock(struct etmv4_drvdata *drvdata)
205 {
206 	if (WARN_ON(!drvdata->csdev))
207 		return;
208 	/* Writing 0x1 to OS Lock locks the trace registers */
209 	etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
210 	drvdata->os_unlock = false;
211 }
212 
etm4_cs_lock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)213 static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
214 			 struct csdev_access *csa)
215 {
216 	/* Software Lock is only accessible via memory mapped interface */
217 	if (csa->io_mem)
218 		CS_LOCK(csa->base);
219 }
220 
etm4_cs_unlock(struct etmv4_drvdata * drvdata,struct csdev_access * csa)221 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
222 			   struct csdev_access *csa)
223 {
224 	if (csa->io_mem)
225 		CS_UNLOCK(csa->base);
226 }
227 
etm4_cpu_id(struct coresight_device * csdev)228 static int etm4_cpu_id(struct coresight_device *csdev)
229 {
230 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
231 
232 	return drvdata->cpu;
233 }
234 
etm4_release_trace_id(struct etmv4_drvdata * drvdata)235 void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
236 {
237 	coresight_trace_id_put_cpu_id(drvdata->cpu);
238 }
239 
240 struct etm4_enable_arg {
241 	struct etmv4_drvdata *drvdata;
242 	int rc;
243 };
244 
245 /*
246  * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
247  * When the CPU supports FEAT_TRF, we could move the ETM to a trace
248  * prohibited state by filtering the Exception levels via TRFCR_EL1.
249  */
etm4x_prohibit_trace(struct etmv4_drvdata * drvdata)250 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
251 {
252 	u64 trfcr;
253 
254 	/* If the CPU doesn't support FEAT_TRF, nothing to do */
255 	if (!drvdata->trfcr)
256 		return;
257 
258 	trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
259 
260 	write_trfcr(trfcr);
261 	kvm_tracing_set_el1_configuration(trfcr);
262 }
263 
etm4x_get_kern_user_filter(struct etmv4_drvdata * drvdata)264 static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata)
265 {
266 	u64 trfcr = drvdata->trfcr;
267 
268 	if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
269 		trfcr &= ~TRFCR_EL1_ExTRE;
270 	if (drvdata->config.mode & ETM_MODE_EXCL_USER)
271 		trfcr &= ~TRFCR_EL1_E0TRE;
272 
273 	return trfcr;
274 }
275 
276 /*
277  * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
278  * as configured by the drvdata->config.mode for the current
279  * session. Even though we have TRCVICTLR bits to filter the
280  * trace in the ELs, it doesn't prevent the ETM from generating
281  * a packet (e.g, TraceInfo) that might contain the addresses from
282  * the excluded levels. Thus we use the additional controls provided
283  * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
284  * is generated for the excluded ELs.
285  */
etm4x_allow_trace(struct etmv4_drvdata * drvdata)286 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
287 {
288 	u64 trfcr, guest_trfcr;
289 
290 	/* If the CPU doesn't support FEAT_TRF, nothing to do */
291 	if (!drvdata->trfcr)
292 		return;
293 
294 	if (drvdata->config.mode & ETM_MODE_EXCL_HOST)
295 		trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
296 	else
297 		trfcr = etm4x_get_kern_user_filter(drvdata);
298 
299 	write_trfcr(trfcr);
300 
301 	/* Set filters for guests and pass to KVM */
302 	if (drvdata->config.mode & ETM_MODE_EXCL_GUEST)
303 		guest_trfcr = drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE);
304 	else
305 		guest_trfcr = etm4x_get_kern_user_filter(drvdata);
306 
307 	/* TRFCR_EL1 doesn't have CX so mask it out. */
308 	guest_trfcr &= ~TRFCR_EL2_CX;
309 	kvm_tracing_set_el1_configuration(guest_trfcr);
310 }
311 
312 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE
313 
314 #define HISI_HIP08_AMBA_ID		0x000b6d01
315 #define ETM4_AMBA_MASK			0xfffff
316 #define HISI_HIP08_CORE_COMMIT_MASK	0x3000
317 #define HISI_HIP08_CORE_COMMIT_SHIFT	12
318 #define HISI_HIP08_CORE_COMMIT_FULL	0b00
319 #define HISI_HIP08_CORE_COMMIT_LVL_1	0b01
320 #define HISI_HIP08_CORE_COMMIT_REG	sys_reg(3, 1, 15, 2, 5)
321 
322 struct etm4_arch_features {
323 	void (*arch_callback)(bool enable);
324 };
325 
etm4_hisi_match_pid(unsigned int id)326 static bool etm4_hisi_match_pid(unsigned int id)
327 {
328 	return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
329 }
330 
etm4_hisi_config_core_commit(bool enable)331 static void etm4_hisi_config_core_commit(bool enable)
332 {
333 	u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
334 		    HISI_HIP08_CORE_COMMIT_FULL;
335 	u64 val;
336 
337 	/*
338 	 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
339 	 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
340 	 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
341 	 * speed(minimun value). So bit 12 and 13 should be cleared together.
342 	 */
343 	val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
344 	val &= ~HISI_HIP08_CORE_COMMIT_MASK;
345 	val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
346 	write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
347 }
348 
349 static struct etm4_arch_features etm4_features[] = {
350 	[ETM4_IMPDEF_HISI_CORE_COMMIT] = {
351 		.arch_callback = etm4_hisi_config_core_commit,
352 	},
353 	{},
354 };
355 
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)356 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
357 {
358 	struct etm4_arch_features *ftr;
359 	int bit;
360 
361 	for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
362 		ftr = &etm4_features[bit];
363 
364 		if (ftr->arch_callback)
365 			ftr->arch_callback(true);
366 	}
367 }
368 
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)369 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
370 {
371 	struct etm4_arch_features *ftr;
372 	int bit;
373 
374 	for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
375 		ftr = &etm4_features[bit];
376 
377 		if (ftr->arch_callback)
378 			ftr->arch_callback(false);
379 	}
380 }
381 
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)382 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
383 				     struct csdev_access *csa)
384 {
385 	/*
386 	 * TRCPIDR* registers are not required for ETMs with system
387 	 * instructions. They must be identified by the MIDR+REVIDRs.
388 	 * Skip the TRCPID checks for now.
389 	 */
390 	if (!csa->io_mem)
391 		return;
392 
393 	if (etm4_hisi_match_pid(coresight_get_pid(csa)))
394 		set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
395 }
396 #else
etm4_enable_arch_specific(struct etmv4_drvdata * drvdata)397 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
398 {
399 }
400 
etm4_disable_arch_specific(struct etmv4_drvdata * drvdata)401 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
402 {
403 }
404 
etm4_check_arch_features(struct etmv4_drvdata * drvdata,struct csdev_access * csa)405 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
406 				     struct csdev_access *csa)
407 {
408 }
409 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
410 
etm4x_sys_ins_barrier(struct csdev_access * csa,u32 offset,int pos,int val)411 static void etm4x_sys_ins_barrier(struct csdev_access *csa, u32 offset, int pos, int val)
412 {
413 	if (!csa->io_mem)
414 		isb();
415 }
416 
417 /*
418  * etm4x_wait_status: Poll for TRCSTATR.<pos> == <val>. While using system
419  * instruction to access the trace unit, each access must be separated by a
420  * synchronization barrier. See ARM IHI0064H.b section "4.3.7 Synchronization of
421  * register updates", for system instructions section, in "Notes":
422  *
423  *   "In particular, whenever disabling or enabling the trace unit, a poll of
424  *    TRCSTATR needs explicit synchronization between each read of TRCSTATR"
425  */
etm4x_wait_status(struct csdev_access * csa,int pos,int val)426 static int etm4x_wait_status(struct csdev_access *csa, int pos, int val)
427 {
428 	if (!csa->io_mem)
429 		return coresight_timeout_action(csa, TRCSTATR, pos, val,
430 						etm4x_sys_ins_barrier);
431 	return coresight_timeout(csa, TRCSTATR, pos, val);
432 }
433 
etm4_enable_hw(struct etmv4_drvdata * drvdata)434 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
435 {
436 	int i, rc;
437 	struct etmv4_config *config = &drvdata->config;
438 	struct coresight_device *csdev = drvdata->csdev;
439 	struct device *etm_dev = &csdev->dev;
440 	struct csdev_access *csa = &csdev->access;
441 
442 
443 	etm4_cs_unlock(drvdata, csa);
444 	etm4_enable_arch_specific(drvdata);
445 
446 	etm4_os_unlock(drvdata);
447 
448 	rc = coresight_claim_device_unlocked(csdev);
449 	if (rc)
450 		goto done;
451 
452 	/* Disable the trace unit before programming trace registers */
453 	etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
454 
455 	/*
456 	 * If we use system instructions, we need to synchronize the
457 	 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
458 	 * See ARM IHI0064F, section
459 	 * "4.3.7 Synchronization of register updates"
460 	 */
461 	if (!csa->io_mem)
462 		isb();
463 
464 	/* wait for TRCSTATR.IDLE to go up */
465 	if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1))
466 		dev_err(etm_dev,
467 			"timeout while waiting for Idle Trace Status\n");
468 	if (drvdata->nr_pe)
469 		etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
470 	etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
471 	/* nothing specific implemented */
472 	etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
473 	etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
474 	etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
475 	if (drvdata->stallctl)
476 		etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
477 	etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
478 	etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
479 	etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
480 	etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
481 	etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
482 	etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
483 	etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
484 	etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
485 	if (drvdata->nr_pe_cmp)
486 		etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
487 	for (i = 0; i < drvdata->nrseqstate - 1; i++)
488 		etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
489 	if (drvdata->nrseqstate) {
490 		etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
491 		etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
492 	}
493 	etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
494 	for (i = 0; i < drvdata->nr_cntr; i++) {
495 		etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
496 		etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
497 		etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
498 	}
499 
500 	/*
501 	 * Resource selector pair 0 is always implemented and reserved.  As
502 	 * such start at 2.
503 	 */
504 	for (i = 2; i < drvdata->nr_resource * 2; i++)
505 		etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
506 
507 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
508 		/* always clear status bit on restart if using single-shot */
509 		if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
510 			config->ss_status[i] &= ~TRCSSCSRn_STATUS;
511 		etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
512 		etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
513 		if (etm4x_sspcicrn_present(drvdata, i))
514 			etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
515 	}
516 	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
517 		etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
518 		etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
519 	}
520 	for (i = 0; i < drvdata->numcidc; i++)
521 		etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
522 	etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
523 	if (drvdata->numcidc > 4)
524 		etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
525 
526 	for (i = 0; i < drvdata->numvmidc; i++)
527 		etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
528 	etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
529 	if (drvdata->numvmidc > 4)
530 		etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
531 
532 	if (!drvdata->skip_power_up) {
533 		u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
534 
535 		/*
536 		 * Request to keep the trace unit powered and also
537 		 * emulation of powerdown
538 		 */
539 		etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
540 	}
541 
542 	/*
543 	 * ETE mandates that the TRCRSR is written to before
544 	 * enabling it.
545 	 */
546 	if (etm4x_is_ete(drvdata))
547 		etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
548 
549 	etm4x_allow_trace(drvdata);
550 	/* Enable the trace unit */
551 	etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
552 
553 	/* Synchronize the register updates for sysreg access */
554 	if (!csa->io_mem)
555 		isb();
556 
557 	/* wait for TRCSTATR.IDLE to go back down to '0' */
558 	if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0))
559 		dev_err(etm_dev,
560 			"timeout while waiting for Idle Trace Status\n");
561 
562 	/*
563 	 * As recommended by section 4.3.7 ("Synchronization when using the
564 	 * memory-mapped interface") of ARM IHI 0064D
565 	 */
566 	dsb(sy);
567 	isb();
568 
569 done:
570 	etm4_cs_lock(drvdata, csa);
571 
572 	dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
573 		drvdata->cpu, rc);
574 	return rc;
575 }
576 
etm4_enable_hw_smp_call(void * info)577 static void etm4_enable_hw_smp_call(void *info)
578 {
579 	struct etm4_enable_arg *arg = info;
580 
581 	if (WARN_ON(!arg))
582 		return;
583 	arg->rc = etm4_enable_hw(arg->drvdata);
584 }
585 
586 /*
587  * The goal of function etm4_config_timestamp_event() is to configure a
588  * counter that will tell the tracer to emit a timestamp packet when it
589  * reaches zero.  This is done in order to get a more fine grained idea
590  * of when instructions are executed so that they can be correlated
591  * with execution on other CPUs.
592  *
593  * To do this the counter itself is configured to self reload and
594  * TRCRSCTLR1 (always true) used to get the counter to decrement.  From
595  * there a resource selector is configured with the counter and the
596  * timestamp control register to use the resource selector to trigger the
597  * event that will insert a timestamp packet in the stream.
598  */
etm4_config_timestamp_event(struct etmv4_drvdata * drvdata)599 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
600 {
601 	int ctridx, ret = -EINVAL;
602 	int counter, rselector;
603 	u32 val = 0;
604 	struct etmv4_config *config = &drvdata->config;
605 
606 	/* No point in trying if we don't have at least one counter */
607 	if (!drvdata->nr_cntr)
608 		goto out;
609 
610 	/* Find a counter that hasn't been initialised */
611 	for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
612 		if (config->cntr_val[ctridx] == 0)
613 			break;
614 
615 	/* All the counters have been configured already, bail out */
616 	if (ctridx == drvdata->nr_cntr) {
617 		pr_debug("%s: no available counter found\n", __func__);
618 		ret = -ENOSPC;
619 		goto out;
620 	}
621 
622 	/*
623 	 * Searching for an available resource selector to use, starting at
624 	 * '2' since every implementation has at least 2 resource selector.
625 	 * ETMIDR4 gives the number of resource selector _pairs_,
626 	 * hence multiply by 2.
627 	 */
628 	for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
629 		if (!config->res_ctrl[rselector])
630 			break;
631 
632 	if (rselector == drvdata->nr_resource * 2) {
633 		pr_debug("%s: no available resource selector found\n",
634 			 __func__);
635 		ret = -ENOSPC;
636 		goto out;
637 	}
638 
639 	/* Remember what counter we used */
640 	counter = 1 << ctridx;
641 
642 	/*
643 	 * Initialise original and reload counter value to the smallest
644 	 * possible value in order to get as much precision as we can.
645 	 */
646 	config->cntr_val[ctridx] = 1;
647 	config->cntrldvr[ctridx] = 1;
648 
649 	/* Set the trace counter control register */
650 	val =  0x1 << 16	|  /* Bit 16, reload counter automatically */
651 	       0x0 << 7		|  /* Select single resource selector */
652 	       0x1;		   /* Resource selector 1, i.e always true */
653 
654 	config->cntr_ctrl[ctridx] = val;
655 
656 	val = 0x2 << 16		| /* Group 0b0010 - Counter and sequencers */
657 	      counter << 0;	  /* Counter to use */
658 
659 	config->res_ctrl[rselector] = val;
660 
661 	val = 0x0 << 7		| /* Select single resource selector */
662 	      rselector;	  /* Resource selector */
663 
664 	config->ts_ctrl = val;
665 
666 	ret = 0;
667 out:
668 	return ret;
669 }
670 
etm4_parse_event_config(struct coresight_device * csdev,struct perf_event * event)671 static int etm4_parse_event_config(struct coresight_device *csdev,
672 				   struct perf_event *event)
673 {
674 	int ret = 0;
675 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
676 	struct etmv4_config *config = &drvdata->config;
677 	struct perf_event_attr *attr = &event->attr;
678 	unsigned long cfg_hash;
679 	int preset, cc_threshold;
680 
681 	/* Clear configuration from previous run */
682 	memset(config, 0, sizeof(struct etmv4_config));
683 
684 	if (attr->exclude_kernel)
685 		config->mode = ETM_MODE_EXCL_KERN;
686 
687 	if (attr->exclude_user)
688 		config->mode = ETM_MODE_EXCL_USER;
689 
690 	if (attr->exclude_host)
691 		config->mode |= ETM_MODE_EXCL_HOST;
692 
693 	if (attr->exclude_guest)
694 		config->mode |= ETM_MODE_EXCL_GUEST;
695 
696 	/* Always start from the default config */
697 	etm4_set_default_config(config);
698 
699 	/* Configure filters specified on the perf cmd line, if any. */
700 	ret = etm4_set_event_filters(drvdata, event);
701 	if (ret)
702 		goto out;
703 
704 	/* Go from generic option to ETMv4 specifics */
705 	if (attr->config & BIT(ETM_OPT_CYCACC)) {
706 		config->cfg |= TRCCONFIGR_CCI;
707 		/* TRM: Must program this for cycacc to work */
708 		cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
709 		if (!cc_threshold)
710 			cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
711 		if (cc_threshold < drvdata->ccitmin)
712 			cc_threshold = drvdata->ccitmin;
713 		config->ccctlr = cc_threshold;
714 	}
715 	if (attr->config & BIT(ETM_OPT_TS)) {
716 		/*
717 		 * Configure timestamps to be emitted at regular intervals in
718 		 * order to correlate instructions executed on different CPUs
719 		 * (CPU-wide trace scenarios).
720 		 */
721 		ret = etm4_config_timestamp_event(drvdata);
722 
723 		/*
724 		 * No need to go further if timestamp intervals can't
725 		 * be configured.
726 		 */
727 		if (ret)
728 			goto out;
729 
730 		/* bit[11], Global timestamp tracing bit */
731 		config->cfg |= TRCCONFIGR_TS;
732 	}
733 
734 	/* Only trace contextID when runs in root PID namespace */
735 	if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
736 	    task_is_in_init_pid_ns(current))
737 		/* bit[6], Context ID tracing bit */
738 		config->cfg |= TRCCONFIGR_CID;
739 
740 	/*
741 	 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
742 	 * for recording CONTEXTIDR_EL2.  Do not enable VMID tracing if the
743 	 * kernel is not running in EL2.
744 	 */
745 	if (attr->config & BIT(ETM_OPT_CTXTID2)) {
746 		if (!is_kernel_in_hyp_mode()) {
747 			ret = -EINVAL;
748 			goto out;
749 		}
750 		/* Only trace virtual contextID when runs in root PID namespace */
751 		if (task_is_in_init_pid_ns(current))
752 			config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
753 	}
754 
755 	/* return stack - enable if selected and supported */
756 	if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
757 		/* bit[12], Return stack enable bit */
758 		config->cfg |= TRCCONFIGR_RS;
759 
760 	/*
761 	 * Set any selected configuration and preset.
762 	 *
763 	 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
764 	 * in the perf attributes defined in coresight-etm-perf.c.
765 	 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
766 	 * A zero configid means no configuration active, preset = 0 means no preset selected.
767 	 */
768 	if (attr->config2 & GENMASK_ULL(63, 32)) {
769 		cfg_hash = (u32)(attr->config2 >> 32);
770 		preset = attr->config & 0xF;
771 		ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
772 	}
773 
774 	/* branch broadcast - enable if selected and supported */
775 	if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
776 		if (!drvdata->trcbb) {
777 			/*
778 			 * Missing BB support could cause silent decode errors
779 			 * so fail to open if it's not supported.
780 			 */
781 			ret = -EINVAL;
782 			goto out;
783 		} else {
784 			config->cfg |= BIT(ETM4_CFG_BIT_BB);
785 		}
786 	}
787 
788 out:
789 	return ret;
790 }
791 
etm4_enable_perf(struct coresight_device * csdev,struct perf_event * event,struct coresight_path * path)792 static int etm4_enable_perf(struct coresight_device *csdev,
793 			    struct perf_event *event,
794 			    struct coresight_path *path)
795 {
796 	int ret = 0;
797 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
798 
799 	if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
800 		ret = -EINVAL;
801 		goto out;
802 	}
803 
804 	/* Configure the tracer based on the session's specifics */
805 	ret = etm4_parse_event_config(csdev, event);
806 	if (ret)
807 		goto out;
808 
809 	drvdata->trcid = path->trace_id;
810 
811 	/* And enable it */
812 	ret = etm4_enable_hw(drvdata);
813 
814 out:
815 	return ret;
816 }
817 
etm4_enable_sysfs(struct coresight_device * csdev,struct coresight_path * path)818 static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_path *path)
819 {
820 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
821 	struct etm4_enable_arg arg = { };
822 	unsigned long cfg_hash;
823 	int ret, preset;
824 
825 	/* enable any config activated by configfs */
826 	cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
827 	if (cfg_hash) {
828 		ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
829 		if (ret)
830 			return ret;
831 	}
832 
833 	raw_spin_lock(&drvdata->spinlock);
834 
835 	drvdata->trcid = path->trace_id;
836 
837 	/*
838 	 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
839 	 * ensures that register writes occur when cpu is powered.
840 	 */
841 	arg.drvdata = drvdata;
842 	ret = smp_call_function_single(drvdata->cpu,
843 				       etm4_enable_hw_smp_call, &arg, 1);
844 	if (!ret)
845 		ret = arg.rc;
846 	if (!ret)
847 		drvdata->sticky_enable = true;
848 
849 	if (ret)
850 		etm4_release_trace_id(drvdata);
851 
852 	raw_spin_unlock(&drvdata->spinlock);
853 
854 	if (!ret)
855 		dev_dbg(&csdev->dev, "ETM tracing enabled\n");
856 	return ret;
857 }
858 
etm4_enable(struct coresight_device * csdev,struct perf_event * event,enum cs_mode mode,struct coresight_path * path)859 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
860 		       enum cs_mode mode, struct coresight_path *path)
861 {
862 	int ret;
863 
864 	if (!coresight_take_mode(csdev, mode)) {
865 		/* Someone is already using the tracer */
866 		return -EBUSY;
867 	}
868 
869 	switch (mode) {
870 	case CS_MODE_SYSFS:
871 		ret = etm4_enable_sysfs(csdev, path);
872 		break;
873 	case CS_MODE_PERF:
874 		ret = etm4_enable_perf(csdev, event, path);
875 		break;
876 	default:
877 		ret = -EINVAL;
878 	}
879 
880 	/* The tracer didn't start */
881 	if (ret)
882 		coresight_set_mode(csdev, CS_MODE_DISABLED);
883 
884 	return ret;
885 }
886 
etm4_disable_hw(void * info)887 static void etm4_disable_hw(void *info)
888 {
889 	u32 control;
890 	struct etmv4_drvdata *drvdata = info;
891 	struct etmv4_config *config = &drvdata->config;
892 	struct coresight_device *csdev = drvdata->csdev;
893 	struct device *etm_dev = &csdev->dev;
894 	struct csdev_access *csa = &csdev->access;
895 	int i;
896 
897 	etm4_cs_unlock(drvdata, csa);
898 	etm4_disable_arch_specific(drvdata);
899 
900 	if (!drvdata->skip_power_up) {
901 		/* power can be removed from the trace unit now */
902 		control = etm4x_relaxed_read32(csa, TRCPDCR);
903 		control &= ~TRCPDCR_PU;
904 		etm4x_relaxed_write32(csa, control, TRCPDCR);
905 	}
906 
907 	control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
908 
909 	/* EN, bit[0] Trace unit enable bit */
910 	control &= ~0x1;
911 
912 	/*
913 	 * If the CPU supports v8.4 Trace filter Control,
914 	 * set the ETM to trace prohibited region.
915 	 */
916 	etm4x_prohibit_trace(drvdata);
917 	/*
918 	 * Make sure everything completes before disabling, as recommended
919 	 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
920 	 * SSTATUS") of ARM IHI 0064D
921 	 */
922 	dsb(sy);
923 	isb();
924 	/* Trace synchronization barrier, is a nop if not supported */
925 	tsb_csync();
926 	etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
927 
928 	/*
929 	 * As recommended by section 4.3.7 ("Synchronization when using system
930 	 * instructions to progrom the trace unit") of ARM IHI 0064H.b, the
931 	 * self-hosted trace analyzer must perform a Context synchronization
932 	 * event between writing to the TRCPRGCTLR and reading the TRCSTATR.
933 	 */
934 	if (!csa->io_mem)
935 		isb();
936 
937 	/* wait for TRCSTATR.PMSTABLE to go to '1' */
938 	if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1))
939 		dev_err(etm_dev,
940 			"timeout while waiting for PM stable Trace Status\n");
941 	/*
942 	 * As recommended by section 4.3.7 (Synchronization of register updates)
943 	 * of ARM IHI 0064H.b.
944 	 */
945 	isb();
946 
947 	/* read the status of the single shot comparators */
948 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
949 		config->ss_status[i] =
950 			etm4x_relaxed_read32(csa, TRCSSCSRn(i));
951 	}
952 
953 	/* read back the current counter values */
954 	for (i = 0; i < drvdata->nr_cntr; i++) {
955 		config->cntr_val[i] =
956 			etm4x_relaxed_read32(csa, TRCCNTVRn(i));
957 	}
958 
959 	coresight_disclaim_device_unlocked(csdev);
960 	etm4_cs_lock(drvdata, csa);
961 
962 	dev_dbg(&drvdata->csdev->dev,
963 		"cpu: %d disable smp call done\n", drvdata->cpu);
964 }
965 
etm4_disable_perf(struct coresight_device * csdev,struct perf_event * event)966 static int etm4_disable_perf(struct coresight_device *csdev,
967 			     struct perf_event *event)
968 {
969 	u32 control;
970 	struct etm_filters *filters = event->hw.addr_filters;
971 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
972 	struct perf_event_attr *attr = &event->attr;
973 
974 	if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
975 		return -EINVAL;
976 
977 	etm4_disable_hw(drvdata);
978 	/*
979 	 * The config_id occupies bits 63:32 of the config2 perf event attr
980 	 * field. If this is non-zero then we will have enabled a config.
981 	 */
982 	if (attr->config2 & GENMASK_ULL(63, 32))
983 		cscfg_csdev_disable_active_config(csdev);
984 
985 	/*
986 	 * Check if the start/stop logic was active when the unit was stopped.
987 	 * That way we can re-enable the start/stop logic when the process is
988 	 * scheduled again.  Configuration of the start/stop logic happens in
989 	 * function etm4_set_event_filters().
990 	 */
991 	control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
992 	/* TRCVICTLR::SSSTATUS, bit[9] */
993 	filters->ssstatus = (control & BIT(9));
994 
995 	/*
996 	 * perf will release trace ids when _free_aux() is
997 	 * called at the end of the session.
998 	 */
999 
1000 	return 0;
1001 }
1002 
etm4_disable_sysfs(struct coresight_device * csdev)1003 static void etm4_disable_sysfs(struct coresight_device *csdev)
1004 {
1005 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1006 
1007 	/*
1008 	 * Taking hotplug lock here protects from clocks getting disabled
1009 	 * with tracing being left on (crash scenario) if user disable occurs
1010 	 * after cpu online mask indicates the cpu is offline but before the
1011 	 * DYING hotplug callback is serviced by the ETM driver.
1012 	 */
1013 	cpus_read_lock();
1014 	raw_spin_lock(&drvdata->spinlock);
1015 
1016 	/*
1017 	 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
1018 	 * ensures that register writes occur when cpu is powered.
1019 	 */
1020 	smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
1021 
1022 	raw_spin_unlock(&drvdata->spinlock);
1023 	cpus_read_unlock();
1024 
1025 	/*
1026 	 * we only release trace IDs when resetting sysfs.
1027 	 * This permits sysfs users to read the trace ID after the trace
1028 	 * session has completed. This maintains operational behaviour with
1029 	 * prior trace id allocation method
1030 	 */
1031 
1032 	dev_dbg(&csdev->dev, "ETM tracing disabled\n");
1033 }
1034 
etm4_disable(struct coresight_device * csdev,struct perf_event * event)1035 static void etm4_disable(struct coresight_device *csdev,
1036 			 struct perf_event *event)
1037 {
1038 	enum cs_mode mode;
1039 
1040 	/*
1041 	 * For as long as the tracer isn't disabled another entity can't
1042 	 * change its status.  As such we can read the status here without
1043 	 * fearing it will change under us.
1044 	 */
1045 	mode = coresight_get_mode(csdev);
1046 
1047 	switch (mode) {
1048 	case CS_MODE_DISABLED:
1049 		break;
1050 	case CS_MODE_SYSFS:
1051 		etm4_disable_sysfs(csdev);
1052 		break;
1053 	case CS_MODE_PERF:
1054 		etm4_disable_perf(csdev, event);
1055 		break;
1056 	}
1057 
1058 	if (mode)
1059 		coresight_set_mode(csdev, CS_MODE_DISABLED);
1060 }
1061 
1062 static const struct coresight_ops_source etm4_source_ops = {
1063 	.cpu_id		= etm4_cpu_id,
1064 	.enable		= etm4_enable,
1065 	.disable	= etm4_disable,
1066 };
1067 
1068 static const struct coresight_ops etm4_cs_ops = {
1069 	.trace_id	= coresight_etm_get_trace_id,
1070 	.source_ops	= &etm4_source_ops,
1071 };
1072 
cpu_supports_sysreg_trace(void)1073 static inline bool cpu_supports_sysreg_trace(void)
1074 {
1075 	u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1076 
1077 	return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1078 }
1079 
etm4_init_sysreg_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1080 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1081 				    struct csdev_access *csa)
1082 {
1083 	u32 devarch;
1084 
1085 	if (!cpu_supports_sysreg_trace())
1086 		return false;
1087 
1088 	/*
1089 	 * ETMs implementing sysreg access must implement TRCDEVARCH.
1090 	 */
1091 	devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1092 	switch (devarch & ETM_DEVARCH_ID_MASK) {
1093 	case ETM_DEVARCH_ETMv4x_ARCH:
1094 		*csa = (struct csdev_access) {
1095 			.io_mem	= false,
1096 			.read	= etm4x_sysreg_read,
1097 			.write	= etm4x_sysreg_write,
1098 		};
1099 		break;
1100 	case ETM_DEVARCH_ETE_ARCH:
1101 		*csa = (struct csdev_access) {
1102 			.io_mem	= false,
1103 			.read	= ete_sysreg_read,
1104 			.write	= ete_sysreg_write,
1105 		};
1106 		break;
1107 	default:
1108 		return false;
1109 	}
1110 
1111 	drvdata->arch = etm_devarch_to_arch(devarch);
1112 	return true;
1113 }
1114 
is_devtype_cpu_trace(void __iomem * base)1115 static bool is_devtype_cpu_trace(void __iomem *base)
1116 {
1117 	u32 devtype = readl(base + TRCDEVTYPE);
1118 
1119 	return (devtype == CS_DEVTYPE_PE_TRACE);
1120 }
1121 
etm4_init_iomem_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1122 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1123 				   struct csdev_access *csa)
1124 {
1125 	u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1126 
1127 	if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1128 		return false;
1129 
1130 	/*
1131 	 * All ETMs must implement TRCDEVARCH to indicate that
1132 	 * the component is an ETMv4. Even though TRCIDR1 also
1133 	 * contains the information, it is part of the "Trace"
1134 	 * register and must be accessed with the OSLK cleared,
1135 	 * with MMIO. But we cannot touch the OSLK until we are
1136 	 * sure this is an ETM. So rely only on the TRCDEVARCH.
1137 	 */
1138 	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1139 		pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1140 		return false;
1141 	}
1142 
1143 	drvdata->arch = etm_devarch_to_arch(devarch);
1144 	*csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1145 	return true;
1146 }
1147 
etm4_init_csdev_access(struct etmv4_drvdata * drvdata,struct csdev_access * csa)1148 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1149 				   struct csdev_access *csa)
1150 {
1151 	/*
1152 	 * Always choose the memory mapped io, if there is
1153 	 * a memory map to prevent sysreg access on broken
1154 	 * systems.
1155 	 */
1156 	if (drvdata->base)
1157 		return etm4_init_iomem_access(drvdata, csa);
1158 
1159 	if (etm4_init_sysreg_access(drvdata, csa))
1160 		return true;
1161 
1162 	return false;
1163 }
1164 
cpu_detect_trace_filtering(struct etmv4_drvdata * drvdata)1165 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1166 {
1167 	u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1168 	u64 trfcr;
1169 
1170 	drvdata->trfcr = 0;
1171 	if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1172 		return;
1173 
1174 	/*
1175 	 * If the CPU supports v8.4 SelfHosted Tracing, enable
1176 	 * tracing at the kernel EL and EL0, forcing to use the
1177 	 * virtual time as the timestamp.
1178 	 */
1179 	trfcr = (TRFCR_EL1_TS_VIRTUAL |
1180 		 TRFCR_EL1_ExTRE |
1181 		 TRFCR_EL1_E0TRE);
1182 
1183 	/* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1184 	if (is_kernel_in_hyp_mode())
1185 		trfcr |= TRFCR_EL2_CX;
1186 
1187 	drvdata->trfcr = trfcr;
1188 }
1189 
1190 /*
1191  * The following errata on applicable cpu ranges, affect the CCITMIN filed
1192  * in TCRIDR3 register. Software read for the field returns 0x100 limiting
1193  * the cycle threshold granularity, whereas the right value should have
1194  * been 0x4, which is well supported in the hardware.
1195  */
1196 static struct midr_range etm_wrong_ccitmin_cpus[] = {
1197 	/* Erratum #1490853 - Cortex-A76 */
1198 	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
1199 	/* Erratum #1490853 - Neoverse-N1 */
1200 	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
1201 	/* Erratum #1491015 - Cortex-A77 */
1202 	MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
1203 	/* Erratum #1502854 - Cortex-X1 */
1204 	MIDR_REV(MIDR_CORTEX_X1, 0, 0),
1205 	/* Erratum #1619801 - Neoverse-V1 */
1206 	MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
1207 	{},
1208 };
1209 
etm4_fixup_wrong_ccitmin(struct etmv4_drvdata * drvdata)1210 static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
1211 {
1212 	/*
1213 	 * Erratum affected cpus will read 256 as the minimum
1214 	 * instruction trace cycle counting threshold whereas
1215 	 * the correct value should be 4 instead. Override the
1216 	 * recorded value for 'drvdata->ccitmin' to workaround
1217 	 * this problem.
1218 	 */
1219 	if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) {
1220 		if (drvdata->ccitmin == 256)
1221 			drvdata->ccitmin = 4;
1222 	}
1223 }
1224 
etm4_init_arch_data(void * info)1225 static void etm4_init_arch_data(void *info)
1226 {
1227 	u32 etmidr0;
1228 	u32 etmidr2;
1229 	u32 etmidr3;
1230 	u32 etmidr4;
1231 	u32 etmidr5;
1232 	struct etm4_init_arg *init_arg = info;
1233 	struct etmv4_drvdata *drvdata;
1234 	struct csdev_access *csa;
1235 	struct device *dev = init_arg->dev;
1236 	int i;
1237 
1238 	drvdata = dev_get_drvdata(init_arg->dev);
1239 	csa = init_arg->csa;
1240 
1241 	/*
1242 	 * If we are unable to detect the access mechanism,
1243 	 * or unable to detect the trace unit type, fail
1244 	 * early.
1245 	 */
1246 	if (!etm4_init_csdev_access(drvdata, csa))
1247 		return;
1248 
1249 	if (!csa->io_mem ||
1250 	    fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
1251 		drvdata->skip_power_up = true;
1252 
1253 	/* Detect the support for OS Lock before we actually use it */
1254 	etm_detect_os_lock(drvdata, csa);
1255 
1256 	/* Make sure all registers are accessible */
1257 	etm4_os_unlock_csa(drvdata, csa);
1258 	etm4_cs_unlock(drvdata, csa);
1259 
1260 	etm4_check_arch_features(drvdata, csa);
1261 
1262 	/* find all capabilities of the tracing unit */
1263 	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1264 
1265 	/* INSTP0, bits[2:1] P0 tracing support field */
1266 	drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1267 	/* TRCBB, bit[5] Branch broadcast tracing support bit */
1268 	drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1269 	/* TRCCOND, bit[6] Conditional instruction tracing support bit */
1270 	drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1271 	/* TRCCCI, bit[7] Cycle counting instruction bit */
1272 	drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1273 	/* RETSTACK, bit[9] Return stack bit */
1274 	drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1275 	/* NUMEVENT, bits[11:10] Number of events field */
1276 	drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1277 	/* QSUPP, bits[16:15] Q element support field */
1278 	drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1279 	if (drvdata->q_support)
1280 		drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
1281 	/* TSSIZE, bits[28:24] Global timestamp size field */
1282 	drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1283 
1284 	/* maximum size of resources */
1285 	etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1286 	/* CIDSIZE, bits[9:5] Indicates the Context ID size */
1287 	drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1288 	/* VMIDSIZE, bits[14:10] Indicates the VMID size */
1289 	drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1290 	/* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1291 	drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1292 
1293 	etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1294 	/* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1295 	drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1296 	etm4_fixup_wrong_ccitmin(drvdata);
1297 
1298 	/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1299 	drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1300 	drvdata->config.s_ex_level = drvdata->s_ex_level;
1301 	/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1302 	drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1303 	/*
1304 	 * TRCERR, bit[24] whether a trace unit can trace a
1305 	 * system error exception.
1306 	 */
1307 	drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1308 	/* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1309 	drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1310 	/* STALLCTL, bit[26] is stall control implemented? */
1311 	drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1312 	/* SYSSTALL, bit[27] implementation can support stall control? */
1313 	drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1314 	/*
1315 	 * NUMPROC - the number of PEs available for tracing, 5bits
1316 	 *         = TRCIDR3.bits[13:12]bits[30:28]
1317 	 *  bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1318 	 *  bits[3:0] = TRCIDR3.bits[30:28]
1319 	 */
1320 	drvdata->nr_pe =  (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1321 			   FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1322 	/* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1323 	drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1324 
1325 	/* number of resources trace unit supports */
1326 	etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1327 	/* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1328 	drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1329 	/* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1330 	drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1331 	/*
1332 	 * NUMRSPAIR, bits[19:16]
1333 	 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1334 	 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1335 	 * As such add 1 to the value of NUMRSPAIR for a better representation.
1336 	 *
1337 	 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1338 	 * the default TRUE and FALSE resource selectors are omitted.
1339 	 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1340 	 */
1341 	drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1342 	if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1343 		drvdata->nr_resource += 1;
1344 	/*
1345 	 * NUMSSCC, bits[23:20] the number of single-shot
1346 	 * comparator control for tracing. Read any status regs as these
1347 	 * also contain RO capability data.
1348 	 */
1349 	drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1350 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1351 		drvdata->config.ss_status[i] =
1352 			etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1353 	}
1354 	/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1355 	drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1356 	/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1357 	drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1358 
1359 	etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1360 	/* NUMEXTIN, bits[8:0] number of external inputs implemented */
1361 	drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1362 	/* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1363 	drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1364 	/* ATBTRIG, bit[22] implementation can support ATB triggers? */
1365 	drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1366 	/*
1367 	 * LPOVERRIDE, bit[23] implementation supports
1368 	 * low-power state override
1369 	 */
1370 	drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1371 	/* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1372 	drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1373 	/* NUMCNTR, bits[30:28] number of counters available for tracing */
1374 	drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1375 	etm4_cs_lock(drvdata, csa);
1376 	cpu_detect_trace_filtering(drvdata);
1377 }
1378 
etm4_get_victlr_access_type(struct etmv4_config * config)1379 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1380 {
1381 	return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1382 }
1383 
1384 /* Set ELx trace filter access in the TRCVICTLR register */
etm4_set_victlr_access(struct etmv4_config * config)1385 static void etm4_set_victlr_access(struct etmv4_config *config)
1386 {
1387 	config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1388 	config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1389 }
1390 
etm4_set_default_config(struct etmv4_config * config)1391 static void etm4_set_default_config(struct etmv4_config *config)
1392 {
1393 	/* disable all events tracing */
1394 	config->eventctrl0 = 0x0;
1395 	config->eventctrl1 = 0x0;
1396 
1397 	/* disable stalling */
1398 	config->stall_ctrl = 0x0;
1399 
1400 	/* enable trace synchronization every 4096 bytes, if available */
1401 	config->syncfreq = 0xC;
1402 
1403 	/* disable timestamp event */
1404 	config->ts_ctrl = 0x0;
1405 
1406 	/* TRCVICTLR::EVENT = 0x01, select the always on logic */
1407 	config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1408 
1409 	/* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1410 	etm4_set_victlr_access(config);
1411 }
1412 
etm4_get_ns_access_type(struct etmv4_config * config)1413 static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1414 {
1415 	u64 access_type = 0;
1416 
1417 	/*
1418 	 * EXLEVEL_NS, for NonSecure Exception levels.
1419 	 * The mask here is a generic value and must be
1420 	 * shifted to the corresponding field for the registers
1421 	 */
1422 	if (!is_kernel_in_hyp_mode()) {
1423 		/* Stay away from hypervisor mode for non-VHE */
1424 		access_type =  ETM_EXLEVEL_NS_HYP;
1425 		if (config->mode & ETM_MODE_EXCL_KERN)
1426 			access_type |= ETM_EXLEVEL_NS_OS;
1427 	} else if (config->mode & ETM_MODE_EXCL_KERN) {
1428 		access_type = ETM_EXLEVEL_NS_HYP;
1429 	}
1430 
1431 	if (config->mode & ETM_MODE_EXCL_USER)
1432 		access_type |= ETM_EXLEVEL_NS_APP;
1433 
1434 	return access_type;
1435 }
1436 
1437 /*
1438  * Construct the exception level masks for a given config.
1439  * This must be shifted to the corresponding register field
1440  * for usage.
1441  */
etm4_get_access_type(struct etmv4_config * config)1442 static u64 etm4_get_access_type(struct etmv4_config *config)
1443 {
1444 	/* All Secure exception levels are excluded from the trace */
1445 	return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1446 }
1447 
etm4_get_comparator_access_type(struct etmv4_config * config)1448 static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1449 {
1450 	return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1451 }
1452 
etm4_set_comparator_filter(struct etmv4_config * config,u64 start,u64 stop,int comparator)1453 static void etm4_set_comparator_filter(struct etmv4_config *config,
1454 				       u64 start, u64 stop, int comparator)
1455 {
1456 	u64 access_type = etm4_get_comparator_access_type(config);
1457 
1458 	/* First half of default address comparator */
1459 	config->addr_val[comparator] = start;
1460 	config->addr_acc[comparator] = access_type;
1461 	config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1462 
1463 	/* Second half of default address comparator */
1464 	config->addr_val[comparator + 1] = stop;
1465 	config->addr_acc[comparator + 1] = access_type;
1466 	config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1467 
1468 	/*
1469 	 * Configure the ViewInst function to include this address range
1470 	 * comparator.
1471 	 *
1472 	 * @comparator is divided by two since it is the index in the
1473 	 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1474 	 * address range comparator _pairs_.
1475 	 *
1476 	 * Therefore:
1477 	 *	index 0 -> compatator pair 0
1478 	 *	index 2 -> comparator pair 1
1479 	 *	index 4 -> comparator pair 2
1480 	 *	...
1481 	 *	index 14 -> comparator pair 7
1482 	 */
1483 	config->viiectlr |= BIT(comparator / 2);
1484 }
1485 
etm4_set_start_stop_filter(struct etmv4_config * config,u64 address,int comparator,enum etm_addr_type type)1486 static void etm4_set_start_stop_filter(struct etmv4_config *config,
1487 				       u64 address, int comparator,
1488 				       enum etm_addr_type type)
1489 {
1490 	int shift;
1491 	u64 access_type = etm4_get_comparator_access_type(config);
1492 
1493 	/* Configure the comparator */
1494 	config->addr_val[comparator] = address;
1495 	config->addr_acc[comparator] = access_type;
1496 	config->addr_type[comparator] = type;
1497 
1498 	/*
1499 	 * Configure ViewInst Start-Stop control register.
1500 	 * Addresses configured to start tracing go from bit 0 to n-1,
1501 	 * while those configured to stop tracing from 16 to 16 + n-1.
1502 	 */
1503 	shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1504 	config->vissctlr |= BIT(shift + comparator);
1505 }
1506 
etm4_set_default_filter(struct etmv4_config * config)1507 static void etm4_set_default_filter(struct etmv4_config *config)
1508 {
1509 	/* Trace everything 'default' filter achieved by no filtering */
1510 	config->viiectlr = 0x0;
1511 
1512 	/*
1513 	 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1514 	 * in the started state
1515 	 */
1516 	config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1517 	config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1518 
1519 	/* No start-stop filtering for ViewInst */
1520 	config->vissctlr = 0x0;
1521 }
1522 
etm4_set_default(struct etmv4_config * config)1523 static void etm4_set_default(struct etmv4_config *config)
1524 {
1525 	if (WARN_ON_ONCE(!config))
1526 		return;
1527 
1528 	/*
1529 	 * Make default initialisation trace everything
1530 	 *
1531 	 * This is done by a minimum default config sufficient to enable
1532 	 * full instruction trace - with a default filter for trace all
1533 	 * achieved by having no filtering.
1534 	 */
1535 	etm4_set_default_config(config);
1536 	etm4_set_default_filter(config);
1537 }
1538 
etm4_get_next_comparator(struct etmv4_drvdata * drvdata,u32 type)1539 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1540 {
1541 	int nr_comparator, index = 0;
1542 	struct etmv4_config *config = &drvdata->config;
1543 
1544 	/*
1545 	 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1546 	 * for the total number of comparators.
1547 	 */
1548 	nr_comparator = drvdata->nr_addr_cmp * 2;
1549 
1550 	/* Go through the tally of comparators looking for a free one. */
1551 	while (index < nr_comparator) {
1552 		switch (type) {
1553 		case ETM_ADDR_TYPE_RANGE:
1554 			if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1555 			    config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1556 				return index;
1557 
1558 			/* Address range comparators go in pairs */
1559 			index += 2;
1560 			break;
1561 		case ETM_ADDR_TYPE_START:
1562 		case ETM_ADDR_TYPE_STOP:
1563 			if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1564 				return index;
1565 
1566 			/* Start/stop address can have odd indexes */
1567 			index += 1;
1568 			break;
1569 		default:
1570 			return -EINVAL;
1571 		}
1572 	}
1573 
1574 	/* If we are here all the comparators have been used. */
1575 	return -ENOSPC;
1576 }
1577 
etm4_set_event_filters(struct etmv4_drvdata * drvdata,struct perf_event * event)1578 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1579 				  struct perf_event *event)
1580 {
1581 	int i, comparator, ret = 0;
1582 	u64 address;
1583 	struct etmv4_config *config = &drvdata->config;
1584 	struct etm_filters *filters = event->hw.addr_filters;
1585 
1586 	if (!filters)
1587 		goto default_filter;
1588 
1589 	/* Sync events with what Perf got */
1590 	perf_event_addr_filters_sync(event);
1591 
1592 	/*
1593 	 * If there are no filters to deal with simply go ahead with
1594 	 * the default filter, i.e the entire address range.
1595 	 */
1596 	if (!filters->nr_filters)
1597 		goto default_filter;
1598 
1599 	for (i = 0; i < filters->nr_filters; i++) {
1600 		struct etm_filter *filter = &filters->etm_filter[i];
1601 		enum etm_addr_type type = filter->type;
1602 
1603 		/* See if a comparator is free. */
1604 		comparator = etm4_get_next_comparator(drvdata, type);
1605 		if (comparator < 0) {
1606 			ret = comparator;
1607 			goto out;
1608 		}
1609 
1610 		switch (type) {
1611 		case ETM_ADDR_TYPE_RANGE:
1612 			etm4_set_comparator_filter(config,
1613 						   filter->start_addr,
1614 						   filter->stop_addr,
1615 						   comparator);
1616 			/*
1617 			 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1618 			 * in the started state
1619 			 */
1620 			config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1621 
1622 			/* No start-stop filtering for ViewInst */
1623 			config->vissctlr = 0x0;
1624 			break;
1625 		case ETM_ADDR_TYPE_START:
1626 		case ETM_ADDR_TYPE_STOP:
1627 			/* Get the right start or stop address */
1628 			address = (type == ETM_ADDR_TYPE_START ?
1629 				   filter->start_addr :
1630 				   filter->stop_addr);
1631 
1632 			/* Configure comparator */
1633 			etm4_set_start_stop_filter(config, address,
1634 						   comparator, type);
1635 
1636 			/*
1637 			 * If filters::ssstatus == 1, trace acquisition was
1638 			 * started but the process was yanked away before the
1639 			 * stop address was hit.  As such the start/stop
1640 			 * logic needs to be re-started so that tracing can
1641 			 * resume where it left.
1642 			 *
1643 			 * The start/stop logic status when a process is
1644 			 * scheduled out is checked in function
1645 			 * etm4_disable_perf().
1646 			 */
1647 			if (filters->ssstatus)
1648 				config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1649 
1650 			/* No include/exclude filtering for ViewInst */
1651 			config->viiectlr = 0x0;
1652 			break;
1653 		default:
1654 			ret = -EINVAL;
1655 			goto out;
1656 		}
1657 	}
1658 
1659 	goto out;
1660 
1661 
1662 default_filter:
1663 	etm4_set_default_filter(config);
1664 
1665 out:
1666 	return ret;
1667 }
1668 
etm4_config_trace_mode(struct etmv4_config * config)1669 void etm4_config_trace_mode(struct etmv4_config *config)
1670 {
1671 	u32 mode;
1672 
1673 	mode = config->mode;
1674 	mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1675 
1676 	/* excluding kernel AND user space doesn't make sense */
1677 	WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1678 
1679 	/* nothing to do if neither flags are set */
1680 	if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1681 		return;
1682 
1683 	etm4_set_victlr_access(config);
1684 }
1685 
etm4_online_cpu(unsigned int cpu)1686 static int etm4_online_cpu(unsigned int cpu)
1687 {
1688 	if (!etmdrvdata[cpu])
1689 		return etm4_probe_cpu(cpu);
1690 
1691 	if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1692 		coresight_enable_sysfs(etmdrvdata[cpu]->csdev);
1693 	return 0;
1694 }
1695 
etm4_starting_cpu(unsigned int cpu)1696 static int etm4_starting_cpu(unsigned int cpu)
1697 {
1698 	if (!etmdrvdata[cpu])
1699 		return 0;
1700 
1701 	raw_spin_lock(&etmdrvdata[cpu]->spinlock);
1702 	if (!etmdrvdata[cpu]->os_unlock)
1703 		etm4_os_unlock(etmdrvdata[cpu]);
1704 
1705 	if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1706 		etm4_enable_hw(etmdrvdata[cpu]);
1707 	raw_spin_unlock(&etmdrvdata[cpu]->spinlock);
1708 	return 0;
1709 }
1710 
etm4_dying_cpu(unsigned int cpu)1711 static int etm4_dying_cpu(unsigned int cpu)
1712 {
1713 	if (!etmdrvdata[cpu])
1714 		return 0;
1715 
1716 	raw_spin_lock(&etmdrvdata[cpu]->spinlock);
1717 	if (coresight_get_mode(etmdrvdata[cpu]->csdev))
1718 		etm4_disable_hw(etmdrvdata[cpu]);
1719 	raw_spin_unlock(&etmdrvdata[cpu]->spinlock);
1720 	return 0;
1721 }
1722 
__etm4_cpu_save(struct etmv4_drvdata * drvdata)1723 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1724 {
1725 	int i, ret = 0;
1726 	struct etmv4_save_state *state;
1727 	struct coresight_device *csdev = drvdata->csdev;
1728 	struct csdev_access *csa;
1729 	struct device *etm_dev;
1730 
1731 	if (WARN_ON(!csdev))
1732 		return -ENODEV;
1733 
1734 	etm_dev = &csdev->dev;
1735 	csa = &csdev->access;
1736 
1737 	/*
1738 	 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1739 	 * of ARM IHI 0064D
1740 	 */
1741 	dsb(sy);
1742 	isb();
1743 
1744 	etm4_cs_unlock(drvdata, csa);
1745 	/* Lock the OS lock to disable trace and external debugger access */
1746 	etm4_os_lock(drvdata);
1747 
1748 	/* wait for TRCSTATR.PMSTABLE to go up */
1749 	if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1750 		dev_err(etm_dev,
1751 			"timeout while waiting for PM Stable Status\n");
1752 		etm4_os_unlock(drvdata);
1753 		ret = -EBUSY;
1754 		goto out;
1755 	}
1756 
1757 	state = drvdata->save_state;
1758 
1759 	state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1760 	if (drvdata->nr_pe)
1761 		state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1762 	state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1763 	state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1764 	state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1765 	state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1766 	if (drvdata->stallctl)
1767 		state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1768 	state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1769 	state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1770 	state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1771 	state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1772 	state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1773 	if (drvdata->q_filt)
1774 		state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1775 
1776 	state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1777 	state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1778 	state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1779 	if (drvdata->nr_pe_cmp)
1780 		state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1781 
1782 	for (i = 0; i < drvdata->nrseqstate - 1; i++)
1783 		state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1784 
1785 	if (drvdata->nrseqstate) {
1786 		state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1787 		state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1788 	}
1789 	state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1790 
1791 	for (i = 0; i < drvdata->nr_cntr; i++) {
1792 		state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1793 		state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1794 		state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1795 	}
1796 
1797 	/* Resource selector pair 0 is reserved */
1798 	for (i = 2; i < drvdata->nr_resource * 2; i++)
1799 		state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1800 
1801 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1802 		state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1803 		state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1804 		if (etm4x_sspcicrn_present(drvdata, i))
1805 			state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1806 	}
1807 
1808 	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1809 		state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1810 		state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1811 	}
1812 
1813 	/*
1814 	 * Data trace stream is architecturally prohibited for A profile cores
1815 	 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1816 	 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1817 	 * unit") of ARM IHI 0064D.
1818 	 */
1819 
1820 	for (i = 0; i < drvdata->numcidc; i++)
1821 		state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1822 
1823 	for (i = 0; i < drvdata->numvmidc; i++)
1824 		state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1825 
1826 	state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1827 	if (drvdata->numcidc > 4)
1828 		state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1829 
1830 	state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1831 	if (drvdata->numvmidc > 4)
1832 		state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1833 
1834 	state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1835 
1836 	if (!drvdata->skip_power_up)
1837 		state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1838 
1839 	/* wait for TRCSTATR.IDLE to go up */
1840 	if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) {
1841 		dev_err(etm_dev,
1842 			"timeout while waiting for Idle Trace Status\n");
1843 		etm4_os_unlock(drvdata);
1844 		ret = -EBUSY;
1845 		goto out;
1846 	}
1847 
1848 	drvdata->state_needs_restore = true;
1849 
1850 	/*
1851 	 * Power can be removed from the trace unit now. We do this to
1852 	 * potentially save power on systems that respect the TRCPDCR_PU
1853 	 * despite requesting software to save/restore state.
1854 	 */
1855 	if (!drvdata->skip_power_up)
1856 		etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1857 				      TRCPDCR);
1858 out:
1859 	etm4_cs_lock(drvdata, csa);
1860 	return ret;
1861 }
1862 
etm4_cpu_save(struct etmv4_drvdata * drvdata)1863 static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1864 {
1865 	int ret = 0;
1866 
1867 	/* Save the TRFCR irrespective of whether the ETM is ON */
1868 	if (drvdata->trfcr)
1869 		drvdata->save_trfcr = read_trfcr();
1870 	/*
1871 	 * Save and restore the ETM Trace registers only if
1872 	 * the ETM is active.
1873 	 */
1874 	if (coresight_get_mode(drvdata->csdev) && drvdata->save_state)
1875 		ret = __etm4_cpu_save(drvdata);
1876 	return ret;
1877 }
1878 
__etm4_cpu_restore(struct etmv4_drvdata * drvdata)1879 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1880 {
1881 	int i;
1882 	struct etmv4_save_state *state = drvdata->save_state;
1883 	struct csdev_access *csa = &drvdata->csdev->access;
1884 
1885 	if (WARN_ON(!drvdata->csdev))
1886 		return;
1887 
1888 	etm4_cs_unlock(drvdata, csa);
1889 	etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1890 
1891 	etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1892 	if (drvdata->nr_pe)
1893 		etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1894 	etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1895 	etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1896 	etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1897 	etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1898 	if (drvdata->stallctl)
1899 		etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1900 	etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1901 	etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1902 	etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1903 	etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1904 	etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1905 	if (drvdata->q_filt)
1906 		etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1907 
1908 	etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1909 	etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1910 	etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1911 	if (drvdata->nr_pe_cmp)
1912 		etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1913 
1914 	for (i = 0; i < drvdata->nrseqstate - 1; i++)
1915 		etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1916 
1917 	if (drvdata->nrseqstate) {
1918 		etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1919 		etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1920 	}
1921 	etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1922 
1923 	for (i = 0; i < drvdata->nr_cntr; i++) {
1924 		etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1925 		etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1926 		etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1927 	}
1928 
1929 	/* Resource selector pair 0 is reserved */
1930 	for (i = 2; i < drvdata->nr_resource * 2; i++)
1931 		etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1932 
1933 	for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1934 		etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1935 		etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1936 		if (etm4x_sspcicrn_present(drvdata, i))
1937 			etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1938 	}
1939 
1940 	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1941 		etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1942 		etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1943 	}
1944 
1945 	for (i = 0; i < drvdata->numcidc; i++)
1946 		etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1947 
1948 	for (i = 0; i < drvdata->numvmidc; i++)
1949 		etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1950 
1951 	etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1952 	if (drvdata->numcidc > 4)
1953 		etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1954 
1955 	etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1956 	if (drvdata->numvmidc > 4)
1957 		etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1958 
1959 	etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1960 
1961 	if (!drvdata->skip_power_up)
1962 		etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1963 
1964 	drvdata->state_needs_restore = false;
1965 
1966 	/*
1967 	 * As recommended by section 4.3.7 ("Synchronization when using the
1968 	 * memory-mapped interface") of ARM IHI 0064D
1969 	 */
1970 	dsb(sy);
1971 	isb();
1972 
1973 	/* Unlock the OS lock to re-enable trace and external debug access */
1974 	etm4_os_unlock(drvdata);
1975 	etm4_cs_lock(drvdata, csa);
1976 }
1977 
etm4_cpu_restore(struct etmv4_drvdata * drvdata)1978 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1979 {
1980 	if (drvdata->trfcr)
1981 		write_trfcr(drvdata->save_trfcr);
1982 	if (drvdata->state_needs_restore)
1983 		__etm4_cpu_restore(drvdata);
1984 }
1985 
etm4_cpu_pm_notify(struct notifier_block * nb,unsigned long cmd,void * v)1986 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1987 			      void *v)
1988 {
1989 	struct etmv4_drvdata *drvdata;
1990 	unsigned int cpu = smp_processor_id();
1991 
1992 	if (!etmdrvdata[cpu])
1993 		return NOTIFY_OK;
1994 
1995 	drvdata = etmdrvdata[cpu];
1996 
1997 	if (WARN_ON_ONCE(drvdata->cpu != cpu))
1998 		return NOTIFY_BAD;
1999 
2000 	switch (cmd) {
2001 	case CPU_PM_ENTER:
2002 		if (etm4_cpu_save(drvdata))
2003 			return NOTIFY_BAD;
2004 		break;
2005 	case CPU_PM_EXIT:
2006 	case CPU_PM_ENTER_FAILED:
2007 		etm4_cpu_restore(drvdata);
2008 		break;
2009 	default:
2010 		return NOTIFY_DONE;
2011 	}
2012 
2013 	return NOTIFY_OK;
2014 }
2015 
2016 static struct notifier_block etm4_cpu_pm_nb = {
2017 	.notifier_call = etm4_cpu_pm_notify,
2018 };
2019 
2020 /* Setup PM. Deals with error conditions and counts */
etm4_pm_setup(void)2021 static int __init etm4_pm_setup(void)
2022 {
2023 	int ret;
2024 
2025 	ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
2026 	if (ret)
2027 		return ret;
2028 
2029 	ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
2030 					"arm/coresight4:starting",
2031 					etm4_starting_cpu, etm4_dying_cpu);
2032 
2033 	if (ret)
2034 		goto unregister_notifier;
2035 
2036 	ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
2037 					"arm/coresight4:online",
2038 					etm4_online_cpu, NULL);
2039 
2040 	/* HP dyn state ID returned in ret on success */
2041 	if (ret > 0) {
2042 		hp_online = ret;
2043 		return 0;
2044 	}
2045 
2046 	/* failed dyn state - remove others */
2047 	cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2048 
2049 unregister_notifier:
2050 	cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2051 	return ret;
2052 }
2053 
etm4_pm_clear(void)2054 static void etm4_pm_clear(void)
2055 {
2056 	cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2057 	cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2058 	if (hp_online) {
2059 		cpuhp_remove_state_nocalls(hp_online);
2060 		hp_online = 0;
2061 	}
2062 }
2063 
etm4_add_coresight_dev(struct etm4_init_arg * init_arg)2064 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
2065 {
2066 	int ret;
2067 	struct coresight_platform_data *pdata = NULL;
2068 	struct device *dev = init_arg->dev;
2069 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2070 	struct coresight_desc desc = { 0 };
2071 	u8 major, minor;
2072 	char *type_name;
2073 
2074 	if (!drvdata)
2075 		return -EINVAL;
2076 
2077 	desc.access = *init_arg->csa;
2078 
2079 	if (!drvdata->arch)
2080 		return -EINVAL;
2081 
2082 	major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2083 	minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2084 
2085 	if (etm4x_is_ete(drvdata)) {
2086 		type_name = "ete";
2087 		/* ETE v1 has major version == 0b101. Adjust this for logging.*/
2088 		major -= 4;
2089 	} else {
2090 		type_name = "etm";
2091 	}
2092 
2093 	desc.name = devm_kasprintf(dev, GFP_KERNEL,
2094 				   "%s%d", type_name, drvdata->cpu);
2095 	if (!desc.name)
2096 		return -ENOMEM;
2097 
2098 	etm4_set_default(&drvdata->config);
2099 
2100 	pdata = coresight_get_platform_data(dev);
2101 	if (IS_ERR(pdata))
2102 		return PTR_ERR(pdata);
2103 
2104 	dev->platform_data = pdata;
2105 
2106 	desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2107 	desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2108 	desc.ops = &etm4_cs_ops;
2109 	desc.pdata = pdata;
2110 	desc.dev = dev;
2111 	desc.groups = coresight_etmv4_groups;
2112 	drvdata->csdev = coresight_register(&desc);
2113 	if (IS_ERR(drvdata->csdev))
2114 		return PTR_ERR(drvdata->csdev);
2115 
2116 	ret = etm_perf_symlink(drvdata->csdev, true);
2117 	if (ret) {
2118 		coresight_unregister(drvdata->csdev);
2119 		return ret;
2120 	}
2121 
2122 	/* register with config infrastructure & load any current features */
2123 	ret = etm4_cscfg_register(drvdata->csdev);
2124 	if (ret) {
2125 		coresight_unregister(drvdata->csdev);
2126 		return ret;
2127 	}
2128 
2129 	etmdrvdata[drvdata->cpu] = drvdata;
2130 
2131 	dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2132 		 drvdata->cpu, type_name, major, minor);
2133 
2134 	if (boot_enable) {
2135 		coresight_enable_sysfs(drvdata->csdev);
2136 		drvdata->boot_enable = true;
2137 	}
2138 
2139 	return 0;
2140 }
2141 
etm4_probe(struct device * dev)2142 static int etm4_probe(struct device *dev)
2143 {
2144 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2145 	struct csdev_access access = { 0 };
2146 	struct etm4_init_arg init_arg = { 0 };
2147 	struct etm4_init_arg *delayed;
2148 
2149 	if (WARN_ON(!drvdata))
2150 		return -ENOMEM;
2151 
2152 	if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2153 		pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2154 			       PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2155 
2156 	if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2157 		drvdata->save_state = devm_kmalloc(dev,
2158 				sizeof(struct etmv4_save_state), GFP_KERNEL);
2159 		if (!drvdata->save_state)
2160 			return -ENOMEM;
2161 	}
2162 
2163 	raw_spin_lock_init(&drvdata->spinlock);
2164 
2165 	drvdata->cpu = coresight_get_cpu(dev);
2166 	if (drvdata->cpu < 0)
2167 		return drvdata->cpu;
2168 
2169 	init_arg.dev = dev;
2170 	init_arg.csa = &access;
2171 
2172 	/*
2173 	 * Serialize against CPUHP callbacks to avoid race condition
2174 	 * between the smp call and saving the delayed probe.
2175 	 */
2176 	cpus_read_lock();
2177 	if (smp_call_function_single(drvdata->cpu,
2178 				etm4_init_arch_data,  &init_arg, 1)) {
2179 		/* The CPU was offline, try again once it comes online. */
2180 		delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2181 		if (!delayed) {
2182 			cpus_read_unlock();
2183 			return -ENOMEM;
2184 		}
2185 
2186 		*delayed = init_arg;
2187 
2188 		per_cpu(delayed_probe, drvdata->cpu) = delayed;
2189 
2190 		cpus_read_unlock();
2191 		return 0;
2192 	}
2193 	cpus_read_unlock();
2194 
2195 	return etm4_add_coresight_dev(&init_arg);
2196 }
2197 
etm4_probe_amba(struct amba_device * adev,const struct amba_id * id)2198 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2199 {
2200 	struct etmv4_drvdata *drvdata;
2201 	void __iomem *base;
2202 	struct device *dev = &adev->dev;
2203 	struct resource *res = &adev->res;
2204 	int ret;
2205 
2206 	/* Validity for the resource is already checked by the AMBA core */
2207 	base = devm_ioremap_resource(dev, res);
2208 	if (IS_ERR(base))
2209 		return PTR_ERR(base);
2210 
2211 	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2212 	if (!drvdata)
2213 		return -ENOMEM;
2214 
2215 	drvdata->base = base;
2216 	dev_set_drvdata(dev, drvdata);
2217 	ret = etm4_probe(dev);
2218 	if (!ret)
2219 		pm_runtime_put(&adev->dev);
2220 
2221 	return ret;
2222 }
2223 
etm4_probe_platform_dev(struct platform_device * pdev)2224 static int etm4_probe_platform_dev(struct platform_device *pdev)
2225 {
2226 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2227 	struct etmv4_drvdata *drvdata;
2228 	int ret;
2229 
2230 	drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2231 	if (!drvdata)
2232 		return -ENOMEM;
2233 
2234 	drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2235 	if (IS_ERR(drvdata->pclk))
2236 		return -ENODEV;
2237 
2238 	if (res) {
2239 		drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2240 		if (IS_ERR(drvdata->base)) {
2241 			clk_put(drvdata->pclk);
2242 			return PTR_ERR(drvdata->base);
2243 		}
2244 	}
2245 
2246 	dev_set_drvdata(&pdev->dev, drvdata);
2247 	pm_runtime_get_noresume(&pdev->dev);
2248 	pm_runtime_set_active(&pdev->dev);
2249 	pm_runtime_enable(&pdev->dev);
2250 
2251 	ret = etm4_probe(&pdev->dev);
2252 
2253 	pm_runtime_put(&pdev->dev);
2254 	if (ret)
2255 		pm_runtime_disable(&pdev->dev);
2256 
2257 	return ret;
2258 }
2259 
etm4_probe_cpu(unsigned int cpu)2260 static int etm4_probe_cpu(unsigned int cpu)
2261 {
2262 	int ret;
2263 	struct etm4_init_arg init_arg;
2264 	struct csdev_access access = { 0 };
2265 	struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2266 
2267 	if (!iap)
2268 		return 0;
2269 
2270 	init_arg = *iap;
2271 	devm_kfree(init_arg.dev, iap);
2272 	*this_cpu_ptr(&delayed_probe) = NULL;
2273 
2274 	ret = pm_runtime_resume_and_get(init_arg.dev);
2275 	if (ret < 0) {
2276 		dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2277 		return 0;
2278 	}
2279 
2280 	init_arg.csa = &access;
2281 	etm4_init_arch_data(&init_arg);
2282 
2283 	etm4_add_coresight_dev(&init_arg);
2284 
2285 	pm_runtime_put(init_arg.dev);
2286 	return 0;
2287 }
2288 
2289 static struct amba_cs_uci_id uci_id_etm4[] = {
2290 	{
2291 		/*  ETMv4 UCI data */
2292 		.devarch	= ETM_DEVARCH_ETMv4x_ARCH,
2293 		.devarch_mask	= ETM_DEVARCH_ID_MASK,
2294 		.devtype	= CS_DEVTYPE_PE_TRACE,
2295 	}
2296 };
2297 
clear_etmdrvdata(void * info)2298 static void clear_etmdrvdata(void *info)
2299 {
2300 	int cpu = *(int *)info;
2301 
2302 	etmdrvdata[cpu] = NULL;
2303 	per_cpu(delayed_probe, cpu) = NULL;
2304 }
2305 
etm4_remove_dev(struct etmv4_drvdata * drvdata)2306 static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2307 {
2308 	bool had_delayed_probe;
2309 	/*
2310 	 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2311 	 * and CPU hotplug call backs.
2312 	 */
2313 	cpus_read_lock();
2314 
2315 	had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2316 
2317 	/*
2318 	 * The readers for etmdrvdata[] are CPU hotplug call backs
2319 	 * and PM notification call backs. Change etmdrvdata[i] on
2320 	 * CPU i ensures these call backs has consistent view
2321 	 * inside one call back function.
2322 	 */
2323 	if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2324 		clear_etmdrvdata(&drvdata->cpu);
2325 
2326 	cpus_read_unlock();
2327 
2328 	if (!had_delayed_probe) {
2329 		etm_perf_symlink(drvdata->csdev, false);
2330 		cscfg_unregister_csdev(drvdata->csdev);
2331 		coresight_unregister(drvdata->csdev);
2332 	}
2333 }
2334 
etm4_remove_amba(struct amba_device * adev)2335 static void etm4_remove_amba(struct amba_device *adev)
2336 {
2337 	struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2338 
2339 	if (drvdata)
2340 		etm4_remove_dev(drvdata);
2341 }
2342 
etm4_remove_platform_dev(struct platform_device * pdev)2343 static void etm4_remove_platform_dev(struct platform_device *pdev)
2344 {
2345 	struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2346 
2347 	if (drvdata)
2348 		etm4_remove_dev(drvdata);
2349 	pm_runtime_disable(&pdev->dev);
2350 
2351 	if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2352 		clk_put(drvdata->pclk);
2353 }
2354 
2355 static const struct amba_id etm4_ids[] = {
2356 	CS_AMBA_ID(0x000bb95d),			/* Cortex-A53 */
2357 	CS_AMBA_ID(0x000bb95e),			/* Cortex-A57 */
2358 	CS_AMBA_ID(0x000bb95a),			/* Cortex-A72 */
2359 	CS_AMBA_ID(0x000bb959),			/* Cortex-A73 */
2360 	CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2361 	CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2362 	CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2363 	CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2364 	CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2365 	CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2366 	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2367 	CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2368 	CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2369 	CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2370 	CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2371 	CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2372 	CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2373 	CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2374 	CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2375 	/*
2376 	 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2377 	 * CPUs to the list here.
2378 	 */
2379 	CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2380 	{},
2381 };
2382 
2383 MODULE_DEVICE_TABLE(amba, etm4_ids);
2384 
2385 static struct amba_driver etm4x_amba_driver = {
2386 	.drv = {
2387 		.name   = "coresight-etm4x",
2388 		.suppress_bind_attrs = true,
2389 	},
2390 	.probe		= etm4_probe_amba,
2391 	.remove         = etm4_remove_amba,
2392 	.id_table	= etm4_ids,
2393 };
2394 
2395 #ifdef CONFIG_PM
etm4_runtime_suspend(struct device * dev)2396 static int etm4_runtime_suspend(struct device *dev)
2397 {
2398 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2399 
2400 	if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2401 		clk_disable_unprepare(drvdata->pclk);
2402 
2403 	return 0;
2404 }
2405 
etm4_runtime_resume(struct device * dev)2406 static int etm4_runtime_resume(struct device *dev)
2407 {
2408 	struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2409 
2410 	if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2411 		clk_prepare_enable(drvdata->pclk);
2412 
2413 	return 0;
2414 }
2415 #endif
2416 
2417 static const struct dev_pm_ops etm4_dev_pm_ops = {
2418 	SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2419 };
2420 
2421 static const struct of_device_id etm4_sysreg_match[] = {
2422 	{ .compatible	= "arm,coresight-etm4x-sysreg" },
2423 	{ .compatible	= "arm,embedded-trace-extension" },
2424 	{}
2425 };
2426 
2427 #ifdef CONFIG_ACPI
2428 static const struct acpi_device_id etm4x_acpi_ids[] = {
2429 	{"ARMHC500", 0, 0, 0}, /* ARM CoreSight ETM4x */
2430 	{}
2431 };
2432 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2433 #endif
2434 
2435 static struct platform_driver etm4_platform_driver = {
2436 	.probe		= etm4_probe_platform_dev,
2437 	.remove		= etm4_remove_platform_dev,
2438 	.driver			= {
2439 		.name			= "coresight-etm4x",
2440 		.of_match_table		= etm4_sysreg_match,
2441 		.acpi_match_table	= ACPI_PTR(etm4x_acpi_ids),
2442 		.suppress_bind_attrs	= true,
2443 		.pm			= &etm4_dev_pm_ops,
2444 	},
2445 };
2446 
etm4x_init(void)2447 static int __init etm4x_init(void)
2448 {
2449 	int ret;
2450 
2451 	ret = etm4_pm_setup();
2452 
2453 	/* etm4_pm_setup() does its own cleanup - exit on error */
2454 	if (ret)
2455 		return ret;
2456 
2457 	ret = amba_driver_register(&etm4x_amba_driver);
2458 	if (ret) {
2459 		pr_err("Error registering etm4x AMBA driver\n");
2460 		goto clear_pm;
2461 	}
2462 
2463 	ret = platform_driver_register(&etm4_platform_driver);
2464 	if (!ret)
2465 		return 0;
2466 
2467 	pr_err("Error registering etm4x platform driver\n");
2468 	amba_driver_unregister(&etm4x_amba_driver);
2469 
2470 clear_pm:
2471 	etm4_pm_clear();
2472 	return ret;
2473 }
2474 
etm4x_exit(void)2475 static void __exit etm4x_exit(void)
2476 {
2477 	amba_driver_unregister(&etm4x_amba_driver);
2478 	platform_driver_unregister(&etm4_platform_driver);
2479 	etm4_pm_clear();
2480 }
2481 
2482 module_init(etm4x_init);
2483 module_exit(etm4x_exit);
2484 
2485 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2486 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2487 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2488 MODULE_LICENSE("GPL v2");
2489