1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright(c) 2023, Intel Corporation. All rights reserved.
4 */
5
6 #include <linux/irq.h>
7 #include <linux/mei_aux.h>
8 #include <linux/pci.h>
9 #include <linux/sizes.h>
10
11 #include "xe_device_types.h"
12 #include "xe_drv.h"
13 #include "xe_heci_gsc.h"
14 #include "xe_platform_types.h"
15 #include "xe_survivability_mode.h"
16
17 #define GSC_BAR_LENGTH 0x00000FFC
18
19 #define DG1_GSC_HECI2_BASE 0x259000
20 #define PVC_GSC_HECI2_BASE 0x285000
21 #define DG2_GSC_HECI2_BASE 0x374000
22
heci_gsc_irq_mask(struct irq_data * d)23 static void heci_gsc_irq_mask(struct irq_data *d)
24 {
25 /* generic irq handling */
26 }
27
heci_gsc_irq_unmask(struct irq_data * d)28 static void heci_gsc_irq_unmask(struct irq_data *d)
29 {
30 /* generic irq handling */
31 }
32
33 static const struct irq_chip heci_gsc_irq_chip = {
34 .name = "gsc_irq_chip",
35 .irq_mask = heci_gsc_irq_mask,
36 .irq_unmask = heci_gsc_irq_unmask,
37 };
38
heci_gsc_irq_init(int irq)39 static int heci_gsc_irq_init(int irq)
40 {
41 irq_set_chip_and_handler_name(irq, &heci_gsc_irq_chip,
42 handle_simple_irq, "heci_gsc_irq_handler");
43
44 return irq_set_chip_data(irq, NULL);
45 }
46
47 /**
48 * struct heci_gsc_def - graphics security controller heci interface definitions
49 *
50 * @name: name of the heci device
51 * @bar: address of the mmio bar
52 * @bar_size: size of the mmio bar
53 * @use_polling: indication of using polling mode for the device
54 * @slow_firmware: indication of whether the device is slow (needs longer timeouts)
55 */
56 struct heci_gsc_def {
57 const char *name;
58 unsigned long bar;
59 size_t bar_size;
60 bool use_polling;
61 bool slow_firmware;
62 };
63
64 /* gsc resources and definitions */
65 static const struct heci_gsc_def heci_gsc_def_dg1 = {
66 .name = "mei-gscfi",
67 .bar = DG1_GSC_HECI2_BASE,
68 .bar_size = GSC_BAR_LENGTH,
69 };
70
71 static const struct heci_gsc_def heci_gsc_def_dg2 = {
72 .name = "mei-gscfi",
73 .bar = DG2_GSC_HECI2_BASE,
74 .bar_size = GSC_BAR_LENGTH,
75 };
76
77 static const struct heci_gsc_def heci_gsc_def_pvc = {
78 .name = "mei-gscfi",
79 .bar = PVC_GSC_HECI2_BASE,
80 .bar_size = GSC_BAR_LENGTH,
81 .slow_firmware = true,
82 };
83
heci_gsc_release_dev(struct device * dev)84 static void heci_gsc_release_dev(struct device *dev)
85 {
86 struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
87 struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
88
89 kfree(adev);
90 }
91
xe_heci_gsc_fini(void * arg)92 static void xe_heci_gsc_fini(void *arg)
93 {
94 struct xe_heci_gsc *heci_gsc = arg;
95
96 if (heci_gsc->adev) {
97 struct auxiliary_device *aux_dev = &heci_gsc->adev->aux_dev;
98
99 auxiliary_device_delete(aux_dev);
100 auxiliary_device_uninit(aux_dev);
101 heci_gsc->adev = NULL;
102 }
103
104 if (heci_gsc->irq >= 0)
105 irq_free_desc(heci_gsc->irq);
106
107 heci_gsc->irq = -1;
108 }
109
heci_gsc_irq_setup(struct xe_device * xe)110 static int heci_gsc_irq_setup(struct xe_device *xe)
111 {
112 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc;
113 int ret;
114
115 heci_gsc->irq = irq_alloc_desc(0);
116 if (heci_gsc->irq < 0) {
117 drm_err(&xe->drm, "gsc irq error %d\n", heci_gsc->irq);
118 return heci_gsc->irq;
119 }
120
121 ret = heci_gsc_irq_init(heci_gsc->irq);
122 if (ret < 0)
123 drm_err(&xe->drm, "gsc irq init failed %d\n", ret);
124
125 return ret;
126 }
127
heci_gsc_add_device(struct xe_device * xe,const struct heci_gsc_def * def)128 static int heci_gsc_add_device(struct xe_device *xe, const struct heci_gsc_def *def)
129 {
130 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc;
131 struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
132 struct auxiliary_device *aux_dev;
133 struct mei_aux_device *adev;
134 int ret;
135
136 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
137 if (!adev)
138 return -ENOMEM;
139 adev->irq = heci_gsc->irq;
140 adev->bar.parent = &pdev->resource[0];
141 adev->bar.start = def->bar + pdev->resource[0].start;
142 adev->bar.end = adev->bar.start + def->bar_size - 1;
143 adev->bar.flags = IORESOURCE_MEM;
144 adev->bar.desc = IORES_DESC_NONE;
145 adev->slow_firmware = def->slow_firmware;
146
147 aux_dev = &adev->aux_dev;
148 aux_dev->name = def->name;
149 aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
150 PCI_DEVID(pdev->bus->number, pdev->devfn);
151 aux_dev->dev.parent = &pdev->dev;
152 aux_dev->dev.release = heci_gsc_release_dev;
153
154 ret = auxiliary_device_init(aux_dev);
155 if (ret < 0) {
156 drm_err(&xe->drm, "gsc aux init failed %d\n", ret);
157 kfree(adev);
158 return ret;
159 }
160
161 heci_gsc->adev = adev; /* needed by the notifier */
162 ret = auxiliary_device_add(aux_dev);
163 if (ret < 0) {
164 drm_err(&xe->drm, "gsc aux add failed %d\n", ret);
165 heci_gsc->adev = NULL;
166
167 /* adev will be freed with the put_device() and .release sequence */
168 auxiliary_device_uninit(aux_dev);
169 }
170 return ret;
171 }
172
xe_heci_gsc_init(struct xe_device * xe)173 int xe_heci_gsc_init(struct xe_device *xe)
174 {
175 struct xe_heci_gsc *heci_gsc = &xe->heci_gsc;
176 const struct heci_gsc_def *def = NULL;
177 int ret;
178
179 if (!xe->info.has_heci_gscfi && !xe->info.has_heci_cscfi)
180 return 0;
181
182 heci_gsc->irq = -1;
183
184 if (xe->info.platform == XE_BATTLEMAGE) {
185 def = &heci_gsc_def_dg2;
186 } else if (xe->info.platform == XE_PVC) {
187 def = &heci_gsc_def_pvc;
188 } else if (xe->info.platform == XE_DG2) {
189 def = &heci_gsc_def_dg2;
190 } else if (xe->info.platform == XE_DG1) {
191 def = &heci_gsc_def_dg1;
192 }
193
194 if (!def || !def->name) {
195 drm_warn(&xe->drm, "HECI is not implemented!\n");
196 return 0;
197 }
198
199 ret = devm_add_action_or_reset(xe->drm.dev, xe_heci_gsc_fini, heci_gsc);
200 if (ret)
201 return ret;
202
203 if (!def->use_polling && !xe_survivability_mode_is_enabled(xe)) {
204 ret = heci_gsc_irq_setup(xe);
205 if (ret)
206 return ret;
207 }
208
209 return heci_gsc_add_device(xe, def);
210 }
211
xe_heci_gsc_irq_handler(struct xe_device * xe,u32 iir)212 void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir)
213 {
214 int ret;
215
216 if ((iir & GSC_IRQ_INTF(1)) == 0)
217 return;
218
219 if (!xe->info.has_heci_gscfi) {
220 drm_warn_once(&xe->drm, "GSC irq: not supported");
221 return;
222 }
223
224 if (xe->heci_gsc.irq < 0)
225 return;
226
227 ret = generic_handle_irq(xe->heci_gsc.irq);
228 if (ret)
229 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret);
230 }
231
xe_heci_csc_irq_handler(struct xe_device * xe,u32 iir)232 void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir)
233 {
234 int ret;
235
236 if ((iir & CSC_IRQ_INTF(1)) == 0)
237 return;
238
239 if (!xe->info.has_heci_cscfi) {
240 drm_warn_once(&xe->drm, "CSC irq: not supported");
241 return;
242 }
243
244 if (xe->heci_gsc.irq < 0)
245 return;
246
247 ret = generic_handle_irq(xe->heci_gsc.irq);
248 if (ret)
249 drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret);
250 }
251