1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include <linux/math64.h>
7
8 #include "xe_gt_clock.h"
9
10 #include "regs/xe_gt_regs.h"
11 #include "regs/xe_regs.h"
12 #include "xe_assert.h"
13 #include "xe_device.h"
14 #include "xe_gt.h"
15 #include "xe_gt_printk.h"
16 #include "xe_macros.h"
17 #include "xe_mmio.h"
18
19 #define f19_2_mhz 19200000
20 #define f24_mhz 24000000
21 #define f25_mhz 25000000
22 #define f38_4_mhz 38400000
23 #define ts_base_83 83333
24 #define ts_base_52 52083
25 #define ts_base_80 80000
26
read_crystal_clock(struct xe_gt * gt,u32 rpm_config_reg,u32 * freq,u32 * timestamp_base)27 static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
28 u32 *timestamp_base)
29 {
30 u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
31 rpm_config_reg);
32
33 switch (crystal_clock) {
34 case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
35 *freq = f24_mhz;
36 *timestamp_base = ts_base_83;
37 return;
38 case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
39 *freq = f19_2_mhz;
40 *timestamp_base = ts_base_52;
41 return;
42 case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
43 *freq = f38_4_mhz;
44 *timestamp_base = ts_base_52;
45 return;
46 case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
47 *freq = f25_mhz;
48 *timestamp_base = ts_base_80;
49 return;
50 default:
51 xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);
52 *freq = 0;
53 *timestamp_base = 0;
54 return;
55 }
56 }
57
check_ctc_mode(struct xe_gt * gt)58 static void check_ctc_mode(struct xe_gt *gt)
59 {
60 /*
61 * CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
62 * platforms. In theory it could be a valid setting for pre-Xe2
63 * platforms, but there's no documentation on how to properly handle
64 * this case. Reading TIMESTAMP_OVERRIDE, as the driver attempted in
65 * the past has been confirmed as incorrect by the hardware architects.
66 *
67 * For now just warn if we ever encounter hardware in the wild that
68 * has this setting and move on as if it hadn't been set.
69 */
70 if (xe_mmio_read32(>->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
71 xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
72 }
73
xe_gt_clock_init(struct xe_gt * gt)74 int xe_gt_clock_init(struct xe_gt *gt)
75 {
76 u32 freq;
77 u32 c0;
78
79 if (!IS_SRIOV_VF(gt_to_xe(gt)))
80 check_ctc_mode(gt);
81
82 c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
83 read_crystal_clock(gt, c0, &freq, >->info.timestamp_base);
84
85 /*
86 * Now figure out how the command stream's timestamp
87 * register increments from this frequency (it might
88 * increment only every few clock cycle).
89 */
90 freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
91
92 gt->info.reference_clock = freq;
93 return 0;
94 }
95
div_u64_roundup(u64 n,u32 d)96 static u64 div_u64_roundup(u64 n, u32 d)
97 {
98 return div_u64(n + d - 1, d);
99 }
100
101 /**
102 * xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec
103 *
104 * @gt: the &xe_gt
105 * @count: count of GT clock ticks
106 *
107 * Returns: time in msec
108 */
xe_gt_clock_interval_to_ms(struct xe_gt * gt,u64 count)109 u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count)
110 {
111 return div_u64_roundup(count * MSEC_PER_SEC, gt->info.reference_clock);
112 }
113