1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #include "i915_irq.h"
7 #include "i915_reg.h"
8 #include "intel_uncore.h"
9 
gen2_irq_reset(struct intel_uncore * uncore,struct i915_irq_regs regs)10 void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs)
11 {
12 	intel_uncore_write(uncore, regs.imr, 0xffffffff);
13 	intel_uncore_posting_read(uncore, regs.imr);
14 
15 	intel_uncore_write(uncore, regs.ier, 0);
16 
17 	/* IIR can theoretically queue up two events. Be paranoid. */
18 	intel_uncore_write(uncore, regs.iir, 0xffffffff);
19 	intel_uncore_posting_read(uncore, regs.iir);
20 	intel_uncore_write(uncore, regs.iir, 0xffffffff);
21 	intel_uncore_posting_read(uncore, regs.iir);
22 }
23 
24 /*
25  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
26  */
gen2_assert_iir_is_zero(struct intel_uncore * uncore,i915_reg_t reg)27 void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
28 {
29 	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
30 	u32 val = intel_uncore_read(uncore, reg);
31 
32 	if (val == 0)
33 		return;
34 
35 	drm_WARN(&xe->drm, 1,
36 		 "Interrupt register 0x%x is not zero: 0x%08x\n",
37 		 i915_mmio_reg_offset(reg), val);
38 	intel_uncore_write(uncore, reg, 0xffffffff);
39 	intel_uncore_posting_read(uncore, reg);
40 	intel_uncore_write(uncore, reg, 0xffffffff);
41 	intel_uncore_posting_read(uncore, reg);
42 }
43 
gen2_irq_init(struct intel_uncore * uncore,struct i915_irq_regs regs,u32 imr_val,u32 ier_val)44 void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
45 		   u32 imr_val, u32 ier_val)
46 {
47 	gen2_assert_iir_is_zero(uncore, regs.iir);
48 
49 	intel_uncore_write(uncore, regs.ier, ier_val);
50 	intel_uncore_write(uncore, regs.imr, imr_val);
51 	intel_uncore_posting_read(uncore, regs.imr);
52 }
53 
gen2_error_reset(struct intel_uncore * uncore,struct i915_error_regs regs)54 void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
55 {
56 	intel_uncore_write(uncore, regs.emr, 0xffffffff);
57 	intel_uncore_posting_read(uncore, regs.emr);
58 
59 	intel_uncore_write(uncore, regs.eir, 0xffffffff);
60 	intel_uncore_posting_read(uncore, regs.eir);
61 	intel_uncore_write(uncore, regs.eir, 0xffffffff);
62 	intel_uncore_posting_read(uncore, regs.eir);
63 }
64 
gen2_error_init(struct intel_uncore * uncore,struct i915_error_regs regs,u32 emr_val)65 void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
66 		     u32 emr_val)
67 {
68 	intel_uncore_write(uncore, regs.eir, 0xffffffff);
69 	intel_uncore_posting_read(uncore, regs.eir);
70 	intel_uncore_write(uncore, regs.eir, 0xffffffff);
71 	intel_uncore_posting_read(uncore, regs.eir);
72 
73 	intel_uncore_write(uncore, regs.emr, emr_val);
74 	intel_uncore_posting_read(uncore, regs.emr);
75 }
76 
intel_irqs_enabled(struct xe_device * xe)77 bool intel_irqs_enabled(struct xe_device *xe)
78 {
79 	return atomic_read(&xe->irq.enabled);
80 }
81 
intel_synchronize_irq(struct xe_device * xe)82 void intel_synchronize_irq(struct xe_device *xe)
83 {
84 	synchronize_irq(to_pci_dev(xe->drm.dev)->irq);
85 }
86