1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #ifndef _GUC_ACTIONS_SLPC_ABI_H_
7 #define _GUC_ACTIONS_SLPC_ABI_H_
8 
9 #include <linux/types.h>
10 
11 /**
12  * DOC: SLPC SHARED DATA STRUCTURE
13  *
14  *  +----+------+--------------------------------------------------------------+
15  *  | CL | Bytes| Description                                                  |
16  *  +====+======+==============================================================+
17  *  | 1  | 0-3  | SHARED DATA SIZE                                             |
18  *  |    +------+--------------------------------------------------------------+
19  *  |    | 4-7  | GLOBAL STATE                                                 |
20  *  |    +------+--------------------------------------------------------------+
21  *  |    | 8-11 | DISPLAY DATA ADDRESS                                         |
22  *  |    +------+--------------------------------------------------------------+
23  *  |    | 12:63| PADDING                                                      |
24  *  +----+------+--------------------------------------------------------------+
25  *  |    | 0:63 | PADDING(PLATFORM INFO)                                       |
26  *  +----+------+--------------------------------------------------------------+
27  *  | 3  | 0-3  | TASK STATE DATA                                              |
28  *  +    +------+--------------------------------------------------------------+
29  *  |    | 4:63 | PADDING                                                      |
30  *  +----+------+--------------------------------------------------------------+
31  *  |4-21|0:1087| OVERRIDE PARAMS AND BIT FIELDS                               |
32  *  +----+------+--------------------------------------------------------------+
33  *  |    |      | PADDING + EXTRA RESERVED PAGE                                |
34  *  +----+------+--------------------------------------------------------------+
35  */
36 
37 /*
38  * SLPC exposes certain parameters for global configuration by the host.
39  * These are referred to as override parameters, because in most cases
40  * the host will not need to modify the default values used by SLPC.
41  * SLPC remembers the default values which allows the host to easily restore
42  * them by simply unsetting the override. The host can set or unset override
43  * parameters during SLPC (re-)initialization using the SLPC Reset event.
44  * The host can also set or unset override parameters on the fly using the
45  * Parameter Set and Parameter Unset events
46  */
47 
48 #define SLPC_MAX_OVERRIDE_PARAMETERS		256
49 #define SLPC_OVERRIDE_BITFIELD_SIZE \
50 		(SLPC_MAX_OVERRIDE_PARAMETERS / 32)
51 
52 #define SLPC_PAGE_SIZE_BYTES			4096
53 #define SLPC_CACHELINE_SIZE_BYTES		64
54 #define SLPC_SHARED_DATA_SIZE_BYTE_HEADER	SLPC_CACHELINE_SIZE_BYTES
55 #define SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO	SLPC_CACHELINE_SIZE_BYTES
56 #define SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE	SLPC_CACHELINE_SIZE_BYTES
57 #define SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE	SLPC_PAGE_SIZE_BYTES
58 #define SLPC_SHARED_DATA_SIZE_BYTE_MAX		(2 * SLPC_PAGE_SIZE_BYTES)
59 
60 /*
61  * Cacheline size aligned (Total size needed for
62  * SLPM_KMD_MAX_OVERRIDE_PARAMETERS=256 is 1088 bytes)
63  */
64 #define SLPC_OVERRIDE_PARAMS_TOTAL_BYTES	(((((SLPC_MAX_OVERRIDE_PARAMETERS * 4) \
65 						+ ((SLPC_MAX_OVERRIDE_PARAMETERS / 32) * 4)) \
66 		+ (SLPC_CACHELINE_SIZE_BYTES - 1)) / SLPC_CACHELINE_SIZE_BYTES) * \
67 					SLPC_CACHELINE_SIZE_BYTES)
68 
69 #define SLPC_SHARED_DATA_SIZE_BYTE_OTHER	(SLPC_SHARED_DATA_SIZE_BYTE_MAX - \
70 					(SLPC_SHARED_DATA_SIZE_BYTE_HEADER \
71 					+ SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO \
72 					+ SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE \
73 					+ SLPC_OVERRIDE_PARAMS_TOTAL_BYTES \
74 					+ SLPC_SHARED_DATA_MODE_DEFN_TABLE_SIZE))
75 
76 enum slpc_task_enable {
77 	SLPC_PARAM_TASK_DEFAULT = 0,
78 	SLPC_PARAM_TASK_ENABLED,
79 	SLPC_PARAM_TASK_DISABLED,
80 	SLPC_PARAM_TASK_UNKNOWN
81 };
82 
83 enum slpc_global_state {
84 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
85 	SLPC_GLOBAL_STATE_INITIALIZING = 1,
86 	SLPC_GLOBAL_STATE_RESETTING = 2,
87 	SLPC_GLOBAL_STATE_RUNNING = 3,
88 	SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
89 	SLPC_GLOBAL_STATE_ERROR = 5
90 };
91 
92 enum slpc_param_id {
93 	SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
94 	SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
95 	SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
96 	SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
97 	SLPC_PARAM_TASK_ENABLE_DCC = 4,
98 	SLPC_PARAM_TASK_DISABLE_DCC = 5,
99 	SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
100 	SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
101 	SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
102 	SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
103 	SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
104 	SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
105 	SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
106 	SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
107 	SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
108 	SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
109 	SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
110 	SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
111 	SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
112 	SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
113 	SLPC_PARAM_GLOBAL_RT_MODE_TURBO_FREQ_DELTA_MHZ = 20,
114 	SLPC_PARAM_PWRGATE_RC_MODE = 21,
115 	SLPC_PARAM_EDR_MODE_COMPUTE_TIMEOUT_MS = 22,
116 	SLPC_PARAM_EDR_QOS_FREQ_MHZ = 23,
117 	SLPC_PARAM_MEDIA_FF_RATIO_MODE = 24,
118 	SLPC_PARAM_ENABLE_IA_FREQ_LIMITING = 25,
119 	SLPC_PARAM_STRATEGIES = 26,
120 	SLPC_PARAM_POWER_PROFILE = 27,
121 	SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY = 28,
122 	SLPC_MAX_PARAM = 32,
123 };
124 
125 enum slpc_media_ratio_mode {
126 	SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL = 0,
127 	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_ONE = 1,
128 	SLPC_MEDIA_RATIO_MODE_FIXED_ONE_TO_TWO = 2,
129 };
130 
131 enum slpc_gucrc_mode {
132 	SLPC_GUCRC_MODE_HW = 0,
133 	SLPC_GUCRC_MODE_GUCRC_NO_RC6 = 1,
134 	SLPC_GUCRC_MODE_GUCRC_STATIC_TIMEOUT = 2,
135 	SLPC_GUCRC_MODE_GUCRC_DYNAMIC_HYSTERESIS = 3,
136 
137 	SLPC_GUCRC_MODE_MAX,
138 };
139 
140 enum slpc_event_id {
141 	SLPC_EVENT_RESET = 0,
142 	SLPC_EVENT_SHUTDOWN = 1,
143 	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
144 	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
145 	SLPC_EVENT_FLIP_COMPLETE = 4,
146 	SLPC_EVENT_QUERY_TASK_STATE = 5,
147 	SLPC_EVENT_PARAMETER_SET = 6,
148 	SLPC_EVENT_PARAMETER_UNSET = 7,
149 };
150 
151 struct slpc_task_state_data {
152 	union {
153 		u32 task_status_padding;
154 		struct {
155 			u32 status;
156 #define SLPC_GTPERF_TASK_ENABLED	REG_BIT(0)
157 #define SLPC_DCC_TASK_ENABLED		REG_BIT(11)
158 #define SLPC_IN_DCC			REG_BIT(12)
159 #define SLPC_BALANCER_ENABLED		REG_BIT(15)
160 #define SLPC_IBC_TASK_ENABLED		REG_BIT(16)
161 #define SLPC_BALANCER_IA_LMT_ENABLED	REG_BIT(17)
162 #define SLPC_BALANCER_IA_LMT_ACTIVE	REG_BIT(18)
163 		};
164 	};
165 	union {
166 		u32 freq_padding;
167 		struct {
168 #define SLPC_MAX_UNSLICE_FREQ_MASK	REG_GENMASK(7, 0)
169 #define SLPC_MIN_UNSLICE_FREQ_MASK	REG_GENMASK(15, 8)
170 #define SLPC_MAX_SLICE_FREQ_MASK	REG_GENMASK(23, 16)
171 #define SLPC_MIN_SLICE_FREQ_MASK	REG_GENMASK(31, 24)
172 			u32 freq;
173 		};
174 	};
175 } __packed;
176 
177 #define SLPC_CTX_FREQ_REQ_IS_COMPUTE		REG_BIT(28)
178 #define SLPC_OPTIMIZED_STRATEGY_COMPUTE		REG_BIT(0)
179 
180 struct slpc_shared_data_header {
181 	/* Total size in bytes of this shared buffer. */
182 	u32 size;
183 	u32 global_state;
184 	u32 display_data_addr;
185 } __packed;
186 
187 struct slpc_override_params {
188 	u32 bits[SLPC_OVERRIDE_BITFIELD_SIZE];
189 	u32 values[SLPC_MAX_OVERRIDE_PARAMETERS];
190 } __packed;
191 
192 struct slpc_shared_data {
193 	struct slpc_shared_data_header header;
194 	u8 shared_data_header_pad[SLPC_SHARED_DATA_SIZE_BYTE_HEADER -
195 				sizeof(struct slpc_shared_data_header)];
196 
197 	u8 platform_info_pad[SLPC_SHARED_DATA_SIZE_BYTE_PLATFORM_INFO];
198 
199 	struct slpc_task_state_data task_state_data;
200 	u8 task_state_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_TASK_STATE -
201 				sizeof(struct slpc_task_state_data)];
202 
203 	struct slpc_override_params override_params;
204 	u8 override_params_pad[SLPC_OVERRIDE_PARAMS_TOTAL_BYTES -
205 				sizeof(struct slpc_override_params)];
206 
207 	u8 shared_data_pad[SLPC_SHARED_DATA_SIZE_BYTE_OTHER];
208 
209 	/* PAGE 2 (4096 bytes), mode based parameter will be removed soon */
210 	u8 reserved_mode_definition[4096];
211 } __packed;
212 
213 /**
214  * DOC: SLPC H2G MESSAGE FORMAT
215  *
216  *  +---+-------+--------------------------------------------------------------+
217  *  |   | Bits  | Description                                                  |
218  *  +===+=======+==============================================================+
219  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
220  *  |   +-------+--------------------------------------------------------------+
221  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
222  *  |   +-------+--------------------------------------------------------------+
223  *  |   | 27:16 | DATA0 = MBZ                                                  |
224  *  |   +-------+--------------------------------------------------------------+
225  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_PC_SLPM_REQUEST` = 0x3003     |
226  *  +---+-------+--------------------------------------------------------------+
227  *  | 1 |  31:8 | **EVENT_ID**                                                 |
228  *  +   +-------+--------------------------------------------------------------+
229  *  |   |   7:0 | **EVENT_ARGC** - number of data arguments                    |
230  *  +---+-------+--------------------------------------------------------------+
231  *  | 2 |  31:0 | **EVENT_DATA1**                                              |
232  *  +---+-------+--------------------------------------------------------------+
233  *  |...|  31:0 | ...                                                          |
234  *  +---+-------+--------------------------------------------------------------+
235  *  |2+n|  31:0 | **EVENT_DATAn**                                              |
236  *  +---+-------+--------------------------------------------------------------+
237  */
238 
239 #define GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST		0x3003
240 
241 #define HOST2GUC_PC_SLPC_REQUEST_MSG_MIN_LEN \
242 				(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
243 #define HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS		9
244 #define HOST2GUC_PC_SLPC_REQUEST_MSG_MAX_LEN \
245 		(HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \
246 			HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS)
247 #define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0
248 #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID		(0xffu << 8)
249 #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC	(0xffu << 0)
250 #define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N	GUC_HXG_REQUEST_MSG_n_DATAn
251 
252 /**
253  * DOC: SETUP_PC_GUCRC
254  *
255  *  +---+-------+--------------------------------------------------------------+
256  *  |   | Bits  | Description                                                  |
257  *  +===+=======+==============================================================+
258  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
259  *  |   +-------+--------------------------------------------------------------+
260  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_FAST_REQUEST_                            |
261  *  |   +-------+--------------------------------------------------------------+
262  *  |   | 27:16 | DATA0 = MBZ                                                  |
263  *  |   +-------+--------------------------------------------------------------+
264  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC` = 0x3004      |
265  *  +---+-------+--------------------------------------------------------------+
266  *  | 1 |  31:0 | **MODE** = GUCRC_HOST_CONTROL(0), GUCRC_FIRMWARE_CONTROL(1)  |
267  *  +---+-------+--------------------------------------------------------------+
268  */
269 
270 #define GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC		0x3004u
271 #define   GUCRC_HOST_CONTROL				0u
272 #define   GUCRC_FIRMWARE_CONTROL			1u
273 
274 #endif
275