1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/display/drm_hdmi_audio_helper.h>
35 #include <drm/display/drm_hdmi_helper.h>
36 #include <drm/display/drm_hdmi_state_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
38 #include <drm/drm_atomic_helper.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_simple_kms_helper.h>
43 #include <linux/clk.h>
44 #include <linux/component.h>
45 #include <linux/gpio/consumer.h>
46 #include <linux/i2c.h>
47 #include <linux/of.h>
48 #include <linux/of_address.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/rational.h>
51 #include <linux/reset.h>
52 #include <sound/dmaengine_pcm.h>
53 #include <sound/hdmi-codec.h>
54 #include <sound/pcm_drm_eld.h>
55 #include <sound/pcm_params.h>
56 #include <sound/soc.h>
57 #include "media/cec.h"
58 #include "vc4_drv.h"
59 #include "vc4_hdmi.h"
60 #include "vc4_hdmi_regs.h"
61 #include "vc4_regs.h"
62
63 #define VC5_HDMI_HORZA_HFP_SHIFT 16
64 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
65 #define VC5_HDMI_HORZA_VPOS BIT(15)
66 #define VC5_HDMI_HORZA_HPOS BIT(14)
67 #define VC5_HDMI_HORZA_HAP_SHIFT 0
68 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
69
70 #define VC5_HDMI_HORZB_HBP_SHIFT 16
71 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
72 #define VC5_HDMI_HORZB_HSP_SHIFT 0
73 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
74
75 #define VC5_HDMI_VERTA_VSP_SHIFT 24
76 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
77 #define VC5_HDMI_VERTA_VFP_SHIFT 16
78 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
79 #define VC5_HDMI_VERTA_VAL_SHIFT 0
80 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
81
82 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
83 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
84
85 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
86 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
88 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
89
90 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
91
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
94
95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
97
98 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
99
100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
102
103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
105 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
106
107 # define VC4_HD_M_SW_RST BIT(2)
108 # define VC4_HD_M_ENABLE BIT(0)
109
110 #define HSM_MIN_CLOCK_FREQ 120000000
111 #define CEC_CLOCK_FREQ 40000
112
113 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
114
vc4_hdmi_supports_scrambling(struct vc4_hdmi * vc4_hdmi)115 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
116 {
117 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
118
119 lockdep_assert_held(&vc4_hdmi->mutex);
120
121 if (!display->is_hdmi)
122 return false;
123
124 if (!display->hdmi.scdc.supported ||
125 !display->hdmi.scdc.scrambling.supported)
126 return false;
127
128 return true;
129 }
130
vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode * mode,unsigned int bpc,enum hdmi_colorspace fmt)131 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
132 unsigned int bpc,
133 enum hdmi_colorspace fmt)
134 {
135 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
136
137 return clock > HDMI_14_MAX_TMDS_CLK;
138 }
139
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)140 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
141 {
142 struct drm_debugfs_entry *entry = m->private;
143 struct vc4_hdmi *vc4_hdmi = entry->file.data;
144 struct drm_device *drm = vc4_hdmi->connector.dev;
145 struct drm_printer p = drm_seq_file_printer(m);
146 int idx;
147
148 if (!drm_dev_enter(drm, &idx))
149 return -ENODEV;
150
151 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
152
153 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
154 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
155 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
156 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
157 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
158 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
159 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
160 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
161
162 pm_runtime_put(&vc4_hdmi->pdev->dev);
163
164 drm_dev_exit(idx);
165
166 return 0;
167 }
168
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)169 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
170 {
171 struct drm_device *drm = vc4_hdmi->connector.dev;
172 unsigned long flags;
173 int idx;
174
175 /*
176 * We can be called by our bind callback, when the
177 * connector->dev pointer might not be initialised yet.
178 */
179 if (drm && !drm_dev_enter(drm, &idx))
180 return;
181
182 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
183
184 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
185 udelay(1);
186 HDMI_WRITE(HDMI_M_CTL, 0);
187
188 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
189
190 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
191 VC4_HDMI_SW_RESET_HDMI |
192 VC4_HDMI_SW_RESET_FORMAT_DETECT);
193
194 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
195
196 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
197
198 if (drm)
199 drm_dev_exit(idx);
200 }
201
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)202 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
203 {
204 struct drm_device *drm = vc4_hdmi->connector.dev;
205 unsigned long flags;
206 int idx;
207
208 /*
209 * We can be called by our bind callback, when the
210 * connector->dev pointer might not be initialised yet.
211 */
212 if (drm && !drm_dev_enter(drm, &idx))
213 return;
214
215 reset_control_reset(vc4_hdmi->reset);
216
217 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
218
219 HDMI_WRITE(HDMI_DVP_CTL, 0);
220
221 HDMI_WRITE(HDMI_CLOCK_STOP,
222 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
223
224 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
225
226 if (drm)
227 drm_dev_exit(idx);
228 }
229
230 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)231 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
232 {
233 struct drm_device *drm = vc4_hdmi->connector.dev;
234 unsigned long cec_rate;
235 unsigned long flags;
236 u16 clk_cnt;
237 u32 value;
238 int idx;
239
240 /*
241 * This function is called by our runtime_resume implementation
242 * and thus at bind time, when we haven't registered our
243 * connector yet and thus don't have a pointer to the DRM
244 * device.
245 */
246 if (drm && !drm_dev_enter(drm, &idx))
247 return;
248
249 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
250
251 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
252
253 value = HDMI_READ(HDMI_CEC_CNTRL_1);
254 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
255
256 /*
257 * Set the clock divider: the hsm_clock rate and this divider
258 * setting will give a 40 kHz CEC clock.
259 */
260 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
261 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
262 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
263
264 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
265
266 if (drm)
267 drm_dev_exit(idx);
268 }
269 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)270 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
271 #endif
272
vc4_hdmi_reset_link(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx)273 static int vc4_hdmi_reset_link(struct drm_connector *connector,
274 struct drm_modeset_acquire_ctx *ctx)
275 {
276 struct drm_device *drm;
277 struct vc4_hdmi *vc4_hdmi;
278 struct drm_connector_state *conn_state;
279 struct drm_crtc_state *crtc_state;
280 struct drm_crtc *crtc;
281 bool scrambling_needed;
282 u8 config;
283 int ret;
284
285 if (!connector)
286 return 0;
287
288 drm = connector->dev;
289 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
290 if (ret)
291 return ret;
292
293 conn_state = connector->state;
294 crtc = conn_state->crtc;
295 if (!crtc)
296 return 0;
297
298 ret = drm_modeset_lock(&crtc->mutex, ctx);
299 if (ret)
300 return ret;
301
302 crtc_state = crtc->state;
303 if (!crtc_state->active)
304 return 0;
305
306 vc4_hdmi = connector_to_vc4_hdmi(connector);
307 mutex_lock(&vc4_hdmi->mutex);
308
309 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
310 mutex_unlock(&vc4_hdmi->mutex);
311 return 0;
312 }
313
314 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
315 vc4_hdmi->output_bpc,
316 vc4_hdmi->output_format);
317 if (!scrambling_needed) {
318 mutex_unlock(&vc4_hdmi->mutex);
319 return 0;
320 }
321
322 if (conn_state->commit &&
323 !try_wait_for_completion(&conn_state->commit->hw_done)) {
324 mutex_unlock(&vc4_hdmi->mutex);
325 return 0;
326 }
327
328 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
329 if (ret < 0) {
330 drm_err(drm, "Failed to read TMDS config: %d\n", ret);
331 mutex_unlock(&vc4_hdmi->mutex);
332 return 0;
333 }
334
335 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
336 mutex_unlock(&vc4_hdmi->mutex);
337 return 0;
338 }
339
340 mutex_unlock(&vc4_hdmi->mutex);
341
342 /*
343 * HDMI 2.0 says that one should not send scrambled data
344 * prior to configuring the sink scrambling, and that
345 * TMDS clock/data transmission should be suspended when
346 * changing the TMDS clock rate in the sink. So let's
347 * just do a full modeset here, even though some sinks
348 * would be perfectly happy if were to just reconfigure
349 * the SCDC settings on the fly.
350 */
351 return drm_atomic_helper_reset_crtc(crtc, ctx);
352 }
353
vc4_hdmi_handle_hotplug(struct vc4_hdmi * vc4_hdmi,struct drm_modeset_acquire_ctx * ctx,enum drm_connector_status status)354 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
355 struct drm_modeset_acquire_ctx *ctx,
356 enum drm_connector_status status)
357 {
358 struct drm_connector *connector = &vc4_hdmi->connector;
359 int ret;
360
361 /*
362 * NOTE: This function should really be called with vc4_hdmi->mutex
363 * held, but doing so results in reentrancy issues since
364 * cec_s_phys_addr() might call .adap_enable, which leads to that
365 * funtion being called with our mutex held.
366 *
367 * A similar situation occurs with vc4_hdmi_reset_link() that
368 * will call into our KMS hooks if the scrambling was enabled.
369 *
370 * Concurrency isn't an issue at the moment since we don't share
371 * any state with any of the other frameworks so we can ignore
372 * the lock for now.
373 */
374
375 if (status == connector_status_disconnected) {
376 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
377 return;
378 }
379
380 drm_atomic_helper_connector_hdmi_hotplug(connector, status);
381
382 cec_s_phys_addr(vc4_hdmi->cec_adap,
383 connector->display_info.source_physical_address, false);
384
385 if (status != connector_status_connected)
386 return;
387
388 for (;;) {
389 ret = vc4_hdmi_reset_link(connector, ctx);
390 if (ret == -EDEADLK) {
391 drm_modeset_backoff(ctx);
392 continue;
393 }
394
395 break;
396 }
397 }
398
vc4_hdmi_connector_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)399 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
400 struct drm_modeset_acquire_ctx *ctx,
401 bool force)
402 {
403 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
404 enum drm_connector_status status = connector_status_disconnected;
405 int ret;
406
407 /*
408 * NOTE: This function should really take vc4_hdmi->mutex, but
409 * doing so results in reentrancy issues since
410 * vc4_hdmi_handle_hotplug() can call into other functions that
411 * would take the mutex while it's held here.
412 *
413 * Concurrency isn't an issue at the moment since we don't share
414 * any state with any of the other frameworks so we can ignore
415 * the lock for now.
416 */
417
418 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
419 if (ret) {
420 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n",
421 ret);
422 return connector_status_unknown;
423 }
424
425 if (vc4_hdmi->hpd_gpio) {
426 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
427 status = connector_status_connected;
428 } else {
429 if (vc4_hdmi->variant->hp_detect &&
430 vc4_hdmi->variant->hp_detect(vc4_hdmi))
431 status = connector_status_connected;
432 }
433
434 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
435 pm_runtime_put(&vc4_hdmi->pdev->dev);
436
437 return status;
438 }
439
vc4_hdmi_connector_get_modes(struct drm_connector * connector)440 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
441 {
442 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
443 int ret = 0;
444
445 ret = drm_edid_connector_add_modes(connector);
446
447 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
448 struct drm_device *drm = connector->dev;
449 const struct drm_display_mode *mode;
450
451 list_for_each_entry(mode, &connector->probed_modes, head) {
452 if (vc4_hdmi_mode_needs_scrambling(mode, 8, HDMI_COLORSPACE_RGB)) {
453 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
454 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
455 }
456 }
457 }
458
459 return ret;
460 }
461
vc4_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)462 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
463 struct drm_atomic_state *state)
464 {
465 struct drm_connector_state *old_state =
466 drm_atomic_get_old_connector_state(state, connector);
467 struct drm_connector_state *new_state =
468 drm_atomic_get_new_connector_state(state, connector);
469 struct drm_crtc *crtc = new_state->crtc;
470
471 if (!crtc)
472 return 0;
473
474 if (old_state->tv.margins.left != new_state->tv.margins.left ||
475 old_state->tv.margins.right != new_state->tv.margins.right ||
476 old_state->tv.margins.top != new_state->tv.margins.top ||
477 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
478 struct drm_crtc_state *crtc_state;
479 int ret;
480
481 crtc_state = drm_atomic_get_crtc_state(state, crtc);
482 if (IS_ERR(crtc_state))
483 return PTR_ERR(crtc_state);
484
485 /*
486 * Strictly speaking, we should be calling
487 * drm_atomic_helper_check_planes() after our call to
488 * drm_atomic_add_affected_planes(). However, the
489 * connector atomic_check is called as part of
490 * drm_atomic_helper_check_modeset() that already
491 * happens before a call to
492 * drm_atomic_helper_check_planes() in
493 * drm_atomic_helper_check().
494 */
495 ret = drm_atomic_add_affected_planes(state, crtc);
496 if (ret)
497 return ret;
498 }
499
500 if (old_state->colorspace != new_state->colorspace) {
501 struct drm_crtc_state *crtc_state;
502
503 crtc_state = drm_atomic_get_crtc_state(state, crtc);
504 if (IS_ERR(crtc_state))
505 return PTR_ERR(crtc_state);
506
507 crtc_state->mode_changed = true;
508 }
509
510 return drm_atomic_helper_connector_hdmi_check(connector, state);
511 }
512
vc4_hdmi_connector_reset(struct drm_connector * connector)513 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
514 {
515 drm_atomic_helper_connector_reset(connector);
516 __drm_atomic_helper_connector_hdmi_reset(connector, connector->state);
517 drm_atomic_helper_connector_tv_margins_reset(connector);
518 }
519
520 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
521 .force = drm_atomic_helper_connector_hdmi_force,
522 .fill_modes = drm_helper_probe_single_connector_modes,
523 .reset = vc4_hdmi_connector_reset,
524 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
525 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
526 };
527
528 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
529 .detect_ctx = vc4_hdmi_connector_detect_ctx,
530 .get_modes = vc4_hdmi_connector_get_modes,
531 .atomic_check = vc4_hdmi_connector_atomic_check,
532 .mode_valid = drm_hdmi_connector_mode_valid,
533 };
534
535 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs;
536 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs;
537
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)538 static int vc4_hdmi_connector_init(struct drm_device *dev,
539 struct vc4_hdmi *vc4_hdmi)
540 {
541 struct drm_connector *connector = &vc4_hdmi->connector;
542 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
543 unsigned int max_bpc = 8;
544 int ret;
545
546 if (vc4_hdmi->variant->supports_hdr)
547 max_bpc = 12;
548
549 ret = drmm_connector_hdmi_init(dev, connector,
550 "Broadcom", "Videocore",
551 &vc4_hdmi_connector_funcs,
552 &vc4_hdmi_hdmi_connector_funcs,
553 DRM_MODE_CONNECTOR_HDMIA,
554 vc4_hdmi->ddc,
555 BIT(HDMI_COLORSPACE_RGB) |
556 BIT(HDMI_COLORSPACE_YUV422) |
557 BIT(HDMI_COLORSPACE_YUV444),
558 max_bpc);
559 if (ret)
560 return ret;
561
562 ret = drm_connector_hdmi_audio_init(connector, dev->dev,
563 &vc4_hdmi_audio_funcs,
564 8, false, -1);
565 if (ret)
566 return ret;
567
568 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
569
570 /*
571 * Some of the properties below require access to state, like bpc.
572 * Allocate some default initial connector state with our reset helper.
573 */
574 if (connector->funcs->reset)
575 connector->funcs->reset(connector);
576
577 /* Create and attach TV margin props to this connector. */
578 ret = drm_mode_create_tv_margin_properties(dev);
579 if (ret)
580 return ret;
581
582 ret = drm_mode_create_hdmi_colorspace_property(connector, 0);
583 if (ret)
584 return ret;
585
586 drm_connector_attach_colorspace_property(connector);
587 drm_connector_attach_tv_margin_properties(connector);
588
589 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
590 DRM_CONNECTOR_POLL_DISCONNECT);
591
592 connector->interlace_allowed = 1;
593 connector->doublescan_allowed = 0;
594 connector->stereo_allowed = 1;
595
596 ret = drm_connector_attach_broadcast_rgb_property(connector);
597 if (ret)
598 return ret;
599
600 drm_connector_attach_encoder(connector, encoder);
601
602 return 0;
603 }
604
vc4_hdmi_stop_packet(struct vc4_hdmi * vc4_hdmi,enum hdmi_infoframe_type type,bool poll)605 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi,
606 enum hdmi_infoframe_type type,
607 bool poll)
608 {
609 struct drm_device *drm = vc4_hdmi->connector.dev;
610 u32 packet_id = type - 0x80;
611 unsigned long flags;
612 int ret = 0;
613 int idx;
614
615 if (!drm_dev_enter(drm, &idx))
616 return -ENODEV;
617
618 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
619 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
620 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
621 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
622
623 if (poll) {
624 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
625 BIT(packet_id)), 100);
626 }
627
628 drm_dev_exit(idx);
629 return ret;
630 }
631
vc4_hdmi_write_infoframe(struct drm_connector * connector,enum hdmi_infoframe_type type,const u8 * infoframe,size_t len)632 static int vc4_hdmi_write_infoframe(struct drm_connector *connector,
633 enum hdmi_infoframe_type type,
634 const u8 *infoframe, size_t len)
635 {
636 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
637 struct drm_device *drm = connector->dev;
638 u32 packet_id = type - 0x80;
639 const struct vc4_hdmi_register *ram_packet_start =
640 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
641 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
642 u32 packet_reg_next = ram_packet_start->offset +
643 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
644 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
645 ram_packet_start->reg);
646 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
647 unsigned long flags;
648 ssize_t i;
649 int ret;
650 int idx;
651
652 if (!drm_dev_enter(drm, &idx))
653 return 0;
654
655 if (len > sizeof(buffer)) {
656 ret = -ENOMEM;
657 goto out;
658 }
659
660 memcpy(buffer, infoframe, len);
661
662 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
663 VC4_HDMI_RAM_PACKET_ENABLE),
664 "Packet RAM has to be on to store the packet.");
665
666 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true);
667 if (ret) {
668 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret);
669 goto out;
670 }
671
672 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
673
674 for (i = 0; i < len; i += 7) {
675 writel(buffer[i + 0] << 0 |
676 buffer[i + 1] << 8 |
677 buffer[i + 2] << 16,
678 base + packet_reg);
679 packet_reg += 4;
680
681 writel(buffer[i + 3] << 0 |
682 buffer[i + 4] << 8 |
683 buffer[i + 5] << 16 |
684 buffer[i + 6] << 24,
685 base + packet_reg);
686 packet_reg += 4;
687 }
688
689 /*
690 * clear remainder of packet ram as it's included in the
691 * infoframe and triggers a checksum error on hdmi analyser
692 */
693 for (; packet_reg < packet_reg_next; packet_reg += 4)
694 writel(0, base + packet_reg);
695
696 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
697 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
698
699 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
700
701 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
702 BIT(packet_id)), 100);
703 if (ret)
704 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret);
705
706 out:
707 drm_dev_exit(idx);
708 return ret;
709 }
710
711 #define SCRAMBLING_POLLING_DELAY_MS 1000
712
vc4_hdmi_enable_scrambling(struct drm_encoder * encoder)713 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
714 {
715 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
716 struct drm_connector *connector = &vc4_hdmi->connector;
717 struct drm_device *drm = connector->dev;
718 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
719 unsigned long flags;
720 int idx;
721
722 lockdep_assert_held(&vc4_hdmi->mutex);
723
724 if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
725 return;
726
727 if (!vc4_hdmi_mode_needs_scrambling(mode,
728 vc4_hdmi->output_bpc,
729 vc4_hdmi->output_format))
730 return;
731
732 if (!drm_dev_enter(drm, &idx))
733 return;
734
735 drm_scdc_set_high_tmds_clock_ratio(connector, true);
736 drm_scdc_set_scrambling(connector, true);
737
738 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
739 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
740 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
741 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
742
743 drm_dev_exit(idx);
744
745 vc4_hdmi->scdc_enabled = true;
746
747 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
748 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
749 }
750
vc4_hdmi_disable_scrambling(struct drm_encoder * encoder)751 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
752 {
753 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
754 struct drm_connector *connector = &vc4_hdmi->connector;
755 struct drm_device *drm = connector->dev;
756 unsigned long flags;
757 int idx;
758
759 lockdep_assert_held(&vc4_hdmi->mutex);
760
761 if (!vc4_hdmi->scdc_enabled)
762 return;
763
764 vc4_hdmi->scdc_enabled = false;
765
766 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
767 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
768
769 if (!drm_dev_enter(drm, &idx))
770 return;
771
772 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
773 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
774 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
775 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
776
777 drm_scdc_set_scrambling(connector, false);
778 drm_scdc_set_high_tmds_clock_ratio(connector, false);
779
780 drm_dev_exit(idx);
781 }
782
vc4_hdmi_scrambling_wq(struct work_struct * work)783 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
784 {
785 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
786 struct vc4_hdmi,
787 scrambling_work);
788 struct drm_connector *connector = &vc4_hdmi->connector;
789
790 if (drm_scdc_get_scrambling_status(connector))
791 return;
792
793 drm_scdc_set_high_tmds_clock_ratio(connector, true);
794 drm_scdc_set_scrambling(connector, true);
795
796 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
797 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
798 }
799
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)800 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
801 struct drm_atomic_state *state)
802 {
803 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
804 struct drm_device *drm = vc4_hdmi->connector.dev;
805 struct vc4_dev *vc4 = to_vc4_dev(drm);
806 unsigned long flags;
807 int idx;
808
809 mutex_lock(&vc4_hdmi->mutex);
810
811 vc4_hdmi->packet_ram_enabled = false;
812
813 if (!drm_dev_enter(drm, &idx))
814 goto out;
815
816 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
817
818 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
819
820 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
821
822 if (vc4->gen >= VC4_GEN_6_C)
823 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
824 VC4_HD_VID_CTL_BLANKPIX);
825
826 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
827
828 mdelay(1);
829
830 /*
831 * TODO: This should work on BCM2712, but doesn't for some
832 * reason and result in a system lockup.
833 */
834 if (vc4->gen < VC4_GEN_6_C) {
835 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
836 HDMI_WRITE(HDMI_VID_CTL,
837 HDMI_READ(HDMI_VID_CTL) &
838 ~VC4_HD_VID_CTL_ENABLE);
839 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
840 }
841
842 vc4_hdmi_disable_scrambling(encoder);
843
844 drm_dev_exit(idx);
845
846 out:
847 mutex_unlock(&vc4_hdmi->mutex);
848 }
849
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)850 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
851 struct drm_atomic_state *state)
852 {
853 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
854 struct drm_device *drm = vc4_hdmi->connector.dev;
855 unsigned long flags;
856 int ret;
857 int idx;
858
859 mutex_lock(&vc4_hdmi->mutex);
860
861 if (!drm_dev_enter(drm, &idx))
862 goto out;
863
864 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
865 HDMI_WRITE(HDMI_VID_CTL,
866 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
867 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
868
869 if (vc4_hdmi->variant->phy_disable)
870 vc4_hdmi->variant->phy_disable(vc4_hdmi);
871
872 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
873 clk_disable_unprepare(vc4_hdmi->pixel_clock);
874
875 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
876 if (ret < 0)
877 drm_err(drm, "Failed to release power domain: %d\n", ret);
878
879 drm_dev_exit(idx);
880
881 out:
882 mutex_unlock(&vc4_hdmi->mutex);
883 }
884
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)885 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
886 struct drm_connector_state *state,
887 const struct drm_display_mode *mode)
888 {
889 struct drm_device *drm = vc4_hdmi->connector.dev;
890 unsigned long flags;
891 u32 csc_ctl;
892 int idx;
893
894 if (!drm_dev_enter(drm, &idx))
895 return;
896
897 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
898
899 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
900 VC4_HD_CSC_CTL_ORDER);
901
902 if (state->hdmi.is_limited_range) {
903 /* CEA VICs other than #1 requre limited range RGB
904 * output unless overridden by an AVI infoframe.
905 * Apply a colorspace conversion to squash 0-255 down
906 * to 16-235. The matrix here is:
907 *
908 * [ 0 0 0.8594 16]
909 * [ 0 0.8594 0 16]
910 * [ 0.8594 0 0 16]
911 * [ 0 0 0 1]
912 */
913 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
914 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
915 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
916 VC4_HD_CSC_CTL_MODE);
917
918 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
919 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
920 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
921 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
922 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
923 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
924 }
925
926 /* The RGB order applies even when CSC is disabled. */
927 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
928
929 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
930
931 drm_dev_exit(idx);
932 }
933
934 /*
935 * Matrices for (internal) RGB to RGB output.
936 *
937 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
938 */
939 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = {
940 {
941 /*
942 * Full range - unity
943 *
944 * [ 1 0 0 0]
945 * [ 0 1 0 0]
946 * [ 0 0 1 0]
947 */
948 { 0x2000, 0x0000, 0x0000, 0x0000 },
949 { 0x0000, 0x2000, 0x0000, 0x0000 },
950 { 0x0000, 0x0000, 0x2000, 0x0000 },
951 },
952 {
953 /*
954 * Limited range
955 *
956 * CEA VICs other than #1 require limited range RGB
957 * output unless overridden by an AVI infoframe. Apply a
958 * colorspace conversion to squash 0-255 down to 16-235.
959 * The matrix here is:
960 *
961 * [ 0.8594 0 0 16]
962 * [ 0 0.8594 0 16]
963 * [ 0 0 0.8594 16]
964 */
965 { 0x1b80, 0x0000, 0x0000, 0x0400 },
966 { 0x0000, 0x1b80, 0x0000, 0x0400 },
967 { 0x0000, 0x0000, 0x1b80, 0x0400 },
968 },
969 };
970
971 /*
972 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace
973 *
974 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
975 */
976 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = {
977 {
978 /*
979 * Full Range
980 *
981 * [ 0.299000 0.587000 0.114000 0 ]
982 * [ -0.168736 -0.331264 0.500000 128 ]
983 * [ 0.500000 -0.418688 -0.081312 128 ]
984 */
985 { 0x0991, 0x12c9, 0x03a6, 0x0000 },
986 { 0xfa9b, 0xf567, 0x1000, 0x2000 },
987 { 0x1000, 0xf29b, 0xfd67, 0x2000 },
988 },
989 {
990 /* Limited Range
991 *
992 * [ 0.255785 0.502160 0.097523 16 ]
993 * [ -0.147644 -0.289856 0.437500 128 ]
994 * [ 0.437500 -0.366352 -0.071148 128 ]
995 */
996 { 0x082f, 0x1012, 0x031f, 0x0400 },
997 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
998 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
999 },
1000 };
1001
1002 /*
1003 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace
1004 *
1005 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1006 */
1007 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = {
1008 {
1009 /*
1010 * Full Range
1011 *
1012 * [ 0.212600 0.715200 0.072200 0 ]
1013 * [ -0.114572 -0.385428 0.500000 128 ]
1014 * [ 0.500000 -0.454153 -0.045847 128 ]
1015 */
1016 { 0x06ce, 0x16e3, 0x024f, 0x0000 },
1017 { 0xfc56, 0xf3ac, 0x1000, 0x2000 },
1018 { 0x1000, 0xf179, 0xfe89, 0x2000 },
1019 },
1020 {
1021 /*
1022 * Limited Range
1023 *
1024 * [ 0.181906 0.611804 0.061758 16 ]
1025 * [ -0.100268 -0.337232 0.437500 128 ]
1026 * [ 0.437500 -0.397386 -0.040114 128 ]
1027 */
1028 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1029 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
1030 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
1031 },
1032 };
1033
1034 /*
1035 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace
1036 *
1037 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets
1038 */
1039 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = {
1040 {
1041 /*
1042 * Full Range
1043 *
1044 * [ 0.262700 0.678000 0.059300 0 ]
1045 * [ -0.139630 -0.360370 0.500000 128 ]
1046 * [ 0.500000 -0.459786 -0.040214 128 ]
1047 */
1048 { 0x0868, 0x15b2, 0x01e6, 0x0000 },
1049 { 0xfb89, 0xf479, 0x1000, 0x2000 },
1050 { 0x1000, 0xf14a, 0xfeb8, 0x2000 },
1051 },
1052 {
1053 /* Limited Range
1054 *
1055 * [ 0.224732 0.580008 0.050729 16 ]
1056 * [ -0.122176 -0.315324 0.437500 128 ]
1057 * [ 0.437500 -0.402312 -0.035188 128 ]
1058 */
1059 { 0x082f, 0x1012, 0x031f, 0x0400 },
1060 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 },
1061 { 0x0e00, 0xf448, 0xfdba, 0x2000 },
1062 },
1063 };
1064
vc5_hdmi_set_csc_coeffs(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1065 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1066 const u16 coeffs[3][4])
1067 {
1068 lockdep_assert_held(&vc4_hdmi->hw_lock);
1069
1070 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1071 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1072 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1073 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1074 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1075 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1076 }
1077
vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi * vc4_hdmi,const u16 coeffs[3][4])1078 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi,
1079 const u16 coeffs[3][4])
1080 {
1081 lockdep_assert_held(&vc4_hdmi->hw_lock);
1082
1083 /* YUV444 needs the CSC matrices using the channels in a different order */
1084 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]);
1085 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]);
1086 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]);
1087 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]);
1088 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]);
1089 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]);
1090 }
1091
1092 static const u16
vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi * vc4_hdmi,u32 colorspace,bool limited)1093 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4]
1094 {
1095 switch (colorspace) {
1096 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC:
1097 case DRM_MODE_COLORIMETRY_XVYCC_601:
1098 case DRM_MODE_COLORIMETRY_SYCC_601:
1099 case DRM_MODE_COLORIMETRY_OPYCC_601:
1100 case DRM_MODE_COLORIMETRY_BT601_YCC:
1101 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited];
1102
1103 default:
1104 case DRM_MODE_COLORIMETRY_NO_DATA:
1105 case DRM_MODE_COLORIMETRY_BT709_YCC:
1106 case DRM_MODE_COLORIMETRY_XVYCC_709:
1107 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED:
1108 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT:
1109 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited];
1110
1111 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
1112 case DRM_MODE_COLORIMETRY_BT2020_YCC:
1113 case DRM_MODE_COLORIMETRY_BT2020_RGB:
1114 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
1115 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
1116 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited];
1117 }
1118 }
1119
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1120 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1121 struct drm_connector_state *state,
1122 const struct drm_display_mode *mode)
1123 {
1124 struct drm_device *drm = vc4_hdmi->connector.dev;
1125 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0;
1126 unsigned long flags;
1127 const u16 (*csc)[4];
1128 u32 if_cfg = 0;
1129 u32 if_xbar = 0x543210;
1130 u32 csc_chan_ctl = 0;
1131 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1132 VC5_MT_CP_CSC_CTL_MODE);
1133 int idx;
1134
1135 if (!drm_dev_enter(drm, &idx))
1136 return;
1137
1138 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1139
1140 switch (state->hdmi.output_format) {
1141 case HDMI_COLORSPACE_YUV444:
1142 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1143
1144 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc);
1145 break;
1146
1147 case HDMI_COLORSPACE_YUV422:
1148 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range);
1149
1150 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1151 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1152 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1153 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1154
1155 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1156 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1157
1158 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1159 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1160
1161 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc);
1162 break;
1163
1164 case HDMI_COLORSPACE_RGB:
1165 if_xbar = 0x354021;
1166
1167 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]);
1168 break;
1169
1170 default:
1171 break;
1172 }
1173
1174 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1175 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1176 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1177 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1178
1179 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1180
1181 drm_dev_exit(idx);
1182 }
1183
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1184 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1185 struct drm_connector_state *state,
1186 const struct drm_display_mode *mode)
1187 {
1188 struct drm_device *drm = vc4_hdmi->connector.dev;
1189 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1190 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1191 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1192 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1193 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1194 VC4_HDMI_VERTA_VSP) |
1195 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1196 VC4_HDMI_VERTA_VFP) |
1197 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1198 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1199 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1200 interlaced,
1201 VC4_HDMI_VERTB_VBP));
1202 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1203 VC4_SET_FIELD(mode->crtc_vtotal -
1204 mode->crtc_vsync_end,
1205 VC4_HDMI_VERTB_VBP));
1206 unsigned long flags;
1207 u32 reg;
1208 int idx;
1209
1210 if (!drm_dev_enter(drm, &idx))
1211 return;
1212
1213 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1214
1215 HDMI_WRITE(HDMI_HORZA,
1216 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1217 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1218 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1219 VC4_HDMI_HORZA_HAP));
1220
1221 HDMI_WRITE(HDMI_HORZB,
1222 VC4_SET_FIELD((mode->htotal -
1223 mode->hsync_end) * pixel_rep,
1224 VC4_HDMI_HORZB_HBP) |
1225 VC4_SET_FIELD((mode->hsync_end -
1226 mode->hsync_start) * pixel_rep,
1227 VC4_HDMI_HORZB_HSP) |
1228 VC4_SET_FIELD((mode->hsync_start -
1229 mode->hdisplay) * pixel_rep,
1230 VC4_HDMI_HORZB_HFP));
1231
1232 HDMI_WRITE(HDMI_VERTA0, verta);
1233 HDMI_WRITE(HDMI_VERTA1, verta);
1234
1235 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1236 HDMI_WRITE(HDMI_VERTB1, vertb);
1237
1238 reg = HDMI_READ(HDMI_MISC_CONTROL);
1239 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1240 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1241 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1242
1243 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1244
1245 drm_dev_exit(idx);
1246 }
1247
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,const struct drm_display_mode * mode)1248 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1249 struct drm_connector_state *state,
1250 const struct drm_display_mode *mode)
1251 {
1252 struct drm_device *drm = vc4_hdmi->connector.dev;
1253 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1254 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1255 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1256 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1257 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1258 VC5_HDMI_VERTA_VSP) |
1259 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1260 VC5_HDMI_VERTA_VFP) |
1261 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1262 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1263 VC5_HDMI_VERTB_VSPO) |
1264 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1265 interlaced,
1266 VC4_HDMI_VERTB_VBP));
1267 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1268 VC4_SET_FIELD(mode->crtc_vtotal -
1269 mode->crtc_vsync_end,
1270 VC4_HDMI_VERTB_VBP));
1271 unsigned long flags;
1272 unsigned char gcp;
1273 u32 reg;
1274 int idx;
1275
1276 if (!drm_dev_enter(drm, &idx))
1277 return;
1278
1279 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1280
1281 HDMI_WRITE(HDMI_HORZA,
1282 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1283 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1284 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1285 VC5_HDMI_HORZA_HAP) |
1286 VC4_SET_FIELD((mode->hsync_start -
1287 mode->hdisplay) * pixel_rep,
1288 VC5_HDMI_HORZA_HFP));
1289
1290 HDMI_WRITE(HDMI_HORZB,
1291 VC4_SET_FIELD((mode->htotal -
1292 mode->hsync_end) * pixel_rep,
1293 VC5_HDMI_HORZB_HBP) |
1294 VC4_SET_FIELD((mode->hsync_end -
1295 mode->hsync_start) * pixel_rep,
1296 VC5_HDMI_HORZB_HSP));
1297
1298 HDMI_WRITE(HDMI_VERTA0, verta);
1299 HDMI_WRITE(HDMI_VERTA1, verta);
1300
1301 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1302 HDMI_WRITE(HDMI_VERTB1, vertb);
1303
1304 switch (state->hdmi.output_bpc) {
1305 case 12:
1306 gcp = 6;
1307 break;
1308 case 10:
1309 gcp = 5;
1310 break;
1311 case 8:
1312 default:
1313 gcp = 0;
1314 break;
1315 }
1316
1317 /*
1318 * YCC422 is always 36-bit and not considered deep colour so
1319 * doesn't signal in GCP.
1320 */
1321 if (state->hdmi.output_format == HDMI_COLORSPACE_YUV422) {
1322 gcp = 0;
1323 }
1324
1325 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1326 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1327 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1328 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1329 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1330 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1331
1332 reg = HDMI_READ(HDMI_GCP_WORD_1);
1333 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1334 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1335 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
1336 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
1337 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1338
1339 reg = HDMI_READ(HDMI_GCP_CONFIG);
1340 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1341 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1342
1343 reg = HDMI_READ(HDMI_MISC_CONTROL);
1344 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1345 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1346 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1347
1348 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1349
1350 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1351
1352 drm_dev_exit(idx);
1353 }
1354
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)1355 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1356 {
1357 struct drm_device *drm = vc4_hdmi->connector.dev;
1358 unsigned long flags;
1359 u32 drift;
1360 int ret;
1361 int idx;
1362
1363 if (!drm_dev_enter(drm, &idx))
1364 return;
1365
1366 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1367
1368 drift = HDMI_READ(HDMI_FIFO_CTL);
1369 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1370
1371 HDMI_WRITE(HDMI_FIFO_CTL,
1372 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1373 HDMI_WRITE(HDMI_FIFO_CTL,
1374 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1375
1376 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1377
1378 usleep_range(1000, 1100);
1379
1380 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1381
1382 HDMI_WRITE(HDMI_FIFO_CTL,
1383 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1384 HDMI_WRITE(HDMI_FIFO_CTL,
1385 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1386
1387 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1388
1389 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1390 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1391 WARN_ONCE(ret, "Timeout waiting for "
1392 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1393
1394 drm_dev_exit(idx);
1395 }
1396
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)1397 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1398 struct drm_atomic_state *state)
1399 {
1400 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1401 struct drm_device *drm = vc4_hdmi->connector.dev;
1402 struct drm_connector *connector = &vc4_hdmi->connector;
1403 struct drm_connector_state *conn_state =
1404 drm_atomic_get_new_connector_state(state, connector);
1405 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1406 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate;
1407 unsigned long bvb_rate, hsm_rate;
1408 unsigned long flags;
1409 int ret;
1410 int idx;
1411
1412 mutex_lock(&vc4_hdmi->mutex);
1413
1414 if (!drm_dev_enter(drm, &idx))
1415 goto out;
1416
1417 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1418 if (ret < 0) {
1419 drm_err(drm, "Failed to retain power domain: %d\n", ret);
1420 goto err_dev_exit;
1421 }
1422
1423 /*
1424 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1425 * be faster than pixel clock, infinitesimally faster, tested in
1426 * simulation. Otherwise, exact value is unimportant for HDMI
1427 * operation." This conflicts with bcm2835's vc4 documentation, which
1428 * states HSM's clock has to be at least 108% of the pixel clock.
1429 *
1430 * Real life tests reveal that vc4's firmware statement holds up, and
1431 * users are able to use pixel clocks closer to HSM's, namely for
1432 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1433 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1434 * 162MHz.
1435 *
1436 * Additionally, the AXI clock needs to be at least 25% of
1437 * pixel clock, but HSM ends up being the limiting factor.
1438 */
1439 hsm_rate = max_t(unsigned long,
1440 HSM_MIN_CLOCK_FREQ,
1441 div_u64(tmds_char_rate, 100) * 101);
1442 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1443 if (ret) {
1444 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret);
1445 goto err_put_runtime_pm;
1446 }
1447
1448 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1449 if (ret) {
1450 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret);
1451 goto err_put_runtime_pm;
1452 }
1453
1454 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1455 if (ret) {
1456 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret);
1457 goto err_put_runtime_pm;
1458 }
1459
1460 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1461
1462 if (tmds_char_rate > 297000000)
1463 bvb_rate = 300000000;
1464 else if (tmds_char_rate > 148500000)
1465 bvb_rate = 150000000;
1466 else
1467 bvb_rate = 75000000;
1468
1469 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1470 if (ret) {
1471 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret);
1472 goto err_disable_pixel_clock;
1473 }
1474
1475 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1476 if (ret) {
1477 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret);
1478 goto err_disable_pixel_clock;
1479 }
1480
1481 if (vc4_hdmi->variant->phy_init)
1482 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state);
1483
1484 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1485
1486 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1487 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1488 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1489 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1490
1491 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1492
1493 if (vc4_hdmi->variant->set_timings)
1494 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1495
1496 drm_dev_exit(idx);
1497
1498 mutex_unlock(&vc4_hdmi->mutex);
1499
1500 return;
1501
1502 err_disable_pixel_clock:
1503 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1504 err_put_runtime_pm:
1505 pm_runtime_put(&vc4_hdmi->pdev->dev);
1506 err_dev_exit:
1507 drm_dev_exit(idx);
1508 out:
1509 mutex_unlock(&vc4_hdmi->mutex);
1510 return;
1511 }
1512
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1513 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1514 struct drm_atomic_state *state)
1515 {
1516 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1517 struct drm_device *drm = vc4_hdmi->connector.dev;
1518 struct drm_connector *connector = &vc4_hdmi->connector;
1519 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1520 struct drm_connector_state *conn_state =
1521 drm_atomic_get_new_connector_state(state, connector);
1522 unsigned long flags;
1523 int idx;
1524
1525 mutex_lock(&vc4_hdmi->mutex);
1526
1527 if (!drm_dev_enter(drm, &idx))
1528 goto out;
1529
1530 if (vc4_hdmi->variant->csc_setup)
1531 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1532
1533 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1534 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1535 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1536
1537 drm_dev_exit(idx);
1538
1539 out:
1540 mutex_unlock(&vc4_hdmi->mutex);
1541 }
1542
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1543 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1544 struct drm_atomic_state *state)
1545 {
1546 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1547 struct drm_connector *connector = &vc4_hdmi->connector;
1548 struct drm_device *drm = connector->dev;
1549 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1550 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1551 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1552 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1553 unsigned long flags;
1554 int ret;
1555 int idx;
1556
1557 mutex_lock(&vc4_hdmi->mutex);
1558
1559 if (!drm_dev_enter(drm, &idx))
1560 goto out;
1561
1562 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1563
1564 HDMI_WRITE(HDMI_VID_CTL,
1565 (HDMI_READ(HDMI_VID_CTL) &
1566 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) |
1567 VC4_HD_VID_CTL_ENABLE |
1568 VC4_HD_VID_CTL_CLRRGB |
1569 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1570 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1571 VC4_HD_VID_CTL_BLANK_INSERT_EN |
1572 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1573 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1574
1575 HDMI_WRITE(HDMI_VID_CTL,
1576 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1577
1578 if (display->is_hdmi) {
1579 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1580 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1581 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1582
1583 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1584
1585 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1586 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1587 WARN_ONCE(ret, "Timeout waiting for "
1588 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1589 } else {
1590 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1591 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1592 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1593 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1594 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1595 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1596
1597 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1598
1599 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1600 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1601 WARN_ONCE(ret, "Timeout waiting for "
1602 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1603 }
1604
1605 if (display->is_hdmi) {
1606 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1607
1608 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1609 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1610
1611 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1612 VC4_HDMI_RAM_PACKET_ENABLE);
1613
1614 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1615 vc4_hdmi->packet_ram_enabled = true;
1616
1617 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
1618 }
1619
1620 vc4_hdmi_recenter_fifo(vc4_hdmi);
1621 vc4_hdmi_enable_scrambling(encoder);
1622
1623 drm_dev_exit(idx);
1624
1625 out:
1626 mutex_unlock(&vc4_hdmi->mutex);
1627 }
1628
vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1629 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1630 struct drm_crtc_state *crtc_state,
1631 struct drm_connector_state *conn_state)
1632 {
1633 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1634
1635 mutex_lock(&vc4_hdmi->mutex);
1636 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1637 &crtc_state->adjusted_mode);
1638 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc;
1639 vc4_hdmi->output_format = conn_state->hdmi.output_format;
1640 mutex_unlock(&vc4_hdmi->mutex);
1641 }
1642
1643 static enum drm_mode_status
vc4_hdmi_connector_clock_valid(const struct drm_connector * connector,const struct drm_display_mode * mode,unsigned long long clock)1644 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector,
1645 const struct drm_display_mode *mode,
1646 unsigned long long clock)
1647 {
1648 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1649 struct vc4_dev *vc4 = to_vc4_dev(connector->dev);
1650
1651 if (clock > vc4_hdmi->variant->max_pixel_clock)
1652 return MODE_CLOCK_HIGH;
1653
1654 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
1655 return MODE_CLOCK_HIGH;
1656
1657 /* 4096x2160@60 is not reliable without overclocking core */
1658 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 &&
1659 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
1660 drm_mode_vrefresh(mode) >= 50)
1661 return MODE_CLOCK_HIGH;
1662
1663 return MODE_OK;
1664 }
1665
1666 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = {
1667 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid,
1668 .write_infoframe = vc4_hdmi_write_infoframe,
1669 };
1670
1671 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1672 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1673
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1674 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1675 struct drm_crtc_state *crtc_state,
1676 struct drm_connector_state *conn_state)
1677 {
1678 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1679 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1680 unsigned long long tmds_char_rate = mode->clock * 1000;
1681 unsigned long long tmds_bit_rate;
1682
1683 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1684 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1685 /* Only try to fixup DBLCLK modes to get 480i and 576i
1686 * working.
1687 * A generic solution for all modes with odd horizontal
1688 * timing values seems impossible based on trying to
1689 * solve it for 1366x768 monitors.
1690 */
1691 if ((mode->hsync_start - mode->hdisplay) & 1)
1692 mode->hsync_start--;
1693 if ((mode->hsync_end - mode->hsync_start) & 1)
1694 mode->hsync_end--;
1695 }
1696
1697 /* Now check whether we still have odd values remaining */
1698 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1699 (mode->hsync_end % 2) || (mode->htotal % 2))
1700 return -EINVAL;
1701 }
1702
1703 /*
1704 * The 1440p@60 pixel rate is in the same range than the first
1705 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1706 * bandwidth). Slightly lower the frequency to bring it out of
1707 * the WiFi range.
1708 */
1709 tmds_bit_rate = tmds_char_rate * 10;
1710 if (vc4_hdmi->disable_wifi_frequencies &&
1711 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1712 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1713 mode->clock = 238560;
1714 tmds_char_rate = mode->clock * 1000;
1715 }
1716
1717 return 0;
1718 }
1719
1720 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)1721 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1722 const struct drm_display_mode *mode)
1723 {
1724 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1725
1726 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1727 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1728 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1729 (mode->hsync_end % 2) || (mode->htotal % 2)))
1730 return MODE_H_ILLEGAL;
1731
1732 return MODE_OK;
1733 }
1734
1735 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1736 .atomic_check = vc4_hdmi_encoder_atomic_check,
1737 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1738 .mode_valid = vc4_hdmi_encoder_mode_valid,
1739 };
1740
vc4_hdmi_late_register(struct drm_encoder * encoder)1741 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1742 {
1743 struct drm_device *drm = encoder->dev;
1744 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1745 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1746
1747 drm_debugfs_add_file(drm, variant->debugfs_name,
1748 vc4_hdmi_debugfs_regs, vc4_hdmi);
1749
1750 return 0;
1751 }
1752
1753 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1754 .late_register = vc4_hdmi_late_register,
1755 };
1756
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1757 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1758 {
1759 int i;
1760 u32 channel_map = 0;
1761
1762 for (i = 0; i < 8; i++) {
1763 if (channel_mask & BIT(i))
1764 channel_map |= i << (3 * i);
1765 }
1766 return channel_map;
1767 }
1768
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1769 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1770 {
1771 int i;
1772 u32 channel_map = 0;
1773
1774 for (i = 0; i < 8; i++) {
1775 if (channel_mask & BIT(i))
1776 channel_map |= i << (4 * i);
1777 }
1778 return channel_map;
1779 }
1780
vc5_hdmi_hp_detect(struct vc4_hdmi * vc4_hdmi)1781 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1782 {
1783 struct drm_device *drm = vc4_hdmi->connector.dev;
1784 unsigned long flags;
1785 u32 hotplug;
1786 int idx;
1787
1788 if (!drm_dev_enter(drm, &idx))
1789 return false;
1790
1791 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1792 hotplug = HDMI_READ(HDMI_HOTPLUG);
1793 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1794
1795 drm_dev_exit(idx);
1796
1797 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1798 }
1799
1800 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1801 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1802 unsigned int samplerate)
1803 {
1804 struct drm_device *drm = vc4_hdmi->connector.dev;
1805 u32 hsm_clock;
1806 unsigned long flags;
1807 unsigned long n, m;
1808 int idx;
1809
1810 if (!drm_dev_enter(drm, &idx))
1811 return;
1812
1813 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1814 rational_best_approximation(hsm_clock, samplerate,
1815 VC4_HD_MAI_SMP_N_MASK >>
1816 VC4_HD_MAI_SMP_N_SHIFT,
1817 (VC4_HD_MAI_SMP_M_MASK >>
1818 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1819 &n, &m);
1820
1821 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1822 HDMI_WRITE(HDMI_MAI_SMP,
1823 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1824 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1825 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1826
1827 drm_dev_exit(idx);
1828 }
1829
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi,unsigned int samplerate)1830 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1831 {
1832 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1833 u32 n, cts;
1834 u64 tmp;
1835
1836 lockdep_assert_held(&vc4_hdmi->mutex);
1837 lockdep_assert_held(&vc4_hdmi->hw_lock);
1838
1839 n = 128 * samplerate / 1000;
1840 tmp = (u64)(mode->clock * 1000) * n;
1841 do_div(tmp, 128 * samplerate);
1842 cts = tmp;
1843
1844 HDMI_WRITE(HDMI_CRP_CFG,
1845 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1846 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1847
1848 /*
1849 * We could get slightly more accurate clocks in some cases by
1850 * providing a CTS_1 value. The two CTS values are alternated
1851 * between based on the period fields
1852 */
1853 HDMI_WRITE(HDMI_CTS_0, cts);
1854 HDMI_WRITE(HDMI_CTS_1, cts);
1855 }
1856
dai_to_hdmi(struct snd_soc_dai * dai)1857 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1858 {
1859 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1860
1861 return snd_soc_card_get_drvdata(card);
1862 }
1863
vc4_hdmi_audio_can_stream(struct vc4_hdmi * vc4_hdmi)1864 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1865 {
1866 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1867
1868 lockdep_assert_held(&vc4_hdmi->mutex);
1869
1870 /*
1871 * If the encoder is currently in DVI mode, treat the codec DAI
1872 * as missing.
1873 */
1874 if (!display->is_hdmi)
1875 return false;
1876
1877 return true;
1878 }
1879
vc4_hdmi_audio_startup(struct drm_connector * connector)1880 static int vc4_hdmi_audio_startup(struct drm_connector *connector)
1881 {
1882 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1883 struct drm_device *drm = vc4_hdmi->connector.dev;
1884 unsigned long flags;
1885 int ret = 0;
1886 int idx;
1887
1888 mutex_lock(&vc4_hdmi->mutex);
1889
1890 if (!drm_dev_enter(drm, &idx)) {
1891 ret = -ENODEV;
1892 goto out;
1893 }
1894
1895 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
1896 ret = -ENOTSUPP;
1897 goto out_dev_exit;
1898 }
1899
1900 vc4_hdmi->audio.streaming = true;
1901
1902 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1903 HDMI_WRITE(HDMI_MAI_CTL,
1904 VC4_HD_MAI_CTL_RESET |
1905 VC4_HD_MAI_CTL_FLUSH |
1906 VC4_HD_MAI_CTL_DLATE |
1907 VC4_HD_MAI_CTL_ERRORE |
1908 VC4_HD_MAI_CTL_ERRORF);
1909 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1910
1911 if (vc4_hdmi->variant->phy_rng_enable)
1912 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1913
1914 out_dev_exit:
1915 drm_dev_exit(idx);
1916 out:
1917 mutex_unlock(&vc4_hdmi->mutex);
1918
1919 return ret;
1920 }
1921
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1922 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1923 {
1924 struct device *dev = &vc4_hdmi->pdev->dev;
1925 unsigned long flags;
1926 int ret;
1927
1928 lockdep_assert_held(&vc4_hdmi->mutex);
1929
1930 vc4_hdmi->audio.streaming = false;
1931 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false);
1932 if (ret)
1933 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1934
1935 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1936
1937 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1938 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1939 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1940
1941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1942 }
1943
vc4_hdmi_audio_shutdown(struct drm_connector * connector)1944 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector)
1945 {
1946 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
1947 struct drm_device *drm = vc4_hdmi->connector.dev;
1948 unsigned long flags;
1949 int idx;
1950
1951 mutex_lock(&vc4_hdmi->mutex);
1952
1953 if (!drm_dev_enter(drm, &idx))
1954 goto out;
1955
1956 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1957
1958 HDMI_WRITE(HDMI_MAI_CTL,
1959 VC4_HD_MAI_CTL_DLATE |
1960 VC4_HD_MAI_CTL_ERRORE |
1961 VC4_HD_MAI_CTL_ERRORF);
1962
1963 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1964
1965 if (vc4_hdmi->variant->phy_rng_disable)
1966 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1967
1968 vc4_hdmi->audio.streaming = false;
1969 vc4_hdmi_audio_reset(vc4_hdmi);
1970
1971 drm_dev_exit(idx);
1972
1973 out:
1974 mutex_unlock(&vc4_hdmi->mutex);
1975 }
1976
sample_rate_to_mai_fmt(int samplerate)1977 static int sample_rate_to_mai_fmt(int samplerate)
1978 {
1979 switch (samplerate) {
1980 case 8000:
1981 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1982 case 11025:
1983 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1984 case 12000:
1985 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1986 case 16000:
1987 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1988 case 22050:
1989 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1990 case 24000:
1991 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1992 case 32000:
1993 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1994 case 44100:
1995 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1996 case 48000:
1997 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1998 case 64000:
1999 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2000 case 88200:
2001 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2002 case 96000:
2003 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2004 case 128000:
2005 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2006 case 176400:
2007 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2008 case 192000:
2009 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2010 default:
2011 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2012 }
2013 }
2014
2015 /* HDMI audio codec callbacks */
vc4_hdmi_audio_prepare(struct drm_connector * connector,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2016 static int vc4_hdmi_audio_prepare(struct drm_connector *connector,
2017 struct hdmi_codec_daifmt *daifmt,
2018 struct hdmi_codec_params *params)
2019 {
2020 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
2021 struct drm_device *drm = vc4_hdmi->connector.dev;
2022 struct vc4_dev *vc4 = to_vc4_dev(drm);
2023 unsigned int sample_rate = params->sample_rate;
2024 unsigned int channels = params->channels;
2025 unsigned long flags;
2026 u32 audio_packet_config, channel_mask;
2027 u32 channel_map;
2028 u32 mai_audio_format;
2029 u32 mai_sample_rate;
2030 int ret = 0;
2031 int idx;
2032
2033 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2034 sample_rate, params->sample_width, channels);
2035
2036 mutex_lock(&vc4_hdmi->mutex);
2037
2038 if (!drm_dev_enter(drm, &idx)) {
2039 ret = -ENODEV;
2040 goto out;
2041 }
2042
2043 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2044 ret = -EINVAL;
2045 goto out_dev_exit;
2046 }
2047
2048 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2049
2050 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2051 HDMI_WRITE(HDMI_MAI_CTL,
2052 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2053 VC4_HD_MAI_CTL_WHOLSMP |
2054 VC4_HD_MAI_CTL_CHALIGN |
2055 VC4_HD_MAI_CTL_ENABLE);
2056
2057 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2058 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2059 params->channels == 8)
2060 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2061 else
2062 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2063 HDMI_WRITE(HDMI_MAI_FMT,
2064 VC4_SET_FIELD(mai_sample_rate,
2065 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2066 VC4_SET_FIELD(mai_audio_format,
2067 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2068
2069 /* The B frame identifier should match the value used by alsa-lib (8) */
2070 audio_packet_config =
2071 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2072 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2073 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2074
2075 channel_mask = GENMASK(channels - 1, 0);
2076 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2077 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2078
2079 /* Set the MAI threshold */
2080 switch (vc4->gen) {
2081 case VC4_GEN_6_D:
2082 HDMI_WRITE(HDMI_MAI_THR,
2083 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) |
2084 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) |
2085 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) |
2086 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW));
2087 break;
2088 case VC4_GEN_6_C:
2089 case VC4_GEN_5:
2090 HDMI_WRITE(HDMI_MAI_THR,
2091 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
2092 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
2093 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) |
2094 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW));
2095 break;
2096 case VC4_GEN_4:
2097 HDMI_WRITE(HDMI_MAI_THR,
2098 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) |
2099 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) |
2100 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) |
2101 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW));
2102 break;
2103 default:
2104 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen);
2105 break;
2106 }
2107
2108 HDMI_WRITE(HDMI_MAI_CONFIG,
2109 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2110 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2111 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2112
2113 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2114 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2115 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2116
2117 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2118
2119 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2120
2121 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector,
2122 ¶ms->cea);
2123 if (ret)
2124 goto out_dev_exit;
2125
2126 out_dev_exit:
2127 drm_dev_exit(idx);
2128 out:
2129 mutex_unlock(&vc4_hdmi->mutex);
2130
2131 return ret;
2132 }
2133
2134 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2135 .name = "vc4-hdmi-cpu-dai-component",
2136 .legacy_dai_naming = 1,
2137 };
2138
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)2139 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2140 {
2141 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2142
2143 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2144
2145 return 0;
2146 }
2147
2148 static const struct snd_soc_dai_ops vc4_snd_dai_ops = {
2149 .probe = vc4_hdmi_audio_cpu_dai_probe,
2150 };
2151
2152 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2153 .name = "vc4-hdmi-cpu-dai",
2154 .ops = &vc4_snd_dai_ops,
2155 .playback = {
2156 .stream_name = "Playback",
2157 .channels_min = 1,
2158 .channels_max = 8,
2159 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2160 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2161 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2162 SNDRV_PCM_RATE_192000,
2163 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2164 },
2165 };
2166
2167 static const struct snd_dmaengine_pcm_config pcm_conf = {
2168 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2169 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2170 };
2171
2172 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = {
2173 .startup = vc4_hdmi_audio_startup,
2174 .prepare = vc4_hdmi_audio_prepare,
2175 .shutdown = vc4_hdmi_audio_shutdown,
2176 };
2177
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)2178 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2179 {
2180 const struct vc4_hdmi_register *mai_data =
2181 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2182 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2183 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2184 struct device *dev = &vc4_hdmi->pdev->dev;
2185 const __be32 *addr;
2186 int index, len;
2187 int ret;
2188
2189 /*
2190 * ASoC makes it a bit hard to retrieve a pointer to the
2191 * vc4_hdmi structure. Registering the card will overwrite our
2192 * device drvdata with a pointer to the snd_soc_card structure,
2193 * which can then be used to retrieve whatever drvdata we want
2194 * to associate.
2195 *
2196 * However, that doesn't fly in the case where we wouldn't
2197 * register an ASoC card (because of an old DT that is missing
2198 * the dmas properties for example), then the card isn't
2199 * registered and the device drvdata wouldn't be set.
2200 *
2201 * We can deal with both cases by making sure a snd_soc_card
2202 * pointer and a vc4_hdmi structure are pointing to the same
2203 * memory address, so we can treat them indistinctly without any
2204 * issue.
2205 */
2206 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2207 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2208
2209 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2210 dev_warn(dev,
2211 "'dmas' DT property is missing or empty, no HDMI audio\n");
2212 return 0;
2213 }
2214
2215 if (mai_data->reg != VC4_HD) {
2216 WARN_ONCE(true, "MAI isn't in the HD block\n");
2217 return -EINVAL;
2218 }
2219
2220 /*
2221 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2222 * the bus address specified in the DT, because the physical address
2223 * (the one returned by platform_get_resource()) is not appropriate
2224 * for DMA transfers.
2225 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2226 */
2227 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2228 /* Before BCM2711, we don't have a named register range */
2229 if (index < 0)
2230 index = 1;
2231
2232 addr = of_get_address(dev->of_node, index, NULL, NULL);
2233 if (!addr)
2234 return -EINVAL;
2235
2236 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2237 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2238 vc4_hdmi->audio.dma_data.maxburst = 2;
2239
2240 /*
2241 * NOTE: Strictly speaking, we should probably use a DRM-managed
2242 * registration there to avoid removing all the audio components
2243 * by the time the driver doesn't have any user anymore.
2244 *
2245 * However, the ASoC core uses a number of devm_kzalloc calls
2246 * when registering, even when using non-device-managed
2247 * functions (such as in snd_soc_register_component()).
2248 *
2249 * If we call snd_soc_unregister_component() in a DRM-managed
2250 * action, the device-managed actions have already been executed
2251 * and thus we would access memory that has been freed.
2252 *
2253 * Using device-managed hooks here probably leaves us open to a
2254 * bunch of issues if userspace still has a handle on the ALSA
2255 * device when the device is removed. However, this is mitigated
2256 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2257 * path to prevent the access to the device resources if it
2258 * isn't there anymore.
2259 *
2260 * Then, the vc4_hdmi structure is DRM-managed and thus only
2261 * freed whenever the last user has closed the DRM device file.
2262 * It should thus outlive ALSA in most situations.
2263 */
2264 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2265 if (ret) {
2266 dev_err(dev, "Could not register PCM component: %d\n", ret);
2267 return ret;
2268 }
2269
2270 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2271 &vc4_hdmi_audio_cpu_dai_drv, 1);
2272 if (ret) {
2273 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2274 return ret;
2275 }
2276
2277 dai_link->cpus = &vc4_hdmi->audio.cpu;
2278 dai_link->codecs = &vc4_hdmi->audio.codec;
2279 dai_link->platforms = &vc4_hdmi->audio.platform;
2280
2281 dai_link->num_cpus = 1;
2282 dai_link->num_codecs = 1;
2283 dai_link->num_platforms = 1;
2284
2285 dai_link->name = "MAI";
2286 dai_link->stream_name = "MAI PCM";
2287 dai_link->codecs->dai_name = "i2s-hifi";
2288 dai_link->cpus->dai_name = dev_name(dev);
2289 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev);
2290 dai_link->platforms->name = dev_name(dev);
2291
2292 card->dai_link = dai_link;
2293 card->num_links = 1;
2294 card->name = vc4_hdmi->variant->card_name;
2295 card->driver_name = "vc4-hdmi";
2296 card->dev = dev;
2297 card->owner = THIS_MODULE;
2298
2299 /*
2300 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2301 * stores a pointer to the snd card object in dev->driver_data. This
2302 * means we cannot use it for something else. The hdmi back-pointer is
2303 * now stored in card->drvdata and should be retrieved with
2304 * snd_soc_card_get_drvdata() if needed.
2305 */
2306 snd_soc_card_set_drvdata(card, vc4_hdmi);
2307 ret = devm_snd_soc_register_card(dev, card);
2308 if (ret)
2309 dev_err_probe(dev, ret, "Could not register sound card\n");
2310
2311 return ret;
2312
2313 }
2314
vc4_hdmi_hpd_irq_thread(int irq,void * priv)2315 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2316 {
2317 struct vc4_hdmi *vc4_hdmi = priv;
2318 struct drm_connector *connector = &vc4_hdmi->connector;
2319 struct drm_device *dev = connector->dev;
2320
2321 if (dev && dev->registered)
2322 drm_connector_helper_hpd_irq_event(connector);
2323
2324 return IRQ_HANDLED;
2325 }
2326
vc4_hdmi_hotplug_init(struct vc4_hdmi * vc4_hdmi)2327 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2328 {
2329 struct drm_connector *connector = &vc4_hdmi->connector;
2330 struct platform_device *pdev = vc4_hdmi->pdev;
2331 int ret;
2332
2333 if (vc4_hdmi->variant->external_irq_controller) {
2334 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2335 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2336
2337 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2338 NULL,
2339 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2340 "vc4 hdmi hpd connected", vc4_hdmi);
2341 if (ret)
2342 return ret;
2343
2344 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2345 NULL,
2346 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2347 "vc4 hdmi hpd disconnected", vc4_hdmi);
2348 if (ret)
2349 return ret;
2350
2351 connector->polled = DRM_CONNECTOR_POLL_HPD;
2352 }
2353
2354 return 0;
2355 }
2356
2357 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)2358 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2359 {
2360 struct vc4_hdmi *vc4_hdmi = priv;
2361
2362 if (vc4_hdmi->cec_rx_msg.len)
2363 cec_received_msg(vc4_hdmi->cec_adap,
2364 &vc4_hdmi->cec_rx_msg);
2365
2366 return IRQ_HANDLED;
2367 }
2368
vc4_cec_irq_handler_tx_thread(int irq,void * priv)2369 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2370 {
2371 struct vc4_hdmi *vc4_hdmi = priv;
2372
2373 if (vc4_hdmi->cec_tx_ok) {
2374 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2375 0, 0, 0, 0);
2376 } else {
2377 /*
2378 * This CEC implementation makes 1 retry, so if we
2379 * get a NACK, then that means it made 2 attempts.
2380 */
2381 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2382 0, 2, 0, 0);
2383 }
2384 return IRQ_HANDLED;
2385 }
2386
vc4_cec_irq_handler_thread(int irq,void * priv)2387 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2388 {
2389 struct vc4_hdmi *vc4_hdmi = priv;
2390 irqreturn_t ret;
2391
2392 if (vc4_hdmi->cec_irq_was_rx)
2393 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2394 else
2395 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2396
2397 return ret;
2398 }
2399
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)2400 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2401 {
2402 struct drm_device *dev = vc4_hdmi->connector.dev;
2403 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2404 unsigned int i;
2405
2406 lockdep_assert_held(&vc4_hdmi->hw_lock);
2407
2408 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2409 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2410
2411 if (msg->len > 16) {
2412 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2413 return;
2414 }
2415
2416 for (i = 0; i < msg->len; i += 4) {
2417 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2418
2419 msg->msg[i] = val & 0xff;
2420 msg->msg[i + 1] = (val >> 8) & 0xff;
2421 msg->msg[i + 2] = (val >> 16) & 0xff;
2422 msg->msg[i + 3] = (val >> 24) & 0xff;
2423 }
2424 }
2425
vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi * vc4_hdmi)2426 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2427 {
2428 u32 cntrl1;
2429
2430 /*
2431 * We don't need to protect the register access using
2432 * drm_dev_enter() there because the interrupt handler lifetime
2433 * is tied to the device itself, and not to the DRM device.
2434 *
2435 * So when the device will be gone, one of the first thing we
2436 * will be doing will be to unregister the interrupt handler,
2437 * and then unregister the DRM device. drm_dev_enter() would
2438 * thus always succeed if we are here.
2439 */
2440
2441 lockdep_assert_held(&vc4_hdmi->hw_lock);
2442
2443 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2444 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2445 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2446 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2447
2448 return IRQ_WAKE_THREAD;
2449 }
2450
vc4_cec_irq_handler_tx_bare(int irq,void * priv)2451 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2452 {
2453 struct vc4_hdmi *vc4_hdmi = priv;
2454 irqreturn_t ret;
2455
2456 spin_lock(&vc4_hdmi->hw_lock);
2457 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2458 spin_unlock(&vc4_hdmi->hw_lock);
2459
2460 return ret;
2461 }
2462
vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi * vc4_hdmi)2463 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2464 {
2465 u32 cntrl1;
2466
2467 lockdep_assert_held(&vc4_hdmi->hw_lock);
2468
2469 /*
2470 * We don't need to protect the register access using
2471 * drm_dev_enter() there because the interrupt handler lifetime
2472 * is tied to the device itself, and not to the DRM device.
2473 *
2474 * So when the device will be gone, one of the first thing we
2475 * will be doing will be to unregister the interrupt handler,
2476 * and then unregister the DRM device. drm_dev_enter() would
2477 * thus always succeed if we are here.
2478 */
2479
2480 vc4_hdmi->cec_rx_msg.len = 0;
2481 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2482 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2483 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2484 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2485 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2486
2487 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2488
2489 return IRQ_WAKE_THREAD;
2490 }
2491
vc4_cec_irq_handler_rx_bare(int irq,void * priv)2492 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2493 {
2494 struct vc4_hdmi *vc4_hdmi = priv;
2495 irqreturn_t ret;
2496
2497 spin_lock(&vc4_hdmi->hw_lock);
2498 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2499 spin_unlock(&vc4_hdmi->hw_lock);
2500
2501 return ret;
2502 }
2503
vc4_cec_irq_handler(int irq,void * priv)2504 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2505 {
2506 struct vc4_hdmi *vc4_hdmi = priv;
2507 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2508 irqreturn_t ret;
2509 u32 cntrl5;
2510
2511 /*
2512 * We don't need to protect the register access using
2513 * drm_dev_enter() there because the interrupt handler lifetime
2514 * is tied to the device itself, and not to the DRM device.
2515 *
2516 * So when the device will be gone, one of the first thing we
2517 * will be doing will be to unregister the interrupt handler,
2518 * and then unregister the DRM device. drm_dev_enter() would
2519 * thus always succeed if we are here.
2520 */
2521
2522 if (!(stat & VC4_HDMI_CPU_CEC))
2523 return IRQ_NONE;
2524
2525 spin_lock(&vc4_hdmi->hw_lock);
2526 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2527 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2528 if (vc4_hdmi->cec_irq_was_rx)
2529 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2530 else
2531 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2532
2533 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2534 spin_unlock(&vc4_hdmi->hw_lock);
2535
2536 return ret;
2537 }
2538
vc4_hdmi_cec_enable(struct cec_adapter * adap)2539 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2540 {
2541 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2542 struct drm_device *drm = vc4_hdmi->connector.dev;
2543 /* clock period in microseconds */
2544 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2545 unsigned long flags;
2546 u32 val;
2547 int ret;
2548 int idx;
2549
2550 if (!drm_dev_enter(drm, &idx))
2551 /*
2552 * We can't return an error code, because the CEC
2553 * framework will emit WARN_ON messages at unbind
2554 * otherwise.
2555 */
2556 return 0;
2557
2558 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2559 if (ret) {
2560 drm_dev_exit(idx);
2561 return ret;
2562 }
2563
2564 mutex_lock(&vc4_hdmi->mutex);
2565
2566 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2567
2568 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2569 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2570 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2571 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2572 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2573 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2574
2575 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2576 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2577 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2578 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2579 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2580 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2581 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2582 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2583 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2584 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2585 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2586 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2587 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2588 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2589 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2590 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2591 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2592 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2593 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2594
2595 if (!vc4_hdmi->variant->external_irq_controller)
2596 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2597
2598 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2599
2600 mutex_unlock(&vc4_hdmi->mutex);
2601 drm_dev_exit(idx);
2602
2603 return 0;
2604 }
2605
vc4_hdmi_cec_disable(struct cec_adapter * adap)2606 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2607 {
2608 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2609 struct drm_device *drm = vc4_hdmi->connector.dev;
2610 unsigned long flags;
2611 int idx;
2612
2613 if (!drm_dev_enter(drm, &idx))
2614 /*
2615 * We can't return an error code, because the CEC
2616 * framework will emit WARN_ON messages at unbind
2617 * otherwise.
2618 */
2619 return 0;
2620
2621 mutex_lock(&vc4_hdmi->mutex);
2622
2623 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2624
2625 if (!vc4_hdmi->variant->external_irq_controller)
2626 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2627
2628 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2629 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2630
2631 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2632
2633 mutex_unlock(&vc4_hdmi->mutex);
2634
2635 pm_runtime_put(&vc4_hdmi->pdev->dev);
2636
2637 drm_dev_exit(idx);
2638
2639 return 0;
2640 }
2641
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)2642 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2643 {
2644 if (enable)
2645 return vc4_hdmi_cec_enable(adap);
2646 else
2647 return vc4_hdmi_cec_disable(adap);
2648 }
2649
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)2650 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2651 {
2652 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2653 struct drm_device *drm = vc4_hdmi->connector.dev;
2654 unsigned long flags;
2655 int idx;
2656
2657 if (!drm_dev_enter(drm, &idx))
2658 /*
2659 * We can't return an error code, because the CEC
2660 * framework will emit WARN_ON messages at unbind
2661 * otherwise.
2662 */
2663 return 0;
2664
2665 mutex_lock(&vc4_hdmi->mutex);
2666 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2667 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2668 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2669 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2670 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2671 mutex_unlock(&vc4_hdmi->mutex);
2672
2673 drm_dev_exit(idx);
2674
2675 return 0;
2676 }
2677
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)2678 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2679 u32 signal_free_time, struct cec_msg *msg)
2680 {
2681 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2682 struct drm_device *dev = vc4_hdmi->connector.dev;
2683 unsigned long flags;
2684 u32 val;
2685 unsigned int i;
2686 int idx;
2687
2688 if (!drm_dev_enter(dev, &idx))
2689 return -ENODEV;
2690
2691 if (msg->len > 16) {
2692 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2693 drm_dev_exit(idx);
2694 return -ENOMEM;
2695 }
2696
2697 mutex_lock(&vc4_hdmi->mutex);
2698
2699 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2700
2701 for (i = 0; i < msg->len; i += 4)
2702 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2703 (msg->msg[i]) |
2704 (msg->msg[i + 1] << 8) |
2705 (msg->msg[i + 2] << 16) |
2706 (msg->msg[i + 3] << 24));
2707
2708 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2709 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2710 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2711 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2712 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2713 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2714
2715 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2716
2717 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2718 mutex_unlock(&vc4_hdmi->mutex);
2719 drm_dev_exit(idx);
2720
2721 return 0;
2722 }
2723
2724 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2725 .adap_enable = vc4_hdmi_cec_adap_enable,
2726 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2727 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2728 };
2729
vc4_hdmi_cec_release(void * ptr)2730 static void vc4_hdmi_cec_release(void *ptr)
2731 {
2732 struct vc4_hdmi *vc4_hdmi = ptr;
2733
2734 cec_unregister_adapter(vc4_hdmi->cec_adap);
2735 vc4_hdmi->cec_adap = NULL;
2736 }
2737
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2738 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2739 {
2740 struct cec_connector_info conn_info;
2741 struct platform_device *pdev = vc4_hdmi->pdev;
2742 struct device *dev = &pdev->dev;
2743 int ret;
2744
2745 if (!of_property_present(dev->of_node, "interrupts")) {
2746 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2747 return 0;
2748 }
2749
2750 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2751 vc4_hdmi,
2752 vc4_hdmi->variant->card_name,
2753 CEC_CAP_DEFAULTS |
2754 CEC_CAP_CONNECTOR_INFO, 1);
2755 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2756 if (ret < 0)
2757 return ret;
2758
2759 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2760 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2761
2762 if (vc4_hdmi->variant->external_irq_controller) {
2763 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2764 vc4_cec_irq_handler_rx_bare,
2765 vc4_cec_irq_handler_rx_thread, 0,
2766 "vc4 hdmi cec rx", vc4_hdmi);
2767 if (ret)
2768 goto err_delete_cec_adap;
2769
2770 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2771 vc4_cec_irq_handler_tx_bare,
2772 vc4_cec_irq_handler_tx_thread, 0,
2773 "vc4 hdmi cec tx", vc4_hdmi);
2774 if (ret)
2775 goto err_delete_cec_adap;
2776 } else {
2777 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2778 vc4_cec_irq_handler,
2779 vc4_cec_irq_handler_thread, 0,
2780 "vc4 hdmi cec", vc4_hdmi);
2781 if (ret)
2782 goto err_delete_cec_adap;
2783 }
2784
2785 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2786 if (ret < 0)
2787 goto err_delete_cec_adap;
2788
2789 /*
2790 * NOTE: Strictly speaking, we should probably use a DRM-managed
2791 * registration there to avoid removing the CEC adapter by the
2792 * time the DRM driver doesn't have any user anymore.
2793 *
2794 * However, the CEC framework already cleans up the CEC adapter
2795 * only when the last user has closed its file descriptor, so we
2796 * don't need to handle it in DRM.
2797 *
2798 * By the time the device-managed hook is executed, we will give
2799 * up our reference to the CEC adapter and therefore don't
2800 * really care when it's actually freed.
2801 *
2802 * There's still a problematic sequence: if we unregister our
2803 * CEC adapter, but the userspace keeps a handle on the CEC
2804 * adapter but not the DRM device for some reason. In such a
2805 * case, our vc4_hdmi structure will be freed, but the
2806 * cec_adapter structure will have a dangling pointer to what
2807 * used to be our HDMI controller. If we get a CEC call at that
2808 * moment, we could end up with a use-after-free. Fortunately,
2809 * the CEC framework already handles this too, by calling
2810 * cec_is_registered() in cec_ioctl() and cec_poll().
2811 */
2812 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2813 if (ret)
2814 return ret;
2815
2816 return 0;
2817
2818 err_delete_cec_adap:
2819 cec_delete_adapter(vc4_hdmi->cec_adap);
2820
2821 return ret;
2822 }
2823 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)2824 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2825 {
2826 return 0;
2827 }
2828 #endif
2829
vc4_hdmi_free_regset(struct drm_device * drm,void * ptr)2830 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2831 {
2832 struct debugfs_reg32 *regs = ptr;
2833
2834 kfree(regs);
2835 }
2836
vc4_hdmi_build_regset(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)2837 static int vc4_hdmi_build_regset(struct drm_device *drm,
2838 struct vc4_hdmi *vc4_hdmi,
2839 struct debugfs_regset32 *regset,
2840 enum vc4_hdmi_regs reg)
2841 {
2842 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2843 struct debugfs_reg32 *regs, *new_regs;
2844 unsigned int count = 0;
2845 unsigned int i;
2846 int ret;
2847
2848 regs = kcalloc(variant->num_registers, sizeof(*regs),
2849 GFP_KERNEL);
2850 if (!regs)
2851 return -ENOMEM;
2852
2853 for (i = 0; i < variant->num_registers; i++) {
2854 const struct vc4_hdmi_register *field = &variant->registers[i];
2855
2856 if (field->reg != reg)
2857 continue;
2858
2859 regs[count].name = field->name;
2860 regs[count].offset = field->offset;
2861 count++;
2862 }
2863
2864 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
2865 if (!new_regs)
2866 return -ENOMEM;
2867
2868 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
2869 regset->regs = new_regs;
2870 regset->nregs = count;
2871
2872 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
2873 if (ret)
2874 return ret;
2875
2876 return 0;
2877 }
2878
vc4_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2879 static int vc4_hdmi_init_resources(struct drm_device *drm,
2880 struct vc4_hdmi *vc4_hdmi)
2881 {
2882 struct platform_device *pdev = vc4_hdmi->pdev;
2883 struct device *dev = &pdev->dev;
2884 int ret;
2885
2886 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
2887 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2888 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2889
2890 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
2891 if (IS_ERR(vc4_hdmi->hd_regs))
2892 return PTR_ERR(vc4_hdmi->hd_regs);
2893
2894 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
2895 if (ret)
2896 return ret;
2897
2898 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
2899 if (ret)
2900 return ret;
2901
2902 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
2903 if (IS_ERR(vc4_hdmi->pixel_clock)) {
2904 ret = PTR_ERR(vc4_hdmi->pixel_clock);
2905 if (ret != -EPROBE_DEFER)
2906 drm_err(drm, "Failed to get pixel clock\n");
2907 return ret;
2908 }
2909
2910 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2911 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2912 drm_err(drm, "Failed to get HDMI state machine clock\n");
2913 return PTR_ERR(vc4_hdmi->hsm_clock);
2914 }
2915 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
2916 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
2917
2918 return 0;
2919 }
2920
vc5_hdmi_init_resources(struct drm_device * drm,struct vc4_hdmi * vc4_hdmi)2921 static int vc5_hdmi_init_resources(struct drm_device *drm,
2922 struct vc4_hdmi *vc4_hdmi)
2923 {
2924 struct platform_device *pdev = vc4_hdmi->pdev;
2925 struct device *dev = &pdev->dev;
2926 struct resource *res;
2927 int ret;
2928
2929 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev,
2930 "hdmi");
2931 if (IS_ERR(vc4_hdmi->hdmicore_regs))
2932 return PTR_ERR(vc4_hdmi->hdmicore_regs);
2933
2934 /* This is shared between both HDMI controllers. Cannot
2935 * claim for both instances. Lets not convert to using
2936 * devm_platform_ioremap_resource_byname() like
2937 * the rest
2938 */
2939 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2940 if (!res)
2941 return -ENODEV;
2942
2943 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2944 if (!vc4_hdmi->hd_regs)
2945 return -ENOMEM;
2946
2947 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev,
2948 "cec");
2949 if (IS_ERR(vc4_hdmi->cec_regs))
2950 return PTR_ERR(vc4_hdmi->cec_regs);
2951
2952 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev,
2953 "csc");
2954 if (IS_ERR(vc4_hdmi->csc_regs))
2955 return PTR_ERR(vc4_hdmi->csc_regs);
2956
2957 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev,
2958 "dvp");
2959 if (IS_ERR(vc4_hdmi->dvp_regs))
2960 return PTR_ERR(vc4_hdmi->dvp_regs);
2961
2962 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev,
2963 "phy");
2964
2965 if (IS_ERR(vc4_hdmi->phy_regs))
2966 return PTR_ERR(vc4_hdmi->phy_regs);
2967
2968 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev,
2969 "packet");
2970 if (IS_ERR(vc4_hdmi->ram_regs))
2971 return PTR_ERR(vc4_hdmi->ram_regs);
2972
2973 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm");
2974 if (IS_ERR(vc4_hdmi->rm_regs))
2975 return PTR_ERR(vc4_hdmi->rm_regs);
2976
2977 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2978 if (IS_ERR(vc4_hdmi->hsm_clock)) {
2979 drm_err(drm, "Failed to get HDMI state machine clock\n");
2980 return PTR_ERR(vc4_hdmi->hsm_clock);
2981 }
2982
2983 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2984 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2985 drm_err(drm, "Failed to get pixel bvb clock\n");
2986 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2987 }
2988
2989 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2990 if (IS_ERR(vc4_hdmi->audio_clock)) {
2991 drm_err(drm, "Failed to get audio clock\n");
2992 return PTR_ERR(vc4_hdmi->audio_clock);
2993 }
2994
2995 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2996 if (IS_ERR(vc4_hdmi->cec_clock)) {
2997 drm_err(drm, "Failed to get CEC clock\n");
2998 return PTR_ERR(vc4_hdmi->cec_clock);
2999 }
3000
3001 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3002 if (IS_ERR(vc4_hdmi->reset)) {
3003 drm_err(drm, "Failed to get HDMI reset line\n");
3004 return PTR_ERR(vc4_hdmi->reset);
3005 }
3006
3007 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3008 if (ret)
3009 return ret;
3010
3011 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3012 if (ret)
3013 return ret;
3014
3015 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3016 if (ret)
3017 return ret;
3018
3019 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3020 if (ret)
3021 return ret;
3022
3023 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3024 if (ret)
3025 return ret;
3026
3027 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3028 if (ret)
3029 return ret;
3030
3031 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3032 if (ret)
3033 return ret;
3034
3035 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3036 if (ret)
3037 return ret;
3038
3039 return 0;
3040 }
3041
vc4_hdmi_runtime_suspend(struct device * dev)3042 static int vc4_hdmi_runtime_suspend(struct device *dev)
3043 {
3044 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3045
3046 clk_disable_unprepare(vc4_hdmi->audio_clock);
3047 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3048
3049 return 0;
3050 }
3051
vc4_hdmi_runtime_resume(struct device * dev)3052 static int vc4_hdmi_runtime_resume(struct device *dev)
3053 {
3054 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3055 unsigned long __maybe_unused flags;
3056 u32 __maybe_unused value;
3057 unsigned long rate;
3058 int ret;
3059
3060 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3061 if (ret)
3062 return ret;
3063
3064 /*
3065 * Whenever the RaspberryPi boots without an HDMI monitor
3066 * plugged in, the firmware won't have initialized the HSM clock
3067 * rate and it will be reported as 0.
3068 *
3069 * If we try to access a register of the controller in such a
3070 * case, it will lead to a silent CPU stall. Let's make sure we
3071 * prevent such a case.
3072 */
3073 rate = clk_get_rate(vc4_hdmi->hsm_clock);
3074 if (!rate) {
3075 ret = -EINVAL;
3076 goto err_disable_clk;
3077 }
3078
3079 ret = clk_prepare_enable(vc4_hdmi->audio_clock);
3080 if (ret)
3081 goto err_disable_clk;
3082
3083 if (vc4_hdmi->variant->reset)
3084 vc4_hdmi->variant->reset(vc4_hdmi);
3085
3086 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3087 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3088 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3089 /* Set the logical address to Unregistered */
3090 value |= VC4_HDMI_CEC_ADDR_MASK;
3091 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3092 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3093
3094 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3095
3096 if (!vc4_hdmi->variant->external_irq_controller) {
3097 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3098 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3099 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3100 }
3101 #endif
3102
3103 return 0;
3104
3105 err_disable_clk:
3106 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3107 return ret;
3108 }
3109
vc4_hdmi_put_ddc_device(void * ptr)3110 static void vc4_hdmi_put_ddc_device(void *ptr)
3111 {
3112 struct vc4_hdmi *vc4_hdmi = ptr;
3113
3114 put_device(&vc4_hdmi->ddc->dev);
3115 }
3116
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)3117 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3118 {
3119 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3120 struct platform_device *pdev = to_platform_device(dev);
3121 struct drm_device *drm = dev_get_drvdata(master);
3122 struct vc4_hdmi *vc4_hdmi;
3123 struct drm_encoder *encoder;
3124 struct device_node *ddc_node;
3125 int ret;
3126
3127 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3128 if (!vc4_hdmi)
3129 return -ENOMEM;
3130
3131 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3132 if (ret)
3133 return ret;
3134
3135 spin_lock_init(&vc4_hdmi->hw_lock);
3136 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3137
3138 dev_set_drvdata(dev, vc4_hdmi);
3139 encoder = &vc4_hdmi->encoder.base;
3140 vc4_hdmi->encoder.type = variant->encoder_type;
3141 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3142 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3143 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3144 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3145 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3146 vc4_hdmi->pdev = pdev;
3147 vc4_hdmi->variant = variant;
3148
3149 /*
3150 * Since we don't know the state of the controller and its
3151 * display (if any), let's assume it's always enabled.
3152 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3153 * sure it's disabled, and avoid any inconsistency.
3154 */
3155 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3156 vc4_hdmi->scdc_enabled = true;
3157
3158 ret = variant->init_resources(drm, vc4_hdmi);
3159 if (ret)
3160 return ret;
3161
3162 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3163 if (!ddc_node) {
3164 drm_err(drm, "Failed to find ddc node in device tree\n");
3165 return -ENODEV;
3166 }
3167
3168 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3169 of_node_put(ddc_node);
3170 if (!vc4_hdmi->ddc) {
3171 drm_err(drm, "Failed to get ddc i2c adapter by node\n");
3172 return -EPROBE_DEFER;
3173 }
3174
3175 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3176 if (ret)
3177 return ret;
3178
3179 /* Only use the GPIO HPD pin if present in the DT, otherwise
3180 * we'll use the HDMI core's register.
3181 */
3182 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3183 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3184 return PTR_ERR(vc4_hdmi->hpd_gpio);
3185 }
3186
3187 vc4_hdmi->disable_wifi_frequencies =
3188 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3189
3190 ret = devm_pm_runtime_enable(dev);
3191 if (ret)
3192 return ret;
3193
3194 /*
3195 * We need to have the device powered up at this point to call
3196 * our reset hook and for the CEC init.
3197 */
3198 ret = pm_runtime_resume_and_get(dev);
3199 if (ret)
3200 return ret;
3201
3202 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3203 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") ||
3204 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") ||
3205 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) &&
3206 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3207 clk_prepare_enable(vc4_hdmi->pixel_clock);
3208 clk_prepare_enable(vc4_hdmi->hsm_clock);
3209 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3210 }
3211
3212 ret = drmm_encoder_init(drm, encoder,
3213 &vc4_hdmi_encoder_funcs,
3214 DRM_MODE_ENCODER_TMDS,
3215 NULL);
3216 if (ret)
3217 goto err_put_runtime_pm;
3218
3219 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3220
3221 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3222 if (ret)
3223 goto err_put_runtime_pm;
3224
3225 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3226 if (ret)
3227 goto err_put_runtime_pm;
3228
3229 ret = vc4_hdmi_cec_init(vc4_hdmi);
3230 if (ret)
3231 goto err_put_runtime_pm;
3232
3233 ret = vc4_hdmi_audio_init(vc4_hdmi);
3234 if (ret)
3235 goto err_put_runtime_pm;
3236
3237 pm_runtime_put_sync(dev);
3238
3239 return 0;
3240
3241 err_put_runtime_pm:
3242 pm_runtime_put_sync(dev);
3243
3244 return ret;
3245 }
3246
3247 static const struct component_ops vc4_hdmi_ops = {
3248 .bind = vc4_hdmi_bind,
3249 };
3250
vc4_hdmi_dev_probe(struct platform_device * pdev)3251 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3252 {
3253 return component_add(&pdev->dev, &vc4_hdmi_ops);
3254 }
3255
vc4_hdmi_dev_remove(struct platform_device * pdev)3256 static void vc4_hdmi_dev_remove(struct platform_device *pdev)
3257 {
3258 component_del(&pdev->dev, &vc4_hdmi_ops);
3259 }
3260
3261 static const struct vc4_hdmi_variant bcm2835_variant = {
3262 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3263 .debugfs_name = "hdmi_regs",
3264 .card_name = "vc4-hdmi",
3265 .max_pixel_clock = 162000000,
3266 .registers = vc4_hdmi_fields,
3267 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3268
3269 .init_resources = vc4_hdmi_init_resources,
3270 .csc_setup = vc4_hdmi_csc_setup,
3271 .reset = vc4_hdmi_reset,
3272 .set_timings = vc4_hdmi_set_timings,
3273 .phy_init = vc4_hdmi_phy_init,
3274 .phy_disable = vc4_hdmi_phy_disable,
3275 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3276 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3277 .channel_map = vc4_hdmi_channel_map,
3278 .supports_hdr = false,
3279 };
3280
3281 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3282 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3283 .debugfs_name = "hdmi0_regs",
3284 .card_name = "vc4-hdmi-0",
3285 .max_pixel_clock = 600000000,
3286 .registers = vc5_hdmi_hdmi0_fields,
3287 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3288 .phy_lane_mapping = {
3289 PHY_LANE_0,
3290 PHY_LANE_1,
3291 PHY_LANE_2,
3292 PHY_LANE_CK,
3293 },
3294 .unsupported_odd_h_timings = true,
3295 .external_irq_controller = true,
3296
3297 .init_resources = vc5_hdmi_init_resources,
3298 .csc_setup = vc5_hdmi_csc_setup,
3299 .reset = vc5_hdmi_reset,
3300 .set_timings = vc5_hdmi_set_timings,
3301 .phy_init = vc5_hdmi_phy_init,
3302 .phy_disable = vc5_hdmi_phy_disable,
3303 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3304 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3305 .channel_map = vc5_hdmi_channel_map,
3306 .supports_hdr = true,
3307 .hp_detect = vc5_hdmi_hp_detect,
3308 };
3309
3310 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3311 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3312 .debugfs_name = "hdmi1_regs",
3313 .card_name = "vc4-hdmi-1",
3314 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3315 .registers = vc5_hdmi_hdmi1_fields,
3316 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3317 .phy_lane_mapping = {
3318 PHY_LANE_1,
3319 PHY_LANE_0,
3320 PHY_LANE_CK,
3321 PHY_LANE_2,
3322 },
3323 .unsupported_odd_h_timings = true,
3324 .external_irq_controller = true,
3325
3326 .init_resources = vc5_hdmi_init_resources,
3327 .csc_setup = vc5_hdmi_csc_setup,
3328 .reset = vc5_hdmi_reset,
3329 .set_timings = vc5_hdmi_set_timings,
3330 .phy_init = vc5_hdmi_phy_init,
3331 .phy_disable = vc5_hdmi_phy_disable,
3332 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3333 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3334 .channel_map = vc5_hdmi_channel_map,
3335 .supports_hdr = true,
3336 .hp_detect = vc5_hdmi_hp_detect,
3337 };
3338
3339 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
3340 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3341 .debugfs_name = "hdmi0_regs",
3342 .card_name = "vc4-hdmi-0",
3343 .max_pixel_clock = 600000000,
3344 .registers = vc6_hdmi_hdmi0_fields,
3345 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields),
3346 .phy_lane_mapping = {
3347 PHY_LANE_0,
3348 PHY_LANE_1,
3349 PHY_LANE_2,
3350 PHY_LANE_CK,
3351 },
3352 .unsupported_odd_h_timings = false,
3353 .external_irq_controller = true,
3354
3355 .init_resources = vc5_hdmi_init_resources,
3356 .csc_setup = vc5_hdmi_csc_setup,
3357 .reset = vc5_hdmi_reset,
3358 .set_timings = vc5_hdmi_set_timings,
3359 .phy_init = vc6_hdmi_phy_init,
3360 .phy_disable = vc6_hdmi_phy_disable,
3361 .channel_map = vc5_hdmi_channel_map,
3362 .supports_hdr = true,
3363 .hp_detect = vc5_hdmi_hp_detect,
3364 };
3365
3366 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
3367 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3368 .debugfs_name = "hdmi1_regs",
3369 .card_name = "vc4-hdmi-1",
3370 .max_pixel_clock = 600000000,
3371 .registers = vc6_hdmi_hdmi1_fields,
3372 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields),
3373 .phy_lane_mapping = {
3374 PHY_LANE_0,
3375 PHY_LANE_1,
3376 PHY_LANE_2,
3377 PHY_LANE_CK,
3378 },
3379 .unsupported_odd_h_timings = false,
3380 .external_irq_controller = true,
3381
3382 .init_resources = vc5_hdmi_init_resources,
3383 .csc_setup = vc5_hdmi_csc_setup,
3384 .reset = vc5_hdmi_reset,
3385 .set_timings = vc5_hdmi_set_timings,
3386 .phy_init = vc6_hdmi_phy_init,
3387 .phy_disable = vc6_hdmi_phy_disable,
3388 .channel_map = vc5_hdmi_channel_map,
3389 .supports_hdr = true,
3390 .hp_detect = vc5_hdmi_hp_detect,
3391 };
3392
3393 static const struct of_device_id vc4_hdmi_dt_match[] = {
3394 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3395 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3396 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3397 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant },
3398 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant },
3399 {}
3400 };
3401
3402 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3403 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3404 vc4_hdmi_runtime_resume,
3405 NULL)
3406 };
3407
3408 struct platform_driver vc4_hdmi_driver = {
3409 .probe = vc4_hdmi_dev_probe,
3410 .remove = vc4_hdmi_dev_remove,
3411 .driver = {
3412 .name = "vc4_hdmi",
3413 .of_match_table = vc4_hdmi_dt_match,
3414 .pm = &vc4_hdmi_pm_ops,
3415 },
3416 };
3417