1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2018 Broadcom */
3 
4 /**
5  * DOC: Broadcom V3D scheduling
6  *
7  * The shared DRM GPU scheduler is used to coordinate submitting jobs
8  * to the hardware. Each DRM fd (roughly a client process) gets its
9  * own scheduler entity, which will process jobs in order. The GPU
10  * scheduler will schedule the clients with a FIFO scheduling algorithm.
11  *
12  * For simplicity, and in order to keep latency low for interactive
13  * jobs when bulk background jobs are queued up, we submit a new job
14  * to the HW only when it has completed the last one, instead of
15  * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
16  * `drm_sched_job_add_dependency()` to manage the dependency between bin
17  * and render, instead of having the clients submit jobs using the HW's
18  * semaphores to interlock between them.
19  */
20 
21 #include <linux/sched/clock.h>
22 #include <linux/kthread.h>
23 
24 #include <drm/drm_syncobj.h>
25 
26 #include "v3d_drv.h"
27 #include "v3d_regs.h"
28 #include "v3d_trace.h"
29 
30 #define V3D_CSD_CFG012_WG_COUNT_SHIFT 16
31 
32 static struct v3d_job *
to_v3d_job(struct drm_sched_job * sched_job)33 to_v3d_job(struct drm_sched_job *sched_job)
34 {
35 	return container_of(sched_job, struct v3d_job, base);
36 }
37 
38 static struct v3d_bin_job *
to_bin_job(struct drm_sched_job * sched_job)39 to_bin_job(struct drm_sched_job *sched_job)
40 {
41 	return container_of(sched_job, struct v3d_bin_job, base.base);
42 }
43 
44 static struct v3d_render_job *
to_render_job(struct drm_sched_job * sched_job)45 to_render_job(struct drm_sched_job *sched_job)
46 {
47 	return container_of(sched_job, struct v3d_render_job, base.base);
48 }
49 
50 static struct v3d_tfu_job *
to_tfu_job(struct drm_sched_job * sched_job)51 to_tfu_job(struct drm_sched_job *sched_job)
52 {
53 	return container_of(sched_job, struct v3d_tfu_job, base.base);
54 }
55 
56 static struct v3d_csd_job *
to_csd_job(struct drm_sched_job * sched_job)57 to_csd_job(struct drm_sched_job *sched_job)
58 {
59 	return container_of(sched_job, struct v3d_csd_job, base.base);
60 }
61 
62 static struct v3d_cpu_job *
to_cpu_job(struct drm_sched_job * sched_job)63 to_cpu_job(struct drm_sched_job *sched_job)
64 {
65 	return container_of(sched_job, struct v3d_cpu_job, base.base);
66 }
67 
68 static void
v3d_sched_job_free(struct drm_sched_job * sched_job)69 v3d_sched_job_free(struct drm_sched_job *sched_job)
70 {
71 	struct v3d_job *job = to_v3d_job(sched_job);
72 
73 	v3d_job_cleanup(job);
74 }
75 
76 void
v3d_timestamp_query_info_free(struct v3d_timestamp_query_info * query_info,unsigned int count)77 v3d_timestamp_query_info_free(struct v3d_timestamp_query_info *query_info,
78 			      unsigned int count)
79 {
80 	if (query_info->queries) {
81 		unsigned int i;
82 
83 		for (i = 0; i < count; i++)
84 			drm_syncobj_put(query_info->queries[i].syncobj);
85 
86 		kvfree(query_info->queries);
87 	}
88 }
89 
90 void
v3d_performance_query_info_free(struct v3d_performance_query_info * query_info,unsigned int count)91 v3d_performance_query_info_free(struct v3d_performance_query_info *query_info,
92 				unsigned int count)
93 {
94 	if (query_info->queries) {
95 		unsigned int i;
96 
97 		for (i = 0; i < count; i++) {
98 			drm_syncobj_put(query_info->queries[i].syncobj);
99 			kvfree(query_info->queries[i].kperfmon_ids);
100 		}
101 
102 		kvfree(query_info->queries);
103 	}
104 }
105 
106 static void
v3d_cpu_job_free(struct drm_sched_job * sched_job)107 v3d_cpu_job_free(struct drm_sched_job *sched_job)
108 {
109 	struct v3d_cpu_job *job = to_cpu_job(sched_job);
110 
111 	v3d_timestamp_query_info_free(&job->timestamp_query,
112 				      job->timestamp_query.count);
113 
114 	v3d_performance_query_info_free(&job->performance_query,
115 					job->performance_query.count);
116 
117 	v3d_job_cleanup(&job->base);
118 }
119 
120 static void
v3d_switch_perfmon(struct v3d_dev * v3d,struct v3d_job * job)121 v3d_switch_perfmon(struct v3d_dev *v3d, struct v3d_job *job)
122 {
123 	struct v3d_perfmon *perfmon = v3d->global_perfmon;
124 
125 	if (!perfmon)
126 		perfmon = job->perfmon;
127 
128 	if (perfmon == v3d->active_perfmon)
129 		return;
130 
131 	if (perfmon != v3d->active_perfmon)
132 		v3d_perfmon_stop(v3d, v3d->active_perfmon, true);
133 
134 	if (perfmon && v3d->active_perfmon != perfmon)
135 		v3d_perfmon_start(v3d, perfmon);
136 }
137 
138 static void
v3d_job_start_stats(struct v3d_job * job,enum v3d_queue queue)139 v3d_job_start_stats(struct v3d_job *job, enum v3d_queue queue)
140 {
141 	struct v3d_dev *v3d = job->v3d;
142 	struct v3d_file_priv *file = job->file->driver_priv;
143 	struct v3d_stats *global_stats = &v3d->queue[queue].stats;
144 	struct v3d_stats *local_stats = &file->stats[queue];
145 	u64 now = local_clock();
146 	unsigned long flags;
147 
148 	/*
149 	 * We only need to disable local interrupts to appease lockdep who
150 	 * otherwise would think v3d_job_start_stats vs v3d_stats_update has an
151 	 * unsafe in-irq vs no-irq-off usage problem. This is a false positive
152 	 * because all the locks are per queue and stats type, and all jobs are
153 	 * completely one at a time serialised. More specifically:
154 	 *
155 	 * 1. Locks for GPU queues are updated from interrupt handlers under a
156 	 *    spin lock and started here with preemption disabled.
157 	 *
158 	 * 2. Locks for CPU queues are updated from the worker with preemption
159 	 *    disabled and equally started here with preemption disabled.
160 	 *
161 	 * Therefore both are consistent.
162 	 *
163 	 * 3. Because next job can only be queued after the previous one has
164 	 *    been signaled, and locks are per queue, there is also no scope for
165 	 *    the start part to race with the update part.
166 	 */
167 	if (IS_ENABLED(CONFIG_LOCKDEP))
168 		local_irq_save(flags);
169 	else
170 		preempt_disable();
171 
172 	write_seqcount_begin(&local_stats->lock);
173 	local_stats->start_ns = now;
174 	write_seqcount_end(&local_stats->lock);
175 
176 	write_seqcount_begin(&global_stats->lock);
177 	global_stats->start_ns = now;
178 	write_seqcount_end(&global_stats->lock);
179 
180 	if (IS_ENABLED(CONFIG_LOCKDEP))
181 		local_irq_restore(flags);
182 	else
183 		preempt_enable();
184 }
185 
186 static void
v3d_stats_update(struct v3d_stats * stats,u64 now)187 v3d_stats_update(struct v3d_stats *stats, u64 now)
188 {
189 	write_seqcount_begin(&stats->lock);
190 	stats->enabled_ns += now - stats->start_ns;
191 	stats->jobs_completed++;
192 	stats->start_ns = 0;
193 	write_seqcount_end(&stats->lock);
194 }
195 
196 void
v3d_job_update_stats(struct v3d_job * job,enum v3d_queue queue)197 v3d_job_update_stats(struct v3d_job *job, enum v3d_queue queue)
198 {
199 	struct v3d_dev *v3d = job->v3d;
200 	struct v3d_file_priv *file = job->file->driver_priv;
201 	struct v3d_stats *global_stats = &v3d->queue[queue].stats;
202 	struct v3d_stats *local_stats = &file->stats[queue];
203 	u64 now = local_clock();
204 	unsigned long flags;
205 
206 	/* See comment in v3d_job_start_stats() */
207 	if (IS_ENABLED(CONFIG_LOCKDEP))
208 		local_irq_save(flags);
209 	else
210 		preempt_disable();
211 
212 	v3d_stats_update(local_stats, now);
213 	v3d_stats_update(global_stats, now);
214 
215 	if (IS_ENABLED(CONFIG_LOCKDEP))
216 		local_irq_restore(flags);
217 	else
218 		preempt_enable();
219 }
220 
v3d_bin_job_run(struct drm_sched_job * sched_job)221 static struct dma_fence *v3d_bin_job_run(struct drm_sched_job *sched_job)
222 {
223 	struct v3d_bin_job *job = to_bin_job(sched_job);
224 	struct v3d_dev *v3d = job->base.v3d;
225 	struct drm_device *dev = &v3d->drm;
226 	struct dma_fence *fence;
227 	unsigned long irqflags;
228 
229 	if (unlikely(job->base.base.s_fence->finished.error)) {
230 		spin_lock_irqsave(&v3d->job_lock, irqflags);
231 		v3d->bin_job = NULL;
232 		spin_unlock_irqrestore(&v3d->job_lock, irqflags);
233 		return NULL;
234 	}
235 
236 	/* Lock required around bin_job update vs
237 	 * v3d_overflow_mem_work().
238 	 */
239 	spin_lock_irqsave(&v3d->job_lock, irqflags);
240 	v3d->bin_job = job;
241 	/* Clear out the overflow allocation, so we don't
242 	 * reuse the overflow attached to a previous job.
243 	 */
244 	V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0);
245 	spin_unlock_irqrestore(&v3d->job_lock, irqflags);
246 
247 	v3d_invalidate_caches(v3d);
248 
249 	fence = v3d_fence_create(v3d, V3D_BIN);
250 	if (IS_ERR(fence))
251 		return NULL;
252 
253 	if (job->base.irq_fence)
254 		dma_fence_put(job->base.irq_fence);
255 	job->base.irq_fence = dma_fence_get(fence);
256 
257 	trace_v3d_submit_cl(dev, false, to_v3d_fence(fence)->seqno,
258 			    job->start, job->end);
259 
260 	v3d_job_start_stats(&job->base, V3D_BIN);
261 	v3d_switch_perfmon(v3d, &job->base);
262 
263 	/* Set the current and end address of the control list.
264 	 * Writing the end register is what starts the job.
265 	 */
266 	if (job->qma) {
267 		V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, job->qma);
268 		V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, job->qms);
269 	}
270 	if (job->qts) {
271 		V3D_CORE_WRITE(0, V3D_CLE_CT0QTS,
272 			       V3D_CLE_CT0QTS_ENABLE |
273 			       job->qts);
274 	}
275 	V3D_CORE_WRITE(0, V3D_CLE_CT0QBA, job->start);
276 	V3D_CORE_WRITE(0, V3D_CLE_CT0QEA, job->end);
277 
278 	return fence;
279 }
280 
v3d_render_job_run(struct drm_sched_job * sched_job)281 static struct dma_fence *v3d_render_job_run(struct drm_sched_job *sched_job)
282 {
283 	struct v3d_render_job *job = to_render_job(sched_job);
284 	struct v3d_dev *v3d = job->base.v3d;
285 	struct drm_device *dev = &v3d->drm;
286 	struct dma_fence *fence;
287 
288 	if (unlikely(job->base.base.s_fence->finished.error)) {
289 		v3d->render_job = NULL;
290 		return NULL;
291 	}
292 
293 	v3d->render_job = job;
294 
295 	/* Can we avoid this flush?  We need to be careful of
296 	 * scheduling, though -- imagine job0 rendering to texture and
297 	 * job1 reading, and them being executed as bin0, bin1,
298 	 * render0, render1, so that render1's flush at bin time
299 	 * wasn't enough.
300 	 */
301 	v3d_invalidate_caches(v3d);
302 
303 	fence = v3d_fence_create(v3d, V3D_RENDER);
304 	if (IS_ERR(fence))
305 		return NULL;
306 
307 	if (job->base.irq_fence)
308 		dma_fence_put(job->base.irq_fence);
309 	job->base.irq_fence = dma_fence_get(fence);
310 
311 	trace_v3d_submit_cl(dev, true, to_v3d_fence(fence)->seqno,
312 			    job->start, job->end);
313 
314 	v3d_job_start_stats(&job->base, V3D_RENDER);
315 	v3d_switch_perfmon(v3d, &job->base);
316 
317 	/* XXX: Set the QCFG */
318 
319 	/* Set the current and end address of the control list.
320 	 * Writing the end register is what starts the job.
321 	 */
322 	V3D_CORE_WRITE(0, V3D_CLE_CT1QBA, job->start);
323 	V3D_CORE_WRITE(0, V3D_CLE_CT1QEA, job->end);
324 
325 	return fence;
326 }
327 
328 static struct dma_fence *
v3d_tfu_job_run(struct drm_sched_job * sched_job)329 v3d_tfu_job_run(struct drm_sched_job *sched_job)
330 {
331 	struct v3d_tfu_job *job = to_tfu_job(sched_job);
332 	struct v3d_dev *v3d = job->base.v3d;
333 	struct drm_device *dev = &v3d->drm;
334 	struct dma_fence *fence;
335 
336 	if (unlikely(job->base.base.s_fence->finished.error)) {
337 		v3d->tfu_job = NULL;
338 		return NULL;
339 	}
340 
341 	v3d->tfu_job = job;
342 
343 	fence = v3d_fence_create(v3d, V3D_TFU);
344 	if (IS_ERR(fence))
345 		return NULL;
346 
347 	if (job->base.irq_fence)
348 		dma_fence_put(job->base.irq_fence);
349 	job->base.irq_fence = dma_fence_get(fence);
350 
351 	trace_v3d_submit_tfu(dev, to_v3d_fence(fence)->seqno);
352 
353 	v3d_job_start_stats(&job->base, V3D_TFU);
354 
355 	V3D_WRITE(V3D_TFU_IIA(v3d->ver), job->args.iia);
356 	V3D_WRITE(V3D_TFU_IIS(v3d->ver), job->args.iis);
357 	V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica);
358 	V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua);
359 	V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa);
360 	if (v3d->ver >= 71)
361 		V3D_WRITE(V3D_V7_TFU_IOC, job->args.v71.ioc);
362 	V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios);
363 	V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]);
364 	if (v3d->ver >= 71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
365 		V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]);
366 		V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]);
367 		V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]);
368 	}
369 	/* ICFG kicks off the job. */
370 	V3D_WRITE(V3D_TFU_ICFG(v3d->ver), job->args.icfg | V3D_TFU_ICFG_IOC);
371 
372 	return fence;
373 }
374 
375 static struct dma_fence *
v3d_csd_job_run(struct drm_sched_job * sched_job)376 v3d_csd_job_run(struct drm_sched_job *sched_job)
377 {
378 	struct v3d_csd_job *job = to_csd_job(sched_job);
379 	struct v3d_dev *v3d = job->base.v3d;
380 	struct drm_device *dev = &v3d->drm;
381 	struct dma_fence *fence;
382 	int i, csd_cfg0_reg;
383 
384 	if (unlikely(job->base.base.s_fence->finished.error)) {
385 		v3d->csd_job = NULL;
386 		return NULL;
387 	}
388 
389 	v3d->csd_job = job;
390 
391 	v3d_invalidate_caches(v3d);
392 
393 	fence = v3d_fence_create(v3d, V3D_CSD);
394 	if (IS_ERR(fence))
395 		return NULL;
396 
397 	if (job->base.irq_fence)
398 		dma_fence_put(job->base.irq_fence);
399 	job->base.irq_fence = dma_fence_get(fence);
400 
401 	trace_v3d_submit_csd(dev, to_v3d_fence(fence)->seqno);
402 
403 	v3d_job_start_stats(&job->base, V3D_CSD);
404 	v3d_switch_perfmon(v3d, &job->base);
405 
406 	csd_cfg0_reg = V3D_CSD_QUEUED_CFG0(v3d->ver);
407 	for (i = 1; i <= 6; i++)
408 		V3D_CORE_WRITE(0, csd_cfg0_reg + 4 * i, job->args.cfg[i]);
409 
410 	/* Although V3D 7.1 has an eighth configuration register, we are not
411 	 * using it. Therefore, make sure it remains unused.
412 	 *
413 	 * XXX: Set the CFG7 register
414 	 */
415 	if (v3d->ver >= 71)
416 		V3D_CORE_WRITE(0, V3D_V7_CSD_QUEUED_CFG7, 0);
417 
418 	/* CFG0 write kicks off the job. */
419 	V3D_CORE_WRITE(0, csd_cfg0_reg, job->args.cfg[0]);
420 
421 	return fence;
422 }
423 
424 static void
v3d_rewrite_csd_job_wg_counts_from_indirect(struct v3d_cpu_job * job)425 v3d_rewrite_csd_job_wg_counts_from_indirect(struct v3d_cpu_job *job)
426 {
427 	struct v3d_indirect_csd_info *indirect_csd = &job->indirect_csd;
428 	struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]);
429 	struct v3d_bo *indirect = to_v3d_bo(indirect_csd->indirect);
430 	struct drm_v3d_submit_csd *args = &indirect_csd->job->args;
431 	struct v3d_dev *v3d = job->base.v3d;
432 	u32 num_batches, *wg_counts;
433 
434 	v3d_get_bo_vaddr(bo);
435 	v3d_get_bo_vaddr(indirect);
436 
437 	wg_counts = (uint32_t *)(bo->vaddr + indirect_csd->offset);
438 
439 	if (wg_counts[0] == 0 || wg_counts[1] == 0 || wg_counts[2] == 0)
440 		return;
441 
442 	args->cfg[0] = wg_counts[0] << V3D_CSD_CFG012_WG_COUNT_SHIFT;
443 	args->cfg[1] = wg_counts[1] << V3D_CSD_CFG012_WG_COUNT_SHIFT;
444 	args->cfg[2] = wg_counts[2] << V3D_CSD_CFG012_WG_COUNT_SHIFT;
445 
446 	num_batches = DIV_ROUND_UP(indirect_csd->wg_size, 16) *
447 		      (wg_counts[0] * wg_counts[1] * wg_counts[2]);
448 
449 	/* V3D 7.1.6 and later don't subtract 1 from the number of batches */
450 	if (v3d->ver < 71 || (v3d->ver == 71 && v3d->rev < 6))
451 		args->cfg[4] = num_batches - 1;
452 	else
453 		args->cfg[4] = num_batches;
454 
455 	WARN_ON(args->cfg[4] == ~0);
456 
457 	for (int i = 0; i < 3; i++) {
458 		/* 0xffffffff indicates that the uniform rewrite is not needed */
459 		if (indirect_csd->wg_uniform_offsets[i] != 0xffffffff) {
460 			u32 uniform_idx = indirect_csd->wg_uniform_offsets[i];
461 			((uint32_t *)indirect->vaddr)[uniform_idx] = wg_counts[i];
462 		}
463 	}
464 
465 	v3d_put_bo_vaddr(indirect);
466 	v3d_put_bo_vaddr(bo);
467 }
468 
469 static void
v3d_timestamp_query(struct v3d_cpu_job * job)470 v3d_timestamp_query(struct v3d_cpu_job *job)
471 {
472 	struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query;
473 	struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]);
474 	u8 *value_addr;
475 
476 	v3d_get_bo_vaddr(bo);
477 
478 	for (int i = 0; i < timestamp_query->count; i++) {
479 		value_addr = ((u8 *)bo->vaddr) + timestamp_query->queries[i].offset;
480 		*((u64 *)value_addr) = i == 0 ? ktime_get_ns() : 0ull;
481 
482 		drm_syncobj_replace_fence(timestamp_query->queries[i].syncobj,
483 					  job->base.done_fence);
484 	}
485 
486 	v3d_put_bo_vaddr(bo);
487 }
488 
489 static void
v3d_reset_timestamp_queries(struct v3d_cpu_job * job)490 v3d_reset_timestamp_queries(struct v3d_cpu_job *job)
491 {
492 	struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query;
493 	struct v3d_timestamp_query *queries = timestamp_query->queries;
494 	struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]);
495 	u8 *value_addr;
496 
497 	v3d_get_bo_vaddr(bo);
498 
499 	for (int i = 0; i < timestamp_query->count; i++) {
500 		value_addr = ((u8 *)bo->vaddr) + queries[i].offset;
501 		*((u64 *)value_addr) = 0;
502 
503 		drm_syncobj_replace_fence(queries[i].syncobj, NULL);
504 	}
505 
506 	v3d_put_bo_vaddr(bo);
507 }
508 
write_to_buffer_32(u32 * dst,unsigned int idx,u32 value)509 static void write_to_buffer_32(u32 *dst, unsigned int idx, u32 value)
510 {
511 	dst[idx] = value;
512 }
513 
write_to_buffer_64(u64 * dst,unsigned int idx,u64 value)514 static void write_to_buffer_64(u64 *dst, unsigned int idx, u64 value)
515 {
516 	dst[idx] = value;
517 }
518 
519 static void
write_to_buffer(void * dst,unsigned int idx,bool do_64bit,u64 value)520 write_to_buffer(void *dst, unsigned int idx, bool do_64bit, u64 value)
521 {
522 	if (do_64bit)
523 		write_to_buffer_64(dst, idx, value);
524 	else
525 		write_to_buffer_32(dst, idx, value);
526 }
527 
528 static void
v3d_copy_query_results(struct v3d_cpu_job * job)529 v3d_copy_query_results(struct v3d_cpu_job *job)
530 {
531 	struct v3d_timestamp_query_info *timestamp_query = &job->timestamp_query;
532 	struct v3d_timestamp_query *queries = timestamp_query->queries;
533 	struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]);
534 	struct v3d_bo *timestamp = to_v3d_bo(job->base.bo[1]);
535 	struct v3d_copy_query_results_info *copy = &job->copy;
536 	struct dma_fence *fence;
537 	u8 *query_addr;
538 	bool available, write_result;
539 	u8 *data;
540 	int i;
541 
542 	v3d_get_bo_vaddr(bo);
543 	v3d_get_bo_vaddr(timestamp);
544 
545 	data = ((u8 *)bo->vaddr) + copy->offset;
546 
547 	for (i = 0; i < timestamp_query->count; i++) {
548 		fence = drm_syncobj_fence_get(queries[i].syncobj);
549 		available = fence ? dma_fence_is_signaled(fence) : false;
550 
551 		write_result = available || copy->do_partial;
552 		if (write_result) {
553 			query_addr = ((u8 *)timestamp->vaddr) + queries[i].offset;
554 			write_to_buffer(data, 0, copy->do_64bit, *((u64 *)query_addr));
555 		}
556 
557 		if (copy->availability_bit)
558 			write_to_buffer(data, 1, copy->do_64bit, available ? 1u : 0u);
559 
560 		data += copy->stride;
561 
562 		dma_fence_put(fence);
563 	}
564 
565 	v3d_put_bo_vaddr(timestamp);
566 	v3d_put_bo_vaddr(bo);
567 }
568 
569 static void
v3d_reset_performance_queries(struct v3d_cpu_job * job)570 v3d_reset_performance_queries(struct v3d_cpu_job *job)
571 {
572 	struct v3d_performance_query_info *performance_query = &job->performance_query;
573 	struct v3d_file_priv *v3d_priv = job->base.file->driver_priv;
574 	struct v3d_dev *v3d = job->base.v3d;
575 	struct v3d_perfmon *perfmon;
576 
577 	for (int i = 0; i < performance_query->count; i++) {
578 		for (int j = 0; j < performance_query->nperfmons; j++) {
579 			perfmon = v3d_perfmon_find(v3d_priv,
580 						   performance_query->queries[i].kperfmon_ids[j]);
581 			if (!perfmon) {
582 				DRM_DEBUG("Failed to find perfmon.");
583 				continue;
584 			}
585 
586 			v3d_perfmon_stop(v3d, perfmon, false);
587 
588 			memset(perfmon->values, 0, perfmon->ncounters * sizeof(u64));
589 
590 			v3d_perfmon_put(perfmon);
591 		}
592 
593 		drm_syncobj_replace_fence(performance_query->queries[i].syncobj, NULL);
594 	}
595 }
596 
597 static void
v3d_write_performance_query_result(struct v3d_cpu_job * job,void * data,unsigned int query)598 v3d_write_performance_query_result(struct v3d_cpu_job *job, void *data,
599 				   unsigned int query)
600 {
601 	struct v3d_performance_query_info *performance_query =
602 						&job->performance_query;
603 	struct v3d_file_priv *v3d_priv = job->base.file->driver_priv;
604 	struct v3d_performance_query *perf_query =
605 			&performance_query->queries[query];
606 	struct v3d_dev *v3d = job->base.v3d;
607 	unsigned int i, j, offset;
608 
609 	for (i = 0, offset = 0;
610 	     i < performance_query->nperfmons;
611 	     i++, offset += DRM_V3D_MAX_PERF_COUNTERS) {
612 		struct v3d_perfmon *perfmon;
613 
614 		perfmon = v3d_perfmon_find(v3d_priv,
615 					   perf_query->kperfmon_ids[i]);
616 		if (!perfmon) {
617 			DRM_DEBUG("Failed to find perfmon.");
618 			continue;
619 		}
620 
621 		v3d_perfmon_stop(v3d, perfmon, true);
622 
623 		if (job->copy.do_64bit) {
624 			for (j = 0; j < perfmon->ncounters; j++)
625 				write_to_buffer_64(data, offset + j,
626 						   perfmon->values[j]);
627 		} else {
628 			for (j = 0; j < perfmon->ncounters; j++)
629 				write_to_buffer_32(data, offset + j,
630 						   perfmon->values[j]);
631 		}
632 
633 		v3d_perfmon_put(perfmon);
634 	}
635 }
636 
637 static void
v3d_copy_performance_query(struct v3d_cpu_job * job)638 v3d_copy_performance_query(struct v3d_cpu_job *job)
639 {
640 	struct v3d_performance_query_info *performance_query = &job->performance_query;
641 	struct v3d_copy_query_results_info *copy = &job->copy;
642 	struct v3d_bo *bo = to_v3d_bo(job->base.bo[0]);
643 	struct dma_fence *fence;
644 	bool available, write_result;
645 	u8 *data;
646 
647 	v3d_get_bo_vaddr(bo);
648 
649 	data = ((u8 *)bo->vaddr) + copy->offset;
650 
651 	for (int i = 0; i < performance_query->count; i++) {
652 		fence = drm_syncobj_fence_get(performance_query->queries[i].syncobj);
653 		available = fence ? dma_fence_is_signaled(fence) : false;
654 
655 		write_result = available || copy->do_partial;
656 		if (write_result)
657 			v3d_write_performance_query_result(job, data, i);
658 
659 		if (copy->availability_bit)
660 			write_to_buffer(data, performance_query->ncounters,
661 					copy->do_64bit, available ? 1u : 0u);
662 
663 		data += copy->stride;
664 
665 		dma_fence_put(fence);
666 	}
667 
668 	v3d_put_bo_vaddr(bo);
669 }
670 
671 static const v3d_cpu_job_fn cpu_job_function[] = {
672 	[V3D_CPU_JOB_TYPE_INDIRECT_CSD] = v3d_rewrite_csd_job_wg_counts_from_indirect,
673 	[V3D_CPU_JOB_TYPE_TIMESTAMP_QUERY] = v3d_timestamp_query,
674 	[V3D_CPU_JOB_TYPE_RESET_TIMESTAMP_QUERY] = v3d_reset_timestamp_queries,
675 	[V3D_CPU_JOB_TYPE_COPY_TIMESTAMP_QUERY] = v3d_copy_query_results,
676 	[V3D_CPU_JOB_TYPE_RESET_PERFORMANCE_QUERY] = v3d_reset_performance_queries,
677 	[V3D_CPU_JOB_TYPE_COPY_PERFORMANCE_QUERY] = v3d_copy_performance_query,
678 };
679 
680 static struct dma_fence *
v3d_cpu_job_run(struct drm_sched_job * sched_job)681 v3d_cpu_job_run(struct drm_sched_job *sched_job)
682 {
683 	struct v3d_cpu_job *job = to_cpu_job(sched_job);
684 	struct v3d_dev *v3d = job->base.v3d;
685 
686 	if (job->job_type >= ARRAY_SIZE(cpu_job_function)) {
687 		DRM_DEBUG_DRIVER("Unknown CPU job: %d\n", job->job_type);
688 		return NULL;
689 	}
690 
691 	v3d_job_start_stats(&job->base, V3D_CPU);
692 	trace_v3d_cpu_job_begin(&v3d->drm, job->job_type);
693 
694 	cpu_job_function[job->job_type](job);
695 
696 	trace_v3d_cpu_job_end(&v3d->drm, job->job_type);
697 	v3d_job_update_stats(&job->base, V3D_CPU);
698 
699 	return NULL;
700 }
701 
702 static struct dma_fence *
v3d_cache_clean_job_run(struct drm_sched_job * sched_job)703 v3d_cache_clean_job_run(struct drm_sched_job *sched_job)
704 {
705 	struct v3d_job *job = to_v3d_job(sched_job);
706 	struct v3d_dev *v3d = job->v3d;
707 
708 	v3d_job_start_stats(job, V3D_CACHE_CLEAN);
709 
710 	v3d_clean_caches(v3d);
711 
712 	v3d_job_update_stats(job, V3D_CACHE_CLEAN);
713 
714 	return NULL;
715 }
716 
717 static enum drm_gpu_sched_stat
v3d_gpu_reset_for_timeout(struct v3d_dev * v3d,struct drm_sched_job * sched_job)718 v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
719 {
720 	enum v3d_queue q;
721 
722 	mutex_lock(&v3d->reset_lock);
723 
724 	/* block scheduler */
725 	for (q = 0; q < V3D_MAX_QUEUES; q++)
726 		drm_sched_stop(&v3d->queue[q].sched, sched_job);
727 
728 	if (sched_job)
729 		drm_sched_increase_karma(sched_job);
730 
731 	/* get the GPU back into the init state */
732 	v3d_reset(v3d);
733 
734 	for (q = 0; q < V3D_MAX_QUEUES; q++)
735 		drm_sched_resubmit_jobs(&v3d->queue[q].sched);
736 
737 	/* Unblock schedulers and restart their jobs. */
738 	for (q = 0; q < V3D_MAX_QUEUES; q++) {
739 		drm_sched_start(&v3d->queue[q].sched, 0);
740 	}
741 
742 	mutex_unlock(&v3d->reset_lock);
743 
744 	return DRM_GPU_SCHED_STAT_NOMINAL;
745 }
746 
747 static void
v3d_sched_skip_reset(struct drm_sched_job * sched_job)748 v3d_sched_skip_reset(struct drm_sched_job *sched_job)
749 {
750 	struct drm_gpu_scheduler *sched = sched_job->sched;
751 
752 	spin_lock(&sched->job_list_lock);
753 	list_add(&sched_job->list, &sched->pending_list);
754 	spin_unlock(&sched->job_list_lock);
755 }
756 
757 static enum drm_gpu_sched_stat
v3d_cl_job_timedout(struct drm_sched_job * sched_job,enum v3d_queue q,u32 * timedout_ctca,u32 * timedout_ctra)758 v3d_cl_job_timedout(struct drm_sched_job *sched_job, enum v3d_queue q,
759 		    u32 *timedout_ctca, u32 *timedout_ctra)
760 {
761 	struct v3d_job *job = to_v3d_job(sched_job);
762 	struct v3d_dev *v3d = job->v3d;
763 	u32 ctca = V3D_CORE_READ(0, V3D_CLE_CTNCA(q));
764 	u32 ctra = V3D_CORE_READ(0, V3D_CLE_CTNRA(q));
765 
766 	/* If the current address or return address have changed, then the GPU
767 	 * has probably made progress and we should delay the reset. This
768 	 * could fail if the GPU got in an infinite loop in the CL, but that
769 	 * is pretty unlikely outside of an i-g-t testcase.
770 	 */
771 	if (*timedout_ctca != ctca || *timedout_ctra != ctra) {
772 		*timedout_ctca = ctca;
773 		*timedout_ctra = ctra;
774 
775 		v3d_sched_skip_reset(sched_job);
776 		return DRM_GPU_SCHED_STAT_NOMINAL;
777 	}
778 
779 	return v3d_gpu_reset_for_timeout(v3d, sched_job);
780 }
781 
782 static enum drm_gpu_sched_stat
v3d_bin_job_timedout(struct drm_sched_job * sched_job)783 v3d_bin_job_timedout(struct drm_sched_job *sched_job)
784 {
785 	struct v3d_bin_job *job = to_bin_job(sched_job);
786 
787 	return v3d_cl_job_timedout(sched_job, V3D_BIN,
788 				   &job->timedout_ctca, &job->timedout_ctra);
789 }
790 
791 static enum drm_gpu_sched_stat
v3d_render_job_timedout(struct drm_sched_job * sched_job)792 v3d_render_job_timedout(struct drm_sched_job *sched_job)
793 {
794 	struct v3d_render_job *job = to_render_job(sched_job);
795 
796 	return v3d_cl_job_timedout(sched_job, V3D_RENDER,
797 				   &job->timedout_ctca, &job->timedout_ctra);
798 }
799 
800 static enum drm_gpu_sched_stat
v3d_generic_job_timedout(struct drm_sched_job * sched_job)801 v3d_generic_job_timedout(struct drm_sched_job *sched_job)
802 {
803 	struct v3d_job *job = to_v3d_job(sched_job);
804 
805 	return v3d_gpu_reset_for_timeout(job->v3d, sched_job);
806 }
807 
808 static enum drm_gpu_sched_stat
v3d_csd_job_timedout(struct drm_sched_job * sched_job)809 v3d_csd_job_timedout(struct drm_sched_job *sched_job)
810 {
811 	struct v3d_csd_job *job = to_csd_job(sched_job);
812 	struct v3d_dev *v3d = job->base.v3d;
813 	u32 batches = V3D_CORE_READ(0, V3D_CSD_CURRENT_CFG4(v3d->ver));
814 
815 	/* If we've made progress, skip reset, add the job to the pending
816 	 * list, and let the timer get rearmed.
817 	 */
818 	if (job->timedout_batches != batches) {
819 		job->timedout_batches = batches;
820 
821 		v3d_sched_skip_reset(sched_job);
822 		return DRM_GPU_SCHED_STAT_NOMINAL;
823 	}
824 
825 	return v3d_gpu_reset_for_timeout(v3d, sched_job);
826 }
827 
828 static const struct drm_sched_backend_ops v3d_bin_sched_ops = {
829 	.run_job = v3d_bin_job_run,
830 	.timedout_job = v3d_bin_job_timedout,
831 	.free_job = v3d_sched_job_free,
832 };
833 
834 static const struct drm_sched_backend_ops v3d_render_sched_ops = {
835 	.run_job = v3d_render_job_run,
836 	.timedout_job = v3d_render_job_timedout,
837 	.free_job = v3d_sched_job_free,
838 };
839 
840 static const struct drm_sched_backend_ops v3d_tfu_sched_ops = {
841 	.run_job = v3d_tfu_job_run,
842 	.timedout_job = v3d_generic_job_timedout,
843 	.free_job = v3d_sched_job_free,
844 };
845 
846 static const struct drm_sched_backend_ops v3d_csd_sched_ops = {
847 	.run_job = v3d_csd_job_run,
848 	.timedout_job = v3d_csd_job_timedout,
849 	.free_job = v3d_sched_job_free
850 };
851 
852 static const struct drm_sched_backend_ops v3d_cache_clean_sched_ops = {
853 	.run_job = v3d_cache_clean_job_run,
854 	.timedout_job = v3d_generic_job_timedout,
855 	.free_job = v3d_sched_job_free
856 };
857 
858 static const struct drm_sched_backend_ops v3d_cpu_sched_ops = {
859 	.run_job = v3d_cpu_job_run,
860 	.timedout_job = v3d_generic_job_timedout,
861 	.free_job = v3d_cpu_job_free
862 };
863 
864 static int
v3d_queue_sched_init(struct v3d_dev * v3d,const struct drm_sched_backend_ops * ops,enum v3d_queue queue,const char * name)865 v3d_queue_sched_init(struct v3d_dev *v3d, const struct drm_sched_backend_ops *ops,
866 		     enum v3d_queue queue, const char *name)
867 {
868 	struct drm_sched_init_args args = {
869 		.num_rqs = DRM_SCHED_PRIORITY_COUNT,
870 		.credit_limit = 1,
871 		.timeout = msecs_to_jiffies(500),
872 		.dev = v3d->drm.dev,
873 	};
874 
875 	args.ops = ops;
876 	args.name = name;
877 
878 	return drm_sched_init(&v3d->queue[queue].sched, &args);
879 }
880 
881 int
v3d_sched_init(struct v3d_dev * v3d)882 v3d_sched_init(struct v3d_dev *v3d)
883 {
884 	int ret;
885 
886 	ret = v3d_queue_sched_init(v3d, &v3d_bin_sched_ops, V3D_BIN, "v3d_bin");
887 	if (ret)
888 		return ret;
889 
890 	ret = v3d_queue_sched_init(v3d, &v3d_render_sched_ops, V3D_RENDER,
891 				   "v3d_render");
892 	if (ret)
893 		goto fail;
894 
895 	ret = v3d_queue_sched_init(v3d, &v3d_tfu_sched_ops, V3D_TFU, "v3d_tfu");
896 	if (ret)
897 		goto fail;
898 
899 	if (v3d_has_csd(v3d)) {
900 		ret = v3d_queue_sched_init(v3d, &v3d_csd_sched_ops, V3D_CSD,
901 					   "v3d_csd");
902 		if (ret)
903 			goto fail;
904 
905 		ret = v3d_queue_sched_init(v3d, &v3d_cache_clean_sched_ops,
906 					   V3D_CACHE_CLEAN, "v3d_cache_clean");
907 		if (ret)
908 			goto fail;
909 	}
910 
911 	ret = v3d_queue_sched_init(v3d, &v3d_cpu_sched_ops, V3D_CPU, "v3d_cpu");
912 	if (ret)
913 		goto fail;
914 
915 	return 0;
916 
917 fail:
918 	v3d_sched_fini(v3d);
919 	return ret;
920 }
921 
922 void
v3d_sched_fini(struct v3d_dev * v3d)923 v3d_sched_fini(struct v3d_dev *v3d)
924 {
925 	enum v3d_queue q;
926 
927 	for (q = 0; q < V3D_MAX_QUEUES; q++) {
928 		if (v3d->queue[q].sched.ready)
929 			drm_sched_fini(&v3d->queue[q].sched);
930 	}
931 }
932