1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iommu.h>
12 #include <linux/interconnect.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_domain.h>
17 #include <linux/pm_opp.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20
21 #include <soc/tegra/common.h>
22 #include <soc/tegra/pmc.h>
23
24 #include <drm/drm_atomic.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_blend.h>
27 #include <drm/drm_debugfs.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_framebuffer.h>
30 #include <drm/drm_vblank.h>
31
32 #include "dc.h"
33 #include "drm.h"
34 #include "gem.h"
35 #include "hub.h"
36 #include "plane.h"
37
38 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
39 struct drm_crtc_state *state);
40
tegra_dc_stats_reset(struct tegra_dc_stats * stats)41 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
42 {
43 stats->frames = 0;
44 stats->vblank = 0;
45 stats->underflow = 0;
46 stats->overflow = 0;
47 }
48
49 /* Reads the active copy of a register. */
tegra_dc_readl_active(struct tegra_dc * dc,unsigned long offset)50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
51 {
52 u32 value;
53
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
55 value = tegra_dc_readl(dc, offset);
56 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
57
58 return value;
59 }
60
tegra_plane_offset(struct tegra_plane * plane,unsigned int offset)61 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
62 unsigned int offset)
63 {
64 if (offset >= 0x500 && offset <= 0x638) {
65 offset = 0x000 + (offset - 0x500);
66 return plane->offset + offset;
67 }
68
69 if (offset >= 0x700 && offset <= 0x719) {
70 offset = 0x180 + (offset - 0x700);
71 return plane->offset + offset;
72 }
73
74 if (offset >= 0x800 && offset <= 0x839) {
75 offset = 0x1c0 + (offset - 0x800);
76 return plane->offset + offset;
77 }
78
79 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
80
81 return plane->offset + offset;
82 }
83
tegra_plane_readl(struct tegra_plane * plane,unsigned int offset)84 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
85 unsigned int offset)
86 {
87 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
88 }
89
tegra_plane_writel(struct tegra_plane * plane,u32 value,unsigned int offset)90 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
91 unsigned int offset)
92 {
93 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
94 }
95
tegra_dc_has_output(struct tegra_dc * dc,struct device * dev)96 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
97 {
98 struct device_node *np = dc->dev->of_node;
99 struct of_phandle_iterator it;
100 int err;
101
102 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
103 if (it.node == dev->of_node)
104 return true;
105
106 return false;
107 }
108
109 /*
110 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
111 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
112 * Latching happens mmediately if the display controller is in STOP mode or
113 * on the next frame boundary otherwise.
114 *
115 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
116 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
117 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
118 * into the ACTIVE copy, either immediately if the display controller is in
119 * STOP mode, or at the next frame boundary otherwise.
120 */
tegra_dc_commit(struct tegra_dc * dc)121 void tegra_dc_commit(struct tegra_dc *dc)
122 {
123 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
124 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
125 }
126
compute_dda_inc(unsigned int in,unsigned int out,bool v,unsigned int bpp)127 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
128 unsigned int bpp)
129 {
130 fixed20_12 outf = dfixed_init(out);
131 fixed20_12 inf = dfixed_init(in);
132 u32 dda_inc;
133 int max;
134
135 if (v)
136 max = 15;
137 else {
138 switch (bpp) {
139 case 2:
140 max = 8;
141 break;
142
143 default:
144 WARN_ON_ONCE(1);
145 fallthrough;
146 case 4:
147 max = 4;
148 break;
149 }
150 }
151
152 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
153 inf.full -= dfixed_const(1);
154
155 dda_inc = dfixed_div(inf, outf);
156 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
157
158 return dda_inc;
159 }
160
compute_initial_dda(unsigned int in)161 static inline u32 compute_initial_dda(unsigned int in)
162 {
163 fixed20_12 inf = dfixed_init(in);
164 return dfixed_frac(inf);
165 }
166
tegra_plane_setup_blending_legacy(struct tegra_plane * plane)167 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
168 {
169 u32 background[3] = {
170 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
171 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
172 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
173 };
174 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
175 BLEND_COLOR_KEY_NONE;
176 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
177 struct tegra_plane_state *state;
178 u32 blending[2];
179 unsigned int i;
180
181 /* disable blending for non-overlapping case */
182 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
183 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
184
185 state = to_tegra_plane_state(plane->base.state);
186
187 if (state->opaque) {
188 /*
189 * Since custom fix-weight blending isn't utilized and weight
190 * of top window is set to max, we can enforce dependent
191 * blending which in this case results in transparent bottom
192 * window if top window is opaque and if top window enables
193 * alpha blending, then bottom window is getting alpha value
194 * of 1 minus the sum of alpha components of the overlapping
195 * plane.
196 */
197 background[0] |= BLEND_CONTROL_DEPENDENT;
198 background[1] |= BLEND_CONTROL_DEPENDENT;
199
200 /*
201 * The region where three windows overlap is the intersection
202 * of the two regions where two windows overlap. It contributes
203 * to the area if all of the windows on top of it have an alpha
204 * component.
205 */
206 switch (state->base.normalized_zpos) {
207 case 0:
208 if (state->blending[0].alpha &&
209 state->blending[1].alpha)
210 background[2] |= BLEND_CONTROL_DEPENDENT;
211 break;
212
213 case 1:
214 background[2] |= BLEND_CONTROL_DEPENDENT;
215 break;
216 }
217 } else {
218 /*
219 * Enable alpha blending if pixel format has an alpha
220 * component.
221 */
222 foreground |= BLEND_CONTROL_ALPHA;
223
224 /*
225 * If any of the windows on top of this window is opaque, it
226 * will completely conceal this window within that area. If
227 * top window has an alpha component, it is blended over the
228 * bottom window.
229 */
230 for (i = 0; i < 2; i++) {
231 if (state->blending[i].alpha &&
232 state->blending[i].top)
233 background[i] |= BLEND_CONTROL_DEPENDENT;
234 }
235
236 switch (state->base.normalized_zpos) {
237 case 0:
238 if (state->blending[0].alpha &&
239 state->blending[1].alpha)
240 background[2] |= BLEND_CONTROL_DEPENDENT;
241 break;
242
243 case 1:
244 /*
245 * When both middle and topmost windows have an alpha,
246 * these windows a mixed together and then the result
247 * is blended over the bottom window.
248 */
249 if (state->blending[0].alpha &&
250 state->blending[0].top)
251 background[2] |= BLEND_CONTROL_ALPHA;
252
253 if (state->blending[1].alpha &&
254 state->blending[1].top)
255 background[2] |= BLEND_CONTROL_ALPHA;
256 break;
257 }
258 }
259
260 switch (state->base.normalized_zpos) {
261 case 0:
262 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
263 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
264 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
265 break;
266
267 case 1:
268 /*
269 * If window B / C is topmost, then X / Y registers are
270 * matching the order of blending[...] state indices,
271 * otherwise a swap is required.
272 */
273 if (!state->blending[0].top && state->blending[1].top) {
274 blending[0] = foreground;
275 blending[1] = background[1];
276 } else {
277 blending[0] = background[0];
278 blending[1] = foreground;
279 }
280
281 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
282 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
283 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
284 break;
285
286 case 2:
287 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
288 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
289 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
290 break;
291 }
292 }
293
tegra_plane_setup_blending(struct tegra_plane * plane,const struct tegra_dc_window * window)294 static void tegra_plane_setup_blending(struct tegra_plane *plane,
295 const struct tegra_dc_window *window)
296 {
297 u32 value;
298
299 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
300 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
301 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
302 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
303
304 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
305 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
306 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
307 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
308
309 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
310 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
311 }
312
313 static bool
tegra_plane_use_horizontal_filtering(struct tegra_plane * plane,const struct tegra_dc_window * window)314 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
315 const struct tegra_dc_window *window)
316 {
317 struct tegra_dc *dc = plane->dc;
318
319 if (window->src.w == window->dst.w)
320 return false;
321
322 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
323 return false;
324
325 return true;
326 }
327
328 static bool
tegra_plane_use_vertical_filtering(struct tegra_plane * plane,const struct tegra_dc_window * window)329 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
330 const struct tegra_dc_window *window)
331 {
332 struct tegra_dc *dc = plane->dc;
333
334 if (window->src.h == window->dst.h)
335 return false;
336
337 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
338 return false;
339
340 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
341 return false;
342
343 return true;
344 }
345
tegra_dc_setup_window(struct tegra_plane * plane,const struct tegra_dc_window * window)346 static void tegra_dc_setup_window(struct tegra_plane *plane,
347 const struct tegra_dc_window *window)
348 {
349 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
350 struct tegra_dc *dc = plane->dc;
351 unsigned int planes;
352 u32 value;
353 bool yuv;
354
355 /*
356 * For YUV planar modes, the number of bytes per pixel takes into
357 * account only the luma component and therefore is 1.
358 */
359 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL);
360 if (!yuv)
361 bpp = window->bits_per_pixel / 8;
362 else
363 bpp = (planes > 1) ? 1 : 2;
364
365 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
366 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
367
368 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
369 tegra_plane_writel(plane, value, DC_WIN_POSITION);
370
371 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
372 tegra_plane_writel(plane, value, DC_WIN_SIZE);
373
374 h_offset = window->src.x * bpp;
375 v_offset = window->src.y;
376 h_size = window->src.w * bpp;
377 v_size = window->src.h;
378
379 if (window->reflect_x)
380 h_offset += (window->src.w - 1) * bpp;
381
382 if (window->reflect_y)
383 v_offset += window->src.h - 1;
384
385 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
386 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
387
388 /*
389 * For DDA computations the number of bytes per pixel for YUV planar
390 * modes needs to take into account all Y, U and V components.
391 */
392 if (yuv && planes > 1)
393 bpp = 2;
394
395 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
396 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
397
398 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
399 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
400
401 h_dda = compute_initial_dda(window->src.x);
402 v_dda = compute_initial_dda(window->src.y);
403
404 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
405 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
406
407 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
408 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
409
410 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
411
412 if (yuv && planes > 1) {
413 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
414
415 if (planes > 2)
416 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
417
418 value = window->stride[1] << 16 | window->stride[0];
419 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
420 } else {
421 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
422 }
423
424 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
425 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
426
427 if (dc->soc->supports_block_linear) {
428 unsigned long height = window->tiling.value;
429
430 switch (window->tiling.mode) {
431 case TEGRA_BO_TILING_MODE_PITCH:
432 value = DC_WINBUF_SURFACE_KIND_PITCH;
433 break;
434
435 case TEGRA_BO_TILING_MODE_TILED:
436 value = DC_WINBUF_SURFACE_KIND_TILED;
437 break;
438
439 case TEGRA_BO_TILING_MODE_BLOCK:
440 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
441 DC_WINBUF_SURFACE_KIND_BLOCK;
442 break;
443 }
444
445 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
446 } else {
447 switch (window->tiling.mode) {
448 case TEGRA_BO_TILING_MODE_PITCH:
449 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
450 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
451 break;
452
453 case TEGRA_BO_TILING_MODE_TILED:
454 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
455 DC_WIN_BUFFER_ADDR_MODE_TILE;
456 break;
457
458 case TEGRA_BO_TILING_MODE_BLOCK:
459 /*
460 * No need to handle this here because ->atomic_check
461 * will already have filtered it out.
462 */
463 break;
464 }
465
466 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
467 }
468
469 value = WIN_ENABLE;
470
471 if (yuv) {
472 /* setup default colorspace conversion coefficients */
473 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
474 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
475 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
476 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
477 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
478 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
479 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
480 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
481
482 value |= CSC_ENABLE;
483 } else if (window->bits_per_pixel < 24) {
484 value |= COLOR_EXPAND;
485 }
486
487 if (window->reflect_x)
488 value |= H_DIRECTION;
489
490 if (window->reflect_y)
491 value |= V_DIRECTION;
492
493 if (tegra_plane_use_horizontal_filtering(plane, window)) {
494 /*
495 * Enable horizontal 6-tap filter and set filtering
496 * coefficients to the default values defined in TRM.
497 */
498 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
499 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
500 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
501 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
502 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
503 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
504 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
505 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
506 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
507 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
508 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
509 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
510 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
511 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
512 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
513 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
514
515 value |= H_FILTER;
516 }
517
518 if (tegra_plane_use_vertical_filtering(plane, window)) {
519 unsigned int i, k;
520
521 /*
522 * Enable vertical 2-tap filter and set filtering
523 * coefficients to the default values defined in TRM.
524 */
525 for (i = 0, k = 128; i < 16; i++, k -= 8)
526 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
527
528 value |= V_FILTER;
529 }
530
531 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
532
533 if (dc->soc->has_legacy_blending)
534 tegra_plane_setup_blending_legacy(plane);
535 else
536 tegra_plane_setup_blending(plane, window);
537 }
538
539 static const u32 tegra20_primary_formats[] = {
540 DRM_FORMAT_ARGB4444,
541 DRM_FORMAT_ARGB1555,
542 DRM_FORMAT_RGB565,
543 DRM_FORMAT_RGBA5551,
544 DRM_FORMAT_ABGR8888,
545 DRM_FORMAT_ARGB8888,
546 /* non-native formats */
547 DRM_FORMAT_XRGB1555,
548 DRM_FORMAT_RGBX5551,
549 DRM_FORMAT_XBGR8888,
550 DRM_FORMAT_XRGB8888,
551 };
552
553 static const u64 tegra20_modifiers[] = {
554 DRM_FORMAT_MOD_LINEAR,
555 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
556 DRM_FORMAT_MOD_INVALID
557 };
558
559 static const u32 tegra114_primary_formats[] = {
560 DRM_FORMAT_ARGB4444,
561 DRM_FORMAT_ARGB1555,
562 DRM_FORMAT_RGB565,
563 DRM_FORMAT_RGBA5551,
564 DRM_FORMAT_ABGR8888,
565 DRM_FORMAT_ARGB8888,
566 /* new on Tegra114 */
567 DRM_FORMAT_ABGR4444,
568 DRM_FORMAT_ABGR1555,
569 DRM_FORMAT_BGRA5551,
570 DRM_FORMAT_XRGB1555,
571 DRM_FORMAT_RGBX5551,
572 DRM_FORMAT_XBGR1555,
573 DRM_FORMAT_BGRX5551,
574 DRM_FORMAT_BGR565,
575 DRM_FORMAT_BGRA8888,
576 DRM_FORMAT_RGBA8888,
577 DRM_FORMAT_XRGB8888,
578 DRM_FORMAT_XBGR8888,
579 };
580
581 static const u32 tegra124_primary_formats[] = {
582 DRM_FORMAT_ARGB4444,
583 DRM_FORMAT_ARGB1555,
584 DRM_FORMAT_RGB565,
585 DRM_FORMAT_RGBA5551,
586 DRM_FORMAT_ABGR8888,
587 DRM_FORMAT_ARGB8888,
588 /* new on Tegra114 */
589 DRM_FORMAT_ABGR4444,
590 DRM_FORMAT_ABGR1555,
591 DRM_FORMAT_BGRA5551,
592 DRM_FORMAT_XRGB1555,
593 DRM_FORMAT_RGBX5551,
594 DRM_FORMAT_XBGR1555,
595 DRM_FORMAT_BGRX5551,
596 DRM_FORMAT_BGR565,
597 DRM_FORMAT_BGRA8888,
598 DRM_FORMAT_RGBA8888,
599 DRM_FORMAT_XRGB8888,
600 DRM_FORMAT_XBGR8888,
601 /* new on Tegra124 */
602 DRM_FORMAT_RGBX8888,
603 DRM_FORMAT_BGRX8888,
604 };
605
606 static const u64 tegra124_modifiers[] = {
607 DRM_FORMAT_MOD_LINEAR,
608 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
609 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
610 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
611 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
612 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
613 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
614 DRM_FORMAT_MOD_INVALID
615 };
616
tegra_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)617 static int tegra_plane_atomic_check(struct drm_plane *plane,
618 struct drm_atomic_state *state)
619 {
620 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
621 plane);
622 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
623 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
624 DRM_MODE_REFLECT_X |
625 DRM_MODE_REFLECT_Y;
626 unsigned int rotation = new_plane_state->rotation;
627 struct tegra_bo_tiling *tiling = &plane_state->tiling;
628 struct tegra_plane *tegra = to_tegra_plane(plane);
629 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
630 int err;
631
632 plane_state->peak_memory_bandwidth = 0;
633 plane_state->avg_memory_bandwidth = 0;
634
635 /* no need for further checks if the plane is being disabled */
636 if (!new_plane_state->crtc) {
637 plane_state->total_peak_memory_bandwidth = 0;
638 return 0;
639 }
640
641 err = tegra_plane_format(new_plane_state->fb->format->format,
642 &plane_state->format,
643 &plane_state->swap);
644 if (err < 0)
645 return err;
646
647 /*
648 * Tegra20 and Tegra30 are special cases here because they support
649 * only variants of specific formats with an alpha component, but not
650 * the corresponding opaque formats. However, the opaque formats can
651 * be emulated by disabling alpha blending for the plane.
652 */
653 if (dc->soc->has_legacy_blending) {
654 err = tegra_plane_setup_legacy_state(tegra, plane_state);
655 if (err < 0)
656 return err;
657 }
658
659 err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
660 if (err < 0)
661 return err;
662
663 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
664 !dc->soc->supports_block_linear) {
665 DRM_ERROR("hardware doesn't support block linear mode\n");
666 return -EINVAL;
667 }
668
669 /*
670 * Older userspace used custom BO flag in order to specify the Y
671 * reflection, while modern userspace uses the generic DRM rotation
672 * property in order to achieve the same result. The legacy BO flag
673 * duplicates the DRM rotation property when both are set.
674 */
675 if (tegra_fb_is_bottom_up(new_plane_state->fb))
676 rotation |= DRM_MODE_REFLECT_Y;
677
678 rotation = drm_rotation_simplify(rotation, supported_rotation);
679
680 if (rotation & DRM_MODE_REFLECT_X)
681 plane_state->reflect_x = true;
682 else
683 plane_state->reflect_x = false;
684
685 if (rotation & DRM_MODE_REFLECT_Y)
686 plane_state->reflect_y = true;
687 else
688 plane_state->reflect_y = false;
689
690 /*
691 * Tegra doesn't support different strides for U and V planes so we
692 * error out if the user tries to display a framebuffer with such a
693 * configuration.
694 */
695 if (new_plane_state->fb->format->num_planes > 2) {
696 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
697 DRM_ERROR("unsupported UV-plane configuration\n");
698 return -EINVAL;
699 }
700 }
701
702 err = tegra_plane_state_add(tegra, new_plane_state);
703 if (err < 0)
704 return err;
705
706 return 0;
707 }
708
tegra_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)709 static void tegra_plane_atomic_disable(struct drm_plane *plane,
710 struct drm_atomic_state *state)
711 {
712 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
713 plane);
714 struct tegra_plane *p = to_tegra_plane(plane);
715 u32 value;
716
717 /* rien ne va plus */
718 if (!old_state || !old_state->crtc)
719 return;
720
721 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
722 value &= ~WIN_ENABLE;
723 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
724 }
725
tegra_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)726 static void tegra_plane_atomic_update(struct drm_plane *plane,
727 struct drm_atomic_state *state)
728 {
729 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
730 plane);
731 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
732 struct drm_framebuffer *fb = new_state->fb;
733 struct tegra_plane *p = to_tegra_plane(plane);
734 struct tegra_dc_window window;
735 unsigned int i;
736
737 /* rien ne va plus */
738 if (!new_state->crtc || !new_state->fb)
739 return;
740
741 if (!new_state->visible)
742 return tegra_plane_atomic_disable(plane, state);
743
744 memset(&window, 0, sizeof(window));
745 window.src.x = new_state->src.x1 >> 16;
746 window.src.y = new_state->src.y1 >> 16;
747 window.src.w = drm_rect_width(&new_state->src) >> 16;
748 window.src.h = drm_rect_height(&new_state->src) >> 16;
749 window.dst.x = new_state->dst.x1;
750 window.dst.y = new_state->dst.y1;
751 window.dst.w = drm_rect_width(&new_state->dst);
752 window.dst.h = drm_rect_height(&new_state->dst);
753 window.bits_per_pixel = fb->format->cpp[0] * 8;
754 window.reflect_x = tegra_plane_state->reflect_x;
755 window.reflect_y = tegra_plane_state->reflect_y;
756
757 /* copy from state */
758 window.zpos = new_state->normalized_zpos;
759 window.tiling = tegra_plane_state->tiling;
760 window.format = tegra_plane_state->format;
761 window.swap = tegra_plane_state->swap;
762
763 for (i = 0; i < fb->format->num_planes; i++) {
764 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
765
766 /*
767 * Tegra uses a shared stride for UV planes. Framebuffers are
768 * already checked for this in the tegra_plane_atomic_check()
769 * function, so it's safe to ignore the V-plane pitch here.
770 */
771 if (i < 2)
772 window.stride[i] = fb->pitches[i];
773 }
774
775 tegra_dc_setup_window(p, &window);
776 }
777
778 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
779 .prepare_fb = tegra_plane_prepare_fb,
780 .cleanup_fb = tegra_plane_cleanup_fb,
781 .atomic_check = tegra_plane_atomic_check,
782 .atomic_disable = tegra_plane_atomic_disable,
783 .atomic_update = tegra_plane_atomic_update,
784 };
785
tegra_plane_get_possible_crtcs(struct drm_device * drm)786 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
787 {
788 /*
789 * Ideally this would use drm_crtc_mask(), but that would require the
790 * CRTC to already be in the mode_config's list of CRTCs. However, it
791 * will only be added to that list in the drm_crtc_init_with_planes()
792 * (in tegra_dc_init()), which in turn requires registration of these
793 * planes. So we have ourselves a nice little chicken and egg problem
794 * here.
795 *
796 * We work around this by manually creating the mask from the number
797 * of CRTCs that have been registered, and should therefore always be
798 * the same as drm_crtc_index() after registration.
799 */
800 return 1 << drm->mode_config.num_crtc;
801 }
802
tegra_primary_plane_create(struct drm_device * drm,struct tegra_dc * dc)803 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
804 struct tegra_dc *dc)
805 {
806 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
807 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
808 struct tegra_plane *plane;
809 unsigned int num_formats;
810 const u64 *modifiers;
811 const u32 *formats;
812 int err;
813
814 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
815 if (!plane)
816 return ERR_PTR(-ENOMEM);
817
818 /* Always use window A as primary window */
819 plane->offset = 0xa00;
820 plane->index = 0;
821 plane->dc = dc;
822
823 num_formats = dc->soc->num_primary_formats;
824 formats = dc->soc->primary_formats;
825 modifiers = dc->soc->modifiers;
826
827 err = tegra_plane_interconnect_init(plane);
828 if (err) {
829 kfree(plane);
830 return ERR_PTR(err);
831 }
832
833 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
834 &tegra_plane_funcs, formats,
835 num_formats, modifiers, type, NULL);
836 if (err < 0) {
837 kfree(plane);
838 return ERR_PTR(err);
839 }
840
841 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
842 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
843
844 err = drm_plane_create_rotation_property(&plane->base,
845 DRM_MODE_ROTATE_0,
846 DRM_MODE_ROTATE_0 |
847 DRM_MODE_ROTATE_180 |
848 DRM_MODE_REFLECT_X |
849 DRM_MODE_REFLECT_Y);
850 if (err < 0)
851 dev_err(dc->dev, "failed to create rotation property: %d\n",
852 err);
853
854 return &plane->base;
855 }
856
857 static const u32 tegra_legacy_cursor_plane_formats[] = {
858 DRM_FORMAT_RGBA8888,
859 };
860
861 static const u32 tegra_cursor_plane_formats[] = {
862 DRM_FORMAT_ARGB8888,
863 };
864
tegra_cursor_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)865 static int tegra_cursor_atomic_check(struct drm_plane *plane,
866 struct drm_atomic_state *state)
867 {
868 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
869 plane);
870 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
871 struct tegra_plane *tegra = to_tegra_plane(plane);
872 int err;
873
874 plane_state->peak_memory_bandwidth = 0;
875 plane_state->avg_memory_bandwidth = 0;
876
877 /* no need for further checks if the plane is being disabled */
878 if (!new_plane_state->crtc) {
879 plane_state->total_peak_memory_bandwidth = 0;
880 return 0;
881 }
882
883 /* scaling not supported for cursor */
884 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
885 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
886 return -EINVAL;
887
888 /* only square cursors supported */
889 if (new_plane_state->src_w != new_plane_state->src_h)
890 return -EINVAL;
891
892 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
893 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
894 return -EINVAL;
895
896 err = tegra_plane_state_add(tegra, new_plane_state);
897 if (err < 0)
898 return err;
899
900 return 0;
901 }
902
__tegra_cursor_atomic_update(struct drm_plane * plane,struct drm_plane_state * new_state)903 static void __tegra_cursor_atomic_update(struct drm_plane *plane,
904 struct drm_plane_state *new_state)
905 {
906 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
907 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
908 struct tegra_drm *tegra = plane->dev->dev_private;
909 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
910 u64 dma_mask = *dc->dev->dma_mask;
911 #endif
912 unsigned int x, y;
913 u32 value = 0;
914
915 /* rien ne va plus */
916 if (!new_state->crtc || !new_state->fb)
917 return;
918
919 /*
920 * Legacy display supports hardware clipping of the cursor, but
921 * nvdisplay relies on software to clip the cursor to the screen.
922 */
923 if (!dc->soc->has_nvdisplay)
924 value |= CURSOR_CLIP_DISPLAY;
925
926 switch (new_state->crtc_w) {
927 case 32:
928 value |= CURSOR_SIZE_32x32;
929 break;
930
931 case 64:
932 value |= CURSOR_SIZE_64x64;
933 break;
934
935 case 128:
936 value |= CURSOR_SIZE_128x128;
937 break;
938
939 case 256:
940 value |= CURSOR_SIZE_256x256;
941 break;
942
943 default:
944 WARN(1, "cursor size %ux%u not supported\n",
945 new_state->crtc_w, new_state->crtc_h);
946 return;
947 }
948
949 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
950 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
951
952 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
953 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
954 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
955 #endif
956
957 /* enable cursor and set blend mode */
958 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
959 value |= CURSOR_ENABLE;
960 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
961
962 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
963 value &= ~CURSOR_DST_BLEND_MASK;
964 value &= ~CURSOR_SRC_BLEND_MASK;
965
966 if (dc->soc->has_nvdisplay)
967 value &= ~CURSOR_COMPOSITION_MODE_XOR;
968 else
969 value |= CURSOR_MODE_NORMAL;
970
971 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
972 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
973 value |= CURSOR_ALPHA;
974 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
975
976 /* nvdisplay relies on software for clipping */
977 if (dc->soc->has_nvdisplay) {
978 struct drm_rect src;
979
980 x = new_state->dst.x1;
981 y = new_state->dst.y1;
982
983 drm_rect_fp_to_int(&src, &new_state->src);
984
985 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
986 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
987
988 value = (drm_rect_height(&src) & tegra->vmask) << 16 |
989 (drm_rect_width(&src) & tegra->hmask);
990 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
991 } else {
992 x = new_state->crtc_x;
993 y = new_state->crtc_y;
994 }
995
996 /* position the cursor */
997 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
998 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
999 }
1000
tegra_cursor_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1001 static void tegra_cursor_atomic_update(struct drm_plane *plane,
1002 struct drm_atomic_state *state)
1003 {
1004 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1005
1006 __tegra_cursor_atomic_update(plane, new_state);
1007 }
1008
tegra_cursor_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)1009 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
1010 struct drm_atomic_state *state)
1011 {
1012 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
1013 plane);
1014 struct tegra_dc *dc;
1015 u32 value;
1016
1017 /* rien ne va plus */
1018 if (!old_state || !old_state->crtc)
1019 return;
1020
1021 dc = to_tegra_dc(old_state->crtc);
1022
1023 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1024 value &= ~CURSOR_ENABLE;
1025 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1026 }
1027
tegra_cursor_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state,bool flip)1028 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state,
1029 bool flip)
1030 {
1031 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1032 struct drm_crtc_state *crtc_state;
1033 int min_scale, max_scale;
1034 int err;
1035
1036 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc);
1037 if (WARN_ON(!crtc_state))
1038 return -EINVAL;
1039
1040 if (!crtc_state->active)
1041 return -EINVAL;
1042
1043 if (plane->state->crtc != new_state->crtc ||
1044 plane->state->src_w != new_state->src_w ||
1045 plane->state->src_h != new_state->src_h ||
1046 plane->state->crtc_w != new_state->crtc_w ||
1047 plane->state->crtc_h != new_state->crtc_h ||
1048 plane->state->fb != new_state->fb ||
1049 plane->state->fb == NULL)
1050 return -EINVAL;
1051
1052 min_scale = (1 << 16) / 8;
1053 max_scale = (8 << 16) / 1;
1054
1055 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,
1056 true, true);
1057 if (err < 0)
1058 return err;
1059
1060 if (new_state->visible != plane->state->visible)
1061 return -EINVAL;
1062
1063 return 0;
1064 }
1065
tegra_cursor_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)1066 static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
1067 struct drm_atomic_state *state)
1068 {
1069 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1070 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
1071
1072 plane->state->src_x = new_state->src_x;
1073 plane->state->src_y = new_state->src_y;
1074 plane->state->crtc_x = new_state->crtc_x;
1075 plane->state->crtc_y = new_state->crtc_y;
1076
1077 if (new_state->visible) {
1078 struct tegra_plane *p = to_tegra_plane(plane);
1079 u32 value;
1080
1081 __tegra_cursor_atomic_update(plane, new_state);
1082
1083 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE;
1084 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1085 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1086
1087 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ;
1088 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1089 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1090 }
1091 }
1092
1093 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
1094 .prepare_fb = tegra_plane_prepare_fb,
1095 .cleanup_fb = tegra_plane_cleanup_fb,
1096 .atomic_check = tegra_cursor_atomic_check,
1097 .atomic_update = tegra_cursor_atomic_update,
1098 .atomic_disable = tegra_cursor_atomic_disable,
1099 .atomic_async_check = tegra_cursor_atomic_async_check,
1100 .atomic_async_update = tegra_cursor_atomic_async_update,
1101 };
1102
1103 static const uint64_t linear_modifiers[] = {
1104 DRM_FORMAT_MOD_LINEAR,
1105 DRM_FORMAT_MOD_INVALID
1106 };
1107
tegra_dc_cursor_plane_create(struct drm_device * drm,struct tegra_dc * dc)1108 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1109 struct tegra_dc *dc)
1110 {
1111 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1112 struct tegra_plane *plane;
1113 unsigned int num_formats;
1114 const u32 *formats;
1115 int err;
1116
1117 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1118 if (!plane)
1119 return ERR_PTR(-ENOMEM);
1120
1121 /*
1122 * This index is kind of fake. The cursor isn't a regular plane, but
1123 * its update and activation request bits in DC_CMD_STATE_CONTROL do
1124 * use the same programming. Setting this fake index here allows the
1125 * code in tegra_add_plane_state() to do the right thing without the
1126 * need to special-casing the cursor plane.
1127 */
1128 plane->index = 6;
1129 plane->dc = dc;
1130
1131 if (!dc->soc->has_nvdisplay) {
1132 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1133 formats = tegra_legacy_cursor_plane_formats;
1134
1135 err = tegra_plane_interconnect_init(plane);
1136 if (err) {
1137 kfree(plane);
1138 return ERR_PTR(err);
1139 }
1140 } else {
1141 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1142 formats = tegra_cursor_plane_formats;
1143 }
1144
1145 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1146 &tegra_plane_funcs, formats,
1147 num_formats, linear_modifiers,
1148 DRM_PLANE_TYPE_CURSOR, NULL);
1149 if (err < 0) {
1150 kfree(plane);
1151 return ERR_PTR(err);
1152 }
1153
1154 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1155 drm_plane_create_zpos_immutable_property(&plane->base, 255);
1156
1157 return &plane->base;
1158 }
1159
1160 static const u32 tegra20_overlay_formats[] = {
1161 DRM_FORMAT_ARGB4444,
1162 DRM_FORMAT_ARGB1555,
1163 DRM_FORMAT_RGB565,
1164 DRM_FORMAT_RGBA5551,
1165 DRM_FORMAT_ABGR8888,
1166 DRM_FORMAT_ARGB8888,
1167 /* non-native formats */
1168 DRM_FORMAT_XRGB1555,
1169 DRM_FORMAT_RGBX5551,
1170 DRM_FORMAT_XBGR8888,
1171 DRM_FORMAT_XRGB8888,
1172 /* planar formats */
1173 DRM_FORMAT_UYVY,
1174 DRM_FORMAT_YUYV,
1175 DRM_FORMAT_YUV420,
1176 DRM_FORMAT_YUV422,
1177 };
1178
1179 static const u32 tegra114_overlay_formats[] = {
1180 DRM_FORMAT_ARGB4444,
1181 DRM_FORMAT_ARGB1555,
1182 DRM_FORMAT_RGB565,
1183 DRM_FORMAT_RGBA5551,
1184 DRM_FORMAT_ABGR8888,
1185 DRM_FORMAT_ARGB8888,
1186 /* new on Tegra114 */
1187 DRM_FORMAT_ABGR4444,
1188 DRM_FORMAT_ABGR1555,
1189 DRM_FORMAT_BGRA5551,
1190 DRM_FORMAT_XRGB1555,
1191 DRM_FORMAT_RGBX5551,
1192 DRM_FORMAT_XBGR1555,
1193 DRM_FORMAT_BGRX5551,
1194 DRM_FORMAT_BGR565,
1195 DRM_FORMAT_BGRA8888,
1196 DRM_FORMAT_RGBA8888,
1197 DRM_FORMAT_XRGB8888,
1198 DRM_FORMAT_XBGR8888,
1199 /* planar formats */
1200 DRM_FORMAT_UYVY,
1201 DRM_FORMAT_YUYV,
1202 DRM_FORMAT_YUV420,
1203 DRM_FORMAT_YUV422,
1204 /* semi-planar formats */
1205 DRM_FORMAT_NV12,
1206 DRM_FORMAT_NV21,
1207 DRM_FORMAT_NV16,
1208 DRM_FORMAT_NV61,
1209 DRM_FORMAT_NV24,
1210 DRM_FORMAT_NV42,
1211 };
1212
1213 static const u32 tegra124_overlay_formats[] = {
1214 DRM_FORMAT_ARGB4444,
1215 DRM_FORMAT_ARGB1555,
1216 DRM_FORMAT_RGB565,
1217 DRM_FORMAT_RGBA5551,
1218 DRM_FORMAT_ABGR8888,
1219 DRM_FORMAT_ARGB8888,
1220 /* new on Tegra114 */
1221 DRM_FORMAT_ABGR4444,
1222 DRM_FORMAT_ABGR1555,
1223 DRM_FORMAT_BGRA5551,
1224 DRM_FORMAT_XRGB1555,
1225 DRM_FORMAT_RGBX5551,
1226 DRM_FORMAT_XBGR1555,
1227 DRM_FORMAT_BGRX5551,
1228 DRM_FORMAT_BGR565,
1229 DRM_FORMAT_BGRA8888,
1230 DRM_FORMAT_RGBA8888,
1231 DRM_FORMAT_XRGB8888,
1232 DRM_FORMAT_XBGR8888,
1233 /* new on Tegra124 */
1234 DRM_FORMAT_RGBX8888,
1235 DRM_FORMAT_BGRX8888,
1236 /* planar formats */
1237 DRM_FORMAT_UYVY,
1238 DRM_FORMAT_YUYV,
1239 DRM_FORMAT_YVYU,
1240 DRM_FORMAT_VYUY,
1241 DRM_FORMAT_YUV420, /* YU12 */
1242 DRM_FORMAT_YUV422, /* YU16 */
1243 DRM_FORMAT_YUV444, /* YU24 */
1244 /* semi-planar formats */
1245 DRM_FORMAT_NV12,
1246 DRM_FORMAT_NV21,
1247 DRM_FORMAT_NV16,
1248 DRM_FORMAT_NV61,
1249 DRM_FORMAT_NV24,
1250 DRM_FORMAT_NV42,
1251 };
1252
tegra_dc_overlay_plane_create(struct drm_device * drm,struct tegra_dc * dc,unsigned int index,bool cursor)1253 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1254 struct tegra_dc *dc,
1255 unsigned int index,
1256 bool cursor)
1257 {
1258 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1259 struct tegra_plane *plane;
1260 unsigned int num_formats;
1261 enum drm_plane_type type;
1262 const u32 *formats;
1263 int err;
1264
1265 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1266 if (!plane)
1267 return ERR_PTR(-ENOMEM);
1268
1269 plane->offset = 0xa00 + 0x200 * index;
1270 plane->index = index;
1271 plane->dc = dc;
1272
1273 num_formats = dc->soc->num_overlay_formats;
1274 formats = dc->soc->overlay_formats;
1275
1276 err = tegra_plane_interconnect_init(plane);
1277 if (err) {
1278 kfree(plane);
1279 return ERR_PTR(err);
1280 }
1281
1282 if (!cursor)
1283 type = DRM_PLANE_TYPE_OVERLAY;
1284 else
1285 type = DRM_PLANE_TYPE_CURSOR;
1286
1287 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1288 &tegra_plane_funcs, formats,
1289 num_formats, linear_modifiers,
1290 type, NULL);
1291 if (err < 0) {
1292 kfree(plane);
1293 return ERR_PTR(err);
1294 }
1295
1296 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1297 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1298
1299 err = drm_plane_create_rotation_property(&plane->base,
1300 DRM_MODE_ROTATE_0,
1301 DRM_MODE_ROTATE_0 |
1302 DRM_MODE_ROTATE_180 |
1303 DRM_MODE_REFLECT_X |
1304 DRM_MODE_REFLECT_Y);
1305 if (err < 0)
1306 dev_err(dc->dev, "failed to create rotation property: %d\n",
1307 err);
1308
1309 return &plane->base;
1310 }
1311
tegra_dc_add_shared_planes(struct drm_device * drm,struct tegra_dc * dc)1312 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1313 struct tegra_dc *dc)
1314 {
1315 struct drm_plane *plane, *primary = NULL;
1316 unsigned int i, j;
1317
1318 for (i = 0; i < dc->soc->num_wgrps; i++) {
1319 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1320
1321 if (wgrp->dc == dc->pipe) {
1322 for (j = 0; j < wgrp->num_windows; j++) {
1323 unsigned int index = wgrp->windows[j];
1324
1325 plane = tegra_shared_plane_create(drm, dc,
1326 wgrp->index,
1327 index);
1328 if (IS_ERR(plane))
1329 return plane;
1330
1331 /*
1332 * Choose the first shared plane owned by this
1333 * head as the primary plane.
1334 */
1335 if (!primary) {
1336 plane->type = DRM_PLANE_TYPE_PRIMARY;
1337 primary = plane;
1338 }
1339 }
1340 }
1341 }
1342
1343 return primary;
1344 }
1345
tegra_dc_add_planes(struct drm_device * drm,struct tegra_dc * dc)1346 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1347 struct tegra_dc *dc)
1348 {
1349 struct drm_plane *planes[2], *primary;
1350 unsigned int planes_num;
1351 unsigned int i;
1352 int err;
1353
1354 primary = tegra_primary_plane_create(drm, dc);
1355 if (IS_ERR(primary))
1356 return primary;
1357
1358 if (dc->soc->supports_cursor)
1359 planes_num = 2;
1360 else
1361 planes_num = 1;
1362
1363 for (i = 0; i < planes_num; i++) {
1364 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1365 false);
1366 if (IS_ERR(planes[i])) {
1367 err = PTR_ERR(planes[i]);
1368
1369 while (i--)
1370 planes[i]->funcs->destroy(planes[i]);
1371
1372 primary->funcs->destroy(primary);
1373 return ERR_PTR(err);
1374 }
1375 }
1376
1377 return primary;
1378 }
1379
tegra_dc_destroy(struct drm_crtc * crtc)1380 static void tegra_dc_destroy(struct drm_crtc *crtc)
1381 {
1382 drm_crtc_cleanup(crtc);
1383 }
1384
tegra_crtc_reset(struct drm_crtc * crtc)1385 static void tegra_crtc_reset(struct drm_crtc *crtc)
1386 {
1387 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1388
1389 if (crtc->state)
1390 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1391
1392 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1393 }
1394
1395 static struct drm_crtc_state *
tegra_crtc_atomic_duplicate_state(struct drm_crtc * crtc)1396 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1397 {
1398 struct tegra_dc_state *state = to_dc_state(crtc->state);
1399 struct tegra_dc_state *copy;
1400
1401 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1402 if (!copy)
1403 return NULL;
1404
1405 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1406 copy->clk = state->clk;
1407 copy->pclk = state->pclk;
1408 copy->div = state->div;
1409 copy->planes = state->planes;
1410
1411 return ©->base;
1412 }
1413
tegra_crtc_atomic_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)1414 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1415 struct drm_crtc_state *state)
1416 {
1417 __drm_atomic_helper_crtc_destroy_state(state);
1418 kfree(state);
1419 }
1420
1421 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1422
1423 static const struct debugfs_reg32 tegra_dc_regs[] = {
1424 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1425 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1426 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1427 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1428 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1429 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1430 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1431 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1432 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1433 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1434 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1435 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1436 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1437 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1438 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1439 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1440 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1441 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1442 DEBUGFS_REG32(DC_CMD_INT_MASK),
1443 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1444 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1445 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1446 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1447 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1448 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1449 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1450 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1451 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1452 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1453 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1454 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1455 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1456 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1457 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1458 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1459 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1460 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1461 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1462 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1463 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1464 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1465 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1466 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1467 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1468 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1469 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1470 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1471 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1472 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1473 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1474 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1475 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1476 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1477 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1478 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1479 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1480 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1481 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1482 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1483 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1484 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1485 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1486 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1487 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1488 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1489 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1490 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1491 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1492 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1493 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1494 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1495 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1496 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1497 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1498 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1499 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1500 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1501 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1502 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1503 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1504 DEBUGFS_REG32(DC_DISP_ACTIVE),
1505 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1506 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1507 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1508 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1509 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1510 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1511 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1512 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1513 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1514 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1515 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1516 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1517 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1518 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1519 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1520 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1521 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1522 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1523 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1524 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1525 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1526 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1527 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1528 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1529 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1530 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1531 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1532 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1533 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1534 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1535 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1536 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1537 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1538 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1539 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1540 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1541 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1542 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1543 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1544 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1545 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1546 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1547 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1548 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1549 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1550 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1551 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1552 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1553 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1554 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1555 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1556 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1557 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1558 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1559 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1560 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1561 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1562 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1563 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1564 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1565 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1566 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1567 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1568 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1569 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1570 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1571 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1572 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1573 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1574 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1575 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1576 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1577 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1578 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1579 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1580 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1581 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1582 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1583 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1584 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1585 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1586 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1587 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1588 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1589 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1590 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1591 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1592 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1593 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1594 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1595 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1596 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1597 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1598 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1599 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1600 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1601 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1602 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1603 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1604 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1605 DEBUGFS_REG32(DC_WIN_POSITION),
1606 DEBUGFS_REG32(DC_WIN_SIZE),
1607 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1608 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1609 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1610 DEBUGFS_REG32(DC_WIN_DDA_INC),
1611 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1612 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1613 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1614 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1615 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1616 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1617 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1618 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1619 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1620 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1621 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1622 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1623 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1624 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1625 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1626 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1627 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1628 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1629 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1630 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1631 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1632 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1633 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1634 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1635 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1636 };
1637
tegra_dc_show_regs(struct seq_file * s,void * data)1638 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1639 {
1640 struct drm_info_node *node = s->private;
1641 struct tegra_dc *dc = node->info_ent->data;
1642 unsigned int i;
1643 int err = 0;
1644
1645 drm_modeset_lock(&dc->base.mutex, NULL);
1646
1647 if (!dc->base.state->active) {
1648 err = -EBUSY;
1649 goto unlock;
1650 }
1651
1652 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1653 unsigned int offset = tegra_dc_regs[i].offset;
1654
1655 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1656 offset, tegra_dc_readl(dc, offset));
1657 }
1658
1659 unlock:
1660 drm_modeset_unlock(&dc->base.mutex);
1661 return err;
1662 }
1663
tegra_dc_show_crc(struct seq_file * s,void * data)1664 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1665 {
1666 struct drm_info_node *node = s->private;
1667 struct tegra_dc *dc = node->info_ent->data;
1668 int err = 0;
1669 u32 value;
1670
1671 drm_modeset_lock(&dc->base.mutex, NULL);
1672
1673 if (!dc->base.state->active) {
1674 err = -EBUSY;
1675 goto unlock;
1676 }
1677
1678 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1679 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1680 tegra_dc_commit(dc);
1681
1682 drm_crtc_wait_one_vblank(&dc->base);
1683 drm_crtc_wait_one_vblank(&dc->base);
1684
1685 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1686 seq_printf(s, "%08x\n", value);
1687
1688 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1689
1690 unlock:
1691 drm_modeset_unlock(&dc->base.mutex);
1692 return err;
1693 }
1694
tegra_dc_show_stats(struct seq_file * s,void * data)1695 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1696 {
1697 struct drm_info_node *node = s->private;
1698 struct tegra_dc *dc = node->info_ent->data;
1699
1700 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1701 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1702 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1703 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1704
1705 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
1706 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
1707 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
1708 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
1709
1710 return 0;
1711 }
1712
1713 static struct drm_info_list debugfs_files[] = {
1714 { "regs", tegra_dc_show_regs, 0, NULL },
1715 { "crc", tegra_dc_show_crc, 0, NULL },
1716 { "stats", tegra_dc_show_stats, 0, NULL },
1717 };
1718
tegra_dc_late_register(struct drm_crtc * crtc)1719 static int tegra_dc_late_register(struct drm_crtc *crtc)
1720 {
1721 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1722 struct drm_minor *minor = crtc->dev->primary;
1723 struct dentry *root;
1724 struct tegra_dc *dc = to_tegra_dc(crtc);
1725
1726 #ifdef CONFIG_DEBUG_FS
1727 root = crtc->debugfs_entry;
1728 #else
1729 root = NULL;
1730 #endif
1731
1732 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1733 GFP_KERNEL);
1734 if (!dc->debugfs_files)
1735 return -ENOMEM;
1736
1737 for (i = 0; i < count; i++)
1738 dc->debugfs_files[i].data = dc;
1739
1740 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1741
1742 return 0;
1743 }
1744
tegra_dc_early_unregister(struct drm_crtc * crtc)1745 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1746 {
1747 unsigned int count = ARRAY_SIZE(debugfs_files);
1748 struct drm_minor *minor = crtc->dev->primary;
1749 struct tegra_dc *dc = to_tegra_dc(crtc);
1750 struct dentry *root;
1751
1752 #ifdef CONFIG_DEBUG_FS
1753 root = crtc->debugfs_entry;
1754 #else
1755 root = NULL;
1756 #endif
1757
1758 drm_debugfs_remove_files(dc->debugfs_files, count, root, minor);
1759 kfree(dc->debugfs_files);
1760 dc->debugfs_files = NULL;
1761 }
1762
tegra_dc_get_vblank_counter(struct drm_crtc * crtc)1763 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1764 {
1765 struct tegra_dc *dc = to_tegra_dc(crtc);
1766
1767 /* XXX vblank syncpoints don't work with nvdisplay yet */
1768 if (dc->syncpt && !dc->soc->has_nvdisplay)
1769 return host1x_syncpt_read(dc->syncpt);
1770
1771 /* fallback to software emulated VBLANK counter */
1772 return (u32)drm_crtc_vblank_count(&dc->base);
1773 }
1774
tegra_dc_enable_vblank(struct drm_crtc * crtc)1775 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1776 {
1777 struct tegra_dc *dc = to_tegra_dc(crtc);
1778 u32 value;
1779
1780 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1781 value |= VBLANK_INT;
1782 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1783
1784 return 0;
1785 }
1786
tegra_dc_disable_vblank(struct drm_crtc * crtc)1787 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1788 {
1789 struct tegra_dc *dc = to_tegra_dc(crtc);
1790 u32 value;
1791
1792 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1793 value &= ~VBLANK_INT;
1794 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1795 }
1796
1797 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1798 .page_flip = drm_atomic_helper_page_flip,
1799 .set_config = drm_atomic_helper_set_config,
1800 .destroy = tegra_dc_destroy,
1801 .reset = tegra_crtc_reset,
1802 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1803 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1804 .late_register = tegra_dc_late_register,
1805 .early_unregister = tegra_dc_early_unregister,
1806 .get_vblank_counter = tegra_dc_get_vblank_counter,
1807 .enable_vblank = tegra_dc_enable_vblank,
1808 .disable_vblank = tegra_dc_disable_vblank,
1809 };
1810
tegra_dc_set_timings(struct tegra_dc * dc,struct drm_display_mode * mode)1811 static int tegra_dc_set_timings(struct tegra_dc *dc,
1812 struct drm_display_mode *mode)
1813 {
1814 unsigned int h_ref_to_sync = 1;
1815 unsigned int v_ref_to_sync = 1;
1816 unsigned long value;
1817
1818 if (!dc->soc->has_nvdisplay) {
1819 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1820
1821 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1822 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1823 }
1824
1825 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1826 ((mode->hsync_end - mode->hsync_start) << 0);
1827 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1828
1829 value = ((mode->vtotal - mode->vsync_end) << 16) |
1830 ((mode->htotal - mode->hsync_end) << 0);
1831 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1832
1833 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1834 ((mode->hsync_start - mode->hdisplay) << 0);
1835 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1836
1837 value = (mode->vdisplay << 16) | mode->hdisplay;
1838 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1839
1840 return 0;
1841 }
1842
1843 /**
1844 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1845 * state
1846 * @dc: display controller
1847 * @crtc_state: CRTC atomic state
1848 * @clk: parent clock for display controller
1849 * @pclk: pixel clock
1850 * @div: shift clock divider
1851 *
1852 * Returns:
1853 * 0 on success or a negative error-code on failure.
1854 */
tegra_dc_state_setup_clock(struct tegra_dc * dc,struct drm_crtc_state * crtc_state,struct clk * clk,unsigned long pclk,unsigned int div)1855 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1856 struct drm_crtc_state *crtc_state,
1857 struct clk *clk, unsigned long pclk,
1858 unsigned int div)
1859 {
1860 struct tegra_dc_state *state = to_dc_state(crtc_state);
1861
1862 if (!clk_has_parent(dc->clk, clk))
1863 return -EINVAL;
1864
1865 state->clk = clk;
1866 state->pclk = pclk;
1867 state->div = div;
1868
1869 return 0;
1870 }
1871
tegra_dc_update_voltage_state(struct tegra_dc * dc,struct tegra_dc_state * state)1872 static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
1873 struct tegra_dc_state *state)
1874 {
1875 unsigned long rate, pstate;
1876 struct dev_pm_opp *opp;
1877 int err;
1878
1879 if (!dc->has_opp_table)
1880 return;
1881
1882 /* calculate actual pixel clock rate which depends on internal divider */
1883 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
1884
1885 /* find suitable OPP for the rate */
1886 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
1887
1888 /*
1889 * Very high resolution modes may results in a clock rate that is
1890 * above the characterized maximum. In this case it's okay to fall
1891 * back to the characterized maximum.
1892 */
1893 if (opp == ERR_PTR(-ERANGE))
1894 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
1895
1896 if (IS_ERR(opp)) {
1897 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
1898 rate, opp);
1899 return;
1900 }
1901
1902 pstate = dev_pm_opp_get_required_pstate(opp, 0);
1903 dev_pm_opp_put(opp);
1904
1905 /*
1906 * The minimum core voltage depends on the pixel clock rate (which
1907 * depends on internal clock divider of the CRTC) and not on the
1908 * rate of the display controller clock. This is why we're not using
1909 * dev_pm_opp_set_rate() API and instead controlling the power domain
1910 * directly.
1911 */
1912 err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
1913 if (err)
1914 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
1915 pstate, err);
1916 }
1917
tegra_dc_set_clock_rate(struct tegra_dc * dc,struct tegra_dc_state * state)1918 static void tegra_dc_set_clock_rate(struct tegra_dc *dc,
1919 struct tegra_dc_state *state)
1920 {
1921 int err;
1922
1923 err = clk_set_parent(dc->clk, state->clk);
1924 if (err < 0)
1925 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1926
1927 /*
1928 * Outputs may not want to change the parent clock rate. This is only
1929 * relevant to Tegra20 where only a single display PLL is available.
1930 * Since that PLL would typically be used for HDMI, an internal LVDS
1931 * panel would need to be driven by some other clock such as PLL_P
1932 * which is shared with other peripherals. Changing the clock rate
1933 * should therefore be avoided.
1934 */
1935 if (state->pclk > 0) {
1936 err = clk_set_rate(state->clk, state->pclk);
1937 if (err < 0)
1938 dev_err(dc->dev,
1939 "failed to set clock rate to %lu Hz\n",
1940 state->pclk);
1941
1942 err = clk_set_rate(dc->clk, state->pclk);
1943 if (err < 0)
1944 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1945 dc->clk, state->pclk, err);
1946 }
1947
1948 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1949 state->div);
1950 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1951
1952 tegra_dc_update_voltage_state(dc, state);
1953 }
1954
tegra_dc_stop(struct tegra_dc * dc)1955 static void tegra_dc_stop(struct tegra_dc *dc)
1956 {
1957 u32 value;
1958
1959 /* stop the display controller */
1960 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1961 value &= ~DISP_CTRL_MODE_MASK;
1962 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1963
1964 tegra_dc_commit(dc);
1965 }
1966
tegra_dc_idle(struct tegra_dc * dc)1967 static bool tegra_dc_idle(struct tegra_dc *dc)
1968 {
1969 u32 value;
1970
1971 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1972
1973 return (value & DISP_CTRL_MODE_MASK) == 0;
1974 }
1975
tegra_dc_wait_idle(struct tegra_dc * dc,unsigned long timeout)1976 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1977 {
1978 timeout = jiffies + msecs_to_jiffies(timeout);
1979
1980 while (time_before(jiffies, timeout)) {
1981 if (tegra_dc_idle(dc))
1982 return 0;
1983
1984 usleep_range(1000, 2000);
1985 }
1986
1987 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1988 return -ETIMEDOUT;
1989 }
1990
1991 static void
tegra_crtc_update_memory_bandwidth(struct drm_crtc * crtc,struct drm_atomic_state * state,bool prepare_bandwidth_transition)1992 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
1993 struct drm_atomic_state *state,
1994 bool prepare_bandwidth_transition)
1995 {
1996 const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
1997 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
1998 const struct drm_plane_state *old_plane_state;
1999 const struct drm_crtc_state *old_crtc_state;
2000 struct tegra_dc_window window, old_window;
2001 struct tegra_dc *dc = to_tegra_dc(crtc);
2002 struct tegra_plane *tegra;
2003 struct drm_plane *plane;
2004
2005 if (dc->soc->has_nvdisplay)
2006 return;
2007
2008 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
2009
2010 if (!crtc->state->active) {
2011 if (!old_crtc_state->active)
2012 return;
2013
2014 /*
2015 * When CRTC is disabled on DPMS, the state of attached planes
2016 * is kept unchanged. Hence we need to enforce removal of the
2017 * bandwidths from the ICC paths.
2018 */
2019 drm_atomic_crtc_for_each_plane(plane, crtc) {
2020 tegra = to_tegra_plane(plane);
2021
2022 icc_set_bw(tegra->icc_mem, 0, 0);
2023 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2024 }
2025
2026 return;
2027 }
2028
2029 for_each_old_plane_in_state(old_crtc_state->state, plane,
2030 old_plane_state, i) {
2031 old_tegra_state = to_const_tegra_plane_state(old_plane_state);
2032 new_tegra_state = to_const_tegra_plane_state(plane->state);
2033 tegra = to_tegra_plane(plane);
2034
2035 /*
2036 * We're iterating over the global atomic state and it contains
2037 * planes from another CRTC, hence we need to filter out the
2038 * planes unrelated to this CRTC.
2039 */
2040 if (tegra->dc != dc)
2041 continue;
2042
2043 new_avg_bw = new_tegra_state->avg_memory_bandwidth;
2044 old_avg_bw = old_tegra_state->avg_memory_bandwidth;
2045
2046 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
2047 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
2048
2049 /*
2050 * See the comment related to !crtc->state->active above,
2051 * which explains why bandwidths need to be updated when
2052 * CRTC is turning ON.
2053 */
2054 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
2055 old_crtc_state->active)
2056 continue;
2057
2058 window.src.h = drm_rect_height(&plane->state->src) >> 16;
2059 window.dst.h = drm_rect_height(&plane->state->dst);
2060
2061 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
2062 old_window.dst.h = drm_rect_height(&old_plane_state->dst);
2063
2064 /*
2065 * During the preparation phase (atomic_begin), the memory
2066 * freq should go high before the DC changes are committed
2067 * if bandwidth requirement goes up, otherwise memory freq
2068 * should to stay high if BW requirement goes down. The
2069 * opposite applies to the completion phase (post_commit).
2070 */
2071 if (prepare_bandwidth_transition) {
2072 new_avg_bw = max(old_avg_bw, new_avg_bw);
2073 new_peak_bw = max(old_peak_bw, new_peak_bw);
2074
2075 if (tegra_plane_use_vertical_filtering(tegra, &old_window))
2076 window = old_window;
2077 }
2078
2079 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
2080
2081 if (tegra_plane_use_vertical_filtering(tegra, &window))
2082 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
2083 else
2084 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2085 }
2086 }
2087
tegra_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)2088 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
2089 struct drm_atomic_state *state)
2090 {
2091 struct tegra_dc *dc = to_tegra_dc(crtc);
2092 u32 value;
2093 int err;
2094
2095 if (!tegra_dc_idle(dc)) {
2096 tegra_dc_stop(dc);
2097
2098 /*
2099 * Ignore the return value, there isn't anything useful to do
2100 * in case this fails.
2101 */
2102 tegra_dc_wait_idle(dc, 100);
2103 }
2104
2105 /*
2106 * This should really be part of the RGB encoder driver, but clearing
2107 * these bits has the side-effect of stopping the display controller.
2108 * When that happens no VBLANK interrupts will be raised. At the same
2109 * time the encoder is disabled before the display controller, so the
2110 * above code is always going to timeout waiting for the controller
2111 * to go idle.
2112 *
2113 * Given the close coupling between the RGB encoder and the display
2114 * controller doing it here is still kind of okay. None of the other
2115 * encoder drivers require these bits to be cleared.
2116 *
2117 * XXX: Perhaps given that the display controller is switched off at
2118 * this point anyway maybe clearing these bits isn't even useful for
2119 * the RGB encoder?
2120 */
2121 if (dc->rgb) {
2122 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2123 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2124 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
2125 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2126 }
2127
2128 tegra_dc_stats_reset(&dc->stats);
2129 drm_crtc_vblank_off(crtc);
2130
2131 spin_lock_irq(&crtc->dev->event_lock);
2132
2133 if (crtc->state->event) {
2134 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2135 crtc->state->event = NULL;
2136 }
2137
2138 spin_unlock_irq(&crtc->dev->event_lock);
2139
2140 err = host1x_client_suspend(&dc->client);
2141 if (err < 0)
2142 dev_err(dc->dev, "failed to suspend: %d\n", err);
2143
2144 if (dc->has_opp_table) {
2145 err = dev_pm_genpd_set_performance_state(dc->dev, 0);
2146 if (err)
2147 dev_err(dc->dev,
2148 "failed to clear power domain state: %d\n", err);
2149 }
2150 }
2151
tegra_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)2152 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
2153 struct drm_atomic_state *state)
2154 {
2155 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2156 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
2157 struct tegra_dc *dc = to_tegra_dc(crtc);
2158 u32 value;
2159 int err;
2160
2161 /* apply PLL changes */
2162 tegra_dc_set_clock_rate(dc, crtc_state);
2163
2164 err = host1x_client_resume(&dc->client);
2165 if (err < 0) {
2166 dev_err(dc->dev, "failed to resume: %d\n", err);
2167 return;
2168 }
2169
2170 /* initialize display controller */
2171 if (dc->syncpt) {
2172 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
2173
2174 if (dc->soc->has_nvdisplay)
2175 enable = 1 << 31;
2176 else
2177 enable = 1 << 8;
2178
2179 value = SYNCPT_CNTRL_NO_STALL;
2180 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2181
2182 value = enable | syncpt;
2183 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
2184 }
2185
2186 if (dc->soc->has_nvdisplay) {
2187 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2188 DSC_OBUF_UF_INT;
2189 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2190
2191 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2192 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
2193 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
2194 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
2195 VBLANK_INT | FRAME_END_INT;
2196 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2197
2198 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
2199 FRAME_END_INT;
2200 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2201
2202 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
2203 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2204
2205 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
2206 } else {
2207 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2208 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2209 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2210
2211 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2212 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2213 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2214
2215 /* initialize timer */
2216 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
2217 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
2218 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
2219
2220 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
2221 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
2222 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
2223
2224 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2225 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2226 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2227
2228 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2229 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2230 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2231 }
2232
2233 if (dc->soc->supports_background_color)
2234 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
2235 else
2236 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
2237
2238 /* apply pixel clock changes */
2239 if (!dc->soc->has_nvdisplay) {
2240 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;
2241 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
2242 }
2243
2244 /* program display mode */
2245 tegra_dc_set_timings(dc, mode);
2246
2247 /* interlacing isn't supported yet, so disable it */
2248 if (dc->soc->supports_interlacing) {
2249 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
2250 value &= ~INTERLACE_ENABLE;
2251 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
2252 }
2253
2254 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
2255 value &= ~DISP_CTRL_MODE_MASK;
2256 value |= DISP_CTRL_MODE_C_DISPLAY;
2257 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
2258
2259 if (!dc->soc->has_nvdisplay) {
2260 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2261 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2262 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
2263 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2264 }
2265
2266 /* enable underflow reporting and display red for missing pixels */
2267 if (dc->soc->has_nvdisplay) {
2268 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
2269 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
2270 }
2271
2272 if (dc->rgb) {
2273 /* XXX: parameterize? */
2274 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
2275 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
2276 }
2277
2278 tegra_dc_commit(dc);
2279
2280 drm_crtc_vblank_on(crtc);
2281 }
2282
tegra_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)2283 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
2284 struct drm_atomic_state *state)
2285 {
2286 unsigned long flags;
2287
2288 tegra_crtc_update_memory_bandwidth(crtc, state, true);
2289
2290 if (crtc->state->event) {
2291 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2292
2293 if (drm_crtc_vblank_get(crtc) != 0)
2294 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2295 else
2296 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
2297
2298 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2299
2300 crtc->state->event = NULL;
2301 }
2302 }
2303
tegra_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)2304 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2305 struct drm_atomic_state *state)
2306 {
2307 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2308 crtc);
2309 struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2310 struct tegra_dc *dc = to_tegra_dc(crtc);
2311 u32 value;
2312
2313 value = dc_state->planes << 8 | GENERAL_UPDATE;
2314 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2315 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2316
2317 value = dc_state->planes | GENERAL_ACT_REQ;
2318 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2319 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2320 }
2321
tegra_plane_is_cursor(const struct drm_plane_state * state)2322 static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
2323 {
2324 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
2325 const struct drm_format_info *fmt = state->fb->format;
2326 unsigned int src_w = drm_rect_width(&state->src) >> 16;
2327 unsigned int dst_w = drm_rect_width(&state->dst);
2328
2329 if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2330 return false;
2331
2332 if (soc->supports_cursor)
2333 return true;
2334
2335 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
2336 return false;
2337
2338 return true;
2339 }
2340
2341 static unsigned long
tegra_plane_overlap_mask(struct drm_crtc_state * state,const struct drm_plane_state * plane_state)2342 tegra_plane_overlap_mask(struct drm_crtc_state *state,
2343 const struct drm_plane_state *plane_state)
2344 {
2345 const struct drm_plane_state *other_state;
2346 const struct tegra_plane *tegra;
2347 unsigned long overlap_mask = 0;
2348 struct drm_plane *plane;
2349 struct drm_rect rect;
2350
2351 if (!plane_state->visible || !plane_state->fb)
2352 return 0;
2353
2354 /*
2355 * Data-prefetch FIFO will easily help to overcome temporal memory
2356 * pressure if other plane overlaps with the cursor plane.
2357 */
2358 if (tegra_plane_is_cursor(plane_state))
2359 return 0;
2360
2361 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2362 rect = plane_state->dst;
2363
2364 tegra = to_tegra_plane(other_state->plane);
2365
2366 if (!other_state->visible || !other_state->fb)
2367 continue;
2368
2369 /*
2370 * Ignore cursor plane overlaps because it's not practical to
2371 * assume that it contributes to the bandwidth in overlapping
2372 * area if window width is small.
2373 */
2374 if (tegra_plane_is_cursor(other_state))
2375 continue;
2376
2377 if (drm_rect_intersect(&rect, &other_state->dst))
2378 overlap_mask |= BIT(tegra->index);
2379 }
2380
2381 return overlap_mask;
2382 }
2383
tegra_crtc_calculate_memory_bandwidth(struct drm_crtc * crtc,struct drm_atomic_state * state)2384 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
2385 struct drm_atomic_state *state)
2386 {
2387 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
2388 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
2389 bool all_planes_overlap_simultaneously = true;
2390 const struct tegra_plane_state *tegra_state;
2391 const struct drm_plane_state *plane_state;
2392 struct tegra_dc *dc = to_tegra_dc(crtc);
2393 struct drm_crtc_state *new_state;
2394 struct tegra_plane *tegra;
2395 struct drm_plane *plane;
2396
2397 /*
2398 * The nv-display uses shared planes. The algorithm below assumes
2399 * maximum 3 planes per-CRTC, this assumption isn't applicable to
2400 * the nv-display. Note that T124 support has additional windows,
2401 * but currently they aren't supported by the driver.
2402 */
2403 if (dc->soc->has_nvdisplay)
2404 return 0;
2405
2406 new_state = drm_atomic_get_new_crtc_state(state, crtc);
2407
2408 /*
2409 * For overlapping planes pixel's data is fetched for each plane at
2410 * the same time, hence bandwidths are accumulated in this case.
2411 * This needs to be taken into account for calculating total bandwidth
2412 * consumed by all planes.
2413 *
2414 * Here we get the overlapping state of each plane, which is a
2415 * bitmask of plane indices telling with what planes there is an
2416 * overlap. Note that bitmask[plane] includes BIT(plane) in order
2417 * to make further code nicer and simpler.
2418 */
2419 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2420 tegra_state = to_const_tegra_plane_state(plane_state);
2421 tegra = to_tegra_plane(plane);
2422
2423 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
2424 return -EINVAL;
2425
2426 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
2427 mask = tegra_plane_overlap_mask(new_state, plane_state);
2428 overlap_mask[tegra->index] = mask;
2429
2430 if (hweight_long(mask) != 3)
2431 all_planes_overlap_simultaneously = false;
2432 }
2433
2434 /*
2435 * Then we calculate maximum bandwidth of each plane state.
2436 * The bandwidth includes the plane BW + BW of the "simultaneously"
2437 * overlapping planes, where "simultaneously" means areas where DC
2438 * fetches from the planes simultaneously during of scan-out process.
2439 *
2440 * For example, if plane A overlaps with planes B and C, but B and C
2441 * don't overlap, then the peak bandwidth will be either in area where
2442 * A-and-B or A-and-C planes overlap.
2443 *
2444 * The plane_peak_bw[] contains peak memory bandwidth values of
2445 * each plane, this information is needed by interconnect provider
2446 * in order to set up latency allowance based on the peak BW, see
2447 * tegra_crtc_update_memory_bandwidth().
2448 */
2449 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2450 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
2451
2452 /*
2453 * Note that plane's atomic check doesn't touch the
2454 * total_peak_memory_bandwidth of enabled plane, hence the
2455 * current state contains the old bandwidth state from the
2456 * previous CRTC commit.
2457 */
2458 tegra_state = to_const_tegra_plane_state(plane_state);
2459 tegra = to_tegra_plane(plane);
2460
2461 for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
2462 if (i == tegra->index)
2463 continue;
2464
2465 if (all_planes_overlap_simultaneously)
2466 overlap_bw += plane_peak_bw[i];
2467 else
2468 overlap_bw = max(overlap_bw, plane_peak_bw[i]);
2469 }
2470
2471 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
2472 old_peak_bw = tegra_state->total_peak_memory_bandwidth;
2473
2474 /*
2475 * If plane's peak bandwidth changed (for example plane isn't
2476 * overlapped anymore) and plane isn't in the atomic state,
2477 * then add plane to the state in order to have the bandwidth
2478 * updated.
2479 */
2480 if (old_peak_bw != new_peak_bw) {
2481 struct tegra_plane_state *new_tegra_state;
2482 struct drm_plane_state *new_plane_state;
2483
2484 new_plane_state = drm_atomic_get_plane_state(state, plane);
2485 if (IS_ERR(new_plane_state))
2486 return PTR_ERR(new_plane_state);
2487
2488 new_tegra_state = to_tegra_plane_state(new_plane_state);
2489 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
2490 }
2491 }
2492
2493 return 0;
2494 }
2495
tegra_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)2496 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
2497 struct drm_atomic_state *state)
2498 {
2499 int err;
2500
2501 err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
2502 if (err)
2503 return err;
2504
2505 return 0;
2506 }
2507
tegra_crtc_atomic_post_commit(struct drm_crtc * crtc,struct drm_atomic_state * state)2508 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
2509 struct drm_atomic_state *state)
2510 {
2511 /*
2512 * Display bandwidth is allowed to go down only once hardware state
2513 * is known to be armed, i.e. state was committed and VBLANK event
2514 * received.
2515 */
2516 tegra_crtc_update_memory_bandwidth(crtc, state, false);
2517 }
2518
2519 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2520 .atomic_check = tegra_crtc_atomic_check,
2521 .atomic_begin = tegra_crtc_atomic_begin,
2522 .atomic_flush = tegra_crtc_atomic_flush,
2523 .atomic_enable = tegra_crtc_atomic_enable,
2524 .atomic_disable = tegra_crtc_atomic_disable,
2525 };
2526
tegra_dc_irq(int irq,void * data)2527 static irqreturn_t tegra_dc_irq(int irq, void *data)
2528 {
2529 struct tegra_dc *dc = data;
2530 unsigned long status;
2531
2532 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2533 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2534
2535 if (status & FRAME_END_INT) {
2536 /*
2537 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2538 */
2539 dc->stats.frames_total++;
2540 dc->stats.frames++;
2541 }
2542
2543 if (status & VBLANK_INT) {
2544 /*
2545 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2546 */
2547 drm_crtc_handle_vblank(&dc->base);
2548 dc->stats.vblank_total++;
2549 dc->stats.vblank++;
2550 }
2551
2552 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2553 /*
2554 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2555 */
2556 dc->stats.underflow_total++;
2557 dc->stats.underflow++;
2558 }
2559
2560 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2561 /*
2562 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2563 */
2564 dc->stats.overflow_total++;
2565 dc->stats.overflow++;
2566 }
2567
2568 if (status & HEAD_UF_INT) {
2569 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2570 dc->stats.underflow_total++;
2571 dc->stats.underflow++;
2572 }
2573
2574 return IRQ_HANDLED;
2575 }
2576
tegra_dc_has_window_groups(struct tegra_dc * dc)2577 static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2578 {
2579 unsigned int i;
2580
2581 if (!dc->soc->wgrps)
2582 return true;
2583
2584 for (i = 0; i < dc->soc->num_wgrps; i++) {
2585 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2586
2587 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2588 return true;
2589 }
2590
2591 return false;
2592 }
2593
tegra_dc_early_init(struct host1x_client * client)2594 static int tegra_dc_early_init(struct host1x_client *client)
2595 {
2596 struct drm_device *drm = dev_get_drvdata(client->host);
2597 struct tegra_drm *tegra = drm->dev_private;
2598
2599 tegra->num_crtcs++;
2600
2601 return 0;
2602 }
2603
tegra_dc_init(struct host1x_client * client)2604 static int tegra_dc_init(struct host1x_client *client)
2605 {
2606 struct drm_device *drm = dev_get_drvdata(client->host);
2607 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2608 struct tegra_dc *dc = host1x_client_to_dc(client);
2609 struct tegra_drm *tegra = drm->dev_private;
2610 struct drm_plane *primary = NULL;
2611 struct drm_plane *cursor = NULL;
2612 int err;
2613
2614 /*
2615 * DC has been reset by now, so VBLANK syncpoint can be released
2616 * for general use.
2617 */
2618 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2619
2620 /*
2621 * XXX do not register DCs with no window groups because we cannot
2622 * assign a primary plane to them, which in turn will cause KMS to
2623 * crash.
2624 */
2625 if (!tegra_dc_has_window_groups(dc))
2626 return 0;
2627
2628 /*
2629 * Set the display hub as the host1x client parent for the display
2630 * controller. This is needed for the runtime reference counting that
2631 * ensures the display hub is always powered when any of the display
2632 * controllers are.
2633 */
2634 if (dc->soc->has_nvdisplay)
2635 client->parent = &tegra->hub->client;
2636
2637 dc->syncpt = host1x_syncpt_request(client, flags);
2638 if (!dc->syncpt)
2639 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2640
2641 err = host1x_client_iommu_attach(client);
2642 if (err < 0 && err != -ENODEV) {
2643 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2644 return err;
2645 }
2646
2647 if (dc->soc->wgrps)
2648 primary = tegra_dc_add_shared_planes(drm, dc);
2649 else
2650 primary = tegra_dc_add_planes(drm, dc);
2651
2652 if (IS_ERR(primary)) {
2653 err = PTR_ERR(primary);
2654 goto cleanup;
2655 }
2656
2657 if (dc->soc->supports_cursor) {
2658 cursor = tegra_dc_cursor_plane_create(drm, dc);
2659 if (IS_ERR(cursor)) {
2660 err = PTR_ERR(cursor);
2661 goto cleanup;
2662 }
2663 } else {
2664 /* dedicate one overlay to mouse cursor */
2665 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2666 if (IS_ERR(cursor)) {
2667 err = PTR_ERR(cursor);
2668 goto cleanup;
2669 }
2670 }
2671
2672 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2673 &tegra_crtc_funcs, NULL);
2674 if (err < 0)
2675 goto cleanup;
2676
2677 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2678
2679 /*
2680 * Keep track of the minimum pitch alignment across all display
2681 * controllers.
2682 */
2683 if (dc->soc->pitch_align > tegra->pitch_align)
2684 tegra->pitch_align = dc->soc->pitch_align;
2685
2686 /* track maximum resolution */
2687 if (dc->soc->has_nvdisplay)
2688 drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2689 else
2690 drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2691
2692 err = tegra_dc_rgb_init(drm, dc);
2693 if (err < 0 && err != -ENODEV) {
2694 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2695 goto cleanup;
2696 }
2697
2698 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2699 dev_name(dc->dev), dc);
2700 if (err < 0) {
2701 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2702 err);
2703 goto cleanup;
2704 }
2705
2706 /*
2707 * Inherit the DMA parameters (such as maximum segment size) from the
2708 * parent host1x device.
2709 */
2710 client->dev->dma_parms = client->host->dma_parms;
2711
2712 return 0;
2713
2714 cleanup:
2715 if (!IS_ERR_OR_NULL(cursor))
2716 drm_plane_cleanup(cursor);
2717
2718 if (!IS_ERR(primary))
2719 drm_plane_cleanup(primary);
2720
2721 host1x_client_iommu_detach(client);
2722 host1x_syncpt_put(dc->syncpt);
2723
2724 return err;
2725 }
2726
tegra_dc_exit(struct host1x_client * client)2727 static int tegra_dc_exit(struct host1x_client *client)
2728 {
2729 struct tegra_dc *dc = host1x_client_to_dc(client);
2730 int err;
2731
2732 if (!tegra_dc_has_window_groups(dc))
2733 return 0;
2734
2735 /* avoid a dangling pointer just in case this disappears */
2736 client->dev->dma_parms = NULL;
2737
2738 devm_free_irq(dc->dev, dc->irq, dc);
2739
2740 err = tegra_dc_rgb_exit(dc);
2741 if (err) {
2742 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2743 return err;
2744 }
2745
2746 host1x_client_iommu_detach(client);
2747 host1x_syncpt_put(dc->syncpt);
2748
2749 return 0;
2750 }
2751
tegra_dc_late_exit(struct host1x_client * client)2752 static int tegra_dc_late_exit(struct host1x_client *client)
2753 {
2754 struct drm_device *drm = dev_get_drvdata(client->host);
2755 struct tegra_drm *tegra = drm->dev_private;
2756
2757 tegra->num_crtcs--;
2758
2759 return 0;
2760 }
2761
tegra_dc_runtime_suspend(struct host1x_client * client)2762 static int tegra_dc_runtime_suspend(struct host1x_client *client)
2763 {
2764 struct tegra_dc *dc = host1x_client_to_dc(client);
2765 struct device *dev = client->dev;
2766 int err;
2767
2768 err = reset_control_assert(dc->rst);
2769 if (err < 0) {
2770 dev_err(dev, "failed to assert reset: %d\n", err);
2771 return err;
2772 }
2773
2774 if (dc->soc->has_powergate)
2775 tegra_powergate_power_off(dc->powergate);
2776
2777 clk_disable_unprepare(dc->clk);
2778 pm_runtime_put_sync(dev);
2779
2780 return 0;
2781 }
2782
tegra_dc_runtime_resume(struct host1x_client * client)2783 static int tegra_dc_runtime_resume(struct host1x_client *client)
2784 {
2785 struct tegra_dc *dc = host1x_client_to_dc(client);
2786 struct device *dev = client->dev;
2787 int err;
2788
2789 err = pm_runtime_resume_and_get(dev);
2790 if (err < 0) {
2791 dev_err(dev, "failed to get runtime PM: %d\n", err);
2792 return err;
2793 }
2794
2795 if (dc->soc->has_powergate) {
2796 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2797 dc->rst);
2798 if (err < 0) {
2799 dev_err(dev, "failed to power partition: %d\n", err);
2800 goto put_rpm;
2801 }
2802 } else {
2803 err = clk_prepare_enable(dc->clk);
2804 if (err < 0) {
2805 dev_err(dev, "failed to enable clock: %d\n", err);
2806 goto put_rpm;
2807 }
2808
2809 err = reset_control_deassert(dc->rst);
2810 if (err < 0) {
2811 dev_err(dev, "failed to deassert reset: %d\n", err);
2812 goto disable_clk;
2813 }
2814 }
2815
2816 return 0;
2817
2818 disable_clk:
2819 clk_disable_unprepare(dc->clk);
2820 put_rpm:
2821 pm_runtime_put_sync(dev);
2822 return err;
2823 }
2824
2825 static const struct host1x_client_ops dc_client_ops = {
2826 .early_init = tegra_dc_early_init,
2827 .init = tegra_dc_init,
2828 .exit = tegra_dc_exit,
2829 .late_exit = tegra_dc_late_exit,
2830 .suspend = tegra_dc_runtime_suspend,
2831 .resume = tegra_dc_runtime_resume,
2832 };
2833
2834 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2835 .supports_background_color = false,
2836 .supports_interlacing = false,
2837 .supports_cursor = false,
2838 .supports_block_linear = false,
2839 .supports_sector_layout = false,
2840 .has_legacy_blending = true,
2841 .pitch_align = 8,
2842 .has_powergate = false,
2843 .coupled_pm = true,
2844 .has_nvdisplay = false,
2845 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2846 .primary_formats = tegra20_primary_formats,
2847 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2848 .overlay_formats = tegra20_overlay_formats,
2849 .modifiers = tegra20_modifiers,
2850 .has_win_a_without_filters = true,
2851 .has_win_b_vfilter_mem_client = true,
2852 .has_win_c_without_vert_filter = true,
2853 .plane_tiled_memory_bandwidth_x2 = false,
2854 .has_pll_d2_out0 = false,
2855 };
2856
2857 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2858 .supports_background_color = false,
2859 .supports_interlacing = false,
2860 .supports_cursor = false,
2861 .supports_block_linear = false,
2862 .supports_sector_layout = false,
2863 .has_legacy_blending = true,
2864 .pitch_align = 8,
2865 .has_powergate = false,
2866 .coupled_pm = false,
2867 .has_nvdisplay = false,
2868 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2869 .primary_formats = tegra20_primary_formats,
2870 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2871 .overlay_formats = tegra20_overlay_formats,
2872 .modifiers = tegra20_modifiers,
2873 .has_win_a_without_filters = false,
2874 .has_win_b_vfilter_mem_client = true,
2875 .has_win_c_without_vert_filter = false,
2876 .plane_tiled_memory_bandwidth_x2 = true,
2877 .has_pll_d2_out0 = true,
2878 };
2879
2880 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2881 .supports_background_color = false,
2882 .supports_interlacing = false,
2883 .supports_cursor = false,
2884 .supports_block_linear = false,
2885 .supports_sector_layout = false,
2886 .has_legacy_blending = true,
2887 .pitch_align = 64,
2888 .has_powergate = true,
2889 .coupled_pm = false,
2890 .has_nvdisplay = false,
2891 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2892 .primary_formats = tegra114_primary_formats,
2893 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2894 .overlay_formats = tegra114_overlay_formats,
2895 .modifiers = tegra20_modifiers,
2896 .has_win_a_without_filters = false,
2897 .has_win_b_vfilter_mem_client = false,
2898 .has_win_c_without_vert_filter = false,
2899 .plane_tiled_memory_bandwidth_x2 = true,
2900 .has_pll_d2_out0 = true,
2901 };
2902
2903 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2904 .supports_background_color = true,
2905 .supports_interlacing = true,
2906 .supports_cursor = true,
2907 .supports_block_linear = true,
2908 .supports_sector_layout = false,
2909 .has_legacy_blending = false,
2910 .pitch_align = 64,
2911 .has_powergate = true,
2912 .coupled_pm = false,
2913 .has_nvdisplay = false,
2914 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2915 .primary_formats = tegra124_primary_formats,
2916 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2917 .overlay_formats = tegra124_overlay_formats,
2918 .modifiers = tegra124_modifiers,
2919 .has_win_a_without_filters = false,
2920 .has_win_b_vfilter_mem_client = false,
2921 .has_win_c_without_vert_filter = false,
2922 .plane_tiled_memory_bandwidth_x2 = false,
2923 .has_pll_d2_out0 = true,
2924 };
2925
2926 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2927 .supports_background_color = true,
2928 .supports_interlacing = true,
2929 .supports_cursor = true,
2930 .supports_block_linear = true,
2931 .supports_sector_layout = false,
2932 .has_legacy_blending = false,
2933 .pitch_align = 64,
2934 .has_powergate = true,
2935 .coupled_pm = false,
2936 .has_nvdisplay = false,
2937 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2938 .primary_formats = tegra114_primary_formats,
2939 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2940 .overlay_formats = tegra114_overlay_formats,
2941 .modifiers = tegra124_modifiers,
2942 .has_win_a_without_filters = false,
2943 .has_win_b_vfilter_mem_client = false,
2944 .has_win_c_without_vert_filter = false,
2945 .plane_tiled_memory_bandwidth_x2 = false,
2946 .has_pll_d2_out0 = true,
2947 };
2948
2949 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2950 {
2951 .index = 0,
2952 .dc = 0,
2953 .windows = (const unsigned int[]) { 0 },
2954 .num_windows = 1,
2955 }, {
2956 .index = 1,
2957 .dc = 1,
2958 .windows = (const unsigned int[]) { 1 },
2959 .num_windows = 1,
2960 }, {
2961 .index = 2,
2962 .dc = 1,
2963 .windows = (const unsigned int[]) { 2 },
2964 .num_windows = 1,
2965 }, {
2966 .index = 3,
2967 .dc = 2,
2968 .windows = (const unsigned int[]) { 3 },
2969 .num_windows = 1,
2970 }, {
2971 .index = 4,
2972 .dc = 2,
2973 .windows = (const unsigned int[]) { 4 },
2974 .num_windows = 1,
2975 }, {
2976 .index = 5,
2977 .dc = 2,
2978 .windows = (const unsigned int[]) { 5 },
2979 .num_windows = 1,
2980 },
2981 };
2982
2983 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2984 .supports_background_color = true,
2985 .supports_interlacing = true,
2986 .supports_cursor = true,
2987 .supports_block_linear = true,
2988 .supports_sector_layout = false,
2989 .has_legacy_blending = false,
2990 .pitch_align = 64,
2991 .has_powergate = false,
2992 .coupled_pm = false,
2993 .has_nvdisplay = true,
2994 .wgrps = tegra186_dc_wgrps,
2995 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2996 .plane_tiled_memory_bandwidth_x2 = false,
2997 .has_pll_d2_out0 = false,
2998 };
2999
3000 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
3001 {
3002 .index = 0,
3003 .dc = 0,
3004 .windows = (const unsigned int[]) { 0 },
3005 .num_windows = 1,
3006 }, {
3007 .index = 1,
3008 .dc = 1,
3009 .windows = (const unsigned int[]) { 1 },
3010 .num_windows = 1,
3011 }, {
3012 .index = 2,
3013 .dc = 1,
3014 .windows = (const unsigned int[]) { 2 },
3015 .num_windows = 1,
3016 }, {
3017 .index = 3,
3018 .dc = 2,
3019 .windows = (const unsigned int[]) { 3 },
3020 .num_windows = 1,
3021 }, {
3022 .index = 4,
3023 .dc = 2,
3024 .windows = (const unsigned int[]) { 4 },
3025 .num_windows = 1,
3026 }, {
3027 .index = 5,
3028 .dc = 2,
3029 .windows = (const unsigned int[]) { 5 },
3030 .num_windows = 1,
3031 },
3032 };
3033
3034 static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
3035 .supports_background_color = true,
3036 .supports_interlacing = true,
3037 .supports_cursor = true,
3038 .supports_block_linear = true,
3039 .supports_sector_layout = true,
3040 .has_legacy_blending = false,
3041 .pitch_align = 64,
3042 .has_powergate = false,
3043 .coupled_pm = false,
3044 .has_nvdisplay = true,
3045 .wgrps = tegra194_dc_wgrps,
3046 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
3047 .plane_tiled_memory_bandwidth_x2 = false,
3048 .has_pll_d2_out0 = false,
3049 };
3050
3051 static const struct of_device_id tegra_dc_of_match[] = {
3052 {
3053 .compatible = "nvidia,tegra194-dc",
3054 .data = &tegra194_dc_soc_info,
3055 }, {
3056 .compatible = "nvidia,tegra186-dc",
3057 .data = &tegra186_dc_soc_info,
3058 }, {
3059 .compatible = "nvidia,tegra210-dc",
3060 .data = &tegra210_dc_soc_info,
3061 }, {
3062 .compatible = "nvidia,tegra124-dc",
3063 .data = &tegra124_dc_soc_info,
3064 }, {
3065 .compatible = "nvidia,tegra114-dc",
3066 .data = &tegra114_dc_soc_info,
3067 }, {
3068 .compatible = "nvidia,tegra30-dc",
3069 .data = &tegra30_dc_soc_info,
3070 }, {
3071 .compatible = "nvidia,tegra20-dc",
3072 .data = &tegra20_dc_soc_info,
3073 }, {
3074 /* sentinel */
3075 }
3076 };
3077 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
3078
tegra_dc_parse_dt(struct tegra_dc * dc)3079 static int tegra_dc_parse_dt(struct tegra_dc *dc)
3080 {
3081 struct device_node *np;
3082 u32 value = 0;
3083 int err;
3084
3085 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
3086 if (err < 0) {
3087 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
3088
3089 /*
3090 * If the nvidia,head property isn't present, try to find the
3091 * correct head number by looking up the position of this
3092 * display controller's node within the device tree. Assuming
3093 * that the nodes are ordered properly in the DTS file and
3094 * that the translation into a flattened device tree blob
3095 * preserves that ordering this will actually yield the right
3096 * head number.
3097 *
3098 * If those assumptions don't hold, this will still work for
3099 * cases where only a single display controller is used.
3100 */
3101 for_each_matching_node(np, tegra_dc_of_match) {
3102 if (np == dc->dev->of_node) {
3103 of_node_put(np);
3104 break;
3105 }
3106
3107 value++;
3108 }
3109 }
3110
3111 dc->pipe = value;
3112
3113 return 0;
3114 }
3115
tegra_dc_match_by_pipe(struct device * dev,const void * data)3116 static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
3117 {
3118 struct tegra_dc *dc = dev_get_drvdata(dev);
3119 unsigned int pipe = (unsigned long)(void *)data;
3120
3121 return dc->pipe == pipe;
3122 }
3123
tegra_dc_couple(struct tegra_dc * dc)3124 static int tegra_dc_couple(struct tegra_dc *dc)
3125 {
3126 /*
3127 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
3128 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
3129 * POWER_CONTROL registers during CRTC enabling.
3130 */
3131 if (dc->soc->coupled_pm && dc->pipe == 1) {
3132 struct device *companion;
3133 struct tegra_dc *parent;
3134
3135 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
3136 tegra_dc_match_by_pipe);
3137 if (!companion)
3138 return -EPROBE_DEFER;
3139
3140 parent = dev_get_drvdata(companion);
3141 dc->client.parent = &parent->client;
3142
3143 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
3144 }
3145
3146 return 0;
3147 }
3148
tegra_dc_init_opp_table(struct tegra_dc * dc)3149 static int tegra_dc_init_opp_table(struct tegra_dc *dc)
3150 {
3151 struct tegra_core_opp_params opp_params = {};
3152 int err;
3153
3154 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
3155 if (err && err != -ENODEV)
3156 return err;
3157
3158 if (err)
3159 dc->has_opp_table = false;
3160 else
3161 dc->has_opp_table = true;
3162
3163 return 0;
3164 }
3165
tegra_dc_probe(struct platform_device * pdev)3166 static int tegra_dc_probe(struct platform_device *pdev)
3167 {
3168 u64 dma_mask = dma_get_mask(pdev->dev.parent);
3169 struct tegra_dc *dc;
3170 int err;
3171
3172 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
3173 if (err < 0) {
3174 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
3175 return err;
3176 }
3177
3178 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
3179 if (!dc)
3180 return -ENOMEM;
3181
3182 dc->soc = of_device_get_match_data(&pdev->dev);
3183
3184 INIT_LIST_HEAD(&dc->list);
3185 dc->dev = &pdev->dev;
3186
3187 err = tegra_dc_parse_dt(dc);
3188 if (err < 0)
3189 return err;
3190
3191 err = tegra_dc_couple(dc);
3192 if (err < 0)
3193 return err;
3194
3195 dc->clk = devm_clk_get(&pdev->dev, NULL);
3196 if (IS_ERR(dc->clk)) {
3197 dev_err(&pdev->dev, "failed to get clock\n");
3198 return PTR_ERR(dc->clk);
3199 }
3200
3201 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
3202 if (IS_ERR(dc->rst)) {
3203 dev_err(&pdev->dev, "failed to get reset\n");
3204 return PTR_ERR(dc->rst);
3205 }
3206
3207 /* assert reset and disable clock */
3208 err = clk_prepare_enable(dc->clk);
3209 if (err < 0)
3210 return err;
3211
3212 usleep_range(2000, 4000);
3213
3214 err = reset_control_assert(dc->rst);
3215 if (err < 0) {
3216 clk_disable_unprepare(dc->clk);
3217 return err;
3218 }
3219
3220 usleep_range(2000, 4000);
3221
3222 clk_disable_unprepare(dc->clk);
3223
3224 if (dc->soc->has_powergate) {
3225 if (dc->pipe == 0)
3226 dc->powergate = TEGRA_POWERGATE_DIS;
3227 else
3228 dc->powergate = TEGRA_POWERGATE_DISB;
3229
3230 tegra_powergate_power_off(dc->powergate);
3231 }
3232
3233 err = tegra_dc_init_opp_table(dc);
3234 if (err < 0)
3235 return err;
3236
3237 dc->regs = devm_platform_ioremap_resource(pdev, 0);
3238 if (IS_ERR(dc->regs))
3239 return PTR_ERR(dc->regs);
3240
3241 dc->irq = platform_get_irq(pdev, 0);
3242 if (dc->irq < 0)
3243 return -ENXIO;
3244
3245 err = tegra_dc_rgb_probe(dc);
3246 if (err < 0 && err != -ENODEV)
3247 return dev_err_probe(&pdev->dev, err,
3248 "failed to probe RGB output\n");
3249
3250 platform_set_drvdata(pdev, dc);
3251 pm_runtime_enable(&pdev->dev);
3252
3253 INIT_LIST_HEAD(&dc->client.list);
3254 dc->client.ops = &dc_client_ops;
3255 dc->client.dev = &pdev->dev;
3256
3257 err = host1x_client_register(&dc->client);
3258 if (err < 0) {
3259 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3260 err);
3261 goto disable_pm;
3262 }
3263
3264 return 0;
3265
3266 disable_pm:
3267 pm_runtime_disable(&pdev->dev);
3268 tegra_dc_rgb_remove(dc);
3269
3270 return err;
3271 }
3272
tegra_dc_remove(struct platform_device * pdev)3273 static void tegra_dc_remove(struct platform_device *pdev)
3274 {
3275 struct tegra_dc *dc = platform_get_drvdata(pdev);
3276
3277 host1x_client_unregister(&dc->client);
3278
3279 tegra_dc_rgb_remove(dc);
3280
3281 pm_runtime_disable(&pdev->dev);
3282 }
3283
3284 struct platform_driver tegra_dc_driver = {
3285 .driver = {
3286 .name = "tegra-dc",
3287 .of_match_table = tegra_dc_of_match,
3288 },
3289 .probe = tegra_dc_probe,
3290 .remove = tegra_dc_remove,
3291 };
3292