1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip SoC DP (Display Port) interface driver.
4 *
5 * Copyright (C) Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
9 */
10
11 #include <linux/component.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/clk.h>
20
21 #include <video/of_videomode.h>
22 #include <video/videomode.h>
23
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/drm_atomic.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/bridge/analogix_dp.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_panel.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_simple_kms_helper.h>
32
33 #include "rockchip_drm_drv.h"
34
35 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
36
37 #define GRF_REG_FIELD(_reg, _lsb, _msb) { \
38 .reg = _reg, \
39 .lsb = _lsb, \
40 .msb = _msb, \
41 .valid = true, \
42 }
43
44 struct rockchip_grf_reg_field {
45 u32 reg;
46 u32 lsb;
47 u32 msb;
48 bool valid;
49 };
50
51 /**
52 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
53 * @lcdc_sel: grf register field of lcdc_sel
54 * @chip_type: specific chip type
55 * @reg: register base address
56 */
57 struct rockchip_dp_chip_data {
58 const struct rockchip_grf_reg_field lcdc_sel;
59 u32 chip_type;
60 u32 reg;
61 };
62
63 struct rockchip_dp_device {
64 struct drm_device *drm_dev;
65 struct device *dev;
66 struct rockchip_encoder encoder;
67 struct drm_display_mode mode;
68
69 struct clk *pclk;
70 struct clk *grfclk;
71 struct regmap *grf;
72 struct reset_control *rst;
73
74 const struct rockchip_dp_chip_data *data;
75
76 struct analogix_dp_device *adp;
77 struct analogix_dp_plat_data plat_data;
78 };
79
encoder_to_dp(struct drm_encoder * encoder)80 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
81 {
82 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
83
84 return container_of(rkencoder, struct rockchip_dp_device, encoder);
85 }
86
pdata_encoder_to_dp(struct analogix_dp_plat_data * plat_data)87 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
88 {
89 return container_of(plat_data, struct rockchip_dp_device, plat_data);
90 }
91
rockchip_grf_write(struct regmap * grf,u32 reg,u32 mask,u32 val)92 static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 val)
93 {
94 return regmap_write(grf, reg, (mask << 16) | (val & mask));
95 }
96
rockchip_grf_field_write(struct regmap * grf,const struct rockchip_grf_reg_field * field,u32 val)97 static int rockchip_grf_field_write(struct regmap *grf,
98 const struct rockchip_grf_reg_field *field,
99 u32 val)
100 {
101 u32 mask;
102
103 if (!field->valid)
104 return 0;
105
106 mask = GENMASK(field->msb, field->lsb);
107 val <<= field->lsb;
108
109 return rockchip_grf_write(grf, field->reg, mask, val);
110 }
111
rockchip_dp_pre_init(struct rockchip_dp_device * dp)112 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
113 {
114 reset_control_assert(dp->rst);
115 usleep_range(10, 20);
116 reset_control_deassert(dp->rst);
117
118 return 0;
119 }
120
rockchip_dp_poweron(struct analogix_dp_plat_data * plat_data)121 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
122 {
123 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
124 int ret;
125
126 ret = clk_prepare_enable(dp->pclk);
127 if (ret < 0) {
128 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
129 return ret;
130 }
131
132 ret = rockchip_dp_pre_init(dp);
133 if (ret < 0) {
134 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
135 clk_disable_unprepare(dp->pclk);
136 return ret;
137 }
138
139 return ret;
140 }
141
rockchip_dp_powerdown(struct analogix_dp_plat_data * plat_data)142 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
143 {
144 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
145
146 clk_disable_unprepare(dp->pclk);
147
148 return 0;
149 }
150
rockchip_dp_get_modes(struct analogix_dp_plat_data * plat_data,struct drm_connector * connector)151 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
152 struct drm_connector *connector)
153 {
154 struct drm_display_info *di = &connector->display_info;
155 /* VOP couldn't output YUV video format for eDP rightly */
156 u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;
157
158 if ((di->color_formats & mask)) {
159 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
160 di->color_formats &= ~mask;
161 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
162 di->bpc = 8;
163 }
164
165 return 0;
166 }
167
168 static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)169 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
170 const struct drm_display_mode *mode,
171 struct drm_display_mode *adjusted_mode)
172 {
173 /* do nothing */
174 return true;
175 }
176
rockchip_dp_drm_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted)177 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
178 struct drm_display_mode *mode,
179 struct drm_display_mode *adjusted)
180 {
181 /* do nothing */
182 }
183
184 static
rockchip_dp_drm_get_new_crtc(struct drm_encoder * encoder,struct drm_atomic_state * state)185 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
186 struct drm_atomic_state *state)
187 {
188 struct drm_connector *connector;
189 struct drm_connector_state *conn_state;
190
191 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
192 if (!connector)
193 return NULL;
194
195 conn_state = drm_atomic_get_new_connector_state(state, connector);
196 if (!conn_state)
197 return NULL;
198
199 return conn_state->crtc;
200 }
201
rockchip_dp_drm_encoder_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)202 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
203 struct drm_atomic_state *state)
204 {
205 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
206 struct drm_crtc *crtc;
207 struct drm_crtc_state *old_crtc_state;
208 int ret;
209
210 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
211 if (!crtc)
212 return;
213
214 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
215 /* Coming back from self refresh, nothing to do */
216 if (old_crtc_state && old_crtc_state->self_refresh_active)
217 return;
218
219 ret = clk_prepare_enable(dp->grfclk);
220 if (ret < 0) {
221 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
222 return;
223 }
224
225 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
226 if (ret < 0)
227 return;
228
229 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
230
231 ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, ret);
232 if (ret != 0)
233 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
234
235 clk_disable_unprepare(dp->grfclk);
236 }
237
rockchip_dp_drm_encoder_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)238 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
239 struct drm_atomic_state *state)
240 {
241 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
242 struct drm_crtc *crtc;
243 struct drm_crtc_state *new_crtc_state = NULL;
244 int ret;
245
246 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
247 /* No crtc means we're doing a full shutdown */
248 if (!crtc)
249 return;
250
251 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
252 /* If we're not entering self-refresh, no need to wait for vact */
253 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
254 return;
255
256 ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
257 if (ret)
258 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
259 }
260
261 static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)262 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
263 struct drm_crtc_state *crtc_state,
264 struct drm_connector_state *conn_state)
265 {
266 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
267 struct drm_display_info *di = &conn_state->connector->display_info;
268
269 /*
270 * The hardware IC designed that VOP must output the RGB10 video
271 * format to eDP controller, and if eDP panel only support RGB8,
272 * then eDP controller should cut down the video data, not via VOP
273 * controller, that's why we need to hardcode the VOP output mode
274 * to RGA10 here.
275 */
276
277 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
278 s->output_type = DRM_MODE_CONNECTOR_eDP;
279 s->output_bpc = di->bpc;
280
281 return 0;
282 }
283
284 static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
285 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
286 .mode_set = rockchip_dp_drm_encoder_mode_set,
287 .atomic_enable = rockchip_dp_drm_encoder_enable,
288 .atomic_disable = rockchip_dp_drm_encoder_disable,
289 .atomic_check = rockchip_dp_drm_encoder_atomic_check,
290 };
291
rockchip_dp_of_probe(struct rockchip_dp_device * dp)292 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
293 {
294 struct device *dev = dp->dev;
295 struct device_node *np = dev->of_node;
296
297 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
298 if (IS_ERR(dp->grf)) {
299 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
300 return PTR_ERR(dp->grf);
301 }
302
303 dp->grfclk = devm_clk_get(dev, "grf");
304 if (PTR_ERR(dp->grfclk) == -ENOENT) {
305 dp->grfclk = NULL;
306 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
307 return -EPROBE_DEFER;
308 } else if (IS_ERR(dp->grfclk)) {
309 DRM_DEV_ERROR(dev, "failed to get grf clock\n");
310 return PTR_ERR(dp->grfclk);
311 }
312
313 dp->pclk = devm_clk_get(dev, "pclk");
314 if (IS_ERR(dp->pclk)) {
315 DRM_DEV_ERROR(dev, "failed to get pclk property\n");
316 return PTR_ERR(dp->pclk);
317 }
318
319 dp->rst = devm_reset_control_get(dev, "dp");
320 if (IS_ERR(dp->rst)) {
321 DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
322 return PTR_ERR(dp->rst);
323 }
324
325 return 0;
326 }
327
rockchip_dp_drm_create_encoder(struct rockchip_dp_device * dp)328 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
329 {
330 struct drm_encoder *encoder = &dp->encoder.encoder;
331 struct drm_device *drm_dev = dp->drm_dev;
332 struct device *dev = dp->dev;
333 int ret;
334
335 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
336 dev->of_node);
337 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
338
339 ret = drm_simple_encoder_init(drm_dev, encoder,
340 DRM_MODE_ENCODER_TMDS);
341 if (ret) {
342 DRM_ERROR("failed to initialize encoder with drm\n");
343 return ret;
344 }
345
346 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
347
348 return 0;
349 }
350
rockchip_dp_bind(struct device * dev,struct device * master,void * data)351 static int rockchip_dp_bind(struct device *dev, struct device *master,
352 void *data)
353 {
354 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
355 struct drm_device *drm_dev = data;
356 int ret;
357
358 dp->drm_dev = drm_dev;
359
360 ret = rockchip_dp_drm_create_encoder(dp);
361 if (ret) {
362 DRM_ERROR("failed to create drm encoder\n");
363 return ret;
364 }
365
366 rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder,
367 dev->of_node, 0, 0);
368
369 dp->plat_data.encoder = &dp->encoder.encoder;
370
371 ret = analogix_dp_bind(dp->adp, drm_dev);
372 if (ret)
373 goto err_cleanup_encoder;
374
375 return 0;
376 err_cleanup_encoder:
377 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
378 return ret;
379 }
380
rockchip_dp_unbind(struct device * dev,struct device * master,void * data)381 static void rockchip_dp_unbind(struct device *dev, struct device *master,
382 void *data)
383 {
384 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
385
386 analogix_dp_unbind(dp->adp);
387 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
388 }
389
390 static const struct component_ops rockchip_dp_component_ops = {
391 .bind = rockchip_dp_bind,
392 .unbind = rockchip_dp_unbind,
393 };
394
rockchip_dp_probe(struct platform_device * pdev)395 static int rockchip_dp_probe(struct platform_device *pdev)
396 {
397 struct device *dev = &pdev->dev;
398 const struct rockchip_dp_chip_data *dp_data;
399 struct drm_panel *panel = NULL;
400 struct rockchip_dp_device *dp;
401 struct resource *res;
402 int i;
403 int ret;
404
405 dp_data = of_device_get_match_data(dev);
406 if (!dp_data)
407 return -ENODEV;
408
409 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
410 if (ret < 0 && ret != -ENODEV)
411 return ret;
412
413 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
414 if (!dp)
415 return -ENOMEM;
416
417 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
418
419 i = 0;
420 while (dp_data[i].reg) {
421 if (dp_data[i].reg == res->start) {
422 dp->data = &dp_data[i];
423 break;
424 }
425
426 i++;
427 }
428
429 if (!dp->data)
430 return dev_err_probe(dev, -EINVAL, "no chip-data for %s node\n",
431 dev->of_node->name);
432
433 dp->dev = dev;
434 dp->adp = ERR_PTR(-ENODEV);
435 dp->plat_data.panel = panel;
436 dp->plat_data.dev_type = dp->data->chip_type;
437 dp->plat_data.power_on = rockchip_dp_poweron;
438 dp->plat_data.power_off = rockchip_dp_powerdown;
439 dp->plat_data.get_modes = rockchip_dp_get_modes;
440
441 ret = rockchip_dp_of_probe(dp);
442 if (ret < 0)
443 return ret;
444
445 platform_set_drvdata(pdev, dp);
446
447 dp->adp = analogix_dp_probe(dev, &dp->plat_data);
448 if (IS_ERR(dp->adp))
449 return PTR_ERR(dp->adp);
450
451 ret = component_add(dev, &rockchip_dp_component_ops);
452 if (ret)
453 return ret;
454
455 return 0;
456 }
457
rockchip_dp_remove(struct platform_device * pdev)458 static void rockchip_dp_remove(struct platform_device *pdev)
459 {
460 component_del(&pdev->dev, &rockchip_dp_component_ops);
461 }
462
rockchip_dp_suspend(struct device * dev)463 static int rockchip_dp_suspend(struct device *dev)
464 {
465 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
466
467 if (IS_ERR(dp->adp))
468 return 0;
469
470 return analogix_dp_suspend(dp->adp);
471 }
472
rockchip_dp_resume(struct device * dev)473 static int rockchip_dp_resume(struct device *dev)
474 {
475 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
476
477 if (IS_ERR(dp->adp))
478 return 0;
479
480 return analogix_dp_resume(dp->adp);
481 }
482
483 static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
484 rockchip_dp_resume, NULL);
485
486 static const struct rockchip_dp_chip_data rk3399_edp[] = {
487 {
488 .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5),
489 .chip_type = RK3399_EDP,
490 .reg = 0xff970000,
491 },
492 { /* sentinel */ }
493 };
494
495 static const struct rockchip_dp_chip_data rk3288_dp[] = {
496 {
497 .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5),
498 .chip_type = RK3288_DP,
499 .reg = 0xff970000,
500 },
501 { /* sentinel */ }
502 };
503
504 static const struct of_device_id rockchip_dp_dt_ids[] = {
505 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
506 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
507 {}
508 };
509 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
510
511 struct platform_driver rockchip_dp_driver = {
512 .probe = rockchip_dp_probe,
513 .remove = rockchip_dp_remove,
514 .driver = {
515 .name = "rockchip-dp",
516 .pm = pm_ptr(&rockchip_dp_pm_ops),
517 .of_match_table = rockchip_dp_dt_ids,
518 },
519 };
520