1 /*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
33
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
37
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43 #include <drm/drm_of.h>
44
45 /**
46 * struct panel_desc - Describes a simple panel.
47 */
48 struct panel_desc {
49 /**
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 *
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
55 */
56 const struct drm_display_mode *modes;
57
58 /** @num_modes: Number of elements in modes array. */
59 unsigned int num_modes;
60
61 /**
62 * @timings: Pointer to array of display timings
63 *
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
66 */
67 const struct display_timing *timings;
68
69 /** @num_timings: Number of elements in timings array. */
70 unsigned int num_timings;
71
72 /** @bpc: Bits per color. */
73 unsigned int bpc;
74
75 /** @size: Structure containing the physical size of this panel. */
76 struct {
77 /**
78 * @size.width: Width (in mm) of the active display area.
79 */
80 unsigned int width;
81
82 /**
83 * @size.height: Height (in mm) of the active display area.
84 */
85 unsigned int height;
86 } size;
87
88 /** @delay: Structure containing various delay values for this panel. */
89 struct {
90 /**
91 * @delay.prepare: Time for the panel to become ready.
92 *
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
95 */
96 unsigned int prepare;
97
98 /**
99 * @delay.enable: Time for the panel to display a valid frame.
100 *
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
103 * video data.
104 */
105 unsigned int enable;
106
107 /**
108 * @delay.disable: Time for the panel to turn the display off.
109 *
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
112 */
113 unsigned int disable;
114
115 /**
116 * @delay.unprepare: Time to power down completely.
117 *
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
120 *
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
125 */
126 unsigned int unprepare;
127 } delay;
128
129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
130 u32 bus_format;
131
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
133 u32 bus_flags;
134
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
136 int connector_type;
137 };
138
139 struct panel_simple {
140 struct drm_panel base;
141
142 ktime_t unprepared_time;
143
144 const struct panel_desc *desc;
145
146 struct regulator *supply;
147 struct i2c_adapter *ddc;
148
149 struct gpio_desc *enable_gpio;
150
151 const struct drm_edid *drm_edid;
152
153 struct drm_display_mode override_mode;
154
155 enum drm_panel_orientation orientation;
156 };
157
to_panel_simple(struct drm_panel * panel)158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
159 {
160 return container_of(panel, struct panel_simple, base);
161 }
162
panel_simple_get_timings_modes(struct panel_simple * panel,struct drm_connector * connector)163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 struct drm_connector *connector)
165 {
166 struct drm_display_mode *mode;
167 unsigned int i, num = 0;
168
169 for (i = 0; i < panel->desc->num_timings; i++) {
170 const struct display_timing *dt = &panel->desc->timings[i];
171 struct videomode vm;
172
173 videomode_from_timing(dt, &vm);
174 mode = drm_mode_create(connector->dev);
175 if (!mode) {
176 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 dt->hactive.typ, dt->vactive.typ);
178 continue;
179 }
180
181 drm_display_mode_from_videomode(&vm, mode);
182
183 mode->type |= DRM_MODE_TYPE_DRIVER;
184
185 if (panel->desc->num_timings == 1)
186 mode->type |= DRM_MODE_TYPE_PREFERRED;
187
188 drm_mode_probed_add(connector, mode);
189 num++;
190 }
191
192 return num;
193 }
194
panel_simple_get_display_modes(struct panel_simple * panel,struct drm_connector * connector)195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 struct drm_connector *connector)
197 {
198 struct drm_display_mode *mode;
199 unsigned int i, num = 0;
200
201 for (i = 0; i < panel->desc->num_modes; i++) {
202 const struct drm_display_mode *m = &panel->desc->modes[i];
203
204 mode = drm_mode_duplicate(connector->dev, m);
205 if (!mode) {
206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 m->hdisplay, m->vdisplay,
208 drm_mode_vrefresh(m));
209 continue;
210 }
211
212 mode->type |= DRM_MODE_TYPE_DRIVER;
213
214 if (panel->desc->num_modes == 1)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
216
217 drm_mode_set_name(mode);
218
219 drm_mode_probed_add(connector, mode);
220 num++;
221 }
222
223 return num;
224 }
225
panel_simple_get_non_edid_modes(struct panel_simple * panel,struct drm_connector * connector)226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 struct drm_connector *connector)
228 {
229 struct drm_display_mode *mode;
230 bool has_override = panel->override_mode.type;
231 unsigned int num = 0;
232
233 if (!panel->desc)
234 return 0;
235
236 if (has_override) {
237 mode = drm_mode_duplicate(connector->dev,
238 &panel->override_mode);
239 if (mode) {
240 drm_mode_probed_add(connector, mode);
241 num = 1;
242 } else {
243 dev_err(panel->base.dev, "failed to add override mode\n");
244 }
245 }
246
247 /* Only add timings if override was not there or failed to validate */
248 if (num == 0 && panel->desc->num_timings)
249 num = panel_simple_get_timings_modes(panel, connector);
250
251 /*
252 * Only add fixed modes if timings/override added no mode.
253 *
254 * We should only ever have either the display timings specified
255 * or a fixed mode. Anything else is rather bogus.
256 */
257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
258 if (num == 0)
259 num = panel_simple_get_display_modes(panel, connector);
260
261 connector->display_info.bpc = panel->desc->bpc;
262 connector->display_info.width_mm = panel->desc->size.width;
263 connector->display_info.height_mm = panel->desc->size.height;
264 if (panel->desc->bus_format)
265 drm_display_info_set_bus_formats(&connector->display_info,
266 &panel->desc->bus_format, 1);
267 connector->display_info.bus_flags = panel->desc->bus_flags;
268
269 return num;
270 }
271
panel_simple_wait(ktime_t start_ktime,unsigned int min_ms)272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
273 {
274 ktime_t now_ktime, min_ktime;
275
276 if (!min_ms)
277 return;
278
279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 now_ktime = ktime_get_boottime();
281
282 if (ktime_before(now_ktime, min_ktime))
283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
284 }
285
panel_simple_disable(struct drm_panel * panel)286 static int panel_simple_disable(struct drm_panel *panel)
287 {
288 struct panel_simple *p = to_panel_simple(panel);
289
290 if (p->desc->delay.disable)
291 msleep(p->desc->delay.disable);
292
293 return 0;
294 }
295
panel_simple_suspend(struct device * dev)296 static int panel_simple_suspend(struct device *dev)
297 {
298 struct panel_simple *p = dev_get_drvdata(dev);
299
300 gpiod_set_value_cansleep(p->enable_gpio, 0);
301 regulator_disable(p->supply);
302 p->unprepared_time = ktime_get_boottime();
303
304 drm_edid_free(p->drm_edid);
305 p->drm_edid = NULL;
306
307 return 0;
308 }
309
panel_simple_unprepare(struct drm_panel * panel)310 static int panel_simple_unprepare(struct drm_panel *panel)
311 {
312 int ret;
313
314 pm_runtime_mark_last_busy(panel->dev);
315 ret = pm_runtime_put_autosuspend(panel->dev);
316 if (ret < 0)
317 return ret;
318
319 return 0;
320 }
321
panel_simple_resume(struct device * dev)322 static int panel_simple_resume(struct device *dev)
323 {
324 struct panel_simple *p = dev_get_drvdata(dev);
325 int err;
326
327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
328
329 err = regulator_enable(p->supply);
330 if (err < 0) {
331 dev_err(dev, "failed to enable supply: %d\n", err);
332 return err;
333 }
334
335 gpiod_set_value_cansleep(p->enable_gpio, 1);
336
337 if (p->desc->delay.prepare)
338 msleep(p->desc->delay.prepare);
339
340 return 0;
341 }
342
panel_simple_prepare(struct drm_panel * panel)343 static int panel_simple_prepare(struct drm_panel *panel)
344 {
345 int ret;
346
347 ret = pm_runtime_get_sync(panel->dev);
348 if (ret < 0) {
349 pm_runtime_put_autosuspend(panel->dev);
350 return ret;
351 }
352
353 return 0;
354 }
355
panel_simple_enable(struct drm_panel * panel)356 static int panel_simple_enable(struct drm_panel *panel)
357 {
358 struct panel_simple *p = to_panel_simple(panel);
359
360 if (p->desc->delay.enable)
361 msleep(p->desc->delay.enable);
362
363 return 0;
364 }
365
panel_simple_get_modes(struct drm_panel * panel,struct drm_connector * connector)366 static int panel_simple_get_modes(struct drm_panel *panel,
367 struct drm_connector *connector)
368 {
369 struct panel_simple *p = to_panel_simple(panel);
370 int num = 0;
371
372 /* probe EDID if a DDC bus is available */
373 if (p->ddc) {
374 pm_runtime_get_sync(panel->dev);
375
376 if (!p->drm_edid)
377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc);
378
379 drm_edid_connector_update(connector, p->drm_edid);
380
381 num += drm_edid_connector_add_modes(connector);
382
383 pm_runtime_mark_last_busy(panel->dev);
384 pm_runtime_put_autosuspend(panel->dev);
385 }
386
387 /* add hard-coded panel modes */
388 num += panel_simple_get_non_edid_modes(p, connector);
389
390 /*
391 * TODO: Remove once all drm drivers call
392 * drm_connector_set_orientation_from_panel()
393 */
394 drm_connector_set_panel_orientation(connector, p->orientation);
395
396 return num;
397 }
398
panel_simple_get_timings(struct drm_panel * panel,unsigned int num_timings,struct display_timing * timings)399 static int panel_simple_get_timings(struct drm_panel *panel,
400 unsigned int num_timings,
401 struct display_timing *timings)
402 {
403 struct panel_simple *p = to_panel_simple(panel);
404 unsigned int i;
405
406 if (p->desc->num_timings < num_timings)
407 num_timings = p->desc->num_timings;
408
409 if (timings)
410 for (i = 0; i < num_timings; i++)
411 timings[i] = p->desc->timings[i];
412
413 return p->desc->num_timings;
414 }
415
panel_simple_get_orientation(struct drm_panel * panel)416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
417 {
418 struct panel_simple *p = to_panel_simple(panel);
419
420 return p->orientation;
421 }
422
423 static const struct drm_panel_funcs panel_simple_funcs = {
424 .disable = panel_simple_disable,
425 .unprepare = panel_simple_unprepare,
426 .prepare = panel_simple_prepare,
427 .enable = panel_simple_enable,
428 .get_modes = panel_simple_get_modes,
429 .get_orientation = panel_simple_get_orientation,
430 .get_timings = panel_simple_get_timings,
431 };
432
433 static struct panel_desc panel_dpi;
434
panel_dpi_probe(struct device * dev,struct panel_simple * panel)435 static int panel_dpi_probe(struct device *dev,
436 struct panel_simple *panel)
437 {
438 struct display_timing *timing;
439 const struct device_node *np;
440 struct panel_desc *desc;
441 unsigned int bus_flags;
442 struct videomode vm;
443 int ret;
444
445 np = dev->of_node;
446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
447 if (!desc)
448 return -ENOMEM;
449
450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
451 if (!timing)
452 return -ENOMEM;
453
454 ret = of_get_display_timing(np, "panel-timing", timing);
455 if (ret < 0) {
456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
457 np);
458 return ret;
459 }
460
461 desc->timings = timing;
462 desc->num_timings = 1;
463
464 of_property_read_u32(np, "width-mm", &desc->size.width);
465 of_property_read_u32(np, "height-mm", &desc->size.height);
466
467 /* Extract bus_flags from display_timing */
468 bus_flags = 0;
469 vm.flags = timing->flags;
470 drm_bus_flags_from_videomode(&vm, &bus_flags);
471 desc->bus_flags = bus_flags;
472
473 /* We do not know the connector for the DT node, so guess it */
474 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
475
476 panel->desc = desc;
477
478 return 0;
479 }
480
481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
482 (to_check->field.typ >= bounds->field.min && \
483 to_check->field.typ <= bounds->field.max)
panel_simple_parse_panel_timing_node(struct device * dev,struct panel_simple * panel,const struct display_timing * ot)484 static void panel_simple_parse_panel_timing_node(struct device *dev,
485 struct panel_simple *panel,
486 const struct display_timing *ot)
487 {
488 const struct panel_desc *desc = panel->desc;
489 struct videomode vm;
490 unsigned int i;
491
492 if (WARN_ON(desc->num_modes)) {
493 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
494 return;
495 }
496 if (WARN_ON(!desc->num_timings)) {
497 dev_err(dev, "Reject override mode: no timings specified\n");
498 return;
499 }
500
501 for (i = 0; i < panel->desc->num_timings; i++) {
502 const struct display_timing *dt = &panel->desc->timings[i];
503
504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
512 continue;
513
514 if (ot->flags != dt->flags)
515 continue;
516
517 videomode_from_timing(ot, &vm);
518 drm_display_mode_from_videomode(&vm, &panel->override_mode);
519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
520 DRM_MODE_TYPE_PREFERRED;
521 break;
522 }
523
524 if (WARN_ON(!panel->override_mode.type))
525 dev_err(dev, "Reject override mode: No display_timing found\n");
526 }
527
panel_simple_override_nondefault_lvds_datamapping(struct device * dev,struct panel_simple * panel)528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
529 struct panel_simple *panel)
530 {
531 int ret, bpc;
532
533 ret = drm_of_lvds_get_data_mapping(dev->of_node);
534 if (ret < 0) {
535 if (ret == -EINVAL)
536 dev_warn(dev, "Ignore invalid data-mapping property\n");
537
538 /*
539 * Ignore non-existing or malformatted property, fallback to
540 * default data-mapping, and return 0.
541 */
542 return 0;
543 }
544
545 switch (ret) {
546 default:
547 WARN_ON(1);
548 fallthrough;
549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
550 fallthrough;
551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
552 bpc = 8;
553 break;
554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
555 bpc = 6;
556 }
557
558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
559 struct panel_desc *override_desc;
560
561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
562 if (!override_desc)
563 return -ENOMEM;
564
565 override_desc->bus_format = ret;
566 override_desc->bpc = bpc;
567 panel->desc = override_desc;
568 }
569
570 return 0;
571 }
572
panel_simple_probe(struct device * dev,const struct panel_desc * desc)573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
574 {
575 struct panel_simple *panel;
576 struct display_timing dt;
577 struct device_node *ddc;
578 int connector_type;
579 u32 bus_flags;
580 int err;
581
582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
583 if (!panel)
584 return -ENOMEM;
585
586 panel->desc = desc;
587
588 panel->supply = devm_regulator_get(dev, "power");
589 if (IS_ERR(panel->supply))
590 return PTR_ERR(panel->supply);
591
592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
593 GPIOD_OUT_LOW);
594 if (IS_ERR(panel->enable_gpio))
595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
596 "failed to request GPIO\n");
597
598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
599 if (err) {
600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
601 return err;
602 }
603
604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
605 if (ddc) {
606 panel->ddc = of_find_i2c_adapter_by_node(ddc);
607 of_node_put(ddc);
608
609 if (!panel->ddc)
610 return -EPROBE_DEFER;
611 }
612
613 if (desc == &panel_dpi) {
614 /* Handle the generic panel-dpi binding */
615 err = panel_dpi_probe(dev, panel);
616 if (err)
617 goto free_ddc;
618 desc = panel->desc;
619 } else {
620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
621 panel_simple_parse_panel_timing_node(dev, panel, &dt);
622 }
623
624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
625 /* Optional data-mapping property for overriding bus format */
626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
627 if (err)
628 goto free_ddc;
629 }
630
631 connector_type = desc->connector_type;
632 /* Catch common mistakes for panels. */
633 switch (connector_type) {
634 case 0:
635 dev_warn(dev, "Specify missing connector_type\n");
636 connector_type = DRM_MODE_CONNECTOR_DPI;
637 break;
638 case DRM_MODE_CONNECTOR_LVDS:
639 WARN_ON(desc->bus_flags &
640 ~(DRM_BUS_FLAG_DE_LOW |
641 DRM_BUS_FLAG_DE_HIGH |
642 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
643 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
648 desc->bpc != 6);
649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
651 desc->bpc != 8);
652 break;
653 case DRM_MODE_CONNECTOR_eDP:
654 dev_warn(dev, "eDP panels moved to panel-edp\n");
655 err = -EINVAL;
656 goto free_ddc;
657 case DRM_MODE_CONNECTOR_DSI:
658 if (desc->bpc != 6 && desc->bpc != 8)
659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
660 break;
661 case DRM_MODE_CONNECTOR_DPI:
662 bus_flags = DRM_BUS_FLAG_DE_LOW |
663 DRM_BUS_FLAG_DE_HIGH |
664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
666 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
667 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
670 if (desc->bus_flags & ~bus_flags)
671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
672 if (!(desc->bus_flags & bus_flags))
673 dev_warn(dev, "Specify missing bus_flags\n");
674 if (desc->bus_format == 0)
675 dev_warn(dev, "Specify missing bus_format\n");
676 if (desc->bpc != 6 && desc->bpc != 8)
677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
678 break;
679 default:
680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
681 connector_type = DRM_MODE_CONNECTOR_DPI;
682 break;
683 }
684
685 dev_set_drvdata(dev, panel);
686
687 /*
688 * We use runtime PM for prepare / unprepare since those power the panel
689 * on and off and those can be very slow operations. This is important
690 * to optimize powering the panel on briefly to read the EDID before
691 * fully enabling the panel.
692 */
693 pm_runtime_enable(dev);
694 pm_runtime_set_autosuspend_delay(dev, 1000);
695 pm_runtime_use_autosuspend(dev);
696
697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
698
699 err = drm_panel_of_backlight(&panel->base);
700 if (err) {
701 dev_err_probe(dev, err, "Could not find backlight\n");
702 goto disable_pm_runtime;
703 }
704
705 drm_panel_add(&panel->base);
706
707 return 0;
708
709 disable_pm_runtime:
710 pm_runtime_dont_use_autosuspend(dev);
711 pm_runtime_disable(dev);
712 free_ddc:
713 if (panel->ddc)
714 put_device(&panel->ddc->dev);
715
716 return err;
717 }
718
panel_simple_shutdown(struct device * dev)719 static void panel_simple_shutdown(struct device *dev)
720 {
721 struct panel_simple *panel = dev_get_drvdata(dev);
722
723 /*
724 * NOTE: the following two calls don't really belong here. It is the
725 * responsibility of a correctly written DRM modeset driver to call
726 * drm_atomic_helper_shutdown() at shutdown time and that should
727 * cause the panel to be disabled / unprepared if needed. For now,
728 * however, we'll keep these calls due to the sheer number of
729 * different DRM modeset drivers used with panel-simple. Once we've
730 * confirmed that all DRM modeset drivers using this panel properly
731 * call drm_atomic_helper_shutdown() we can simply delete the two
732 * calls below.
733 *
734 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW
735 * PANEL DRIVERS.
736 *
737 * FIXME: If we're still haven't figured out if all DRM modeset
738 * drivers properly call drm_atomic_helper_shutdown() but we _have_
739 * managed to make sure that DRM modeset drivers get their shutdown()
740 * callback before the panel's shutdown() callback (perhaps using
741 * device link), we could add a WARN_ON here to help move forward.
742 */
743 if (panel->base.enabled)
744 drm_panel_disable(&panel->base);
745 if (panel->base.prepared)
746 drm_panel_unprepare(&panel->base);
747 }
748
panel_simple_remove(struct device * dev)749 static void panel_simple_remove(struct device *dev)
750 {
751 struct panel_simple *panel = dev_get_drvdata(dev);
752
753 drm_panel_remove(&panel->base);
754 panel_simple_shutdown(dev);
755
756 pm_runtime_dont_use_autosuspend(dev);
757 pm_runtime_disable(dev);
758 if (panel->ddc)
759 put_device(&panel->ddc->dev);
760 }
761
762 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
763 .clock = 71100,
764 .hdisplay = 1280,
765 .hsync_start = 1280 + 40,
766 .hsync_end = 1280 + 40 + 80,
767 .htotal = 1280 + 40 + 80 + 40,
768 .vdisplay = 800,
769 .vsync_start = 800 + 3,
770 .vsync_end = 800 + 3 + 10,
771 .vtotal = 800 + 3 + 10 + 10,
772 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
773 };
774
775 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
776 .modes = &ire_am_1280800n3tzqw_t00h_mode,
777 .num_modes = 1,
778 .bpc = 8,
779 .size = {
780 .width = 217,
781 .height = 136,
782 },
783 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
785 .connector_type = DRM_MODE_CONNECTOR_LVDS,
786 };
787
788 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
789 .clock = 9000,
790 .hdisplay = 480,
791 .hsync_start = 480 + 2,
792 .hsync_end = 480 + 2 + 41,
793 .htotal = 480 + 2 + 41 + 2,
794 .vdisplay = 272,
795 .vsync_start = 272 + 2,
796 .vsync_end = 272 + 2 + 10,
797 .vtotal = 272 + 2 + 10 + 2,
798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
799 };
800
801 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
802 .modes = &ire_am_480272h3tmqw_t01h_mode,
803 .num_modes = 1,
804 .bpc = 8,
805 .size = {
806 .width = 99,
807 .height = 58,
808 },
809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
810 };
811
812 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
813 .clock = 33333,
814 .hdisplay = 800,
815 .hsync_start = 800 + 0,
816 .hsync_end = 800 + 0 + 255,
817 .htotal = 800 + 0 + 255 + 0,
818 .vdisplay = 480,
819 .vsync_start = 480 + 2,
820 .vsync_end = 480 + 2 + 45,
821 .vtotal = 480 + 2 + 45 + 0,
822 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
823 };
824
825 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
826 .pixelclock = { 29930000, 33260000, 36590000 },
827 .hactive = { 800, 800, 800 },
828 .hfront_porch = { 1, 40, 168 },
829 .hback_porch = { 88, 88, 88 },
830 .hsync_len = { 1, 128, 128 },
831 .vactive = { 480, 480, 480 },
832 .vfront_porch = { 1, 35, 37 },
833 .vback_porch = { 8, 8, 8 },
834 .vsync_len = { 1, 2, 2 },
835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
837 DISPLAY_FLAGS_SYNC_POSEDGE,
838 };
839
840 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
841 .timings = &ire_am_800480l1tmqw_t00h_timing,
842 .num_timings = 1,
843 .bpc = 8,
844 .size = {
845 .width = 111,
846 .height = 67,
847 },
848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
849 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
850 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
851 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
852 .connector_type = DRM_MODE_CONNECTOR_DPI,
853 };
854
855 static const struct panel_desc ampire_am800480r3tmqwa1h = {
856 .modes = &ire_am800480r3tmqwa1h_mode,
857 .num_modes = 1,
858 .bpc = 6,
859 .size = {
860 .width = 152,
861 .height = 91,
862 },
863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
864 };
865
866 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
867 .pixelclock = { 34500000, 39600000, 50400000 },
868 .hactive = { 800, 800, 800 },
869 .hfront_porch = { 12, 112, 312 },
870 .hback_porch = { 87, 87, 48 },
871 .hsync_len = { 1, 1, 40 },
872 .vactive = { 600, 600, 600 },
873 .vfront_porch = { 1, 21, 61 },
874 .vback_porch = { 38, 38, 19 },
875 .vsync_len = { 1, 1, 20 },
876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
878 DISPLAY_FLAGS_SYNC_POSEDGE,
879 };
880
881 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
882 .timings = &ire_am800600p5tmqw_tb8h_timing,
883 .num_timings = 1,
884 .bpc = 6,
885 .size = {
886 .width = 162,
887 .height = 122,
888 },
889 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
890 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
891 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
892 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
893 .connector_type = DRM_MODE_CONNECTOR_DPI,
894 };
895
896 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
897 .pixelclock = { 26400000, 33300000, 46800000 },
898 .hactive = { 800, 800, 800 },
899 .hfront_porch = { 16, 210, 354 },
900 .hback_porch = { 45, 36, 6 },
901 .hsync_len = { 1, 10, 40 },
902 .vactive = { 480, 480, 480 },
903 .vfront_porch = { 7, 22, 147 },
904 .vback_porch = { 22, 13, 3 },
905 .vsync_len = { 1, 10, 20 },
906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
908 };
909
910 static const struct panel_desc armadeus_st0700_adapt = {
911 .timings = &santek_st0700i5y_rbslw_f_timing,
912 .num_timings = 1,
913 .bpc = 6,
914 .size = {
915 .width = 154,
916 .height = 86,
917 },
918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
920 };
921
922 static const struct drm_display_mode auo_b101aw03_mode = {
923 .clock = 51450,
924 .hdisplay = 1024,
925 .hsync_start = 1024 + 156,
926 .hsync_end = 1024 + 156 + 8,
927 .htotal = 1024 + 156 + 8 + 156,
928 .vdisplay = 600,
929 .vsync_start = 600 + 16,
930 .vsync_end = 600 + 16 + 6,
931 .vtotal = 600 + 16 + 6 + 16,
932 };
933
934 static const struct panel_desc auo_b101aw03 = {
935 .modes = &auo_b101aw03_mode,
936 .num_modes = 1,
937 .bpc = 6,
938 .size = {
939 .width = 223,
940 .height = 125,
941 },
942 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
943 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
944 .connector_type = DRM_MODE_CONNECTOR_LVDS,
945 };
946
947 static const struct drm_display_mode auo_b101xtn01_mode = {
948 .clock = 72000,
949 .hdisplay = 1366,
950 .hsync_start = 1366 + 20,
951 .hsync_end = 1366 + 20 + 70,
952 .htotal = 1366 + 20 + 70,
953 .vdisplay = 768,
954 .vsync_start = 768 + 14,
955 .vsync_end = 768 + 14 + 42,
956 .vtotal = 768 + 14 + 42,
957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
958 };
959
960 static const struct panel_desc auo_b101xtn01 = {
961 .modes = &auo_b101xtn01_mode,
962 .num_modes = 1,
963 .bpc = 6,
964 .size = {
965 .width = 223,
966 .height = 125,
967 },
968 };
969
970 static const struct drm_display_mode auo_b116xw03_mode = {
971 .clock = 70589,
972 .hdisplay = 1366,
973 .hsync_start = 1366 + 40,
974 .hsync_end = 1366 + 40 + 40,
975 .htotal = 1366 + 40 + 40 + 32,
976 .vdisplay = 768,
977 .vsync_start = 768 + 10,
978 .vsync_end = 768 + 10 + 12,
979 .vtotal = 768 + 10 + 12 + 6,
980 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
981 };
982
983 static const struct panel_desc auo_b116xw03 = {
984 .modes = &auo_b116xw03_mode,
985 .num_modes = 1,
986 .bpc = 6,
987 .size = {
988 .width = 256,
989 .height = 144,
990 },
991 .delay = {
992 .prepare = 1,
993 .enable = 200,
994 .disable = 200,
995 .unprepare = 500,
996 },
997 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
998 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
999 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1000 };
1001
1002 static const struct display_timing auo_g070vvn01_timings = {
1003 .pixelclock = { 33300000, 34209000, 45000000 },
1004 .hactive = { 800, 800, 800 },
1005 .hfront_porch = { 20, 40, 200 },
1006 .hback_porch = { 87, 40, 1 },
1007 .hsync_len = { 1, 48, 87 },
1008 .vactive = { 480, 480, 480 },
1009 .vfront_porch = { 5, 13, 200 },
1010 .vback_porch = { 31, 31, 29 },
1011 .vsync_len = { 1, 1, 3 },
1012 };
1013
1014 static const struct panel_desc auo_g070vvn01 = {
1015 .timings = &auo_g070vvn01_timings,
1016 .num_timings = 1,
1017 .bpc = 8,
1018 .size = {
1019 .width = 152,
1020 .height = 91,
1021 },
1022 .delay = {
1023 .prepare = 200,
1024 .enable = 50,
1025 .disable = 50,
1026 .unprepare = 1000,
1027 },
1028 };
1029
1030 static const struct display_timing auo_g101evn010_timing = {
1031 .pixelclock = { 64000000, 68930000, 85000000 },
1032 .hactive = { 1280, 1280, 1280 },
1033 .hfront_porch = { 8, 64, 256 },
1034 .hback_porch = { 8, 64, 256 },
1035 .hsync_len = { 40, 168, 767 },
1036 .vactive = { 800, 800, 800 },
1037 .vfront_porch = { 4, 8, 100 },
1038 .vback_porch = { 4, 8, 100 },
1039 .vsync_len = { 8, 16, 223 },
1040 };
1041
1042 static const struct panel_desc auo_g101evn010 = {
1043 .timings = &auo_g101evn010_timing,
1044 .num_timings = 1,
1045 .bpc = 6,
1046 .size = {
1047 .width = 216,
1048 .height = 135,
1049 },
1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1051 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1052 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1053 };
1054
1055 static const struct drm_display_mode auo_g104sn02_mode = {
1056 .clock = 40000,
1057 .hdisplay = 800,
1058 .hsync_start = 800 + 40,
1059 .hsync_end = 800 + 40 + 216,
1060 .htotal = 800 + 40 + 216 + 128,
1061 .vdisplay = 600,
1062 .vsync_start = 600 + 10,
1063 .vsync_end = 600 + 10 + 35,
1064 .vtotal = 600 + 10 + 35 + 2,
1065 };
1066
1067 static const struct panel_desc auo_g104sn02 = {
1068 .modes = &auo_g104sn02_mode,
1069 .num_modes = 1,
1070 .bpc = 8,
1071 .size = {
1072 .width = 211,
1073 .height = 158,
1074 },
1075 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1076 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1077 };
1078
1079 static const struct drm_display_mode auo_g104stn01_mode = {
1080 .clock = 40000,
1081 .hdisplay = 800,
1082 .hsync_start = 800 + 40,
1083 .hsync_end = 800 + 40 + 88,
1084 .htotal = 800 + 40 + 88 + 128,
1085 .vdisplay = 600,
1086 .vsync_start = 600 + 1,
1087 .vsync_end = 600 + 1 + 23,
1088 .vtotal = 600 + 1 + 23 + 4,
1089 };
1090
1091 static const struct panel_desc auo_g104stn01 = {
1092 .modes = &auo_g104stn01_mode,
1093 .num_modes = 1,
1094 .bpc = 8,
1095 .size = {
1096 .width = 211,
1097 .height = 158,
1098 },
1099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1100 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1101 };
1102
1103 static const struct display_timing auo_g121ean01_timing = {
1104 .pixelclock = { 60000000, 74400000, 90000000 },
1105 .hactive = { 1280, 1280, 1280 },
1106 .hfront_porch = { 20, 50, 100 },
1107 .hback_porch = { 20, 50, 100 },
1108 .hsync_len = { 30, 100, 200 },
1109 .vactive = { 800, 800, 800 },
1110 .vfront_porch = { 2, 10, 25 },
1111 .vback_porch = { 2, 10, 25 },
1112 .vsync_len = { 4, 18, 50 },
1113 };
1114
1115 static const struct panel_desc auo_g121ean01 = {
1116 .timings = &auo_g121ean01_timing,
1117 .num_timings = 1,
1118 .bpc = 8,
1119 .size = {
1120 .width = 261,
1121 .height = 163,
1122 },
1123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1124 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1125 };
1126
1127 static const struct display_timing auo_g133han01_timings = {
1128 .pixelclock = { 134000000, 141200000, 149000000 },
1129 .hactive = { 1920, 1920, 1920 },
1130 .hfront_porch = { 39, 58, 77 },
1131 .hback_porch = { 59, 88, 117 },
1132 .hsync_len = { 28, 42, 56 },
1133 .vactive = { 1080, 1080, 1080 },
1134 .vfront_porch = { 3, 8, 11 },
1135 .vback_porch = { 5, 14, 19 },
1136 .vsync_len = { 4, 14, 19 },
1137 };
1138
1139 static const struct panel_desc auo_g133han01 = {
1140 .timings = &auo_g133han01_timings,
1141 .num_timings = 1,
1142 .bpc = 8,
1143 .size = {
1144 .width = 293,
1145 .height = 165,
1146 },
1147 .delay = {
1148 .prepare = 200,
1149 .enable = 50,
1150 .disable = 50,
1151 .unprepare = 1000,
1152 },
1153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1154 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1155 };
1156
1157 static const struct display_timing auo_g156han04_timings = {
1158 .pixelclock = { 137000000, 141000000, 146000000 },
1159 .hactive = { 1920, 1920, 1920 },
1160 .hfront_porch = { 60, 60, 60 },
1161 .hback_porch = { 90, 92, 111 },
1162 .hsync_len = { 32, 32, 32 },
1163 .vactive = { 1080, 1080, 1080 },
1164 .vfront_porch = { 12, 12, 12 },
1165 .vback_porch = { 24, 36, 56 },
1166 .vsync_len = { 8, 8, 8 },
1167 };
1168
1169 static const struct panel_desc auo_g156han04 = {
1170 .timings = &auo_g156han04_timings,
1171 .num_timings = 1,
1172 .bpc = 8,
1173 .size = {
1174 .width = 344,
1175 .height = 194,
1176 },
1177 .delay = {
1178 .prepare = 50, /* T2 */
1179 .enable = 200, /* T3 */
1180 .disable = 110, /* T10 */
1181 .unprepare = 1000, /* T13 */
1182 },
1183 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1184 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1185 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1186 };
1187
1188 static const struct drm_display_mode auo_g156xtn01_mode = {
1189 .clock = 76000,
1190 .hdisplay = 1366,
1191 .hsync_start = 1366 + 33,
1192 .hsync_end = 1366 + 33 + 67,
1193 .htotal = 1560,
1194 .vdisplay = 768,
1195 .vsync_start = 768 + 4,
1196 .vsync_end = 768 + 4 + 4,
1197 .vtotal = 806,
1198 };
1199
1200 static const struct panel_desc auo_g156xtn01 = {
1201 .modes = &auo_g156xtn01_mode,
1202 .num_modes = 1,
1203 .bpc = 8,
1204 .size = {
1205 .width = 344,
1206 .height = 194,
1207 },
1208 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1209 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1210 };
1211
1212 static const struct display_timing auo_g185han01_timings = {
1213 .pixelclock = { 120000000, 144000000, 175000000 },
1214 .hactive = { 1920, 1920, 1920 },
1215 .hfront_porch = { 36, 120, 148 },
1216 .hback_porch = { 24, 88, 108 },
1217 .hsync_len = { 20, 48, 64 },
1218 .vactive = { 1080, 1080, 1080 },
1219 .vfront_porch = { 6, 10, 40 },
1220 .vback_porch = { 2, 5, 20 },
1221 .vsync_len = { 2, 5, 20 },
1222 };
1223
1224 static const struct panel_desc auo_g185han01 = {
1225 .timings = &auo_g185han01_timings,
1226 .num_timings = 1,
1227 .bpc = 8,
1228 .size = {
1229 .width = 409,
1230 .height = 230,
1231 },
1232 .delay = {
1233 .prepare = 50,
1234 .enable = 200,
1235 .disable = 110,
1236 .unprepare = 1000,
1237 },
1238 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1239 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1240 };
1241
1242 static const struct display_timing auo_g190ean01_timings = {
1243 .pixelclock = { 90000000, 108000000, 135000000 },
1244 .hactive = { 1280, 1280, 1280 },
1245 .hfront_porch = { 126, 184, 1266 },
1246 .hback_porch = { 84, 122, 844 },
1247 .hsync_len = { 70, 102, 704 },
1248 .vactive = { 1024, 1024, 1024 },
1249 .vfront_porch = { 4, 26, 76 },
1250 .vback_porch = { 2, 8, 25 },
1251 .vsync_len = { 2, 8, 25 },
1252 };
1253
1254 static const struct panel_desc auo_g190ean01 = {
1255 .timings = &auo_g190ean01_timings,
1256 .num_timings = 1,
1257 .bpc = 8,
1258 .size = {
1259 .width = 376,
1260 .height = 301,
1261 },
1262 .delay = {
1263 .prepare = 50,
1264 .enable = 200,
1265 .disable = 110,
1266 .unprepare = 1000,
1267 },
1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1269 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1270 };
1271
1272 static const struct display_timing auo_p320hvn03_timings = {
1273 .pixelclock = { 106000000, 148500000, 164000000 },
1274 .hactive = { 1920, 1920, 1920 },
1275 .hfront_porch = { 25, 50, 130 },
1276 .hback_porch = { 25, 50, 130 },
1277 .hsync_len = { 20, 40, 105 },
1278 .vactive = { 1080, 1080, 1080 },
1279 .vfront_porch = { 8, 17, 150 },
1280 .vback_porch = { 8, 17, 150 },
1281 .vsync_len = { 4, 11, 100 },
1282 };
1283
1284 static const struct panel_desc auo_p320hvn03 = {
1285 .timings = &auo_p320hvn03_timings,
1286 .num_timings = 1,
1287 .bpc = 8,
1288 .size = {
1289 .width = 698,
1290 .height = 393,
1291 },
1292 .delay = {
1293 .prepare = 1,
1294 .enable = 450,
1295 .unprepare = 500,
1296 },
1297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1298 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1299 };
1300
1301 static const struct drm_display_mode auo_t215hvn01_mode = {
1302 .clock = 148800,
1303 .hdisplay = 1920,
1304 .hsync_start = 1920 + 88,
1305 .hsync_end = 1920 + 88 + 44,
1306 .htotal = 1920 + 88 + 44 + 148,
1307 .vdisplay = 1080,
1308 .vsync_start = 1080 + 4,
1309 .vsync_end = 1080 + 4 + 5,
1310 .vtotal = 1080 + 4 + 5 + 36,
1311 };
1312
1313 static const struct panel_desc auo_t215hvn01 = {
1314 .modes = &auo_t215hvn01_mode,
1315 .num_modes = 1,
1316 .bpc = 8,
1317 .size = {
1318 .width = 430,
1319 .height = 270,
1320 },
1321 .delay = {
1322 .disable = 5,
1323 .unprepare = 1000,
1324 },
1325 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1327 };
1328
1329 static const struct drm_display_mode avic_tm070ddh03_mode = {
1330 .clock = 51200,
1331 .hdisplay = 1024,
1332 .hsync_start = 1024 + 160,
1333 .hsync_end = 1024 + 160 + 4,
1334 .htotal = 1024 + 160 + 4 + 156,
1335 .vdisplay = 600,
1336 .vsync_start = 600 + 17,
1337 .vsync_end = 600 + 17 + 1,
1338 .vtotal = 600 + 17 + 1 + 17,
1339 };
1340
1341 static const struct panel_desc avic_tm070ddh03 = {
1342 .modes = &avic_tm070ddh03_mode,
1343 .num_modes = 1,
1344 .bpc = 8,
1345 .size = {
1346 .width = 154,
1347 .height = 90,
1348 },
1349 .delay = {
1350 .prepare = 20,
1351 .enable = 200,
1352 .disable = 200,
1353 },
1354 };
1355
1356 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1357 .clock = 30000,
1358 .hdisplay = 800,
1359 .hsync_start = 800 + 40,
1360 .hsync_end = 800 + 40 + 48,
1361 .htotal = 800 + 40 + 48 + 40,
1362 .vdisplay = 480,
1363 .vsync_start = 480 + 13,
1364 .vsync_end = 480 + 13 + 3,
1365 .vtotal = 480 + 13 + 3 + 29,
1366 };
1367
1368 static const struct panel_desc bananapi_s070wv20_ct16 = {
1369 .modes = &bananapi_s070wv20_ct16_mode,
1370 .num_modes = 1,
1371 .bpc = 6,
1372 .size = {
1373 .width = 154,
1374 .height = 86,
1375 },
1376 };
1377
1378 static const struct display_timing boe_av101hdt_a10_timing = {
1379 .pixelclock = { 74210000, 75330000, 76780000, },
1380 .hactive = { 1280, 1280, 1280, },
1381 .hfront_porch = { 10, 42, 33, },
1382 .hback_porch = { 10, 18, 33, },
1383 .hsync_len = { 30, 10, 30, },
1384 .vactive = { 720, 720, 720, },
1385 .vfront_porch = { 200, 183, 200, },
1386 .vback_porch = { 8, 8, 8, },
1387 .vsync_len = { 2, 19, 2, },
1388 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1389 };
1390
1391 static const struct panel_desc boe_av101hdt_a10 = {
1392 .timings = &boe_av101hdt_a10_timing,
1393 .num_timings = 1,
1394 .bpc = 8,
1395 .size = {
1396 .width = 224,
1397 .height = 126,
1398 },
1399 .delay = {
1400 .enable = 50,
1401 .disable = 50,
1402 },
1403 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1404 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1405 };
1406
1407 static const struct display_timing boe_av123z7m_n17_timing = {
1408 .pixelclock = { 86600000, 88000000, 90800000, },
1409 .hactive = { 1920, 1920, 1920, },
1410 .hfront_porch = { 10, 10, 10, },
1411 .hback_porch = { 10, 10, 10, },
1412 .hsync_len = { 9, 12, 25, },
1413 .vactive = { 720, 720, 720, },
1414 .vfront_porch = { 7, 10, 13, },
1415 .vback_porch = { 7, 10, 13, },
1416 .vsync_len = { 7, 11, 14, },
1417 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1418 };
1419
1420 static const struct panel_desc boe_av123z7m_n17 = {
1421 .timings = &boe_av123z7m_n17_timing,
1422 .bpc = 8,
1423 .num_timings = 1,
1424 .size = {
1425 .width = 292,
1426 .height = 110,
1427 },
1428 .delay = {
1429 .prepare = 50,
1430 .disable = 50,
1431 },
1432 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1433 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1434 };
1435
1436 static const struct drm_display_mode boe_bp101wx1_100_mode = {
1437 .clock = 78945,
1438 .hdisplay = 1280,
1439 .hsync_start = 1280 + 0,
1440 .hsync_end = 1280 + 0 + 2,
1441 .htotal = 1280 + 62 + 0 + 2,
1442 .vdisplay = 800,
1443 .vsync_start = 800 + 8,
1444 .vsync_end = 800 + 8 + 2,
1445 .vtotal = 800 + 6 + 8 + 2,
1446 };
1447
1448 static const struct panel_desc boe_bp082wx1_100 = {
1449 .modes = &boe_bp101wx1_100_mode,
1450 .num_modes = 1,
1451 .bpc = 8,
1452 .size = {
1453 .width = 177,
1454 .height = 110,
1455 },
1456 .delay = {
1457 .enable = 50,
1458 .disable = 50,
1459 },
1460 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1461 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1462 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1463 };
1464
1465 static const struct panel_desc boe_bp101wx1_100 = {
1466 .modes = &boe_bp101wx1_100_mode,
1467 .num_modes = 1,
1468 .bpc = 8,
1469 .size = {
1470 .width = 217,
1471 .height = 136,
1472 },
1473 .delay = {
1474 .enable = 50,
1475 .disable = 50,
1476 },
1477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1478 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1480 };
1481
1482 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1483 .pixelclock = { 69922000, 71000000, 72293000 },
1484 .hactive = { 1280, 1280, 1280 },
1485 .hfront_porch = { 48, 48, 48 },
1486 .hback_porch = { 80, 80, 80 },
1487 .hsync_len = { 32, 32, 32 },
1488 .vactive = { 800, 800, 800 },
1489 .vfront_porch = { 3, 3, 3 },
1490 .vback_porch = { 14, 14, 14 },
1491 .vsync_len = { 6, 6, 6 },
1492 };
1493
1494 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1495 .timings = &boe_ev121wxm_n10_1850_timing,
1496 .num_timings = 1,
1497 .bpc = 8,
1498 .size = {
1499 .width = 261,
1500 .height = 163,
1501 },
1502 .delay = {
1503 .prepare = 9,
1504 .enable = 300,
1505 .unprepare = 300,
1506 .disable = 560,
1507 },
1508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1509 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1510 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1511 };
1512
1513 static const struct drm_display_mode boe_hv070wsa_mode = {
1514 .clock = 42105,
1515 .hdisplay = 1024,
1516 .hsync_start = 1024 + 30,
1517 .hsync_end = 1024 + 30 + 30,
1518 .htotal = 1024 + 30 + 30 + 30,
1519 .vdisplay = 600,
1520 .vsync_start = 600 + 10,
1521 .vsync_end = 600 + 10 + 10,
1522 .vtotal = 600 + 10 + 10 + 10,
1523 };
1524
1525 static const struct panel_desc boe_hv070wsa = {
1526 .modes = &boe_hv070wsa_mode,
1527 .num_modes = 1,
1528 .bpc = 8,
1529 .size = {
1530 .width = 154,
1531 .height = 90,
1532 },
1533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1535 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1536 };
1537
1538 static const struct display_timing cct_cmt430b19n00_timing = {
1539 .pixelclock = { 8000000, 9000000, 12000000 },
1540 .hactive = { 480, 480, 480 },
1541 .hfront_porch = { 2, 8, 75 },
1542 .hback_porch = { 3, 43, 43 },
1543 .hsync_len = { 2, 4, 75 },
1544 .vactive = { 272, 272, 272 },
1545 .vfront_porch = { 2, 8, 37 },
1546 .vback_porch = { 2, 12, 12 },
1547 .vsync_len = { 2, 4, 37 },
1548 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW
1549 };
1550
1551 static const struct panel_desc cct_cmt430b19n00 = {
1552 .timings = &cct_cmt430b19n00_timing,
1553 .num_timings = 1,
1554 .bpc = 8,
1555 .size = {
1556 .width = 95,
1557 .height = 53,
1558 },
1559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1561 .connector_type = DRM_MODE_CONNECTOR_DPI,
1562 };
1563
1564 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1565 .clock = 9000,
1566 .hdisplay = 480,
1567 .hsync_start = 480 + 5,
1568 .hsync_end = 480 + 5 + 5,
1569 .htotal = 480 + 5 + 5 + 40,
1570 .vdisplay = 272,
1571 .vsync_start = 272 + 8,
1572 .vsync_end = 272 + 8 + 8,
1573 .vtotal = 272 + 8 + 8 + 8,
1574 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1575 };
1576
1577 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1578 .modes = &cdtech_s043wq26h_ct7_mode,
1579 .num_modes = 1,
1580 .bpc = 8,
1581 .size = {
1582 .width = 95,
1583 .height = 54,
1584 },
1585 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1586 };
1587
1588 /* S070PWS19HP-FC21 2017/04/22 */
1589 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1590 .clock = 51200,
1591 .hdisplay = 1024,
1592 .hsync_start = 1024 + 160,
1593 .hsync_end = 1024 + 160 + 20,
1594 .htotal = 1024 + 160 + 20 + 140,
1595 .vdisplay = 600,
1596 .vsync_start = 600 + 12,
1597 .vsync_end = 600 + 12 + 3,
1598 .vtotal = 600 + 12 + 3 + 20,
1599 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1600 };
1601
1602 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1603 .modes = &cdtech_s070pws19hp_fc21_mode,
1604 .num_modes = 1,
1605 .bpc = 6,
1606 .size = {
1607 .width = 154,
1608 .height = 86,
1609 },
1610 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1611 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1612 .connector_type = DRM_MODE_CONNECTOR_DPI,
1613 };
1614
1615 /* S070SWV29HG-DC44 2017/09/21 */
1616 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1617 .clock = 33300,
1618 .hdisplay = 800,
1619 .hsync_start = 800 + 210,
1620 .hsync_end = 800 + 210 + 2,
1621 .htotal = 800 + 210 + 2 + 44,
1622 .vdisplay = 480,
1623 .vsync_start = 480 + 22,
1624 .vsync_end = 480 + 22 + 2,
1625 .vtotal = 480 + 22 + 2 + 21,
1626 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1627 };
1628
1629 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1630 .modes = &cdtech_s070swv29hg_dc44_mode,
1631 .num_modes = 1,
1632 .bpc = 6,
1633 .size = {
1634 .width = 154,
1635 .height = 86,
1636 },
1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1638 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1639 .connector_type = DRM_MODE_CONNECTOR_DPI,
1640 };
1641
1642 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1643 .clock = 35000,
1644 .hdisplay = 800,
1645 .hsync_start = 800 + 40,
1646 .hsync_end = 800 + 40 + 40,
1647 .htotal = 800 + 40 + 40 + 48,
1648 .vdisplay = 480,
1649 .vsync_start = 480 + 29,
1650 .vsync_end = 480 + 29 + 13,
1651 .vtotal = 480 + 29 + 13 + 3,
1652 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1653 };
1654
1655 static const struct panel_desc cdtech_s070wv95_ct16 = {
1656 .modes = &cdtech_s070wv95_ct16_mode,
1657 .num_modes = 1,
1658 .bpc = 8,
1659 .size = {
1660 .width = 154,
1661 .height = 85,
1662 },
1663 };
1664
1665 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1666 .pixelclock = { 68900000, 71100000, 73400000 },
1667 .hactive = { 1280, 1280, 1280 },
1668 .hfront_porch = { 65, 80, 95 },
1669 .hback_porch = { 64, 79, 94 },
1670 .hsync_len = { 1, 1, 1 },
1671 .vactive = { 800, 800, 800 },
1672 .vfront_porch = { 7, 11, 14 },
1673 .vback_porch = { 7, 11, 14 },
1674 .vsync_len = { 1, 1, 1 },
1675 .flags = DISPLAY_FLAGS_DE_HIGH,
1676 };
1677
1678 static const struct panel_desc chefree_ch101olhlwh_002 = {
1679 .timings = &chefree_ch101olhlwh_002_timing,
1680 .num_timings = 1,
1681 .bpc = 8,
1682 .size = {
1683 .width = 217,
1684 .height = 135,
1685 },
1686 .delay = {
1687 .enable = 200,
1688 .disable = 200,
1689 },
1690 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1692 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1693 };
1694
1695 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1696 .clock = 66770,
1697 .hdisplay = 800,
1698 .hsync_start = 800 + 49,
1699 .hsync_end = 800 + 49 + 33,
1700 .htotal = 800 + 49 + 33 + 17,
1701 .vdisplay = 1280,
1702 .vsync_start = 1280 + 1,
1703 .vsync_end = 1280 + 1 + 7,
1704 .vtotal = 1280 + 1 + 7 + 15,
1705 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1706 };
1707
1708 static const struct panel_desc chunghwa_claa070wp03xg = {
1709 .modes = &chunghwa_claa070wp03xg_mode,
1710 .num_modes = 1,
1711 .bpc = 6,
1712 .size = {
1713 .width = 94,
1714 .height = 150,
1715 },
1716 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1717 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1718 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1719 };
1720
1721 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1722 .clock = 72070,
1723 .hdisplay = 1366,
1724 .hsync_start = 1366 + 58,
1725 .hsync_end = 1366 + 58 + 58,
1726 .htotal = 1366 + 58 + 58 + 58,
1727 .vdisplay = 768,
1728 .vsync_start = 768 + 4,
1729 .vsync_end = 768 + 4 + 4,
1730 .vtotal = 768 + 4 + 4 + 4,
1731 };
1732
1733 static const struct panel_desc chunghwa_claa101wa01a = {
1734 .modes = &chunghwa_claa101wa01a_mode,
1735 .num_modes = 1,
1736 .bpc = 6,
1737 .size = {
1738 .width = 220,
1739 .height = 120,
1740 },
1741 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1742 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1743 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1744 };
1745
1746 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1747 .clock = 69300,
1748 .hdisplay = 1366,
1749 .hsync_start = 1366 + 48,
1750 .hsync_end = 1366 + 48 + 32,
1751 .htotal = 1366 + 48 + 32 + 20,
1752 .vdisplay = 768,
1753 .vsync_start = 768 + 16,
1754 .vsync_end = 768 + 16 + 8,
1755 .vtotal = 768 + 16 + 8 + 16,
1756 };
1757
1758 static const struct panel_desc chunghwa_claa101wb01 = {
1759 .modes = &chunghwa_claa101wb01_mode,
1760 .num_modes = 1,
1761 .bpc = 6,
1762 .size = {
1763 .width = 223,
1764 .height = 125,
1765 },
1766 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1767 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1768 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1769 };
1770
1771 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1772 .pixelclock = { 5000000, 9000000, 12000000 },
1773 .hactive = { 480, 480, 480 },
1774 .hfront_porch = { 12, 12, 12 },
1775 .hback_porch = { 12, 12, 12 },
1776 .hsync_len = { 21, 21, 21 },
1777 .vactive = { 272, 272, 272 },
1778 .vfront_porch = { 4, 4, 4 },
1779 .vback_porch = { 4, 4, 4 },
1780 .vsync_len = { 8, 8, 8 },
1781 };
1782
1783 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1784 .timings = &dataimage_fg040346dsswbg04_timing,
1785 .num_timings = 1,
1786 .bpc = 8,
1787 .size = {
1788 .width = 95,
1789 .height = 54,
1790 },
1791 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1792 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1793 .connector_type = DRM_MODE_CONNECTOR_DPI,
1794 };
1795
1796 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1797 .pixelclock = { 68900000, 71110000, 73400000 },
1798 .hactive = { 1280, 1280, 1280 },
1799 .vactive = { 800, 800, 800 },
1800 .hback_porch = { 100, 100, 100 },
1801 .hfront_porch = { 100, 100, 100 },
1802 .vback_porch = { 5, 5, 5 },
1803 .vfront_porch = { 5, 5, 5 },
1804 .hsync_len = { 24, 24, 24 },
1805 .vsync_len = { 3, 3, 3 },
1806 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1807 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1808 };
1809
1810 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1811 .timings = &dataimage_fg1001l0dsswmg01_timing,
1812 .num_timings = 1,
1813 .bpc = 8,
1814 .size = {
1815 .width = 217,
1816 .height = 136,
1817 },
1818 };
1819
1820 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1821 .clock = 33260,
1822 .hdisplay = 800,
1823 .hsync_start = 800 + 40,
1824 .hsync_end = 800 + 40 + 128,
1825 .htotal = 800 + 40 + 128 + 88,
1826 .vdisplay = 480,
1827 .vsync_start = 480 + 10,
1828 .vsync_end = 480 + 10 + 2,
1829 .vtotal = 480 + 10 + 2 + 33,
1830 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1831 };
1832
1833 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1834 .modes = &dataimage_scf0700c48ggu18_mode,
1835 .num_modes = 1,
1836 .bpc = 8,
1837 .size = {
1838 .width = 152,
1839 .height = 91,
1840 },
1841 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1843 };
1844
1845 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1846 .pixelclock = { 45000000, 51200000, 57000000 },
1847 .hactive = { 1024, 1024, 1024 },
1848 .hfront_porch = { 100, 106, 113 },
1849 .hback_porch = { 100, 106, 113 },
1850 .hsync_len = { 100, 108, 114 },
1851 .vactive = { 600, 600, 600 },
1852 .vfront_porch = { 8, 11, 15 },
1853 .vback_porch = { 8, 11, 15 },
1854 .vsync_len = { 9, 13, 15 },
1855 .flags = DISPLAY_FLAGS_DE_HIGH,
1856 };
1857
1858 static const struct panel_desc dlc_dlc0700yzg_1 = {
1859 .timings = &dlc_dlc0700yzg_1_timing,
1860 .num_timings = 1,
1861 .bpc = 6,
1862 .size = {
1863 .width = 154,
1864 .height = 86,
1865 },
1866 .delay = {
1867 .prepare = 30,
1868 .enable = 200,
1869 .disable = 200,
1870 },
1871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1873 };
1874
1875 static const struct display_timing dlc_dlc1010gig_timing = {
1876 .pixelclock = { 68900000, 71100000, 73400000 },
1877 .hactive = { 1280, 1280, 1280 },
1878 .hfront_porch = { 43, 53, 63 },
1879 .hback_porch = { 43, 53, 63 },
1880 .hsync_len = { 44, 54, 64 },
1881 .vactive = { 800, 800, 800 },
1882 .vfront_porch = { 5, 8, 11 },
1883 .vback_porch = { 5, 8, 11 },
1884 .vsync_len = { 5, 7, 11 },
1885 .flags = DISPLAY_FLAGS_DE_HIGH,
1886 };
1887
1888 static const struct panel_desc dlc_dlc1010gig = {
1889 .timings = &dlc_dlc1010gig_timing,
1890 .num_timings = 1,
1891 .bpc = 8,
1892 .size = {
1893 .width = 216,
1894 .height = 135,
1895 },
1896 .delay = {
1897 .prepare = 60,
1898 .enable = 150,
1899 .disable = 100,
1900 .unprepare = 60,
1901 },
1902 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1903 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1904 };
1905
1906 static const struct drm_display_mode edt_et035012dm6_mode = {
1907 .clock = 6500,
1908 .hdisplay = 320,
1909 .hsync_start = 320 + 20,
1910 .hsync_end = 320 + 20 + 30,
1911 .htotal = 320 + 20 + 68,
1912 .vdisplay = 240,
1913 .vsync_start = 240 + 4,
1914 .vsync_end = 240 + 4 + 4,
1915 .vtotal = 240 + 4 + 4 + 14,
1916 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1917 };
1918
1919 static const struct panel_desc edt_et035012dm6 = {
1920 .modes = &edt_et035012dm6_mode,
1921 .num_modes = 1,
1922 .bpc = 8,
1923 .size = {
1924 .width = 70,
1925 .height = 52,
1926 },
1927 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1928 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1929 };
1930
1931 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1932 .clock = 6520,
1933 .hdisplay = 320,
1934 .hsync_start = 320 + 20,
1935 .hsync_end = 320 + 20 + 68,
1936 .htotal = 320 + 20 + 68,
1937 .vdisplay = 240,
1938 .vsync_start = 240 + 4,
1939 .vsync_end = 240 + 4 + 18,
1940 .vtotal = 240 + 4 + 18,
1941 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1942 };
1943
1944 static const struct panel_desc edt_etm0350g0dh6 = {
1945 .modes = &edt_etm0350g0dh6_mode,
1946 .num_modes = 1,
1947 .bpc = 6,
1948 .size = {
1949 .width = 70,
1950 .height = 53,
1951 },
1952 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1953 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1954 .connector_type = DRM_MODE_CONNECTOR_DPI,
1955 };
1956
1957 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1958 .clock = 10870,
1959 .hdisplay = 480,
1960 .hsync_start = 480 + 8,
1961 .hsync_end = 480 + 8 + 4,
1962 .htotal = 480 + 8 + 4 + 41,
1963
1964 /*
1965 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1966 * fb_align
1967 */
1968
1969 .vdisplay = 288,
1970 .vsync_start = 288 + 2,
1971 .vsync_end = 288 + 2 + 4,
1972 .vtotal = 288 + 2 + 4 + 10,
1973 };
1974
1975 static const struct panel_desc edt_etm043080dh6gp = {
1976 .modes = &edt_etm043080dh6gp_mode,
1977 .num_modes = 1,
1978 .bpc = 8,
1979 .size = {
1980 .width = 100,
1981 .height = 65,
1982 },
1983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1984 .connector_type = DRM_MODE_CONNECTOR_DPI,
1985 };
1986
1987 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1988 .clock = 9000,
1989 .hdisplay = 480,
1990 .hsync_start = 480 + 2,
1991 .hsync_end = 480 + 2 + 41,
1992 .htotal = 480 + 2 + 41 + 2,
1993 .vdisplay = 272,
1994 .vsync_start = 272 + 2,
1995 .vsync_end = 272 + 2 + 10,
1996 .vtotal = 272 + 2 + 10 + 2,
1997 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1998 };
1999
2000 static const struct panel_desc edt_etm0430g0dh6 = {
2001 .modes = &edt_etm0430g0dh6_mode,
2002 .num_modes = 1,
2003 .bpc = 6,
2004 .size = {
2005 .width = 95,
2006 .height = 54,
2007 },
2008 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2010 .connector_type = DRM_MODE_CONNECTOR_DPI,
2011 };
2012
2013 static const struct drm_display_mode edt_et057090dhu_mode = {
2014 .clock = 25175,
2015 .hdisplay = 640,
2016 .hsync_start = 640 + 16,
2017 .hsync_end = 640 + 16 + 30,
2018 .htotal = 640 + 16 + 30 + 114,
2019 .vdisplay = 480,
2020 .vsync_start = 480 + 10,
2021 .vsync_end = 480 + 10 + 3,
2022 .vtotal = 480 + 10 + 3 + 32,
2023 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2024 };
2025
2026 static const struct panel_desc edt_et057090dhu = {
2027 .modes = &edt_et057090dhu_mode,
2028 .num_modes = 1,
2029 .bpc = 6,
2030 .size = {
2031 .width = 115,
2032 .height = 86,
2033 },
2034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2035 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2036 .connector_type = DRM_MODE_CONNECTOR_DPI,
2037 };
2038
2039 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2040 .clock = 33260,
2041 .hdisplay = 800,
2042 .hsync_start = 800 + 40,
2043 .hsync_end = 800 + 40 + 128,
2044 .htotal = 800 + 40 + 128 + 88,
2045 .vdisplay = 480,
2046 .vsync_start = 480 + 10,
2047 .vsync_end = 480 + 10 + 2,
2048 .vtotal = 480 + 10 + 2 + 33,
2049 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2050 };
2051
2052 static const struct panel_desc edt_etm0700g0dh6 = {
2053 .modes = &edt_etm0700g0dh6_mode,
2054 .num_modes = 1,
2055 .bpc = 6,
2056 .size = {
2057 .width = 152,
2058 .height = 91,
2059 },
2060 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2061 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2062 .connector_type = DRM_MODE_CONNECTOR_DPI,
2063 };
2064
2065 static const struct panel_desc edt_etm0700g0bdh6 = {
2066 .modes = &edt_etm0700g0dh6_mode,
2067 .num_modes = 1,
2068 .bpc = 6,
2069 .size = {
2070 .width = 152,
2071 .height = 91,
2072 },
2073 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2074 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2075 .connector_type = DRM_MODE_CONNECTOR_DPI,
2076 };
2077
2078 static const struct display_timing edt_etml0700y5dha_timing = {
2079 .pixelclock = { 40800000, 51200000, 67200000 },
2080 .hactive = { 1024, 1024, 1024 },
2081 .hfront_porch = { 30, 106, 125 },
2082 .hback_porch = { 30, 106, 125 },
2083 .hsync_len = { 30, 108, 126 },
2084 .vactive = { 600, 600, 600 },
2085 .vfront_porch = { 3, 12, 67},
2086 .vback_porch = { 3, 12, 67 },
2087 .vsync_len = { 4, 11, 66 },
2088 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2089 DISPLAY_FLAGS_DE_HIGH,
2090 };
2091
2092 static const struct panel_desc edt_etml0700y5dha = {
2093 .timings = &edt_etml0700y5dha_timing,
2094 .num_timings = 1,
2095 .bpc = 8,
2096 .size = {
2097 .width = 155,
2098 .height = 86,
2099 },
2100 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2101 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2102 };
2103
2104 static const struct display_timing edt_etml1010g3dra_timing = {
2105 .pixelclock = { 66300000, 72400000, 78900000 },
2106 .hactive = { 1280, 1280, 1280 },
2107 .hfront_porch = { 12, 72, 132 },
2108 .hback_porch = { 86, 86, 86 },
2109 .hsync_len = { 2, 2, 2 },
2110 .vactive = { 800, 800, 800 },
2111 .vfront_porch = { 1, 15, 49 },
2112 .vback_porch = { 21, 21, 21 },
2113 .vsync_len = { 2, 2, 2 },
2114 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2115 DISPLAY_FLAGS_DE_HIGH,
2116 };
2117
2118 static const struct panel_desc edt_etml1010g3dra = {
2119 .timings = &edt_etml1010g3dra_timing,
2120 .num_timings = 1,
2121 .bpc = 8,
2122 .size = {
2123 .width = 216,
2124 .height = 135,
2125 },
2126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2127 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2128 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2129 };
2130
2131 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2132 .clock = 25175,
2133 .hdisplay = 640,
2134 .hsync_start = 640,
2135 .hsync_end = 640 + 16,
2136 .htotal = 640 + 16 + 30 + 114,
2137 .vdisplay = 480,
2138 .vsync_start = 480 + 10,
2139 .vsync_end = 480 + 10 + 3,
2140 .vtotal = 480 + 10 + 3 + 35,
2141 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2142 };
2143
2144 static const struct panel_desc edt_etmv570g2dhu = {
2145 .modes = &edt_etmv570g2dhu_mode,
2146 .num_modes = 1,
2147 .bpc = 6,
2148 .size = {
2149 .width = 115,
2150 .height = 86,
2151 },
2152 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2153 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2154 .connector_type = DRM_MODE_CONNECTOR_DPI,
2155 };
2156
2157 static const struct display_timing eink_vb3300_kca_timing = {
2158 .pixelclock = { 40000000, 40000000, 40000000 },
2159 .hactive = { 334, 334, 334 },
2160 .hfront_porch = { 1, 1, 1 },
2161 .hback_porch = { 1, 1, 1 },
2162 .hsync_len = { 1, 1, 1 },
2163 .vactive = { 1405, 1405, 1405 },
2164 .vfront_porch = { 1, 1, 1 },
2165 .vback_porch = { 1, 1, 1 },
2166 .vsync_len = { 1, 1, 1 },
2167 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2168 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2169 };
2170
2171 static const struct panel_desc eink_vb3300_kca = {
2172 .timings = &eink_vb3300_kca_timing,
2173 .num_timings = 1,
2174 .bpc = 6,
2175 .size = {
2176 .width = 157,
2177 .height = 209,
2178 },
2179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2181 .connector_type = DRM_MODE_CONNECTOR_DPI,
2182 };
2183
2184 static const struct display_timing evervision_vgg644804_timing = {
2185 .pixelclock = { 25175000, 25175000, 25175000 },
2186 .hactive = { 640, 640, 640 },
2187 .hfront_porch = { 16, 16, 16 },
2188 .hback_porch = { 82, 114, 170 },
2189 .hsync_len = { 5, 30, 30 },
2190 .vactive = { 480, 480, 480 },
2191 .vfront_porch = { 10, 10, 10 },
2192 .vback_porch = { 30, 32, 34 },
2193 .vsync_len = { 1, 3, 5 },
2194 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2195 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2196 DISPLAY_FLAGS_SYNC_POSEDGE,
2197 };
2198
2199 static const struct panel_desc evervision_vgg644804 = {
2200 .timings = &evervision_vgg644804_timing,
2201 .num_timings = 1,
2202 .bpc = 8,
2203 .size = {
2204 .width = 115,
2205 .height = 86,
2206 },
2207 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2209 };
2210
2211 static const struct display_timing evervision_vgg804821_timing = {
2212 .pixelclock = { 27600000, 33300000, 50000000 },
2213 .hactive = { 800, 800, 800 },
2214 .hfront_porch = { 40, 66, 70 },
2215 .hback_porch = { 40, 67, 70 },
2216 .hsync_len = { 40, 67, 70 },
2217 .vactive = { 480, 480, 480 },
2218 .vfront_porch = { 6, 10, 10 },
2219 .vback_porch = { 7, 11, 11 },
2220 .vsync_len = { 7, 11, 11 },
2221 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2222 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2223 DISPLAY_FLAGS_SYNC_NEGEDGE,
2224 };
2225
2226 static const struct panel_desc evervision_vgg804821 = {
2227 .timings = &evervision_vgg804821_timing,
2228 .num_timings = 1,
2229 .bpc = 8,
2230 .size = {
2231 .width = 108,
2232 .height = 64,
2233 },
2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2235 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2236 };
2237
2238 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2239 .clock = 32260,
2240 .hdisplay = 800,
2241 .hsync_start = 800 + 168,
2242 .hsync_end = 800 + 168 + 64,
2243 .htotal = 800 + 168 + 64 + 88,
2244 .vdisplay = 480,
2245 .vsync_start = 480 + 37,
2246 .vsync_end = 480 + 37 + 2,
2247 .vtotal = 480 + 37 + 2 + 8,
2248 };
2249
2250 static const struct panel_desc foxlink_fl500wvr00_a0t = {
2251 .modes = &foxlink_fl500wvr00_a0t_mode,
2252 .num_modes = 1,
2253 .bpc = 8,
2254 .size = {
2255 .width = 108,
2256 .height = 65,
2257 },
2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2259 };
2260
2261 static const struct drm_display_mode frida_frd350h54004_modes[] = {
2262 { /* 60 Hz */
2263 .clock = 6000,
2264 .hdisplay = 320,
2265 .hsync_start = 320 + 44,
2266 .hsync_end = 320 + 44 + 16,
2267 .htotal = 320 + 44 + 16 + 20,
2268 .vdisplay = 240,
2269 .vsync_start = 240 + 2,
2270 .vsync_end = 240 + 2 + 6,
2271 .vtotal = 240 + 2 + 6 + 2,
2272 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2273 },
2274 { /* 50 Hz */
2275 .clock = 5400,
2276 .hdisplay = 320,
2277 .hsync_start = 320 + 56,
2278 .hsync_end = 320 + 56 + 16,
2279 .htotal = 320 + 56 + 16 + 40,
2280 .vdisplay = 240,
2281 .vsync_start = 240 + 2,
2282 .vsync_end = 240 + 2 + 6,
2283 .vtotal = 240 + 2 + 6 + 2,
2284 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2285 },
2286 };
2287
2288 static const struct panel_desc frida_frd350h54004 = {
2289 .modes = frida_frd350h54004_modes,
2290 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2291 .bpc = 8,
2292 .size = {
2293 .width = 77,
2294 .height = 64,
2295 },
2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2298 .connector_type = DRM_MODE_CONNECTOR_DPI,
2299 };
2300
2301 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2302 .clock = 67185,
2303 .hdisplay = 800,
2304 .hsync_start = 800 + 20,
2305 .hsync_end = 800 + 20 + 24,
2306 .htotal = 800 + 20 + 24 + 20,
2307 .vdisplay = 1280,
2308 .vsync_start = 1280 + 4,
2309 .vsync_end = 1280 + 4 + 8,
2310 .vtotal = 1280 + 4 + 8 + 4,
2311 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2312 };
2313
2314 static const struct panel_desc friendlyarm_hd702e = {
2315 .modes = &friendlyarm_hd702e_mode,
2316 .num_modes = 1,
2317 .size = {
2318 .width = 94,
2319 .height = 151,
2320 },
2321 };
2322
2323 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2324 .clock = 9000,
2325 .hdisplay = 480,
2326 .hsync_start = 480 + 5,
2327 .hsync_end = 480 + 5 + 1,
2328 .htotal = 480 + 5 + 1 + 40,
2329 .vdisplay = 272,
2330 .vsync_start = 272 + 8,
2331 .vsync_end = 272 + 8 + 1,
2332 .vtotal = 272 + 8 + 1 + 8,
2333 };
2334
2335 static const struct panel_desc giantplus_gpg482739qs5 = {
2336 .modes = &giantplus_gpg482739qs5_mode,
2337 .num_modes = 1,
2338 .bpc = 8,
2339 .size = {
2340 .width = 95,
2341 .height = 54,
2342 },
2343 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2344 };
2345
2346 static const struct display_timing giantplus_gpm940b0_timing = {
2347 .pixelclock = { 13500000, 27000000, 27500000 },
2348 .hactive = { 320, 320, 320 },
2349 .hfront_porch = { 14, 686, 718 },
2350 .hback_porch = { 50, 70, 255 },
2351 .hsync_len = { 1, 1, 1 },
2352 .vactive = { 240, 240, 240 },
2353 .vfront_porch = { 1, 1, 179 },
2354 .vback_porch = { 1, 21, 31 },
2355 .vsync_len = { 1, 1, 6 },
2356 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2357 };
2358
2359 static const struct panel_desc giantplus_gpm940b0 = {
2360 .timings = &giantplus_gpm940b0_timing,
2361 .num_timings = 1,
2362 .bpc = 8,
2363 .size = {
2364 .width = 60,
2365 .height = 45,
2366 },
2367 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2368 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2369 };
2370
2371 static const struct display_timing hannstar_hsd070pww1_timing = {
2372 .pixelclock = { 64300000, 71100000, 82000000 },
2373 .hactive = { 1280, 1280, 1280 },
2374 .hfront_porch = { 1, 1, 10 },
2375 .hback_porch = { 1, 1, 10 },
2376 /*
2377 * According to the data sheet, the minimum horizontal blanking interval
2378 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2379 * minimum working horizontal blanking interval to be 60 clocks.
2380 */
2381 .hsync_len = { 58, 158, 661 },
2382 .vactive = { 800, 800, 800 },
2383 .vfront_porch = { 1, 1, 10 },
2384 .vback_porch = { 1, 1, 10 },
2385 .vsync_len = { 1, 21, 203 },
2386 .flags = DISPLAY_FLAGS_DE_HIGH,
2387 };
2388
2389 static const struct panel_desc hannstar_hsd070pww1 = {
2390 .timings = &hannstar_hsd070pww1_timing,
2391 .num_timings = 1,
2392 .bpc = 6,
2393 .size = {
2394 .width = 151,
2395 .height = 94,
2396 },
2397 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2398 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2399 };
2400
2401 static const struct display_timing hannstar_hsd100pxn1_timing = {
2402 .pixelclock = { 55000000, 65000000, 75000000 },
2403 .hactive = { 1024, 1024, 1024 },
2404 .hfront_porch = { 40, 40, 40 },
2405 .hback_porch = { 220, 220, 220 },
2406 .hsync_len = { 20, 60, 100 },
2407 .vactive = { 768, 768, 768 },
2408 .vfront_porch = { 7, 7, 7 },
2409 .vback_porch = { 21, 21, 21 },
2410 .vsync_len = { 10, 10, 10 },
2411 .flags = DISPLAY_FLAGS_DE_HIGH,
2412 };
2413
2414 static const struct panel_desc hannstar_hsd100pxn1 = {
2415 .timings = &hannstar_hsd100pxn1_timing,
2416 .num_timings = 1,
2417 .bpc = 6,
2418 .size = {
2419 .width = 203,
2420 .height = 152,
2421 },
2422 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2423 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2424 };
2425
2426 static const struct display_timing hannstar_hsd101pww2_timing = {
2427 .pixelclock = { 64300000, 71100000, 82000000 },
2428 .hactive = { 1280, 1280, 1280 },
2429 .hfront_porch = { 1, 1, 10 },
2430 .hback_porch = { 1, 1, 10 },
2431 .hsync_len = { 58, 158, 661 },
2432 .vactive = { 800, 800, 800 },
2433 .vfront_porch = { 1, 1, 10 },
2434 .vback_porch = { 1, 1, 10 },
2435 .vsync_len = { 1, 21, 203 },
2436 .flags = DISPLAY_FLAGS_DE_HIGH,
2437 };
2438
2439 static const struct panel_desc hannstar_hsd101pww2 = {
2440 .timings = &hannstar_hsd101pww2_timing,
2441 .num_timings = 1,
2442 .bpc = 8,
2443 .size = {
2444 .width = 217,
2445 .height = 136,
2446 },
2447 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2448 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2449 };
2450
2451 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2452 .clock = 33333,
2453 .hdisplay = 800,
2454 .hsync_start = 800 + 85,
2455 .hsync_end = 800 + 85 + 86,
2456 .htotal = 800 + 85 + 86 + 85,
2457 .vdisplay = 480,
2458 .vsync_start = 480 + 16,
2459 .vsync_end = 480 + 16 + 13,
2460 .vtotal = 480 + 16 + 13 + 16,
2461 };
2462
2463 static const struct panel_desc hitachi_tx23d38vm0caa = {
2464 .modes = &hitachi_tx23d38vm0caa_mode,
2465 .num_modes = 1,
2466 .bpc = 6,
2467 .size = {
2468 .width = 195,
2469 .height = 117,
2470 },
2471 .delay = {
2472 .enable = 160,
2473 .disable = 160,
2474 },
2475 };
2476
2477 static const struct drm_display_mode innolux_at043tn24_mode = {
2478 .clock = 9000,
2479 .hdisplay = 480,
2480 .hsync_start = 480 + 2,
2481 .hsync_end = 480 + 2 + 41,
2482 .htotal = 480 + 2 + 41 + 2,
2483 .vdisplay = 272,
2484 .vsync_start = 272 + 2,
2485 .vsync_end = 272 + 2 + 10,
2486 .vtotal = 272 + 2 + 10 + 2,
2487 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2488 };
2489
2490 static const struct panel_desc innolux_at043tn24 = {
2491 .modes = &innolux_at043tn24_mode,
2492 .num_modes = 1,
2493 .bpc = 8,
2494 .size = {
2495 .width = 95,
2496 .height = 54,
2497 },
2498 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2499 .connector_type = DRM_MODE_CONNECTOR_DPI,
2500 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2501 };
2502
2503 static const struct drm_display_mode innolux_at070tn92_mode = {
2504 .clock = 33333,
2505 .hdisplay = 800,
2506 .hsync_start = 800 + 210,
2507 .hsync_end = 800 + 210 + 20,
2508 .htotal = 800 + 210 + 20 + 46,
2509 .vdisplay = 480,
2510 .vsync_start = 480 + 22,
2511 .vsync_end = 480 + 22 + 10,
2512 .vtotal = 480 + 22 + 23 + 10,
2513 };
2514
2515 static const struct panel_desc innolux_at070tn92 = {
2516 .modes = &innolux_at070tn92_mode,
2517 .num_modes = 1,
2518 .size = {
2519 .width = 154,
2520 .height = 86,
2521 },
2522 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2523 };
2524
2525 static const struct display_timing innolux_g070ace_l01_timing = {
2526 .pixelclock = { 25200000, 35000000, 35700000 },
2527 .hactive = { 800, 800, 800 },
2528 .hfront_porch = { 30, 32, 87 },
2529 .hback_porch = { 30, 32, 87 },
2530 .hsync_len = { 1, 1, 1 },
2531 .vactive = { 480, 480, 480 },
2532 .vfront_porch = { 3, 3, 3 },
2533 .vback_porch = { 13, 13, 13 },
2534 .vsync_len = { 1, 1, 4 },
2535 .flags = DISPLAY_FLAGS_DE_HIGH,
2536 };
2537
2538 static const struct panel_desc innolux_g070ace_l01 = {
2539 .timings = &innolux_g070ace_l01_timing,
2540 .num_timings = 1,
2541 .bpc = 8,
2542 .size = {
2543 .width = 152,
2544 .height = 91,
2545 },
2546 .delay = {
2547 .prepare = 10,
2548 .enable = 50,
2549 .disable = 50,
2550 .unprepare = 500,
2551 },
2552 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2553 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2554 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2555 };
2556
2557 static const struct display_timing innolux_g070y2_l01_timing = {
2558 .pixelclock = { 28000000, 29500000, 32000000 },
2559 .hactive = { 800, 800, 800 },
2560 .hfront_porch = { 61, 91, 141 },
2561 .hback_porch = { 60, 90, 140 },
2562 .hsync_len = { 12, 12, 12 },
2563 .vactive = { 480, 480, 480 },
2564 .vfront_porch = { 4, 9, 30 },
2565 .vback_porch = { 4, 8, 28 },
2566 .vsync_len = { 2, 2, 2 },
2567 .flags = DISPLAY_FLAGS_DE_HIGH,
2568 };
2569
2570 static const struct panel_desc innolux_g070y2_l01 = {
2571 .timings = &innolux_g070y2_l01_timing,
2572 .num_timings = 1,
2573 .bpc = 8,
2574 .size = {
2575 .width = 152,
2576 .height = 91,
2577 },
2578 .delay = {
2579 .prepare = 10,
2580 .enable = 100,
2581 .disable = 100,
2582 .unprepare = 800,
2583 },
2584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2585 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2586 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2587 };
2588
2589 static const struct display_timing innolux_g070ace_lh3_timing = {
2590 .pixelclock = { 25200000, 25400000, 35700000 },
2591 .hactive = { 800, 800, 800 },
2592 .hfront_porch = { 30, 32, 87 },
2593 .hback_porch = { 29, 31, 86 },
2594 .hsync_len = { 1, 1, 1 },
2595 .vactive = { 480, 480, 480 },
2596 .vfront_porch = { 4, 5, 65 },
2597 .vback_porch = { 3, 4, 65 },
2598 .vsync_len = { 1, 1, 1 },
2599 .flags = DISPLAY_FLAGS_DE_HIGH,
2600 };
2601
2602 static const struct panel_desc innolux_g070ace_lh3 = {
2603 .timings = &innolux_g070ace_lh3_timing,
2604 .num_timings = 1,
2605 .bpc = 8,
2606 .size = {
2607 .width = 152,
2608 .height = 91,
2609 },
2610 .delay = {
2611 .prepare = 10,
2612 .enable = 450,
2613 .disable = 200,
2614 .unprepare = 510,
2615 },
2616 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2617 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2618 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2619 };
2620
2621 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2622 .clock = 33333,
2623 .hdisplay = 800,
2624 .hsync_start = 800 + 210,
2625 .hsync_end = 800 + 210 + 20,
2626 .htotal = 800 + 210 + 20 + 46,
2627 .vdisplay = 480,
2628 .vsync_start = 480 + 22,
2629 .vsync_end = 480 + 22 + 10,
2630 .vtotal = 480 + 22 + 23 + 10,
2631 };
2632
2633 static const struct panel_desc innolux_g070y2_t02 = {
2634 .modes = &innolux_g070y2_t02_mode,
2635 .num_modes = 1,
2636 .bpc = 8,
2637 .size = {
2638 .width = 152,
2639 .height = 92,
2640 },
2641 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2642 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2643 .connector_type = DRM_MODE_CONNECTOR_DPI,
2644 };
2645
2646 static const struct display_timing innolux_g101ice_l01_timing = {
2647 .pixelclock = { 60400000, 71100000, 74700000 },
2648 .hactive = { 1280, 1280, 1280 },
2649 .hfront_porch = { 30, 60, 70 },
2650 .hback_porch = { 30, 60, 70 },
2651 .hsync_len = { 22, 40, 60 },
2652 .vactive = { 800, 800, 800 },
2653 .vfront_porch = { 3, 8, 14 },
2654 .vback_porch = { 3, 8, 14 },
2655 .vsync_len = { 4, 7, 12 },
2656 .flags = DISPLAY_FLAGS_DE_HIGH,
2657 };
2658
2659 static const struct panel_desc innolux_g101ice_l01 = {
2660 .timings = &innolux_g101ice_l01_timing,
2661 .num_timings = 1,
2662 .bpc = 8,
2663 .size = {
2664 .width = 217,
2665 .height = 135,
2666 },
2667 .delay = {
2668 .enable = 200,
2669 .disable = 200,
2670 },
2671 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2672 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2673 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2674 };
2675
2676 static const struct display_timing innolux_g121i1_l01_timing = {
2677 .pixelclock = { 67450000, 71000000, 74550000 },
2678 .hactive = { 1280, 1280, 1280 },
2679 .hfront_porch = { 40, 80, 160 },
2680 .hback_porch = { 39, 79, 159 },
2681 .hsync_len = { 1, 1, 1 },
2682 .vactive = { 800, 800, 800 },
2683 .vfront_porch = { 5, 11, 100 },
2684 .vback_porch = { 4, 11, 99 },
2685 .vsync_len = { 1, 1, 1 },
2686 };
2687
2688 static const struct panel_desc innolux_g121i1_l01 = {
2689 .timings = &innolux_g121i1_l01_timing,
2690 .num_timings = 1,
2691 .bpc = 6,
2692 .size = {
2693 .width = 261,
2694 .height = 163,
2695 },
2696 .delay = {
2697 .enable = 200,
2698 .disable = 20,
2699 },
2700 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2701 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2702 };
2703
2704 static const struct display_timing innolux_g121x1_l03_timings = {
2705 .pixelclock = { 57500000, 64900000, 74400000 },
2706 .hactive = { 1024, 1024, 1024 },
2707 .hfront_porch = { 90, 140, 190 },
2708 .hback_porch = { 90, 140, 190 },
2709 .hsync_len = { 36, 40, 60 },
2710 .vactive = { 768, 768, 768 },
2711 .vfront_porch = { 2, 15, 30 },
2712 .vback_porch = { 2, 15, 30 },
2713 .vsync_len = { 2, 8, 20 },
2714 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2715 };
2716
2717 static const struct panel_desc innolux_g121x1_l03 = {
2718 .timings = &innolux_g121x1_l03_timings,
2719 .num_timings = 1,
2720 .bpc = 6,
2721 .size = {
2722 .width = 246,
2723 .height = 185,
2724 },
2725 .delay = {
2726 .enable = 200,
2727 .unprepare = 200,
2728 .disable = 400,
2729 },
2730 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2731 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2732 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2733 };
2734
2735 static const struct panel_desc innolux_g121xce_l01 = {
2736 .timings = &innolux_g121x1_l03_timings,
2737 .num_timings = 1,
2738 .bpc = 8,
2739 .size = {
2740 .width = 246,
2741 .height = 185,
2742 },
2743 .delay = {
2744 .enable = 200,
2745 .unprepare = 200,
2746 .disable = 400,
2747 },
2748 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2749 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2750 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2751 };
2752
2753 static const struct display_timing innolux_g156hce_l01_timings = {
2754 .pixelclock = { 120000000, 141860000, 150000000 },
2755 .hactive = { 1920, 1920, 1920 },
2756 .hfront_porch = { 80, 90, 100 },
2757 .hback_porch = { 80, 90, 100 },
2758 .hsync_len = { 20, 30, 30 },
2759 .vactive = { 1080, 1080, 1080 },
2760 .vfront_porch = { 3, 10, 20 },
2761 .vback_porch = { 3, 10, 20 },
2762 .vsync_len = { 4, 10, 10 },
2763 };
2764
2765 static const struct panel_desc innolux_g156hce_l01 = {
2766 .timings = &innolux_g156hce_l01_timings,
2767 .num_timings = 1,
2768 .bpc = 8,
2769 .size = {
2770 .width = 344,
2771 .height = 194,
2772 },
2773 .delay = {
2774 .prepare = 1, /* T1+T2 */
2775 .enable = 450, /* T5 */
2776 .disable = 200, /* T6 */
2777 .unprepare = 10, /* T3+T7 */
2778 },
2779 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2780 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2781 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2782 };
2783
2784 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2785 .clock = 69300,
2786 .hdisplay = 1366,
2787 .hsync_start = 1366 + 16,
2788 .hsync_end = 1366 + 16 + 34,
2789 .htotal = 1366 + 16 + 34 + 50,
2790 .vdisplay = 768,
2791 .vsync_start = 768 + 2,
2792 .vsync_end = 768 + 2 + 6,
2793 .vtotal = 768 + 2 + 6 + 12,
2794 };
2795
2796 static const struct panel_desc innolux_n156bge_l21 = {
2797 .modes = &innolux_n156bge_l21_mode,
2798 .num_modes = 1,
2799 .bpc = 6,
2800 .size = {
2801 .width = 344,
2802 .height = 193,
2803 },
2804 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2805 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2806 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2807 };
2808
2809 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2810 .clock = 51501,
2811 .hdisplay = 1024,
2812 .hsync_start = 1024 + 128,
2813 .hsync_end = 1024 + 128 + 64,
2814 .htotal = 1024 + 128 + 64 + 128,
2815 .vdisplay = 600,
2816 .vsync_start = 600 + 16,
2817 .vsync_end = 600 + 16 + 4,
2818 .vtotal = 600 + 16 + 4 + 16,
2819 };
2820
2821 static const struct panel_desc innolux_zj070na_01p = {
2822 .modes = &innolux_zj070na_01p_mode,
2823 .num_modes = 1,
2824 .bpc = 6,
2825 .size = {
2826 .width = 154,
2827 .height = 90,
2828 },
2829 };
2830
2831 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2832 .pixelclock = { 5580000, 5850000, 6200000 },
2833 .hactive = { 320, 320, 320 },
2834 .hfront_porch = { 30, 30, 30 },
2835 .hback_porch = { 30, 30, 30 },
2836 .hsync_len = { 1, 5, 17 },
2837 .vactive = { 240, 240, 240 },
2838 .vfront_porch = { 6, 6, 6 },
2839 .vback_porch = { 5, 5, 5 },
2840 .vsync_len = { 1, 2, 11 },
2841 .flags = DISPLAY_FLAGS_DE_HIGH,
2842 };
2843
2844 static const struct panel_desc koe_tx14d24vm1bpa = {
2845 .timings = &koe_tx14d24vm1bpa_timing,
2846 .num_timings = 1,
2847 .bpc = 6,
2848 .size = {
2849 .width = 115,
2850 .height = 86,
2851 },
2852 };
2853
2854 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2855 .pixelclock = { 151820000, 156720000, 159780000 },
2856 .hactive = { 1920, 1920, 1920 },
2857 .hfront_porch = { 105, 130, 142 },
2858 .hback_porch = { 45, 70, 82 },
2859 .hsync_len = { 30, 30, 30 },
2860 .vactive = { 1200, 1200, 1200},
2861 .vfront_porch = { 3, 5, 10 },
2862 .vback_porch = { 2, 5, 10 },
2863 .vsync_len = { 5, 5, 5 },
2864 .flags = DISPLAY_FLAGS_DE_HIGH,
2865 };
2866
2867 static const struct panel_desc koe_tx26d202vm0bwa = {
2868 .timings = &koe_tx26d202vm0bwa_timing,
2869 .num_timings = 1,
2870 .bpc = 8,
2871 .size = {
2872 .width = 217,
2873 .height = 136,
2874 },
2875 .delay = {
2876 .prepare = 1000,
2877 .enable = 1000,
2878 .unprepare = 1000,
2879 .disable = 1000,
2880 },
2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2882 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2883 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2884 };
2885
2886 static const struct display_timing koe_tx31d200vm0baa_timing = {
2887 .pixelclock = { 39600000, 43200000, 48000000 },
2888 .hactive = { 1280, 1280, 1280 },
2889 .hfront_porch = { 16, 36, 56 },
2890 .hback_porch = { 16, 36, 56 },
2891 .hsync_len = { 8, 8, 8 },
2892 .vactive = { 480, 480, 480 },
2893 .vfront_porch = { 6, 21, 33 },
2894 .vback_porch = { 6, 21, 33 },
2895 .vsync_len = { 8, 8, 8 },
2896 .flags = DISPLAY_FLAGS_DE_HIGH,
2897 };
2898
2899 static const struct panel_desc koe_tx31d200vm0baa = {
2900 .timings = &koe_tx31d200vm0baa_timing,
2901 .num_timings = 1,
2902 .bpc = 6,
2903 .size = {
2904 .width = 292,
2905 .height = 109,
2906 },
2907 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2908 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2909 };
2910
2911 static const struct display_timing kyo_tcg121xglp_timing = {
2912 .pixelclock = { 52000000, 65000000, 71000000 },
2913 .hactive = { 1024, 1024, 1024 },
2914 .hfront_porch = { 2, 2, 2 },
2915 .hback_porch = { 2, 2, 2 },
2916 .hsync_len = { 86, 124, 244 },
2917 .vactive = { 768, 768, 768 },
2918 .vfront_porch = { 2, 2, 2 },
2919 .vback_porch = { 2, 2, 2 },
2920 .vsync_len = { 6, 34, 73 },
2921 .flags = DISPLAY_FLAGS_DE_HIGH,
2922 };
2923
2924 static const struct panel_desc kyo_tcg121xglp = {
2925 .timings = &kyo_tcg121xglp_timing,
2926 .num_timings = 1,
2927 .bpc = 8,
2928 .size = {
2929 .width = 246,
2930 .height = 184,
2931 },
2932 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2933 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2934 };
2935
2936 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2937 .clock = 7000,
2938 .hdisplay = 320,
2939 .hsync_start = 320 + 20,
2940 .hsync_end = 320 + 20 + 30,
2941 .htotal = 320 + 20 + 30 + 38,
2942 .vdisplay = 240,
2943 .vsync_start = 240 + 4,
2944 .vsync_end = 240 + 4 + 3,
2945 .vtotal = 240 + 4 + 3 + 15,
2946 };
2947
2948 static const struct panel_desc lemaker_bl035_rgb_002 = {
2949 .modes = &lemaker_bl035_rgb_002_mode,
2950 .num_modes = 1,
2951 .size = {
2952 .width = 70,
2953 .height = 52,
2954 },
2955 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2956 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2957 };
2958
2959 static const struct display_timing lg_lb070wv8_timing = {
2960 .pixelclock = { 31950000, 33260000, 34600000 },
2961 .hactive = { 800, 800, 800 },
2962 .hfront_porch = { 88, 88, 88 },
2963 .hback_porch = { 88, 88, 88 },
2964 .hsync_len = { 80, 80, 80 },
2965 .vactive = { 480, 480, 480 },
2966 .vfront_porch = { 10, 10, 10 },
2967 .vback_porch = { 10, 10, 10 },
2968 .vsync_len = { 25, 25, 25 },
2969 };
2970
2971 static const struct panel_desc lg_lb070wv8 = {
2972 .timings = &lg_lb070wv8_timing,
2973 .num_timings = 1,
2974 .bpc = 8,
2975 .size = {
2976 .width = 151,
2977 .height = 91,
2978 },
2979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2980 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2981 };
2982
2983 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
2984 .clock = 155127,
2985 .hdisplay = 1920,
2986 .hsync_start = 1920 + 128,
2987 .hsync_end = 1920 + 128 + 20,
2988 .htotal = 1920 + 128 + 20 + 12,
2989 .vdisplay = 1200,
2990 .vsync_start = 1200 + 19,
2991 .vsync_end = 1200 + 19 + 4,
2992 .vtotal = 1200 + 19 + 4 + 20,
2993 };
2994
2995 static const struct panel_desc lincolntech_lcd185_101ct = {
2996 .modes = &lincolntech_lcd185_101ct_mode,
2997 .bpc = 8,
2998 .num_modes = 1,
2999 .size = {
3000 .width = 217,
3001 .height = 136,
3002 },
3003 .delay = {
3004 .prepare = 50,
3005 .disable = 50,
3006 },
3007 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3008 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3009 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3010 };
3011
3012 static const struct display_timing logictechno_lt161010_2nh_timing = {
3013 .pixelclock = { 26400000, 33300000, 46800000 },
3014 .hactive = { 800, 800, 800 },
3015 .hfront_porch = { 16, 210, 354 },
3016 .hback_porch = { 46, 46, 46 },
3017 .hsync_len = { 1, 20, 40 },
3018 .vactive = { 480, 480, 480 },
3019 .vfront_porch = { 7, 22, 147 },
3020 .vback_porch = { 23, 23, 23 },
3021 .vsync_len = { 1, 10, 20 },
3022 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3023 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3024 DISPLAY_FLAGS_SYNC_POSEDGE,
3025 };
3026
3027 static const struct panel_desc logictechno_lt161010_2nh = {
3028 .timings = &logictechno_lt161010_2nh_timing,
3029 .num_timings = 1,
3030 .bpc = 6,
3031 .size = {
3032 .width = 154,
3033 .height = 86,
3034 },
3035 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3036 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3037 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3038 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3039 .connector_type = DRM_MODE_CONNECTOR_DPI,
3040 };
3041
3042 static const struct display_timing logictechno_lt170410_2whc_timing = {
3043 .pixelclock = { 68900000, 71100000, 73400000 },
3044 .hactive = { 1280, 1280, 1280 },
3045 .hfront_porch = { 23, 60, 71 },
3046 .hback_porch = { 23, 60, 71 },
3047 .hsync_len = { 15, 40, 47 },
3048 .vactive = { 800, 800, 800 },
3049 .vfront_porch = { 5, 7, 10 },
3050 .vback_porch = { 5, 7, 10 },
3051 .vsync_len = { 6, 9, 12 },
3052 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3053 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3054 DISPLAY_FLAGS_SYNC_POSEDGE,
3055 };
3056
3057 static const struct panel_desc logictechno_lt170410_2whc = {
3058 .timings = &logictechno_lt170410_2whc_timing,
3059 .num_timings = 1,
3060 .bpc = 8,
3061 .size = {
3062 .width = 217,
3063 .height = 136,
3064 },
3065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3067 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3068 };
3069
3070 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
3071 .clock = 33000,
3072 .hdisplay = 800,
3073 .hsync_start = 800 + 112,
3074 .hsync_end = 800 + 112 + 3,
3075 .htotal = 800 + 112 + 3 + 85,
3076 .vdisplay = 480,
3077 .vsync_start = 480 + 38,
3078 .vsync_end = 480 + 38 + 3,
3079 .vtotal = 480 + 38 + 3 + 29,
3080 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3081 };
3082
3083 static const struct panel_desc logictechno_lttd800480070_l2rt = {
3084 .modes = &logictechno_lttd800480070_l2rt_mode,
3085 .num_modes = 1,
3086 .bpc = 8,
3087 .size = {
3088 .width = 154,
3089 .height = 86,
3090 },
3091 .delay = {
3092 .prepare = 45,
3093 .enable = 100,
3094 .disable = 100,
3095 .unprepare = 45
3096 },
3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3098 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3099 .connector_type = DRM_MODE_CONNECTOR_DPI,
3100 };
3101
3102 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3103 .clock = 33000,
3104 .hdisplay = 800,
3105 .hsync_start = 800 + 154,
3106 .hsync_end = 800 + 154 + 3,
3107 .htotal = 800 + 154 + 3 + 43,
3108 .vdisplay = 480,
3109 .vsync_start = 480 + 47,
3110 .vsync_end = 480 + 47 + 3,
3111 .vtotal = 480 + 47 + 3 + 20,
3112 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3113 };
3114
3115 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3116 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3117 .num_modes = 1,
3118 .bpc = 8,
3119 .size = {
3120 .width = 154,
3121 .height = 86,
3122 },
3123 .delay = {
3124 .prepare = 45,
3125 .enable = 100,
3126 .disable = 100,
3127 .unprepare = 45
3128 },
3129 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3130 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3131 .connector_type = DRM_MODE_CONNECTOR_DPI,
3132 };
3133
3134 static const struct drm_display_mode logicpd_type_28_mode = {
3135 .clock = 9107,
3136 .hdisplay = 480,
3137 .hsync_start = 480 + 3,
3138 .hsync_end = 480 + 3 + 42,
3139 .htotal = 480 + 3 + 42 + 2,
3140
3141 .vdisplay = 272,
3142 .vsync_start = 272 + 2,
3143 .vsync_end = 272 + 2 + 11,
3144 .vtotal = 272 + 2 + 11 + 3,
3145 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3146 };
3147
3148 static const struct panel_desc logicpd_type_28 = {
3149 .modes = &logicpd_type_28_mode,
3150 .num_modes = 1,
3151 .bpc = 8,
3152 .size = {
3153 .width = 105,
3154 .height = 67,
3155 },
3156 .delay = {
3157 .prepare = 200,
3158 .enable = 200,
3159 .unprepare = 200,
3160 .disable = 200,
3161 },
3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3163 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3164 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
3165 .connector_type = DRM_MODE_CONNECTOR_DPI,
3166 };
3167
3168 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = {
3169 .clock = 150275,
3170 .hdisplay = 1920,
3171 .hsync_start = 1920 + 32,
3172 .hsync_end = 1920 + 32 + 52,
3173 .htotal = 1920 + 32 + 52 + 24,
3174 .vdisplay = 1200,
3175 .vsync_start = 1200 + 24,
3176 .vsync_end = 1200 + 24 + 8,
3177 .vtotal = 1200 + 24 + 8 + 3,
3178 };
3179
3180 static const struct panel_desc microtips_mf_101hiebcaf0_c = {
3181 .modes = µtips_mf_101hiebcaf0_c_mode,
3182 .bpc = 8,
3183 .num_modes = 1,
3184 .size = {
3185 .width = 217,
3186 .height = 136,
3187 },
3188 .delay = {
3189 .prepare = 50,
3190 .disable = 50,
3191 },
3192 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3194 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3195 };
3196
3197 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = {
3198 .clock = 93301,
3199 .hdisplay = 1920,
3200 .hsync_start = 1920 + 72,
3201 .hsync_end = 1920 + 72 + 72,
3202 .htotal = 1920 + 72 + 72 + 72,
3203 .vdisplay = 720,
3204 .vsync_start = 720 + 3,
3205 .vsync_end = 720 + 3 + 3,
3206 .vtotal = 720 + 3 + 3 + 2,
3207 };
3208
3209 static const struct panel_desc microtips_mf_103hieb0ga0 = {
3210 .modes = µtips_mf_103hieb0ga0_mode,
3211 .bpc = 8,
3212 .num_modes = 1,
3213 .size = {
3214 .width = 244,
3215 .height = 92,
3216 },
3217 .delay = {
3218 .prepare = 50,
3219 .disable = 50,
3220 },
3221 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3222 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3223 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3224 };
3225
3226 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3227 .clock = 30400,
3228 .hdisplay = 800,
3229 .hsync_start = 800 + 0,
3230 .hsync_end = 800 + 1,
3231 .htotal = 800 + 0 + 1 + 160,
3232 .vdisplay = 480,
3233 .vsync_start = 480 + 0,
3234 .vsync_end = 480 + 48 + 1,
3235 .vtotal = 480 + 48 + 1 + 0,
3236 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3237 };
3238
3239 static const struct panel_desc mitsubishi_aa070mc01 = {
3240 .modes = &mitsubishi_aa070mc01_mode,
3241 .num_modes = 1,
3242 .bpc = 8,
3243 .size = {
3244 .width = 152,
3245 .height = 91,
3246 },
3247
3248 .delay = {
3249 .enable = 200,
3250 .unprepare = 200,
3251 .disable = 400,
3252 },
3253 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3254 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3255 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3256 };
3257
3258 static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3259 .clock = 56234,
3260 .hdisplay = 1024,
3261 .hsync_start = 1024 + 24,
3262 .hsync_end = 1024 + 24 + 63,
3263 .htotal = 1024 + 24 + 63 + 1,
3264 .vdisplay = 768,
3265 .vsync_start = 768 + 3,
3266 .vsync_end = 768 + 3 + 6,
3267 .vtotal = 768 + 3 + 6 + 1,
3268 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3269 };
3270
3271 static const struct panel_desc mitsubishi_aa084xe01 = {
3272 .modes = &mitsubishi_aa084xe01_mode,
3273 .num_modes = 1,
3274 .bpc = 8,
3275 .size = {
3276 .width = 1024,
3277 .height = 768,
3278 },
3279 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3280 .connector_type = DRM_MODE_CONNECTOR_DPI,
3281 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3282 };
3283
3284 static const struct display_timing multi_inno_mi0700a2t_30_timing = {
3285 .pixelclock = { 26400000, 33000000, 46800000 },
3286 .hactive = { 800, 800, 800 },
3287 .hfront_porch = { 16, 204, 354 },
3288 .hback_porch = { 46, 46, 46 },
3289 .hsync_len = { 1, 6, 40 },
3290 .vactive = { 480, 480, 480 },
3291 .vfront_porch = { 7, 22, 147 },
3292 .vback_porch = { 23, 23, 23 },
3293 .vsync_len = { 1, 3, 20 },
3294 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3295 DISPLAY_FLAGS_DE_HIGH,
3296 };
3297
3298 static const struct panel_desc multi_inno_mi0700a2t_30 = {
3299 .timings = &multi_inno_mi0700a2t_30_timing,
3300 .num_timings = 1,
3301 .bpc = 6,
3302 .size = {
3303 .width = 153,
3304 .height = 92,
3305 },
3306 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3307 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3308 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3309 };
3310
3311 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3312 .pixelclock = { 29000000, 33000000, 38000000 },
3313 .hactive = { 800, 800, 800 },
3314 .hfront_porch = { 180, 210, 240 },
3315 .hback_porch = { 16, 16, 16 },
3316 .hsync_len = { 30, 30, 30 },
3317 .vactive = { 480, 480, 480 },
3318 .vfront_porch = { 12, 22, 32 },
3319 .vback_porch = { 10, 10, 10 },
3320 .vsync_len = { 13, 13, 13 },
3321 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3322 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3323 DISPLAY_FLAGS_SYNC_POSEDGE,
3324 };
3325
3326 static const struct panel_desc multi_inno_mi0700s4t_6 = {
3327 .timings = &multi_inno_mi0700s4t_6_timing,
3328 .num_timings = 1,
3329 .bpc = 8,
3330 .size = {
3331 .width = 154,
3332 .height = 86,
3333 },
3334 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3335 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3336 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3337 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3338 .connector_type = DRM_MODE_CONNECTOR_DPI,
3339 };
3340
3341 static const struct display_timing multi_inno_mi0800ft_9_timing = {
3342 .pixelclock = { 32000000, 40000000, 50000000 },
3343 .hactive = { 800, 800, 800 },
3344 .hfront_porch = { 16, 210, 354 },
3345 .hback_porch = { 6, 26, 45 },
3346 .hsync_len = { 1, 20, 40 },
3347 .vactive = { 600, 600, 600 },
3348 .vfront_porch = { 1, 12, 77 },
3349 .vback_porch = { 3, 13, 22 },
3350 .vsync_len = { 1, 10, 20 },
3351 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3352 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3353 DISPLAY_FLAGS_SYNC_POSEDGE,
3354 };
3355
3356 static const struct panel_desc multi_inno_mi0800ft_9 = {
3357 .timings = &multi_inno_mi0800ft_9_timing,
3358 .num_timings = 1,
3359 .bpc = 8,
3360 .size = {
3361 .width = 162,
3362 .height = 122,
3363 },
3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3365 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3366 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3367 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3368 .connector_type = DRM_MODE_CONNECTOR_DPI,
3369 };
3370
3371 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3372 .pixelclock = { 68900000, 70000000, 73400000 },
3373 .hactive = { 1280, 1280, 1280 },
3374 .hfront_porch = { 30, 60, 71 },
3375 .hback_porch = { 30, 60, 71 },
3376 .hsync_len = { 10, 10, 48 },
3377 .vactive = { 800, 800, 800 },
3378 .vfront_porch = { 5, 10, 10 },
3379 .vback_porch = { 5, 10, 10 },
3380 .vsync_len = { 5, 6, 13 },
3381 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3382 DISPLAY_FLAGS_DE_HIGH,
3383 };
3384
3385 static const struct panel_desc multi_inno_mi1010ait_1cp = {
3386 .timings = &multi_inno_mi1010ait_1cp_timing,
3387 .num_timings = 1,
3388 .bpc = 8,
3389 .size = {
3390 .width = 217,
3391 .height = 136,
3392 },
3393 .delay = {
3394 .enable = 50,
3395 .disable = 50,
3396 },
3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3398 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3399 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3400 };
3401
3402 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = {
3403 .pixelclock = { 40800000, 51200000, 67200000 },
3404 .hactive = { 1024, 1024, 1024 },
3405 .hfront_porch = { 30, 110, 130 },
3406 .hback_porch = { 30, 110, 130 },
3407 .hsync_len = { 30, 100, 116 },
3408 .vactive = { 600, 600, 600 },
3409 .vfront_porch = { 4, 13, 80 },
3410 .vback_porch = { 4, 13, 80 },
3411 .vsync_len = { 2, 9, 40 },
3412 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3413 DISPLAY_FLAGS_DE_HIGH,
3414 };
3415
3416 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = {
3417 .timings = &multi_inno_mi1010z1t_1cp11_timing,
3418 .num_timings = 1,
3419 .bpc = 6,
3420 .size = {
3421 .width = 260,
3422 .height = 162,
3423 },
3424 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3425 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3426 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3427 };
3428
3429 static const struct display_timing nec_nl12880bc20_05_timing = {
3430 .pixelclock = { 67000000, 71000000, 75000000 },
3431 .hactive = { 1280, 1280, 1280 },
3432 .hfront_porch = { 2, 30, 30 },
3433 .hback_porch = { 6, 100, 100 },
3434 .hsync_len = { 2, 30, 30 },
3435 .vactive = { 800, 800, 800 },
3436 .vfront_porch = { 5, 5, 5 },
3437 .vback_porch = { 11, 11, 11 },
3438 .vsync_len = { 7, 7, 7 },
3439 };
3440
3441 static const struct panel_desc nec_nl12880bc20_05 = {
3442 .timings = &nec_nl12880bc20_05_timing,
3443 .num_timings = 1,
3444 .bpc = 8,
3445 .size = {
3446 .width = 261,
3447 .height = 163,
3448 },
3449 .delay = {
3450 .enable = 50,
3451 .disable = 50,
3452 },
3453 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3454 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3455 };
3456
3457 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3458 .clock = 10870,
3459 .hdisplay = 480,
3460 .hsync_start = 480 + 2,
3461 .hsync_end = 480 + 2 + 41,
3462 .htotal = 480 + 2 + 41 + 2,
3463 .vdisplay = 272,
3464 .vsync_start = 272 + 2,
3465 .vsync_end = 272 + 2 + 4,
3466 .vtotal = 272 + 2 + 4 + 2,
3467 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3468 };
3469
3470 static const struct panel_desc nec_nl4827hc19_05b = {
3471 .modes = &nec_nl4827hc19_05b_mode,
3472 .num_modes = 1,
3473 .bpc = 8,
3474 .size = {
3475 .width = 95,
3476 .height = 54,
3477 },
3478 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3479 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3480 };
3481
3482 static const struct drm_display_mode netron_dy_e231732_mode = {
3483 .clock = 66000,
3484 .hdisplay = 1024,
3485 .hsync_start = 1024 + 160,
3486 .hsync_end = 1024 + 160 + 70,
3487 .htotal = 1024 + 160 + 70 + 90,
3488 .vdisplay = 600,
3489 .vsync_start = 600 + 127,
3490 .vsync_end = 600 + 127 + 20,
3491 .vtotal = 600 + 127 + 20 + 3,
3492 };
3493
3494 static const struct panel_desc netron_dy_e231732 = {
3495 .modes = &netron_dy_e231732_mode,
3496 .num_modes = 1,
3497 .size = {
3498 .width = 154,
3499 .height = 87,
3500 },
3501 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3502 };
3503
3504 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3505 .clock = 9000,
3506 .hdisplay = 480,
3507 .hsync_start = 480 + 2,
3508 .hsync_end = 480 + 2 + 41,
3509 .htotal = 480 + 2 + 41 + 2,
3510 .vdisplay = 272,
3511 .vsync_start = 272 + 2,
3512 .vsync_end = 272 + 2 + 10,
3513 .vtotal = 272 + 2 + 10 + 2,
3514 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3515 };
3516
3517 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3518 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3519 .num_modes = 1,
3520 .bpc = 8,
3521 .size = {
3522 .width = 95,
3523 .height = 54,
3524 },
3525 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3526 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3527 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3528 .connector_type = DRM_MODE_CONNECTOR_DPI,
3529 };
3530
3531 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3532 .pixelclock = { 130000000, 148350000, 163000000 },
3533 .hactive = { 1920, 1920, 1920 },
3534 .hfront_porch = { 80, 100, 100 },
3535 .hback_porch = { 100, 120, 120 },
3536 .hsync_len = { 50, 60, 60 },
3537 .vactive = { 1080, 1080, 1080 },
3538 .vfront_porch = { 12, 30, 30 },
3539 .vback_porch = { 4, 10, 10 },
3540 .vsync_len = { 4, 5, 5 },
3541 };
3542
3543 static const struct panel_desc nlt_nl192108ac18_02d = {
3544 .timings = &nlt_nl192108ac18_02d_timing,
3545 .num_timings = 1,
3546 .bpc = 8,
3547 .size = {
3548 .width = 344,
3549 .height = 194,
3550 },
3551 .delay = {
3552 .unprepare = 500,
3553 },
3554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3555 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3556 };
3557
3558 static const struct drm_display_mode nvd_9128_mode = {
3559 .clock = 29500,
3560 .hdisplay = 800,
3561 .hsync_start = 800 + 130,
3562 .hsync_end = 800 + 130 + 98,
3563 .htotal = 800 + 0 + 130 + 98,
3564 .vdisplay = 480,
3565 .vsync_start = 480 + 10,
3566 .vsync_end = 480 + 10 + 50,
3567 .vtotal = 480 + 0 + 10 + 50,
3568 };
3569
3570 static const struct panel_desc nvd_9128 = {
3571 .modes = &nvd_9128_mode,
3572 .num_modes = 1,
3573 .bpc = 8,
3574 .size = {
3575 .width = 156,
3576 .height = 88,
3577 },
3578 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3579 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3580 };
3581
3582 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3583 .pixelclock = { 30000000, 30000000, 40000000 },
3584 .hactive = { 800, 800, 800 },
3585 .hfront_porch = { 40, 40, 40 },
3586 .hback_porch = { 40, 40, 40 },
3587 .hsync_len = { 1, 48, 48 },
3588 .vactive = { 480, 480, 480 },
3589 .vfront_porch = { 13, 13, 13 },
3590 .vback_porch = { 29, 29, 29 },
3591 .vsync_len = { 3, 3, 3 },
3592 .flags = DISPLAY_FLAGS_DE_HIGH,
3593 };
3594
3595 static const struct panel_desc okaya_rs800480t_7x0gp = {
3596 .timings = &okaya_rs800480t_7x0gp_timing,
3597 .num_timings = 1,
3598 .bpc = 6,
3599 .size = {
3600 .width = 154,
3601 .height = 87,
3602 },
3603 .delay = {
3604 .prepare = 41,
3605 .enable = 50,
3606 .unprepare = 41,
3607 .disable = 50,
3608 },
3609 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3610 };
3611
3612 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3613 .clock = 9000,
3614 .hdisplay = 480,
3615 .hsync_start = 480 + 5,
3616 .hsync_end = 480 + 5 + 30,
3617 .htotal = 480 + 5 + 30 + 10,
3618 .vdisplay = 272,
3619 .vsync_start = 272 + 8,
3620 .vsync_end = 272 + 8 + 5,
3621 .vtotal = 272 + 8 + 5 + 3,
3622 };
3623
3624 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3625 .modes = &olimex_lcd_olinuxino_43ts_mode,
3626 .num_modes = 1,
3627 .size = {
3628 .width = 95,
3629 .height = 54,
3630 },
3631 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3632 };
3633
3634 static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3635 .pixelclock = { 30000000, 30000000, 50000000 },
3636 .hactive = { 800, 800, 800 },
3637 .hfront_porch = { 1, 40, 255 },
3638 .hback_porch = { 1, 40, 87 },
3639 .hsync_len = { 1, 48, 87 },
3640 .vactive = { 480, 480, 480 },
3641 .vfront_porch = { 1, 13, 255 },
3642 .vback_porch = { 1, 29, 29 },
3643 .vsync_len = { 3, 3, 31 },
3644 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3645 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3646 };
3647
3648 static const struct panel_desc ontat_kd50g21_40nt_a1 = {
3649 .timings = &ontat_kd50g21_40nt_a1_timing,
3650 .num_timings = 1,
3651 .bpc = 8,
3652 .size = {
3653 .width = 108,
3654 .height = 65,
3655 },
3656 .delay = {
3657 .prepare = 147, /* 5 VSDs */
3658 .enable = 147, /* 5 VSDs */
3659 .disable = 88, /* 3 VSDs */
3660 .unprepare = 117, /* 4 VSDs */
3661 },
3662 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3663 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3664 .connector_type = DRM_MODE_CONNECTOR_DPI,
3665 };
3666
3667 /*
3668 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3669 * pixel clocks, but this is the timing that was being used in the Adafruit
3670 * installation instructions.
3671 */
3672 static const struct drm_display_mode ontat_yx700wv03_mode = {
3673 .clock = 29500,
3674 .hdisplay = 800,
3675 .hsync_start = 824,
3676 .hsync_end = 896,
3677 .htotal = 992,
3678 .vdisplay = 480,
3679 .vsync_start = 483,
3680 .vsync_end = 493,
3681 .vtotal = 500,
3682 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3683 };
3684
3685 /*
3686 * Specification at:
3687 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3688 */
3689 static const struct panel_desc ontat_yx700wv03 = {
3690 .modes = &ontat_yx700wv03_mode,
3691 .num_modes = 1,
3692 .bpc = 8,
3693 .size = {
3694 .width = 154,
3695 .height = 83,
3696 },
3697 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3698 };
3699
3700 static const struct drm_display_mode ortustech_com37h3m_mode = {
3701 .clock = 22230,
3702 .hdisplay = 480,
3703 .hsync_start = 480 + 40,
3704 .hsync_end = 480 + 40 + 10,
3705 .htotal = 480 + 40 + 10 + 40,
3706 .vdisplay = 640,
3707 .vsync_start = 640 + 4,
3708 .vsync_end = 640 + 4 + 2,
3709 .vtotal = 640 + 4 + 2 + 4,
3710 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3711 };
3712
3713 static const struct panel_desc ortustech_com37h3m = {
3714 .modes = &ortustech_com37h3m_mode,
3715 .num_modes = 1,
3716 .bpc = 8,
3717 .size = {
3718 .width = 56, /* 56.16mm */
3719 .height = 75, /* 74.88mm */
3720 },
3721 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3722 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3723 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3724 };
3725
3726 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3727 .clock = 25000,
3728 .hdisplay = 480,
3729 .hsync_start = 480 + 10,
3730 .hsync_end = 480 + 10 + 10,
3731 .htotal = 480 + 10 + 10 + 15,
3732 .vdisplay = 800,
3733 .vsync_start = 800 + 3,
3734 .vsync_end = 800 + 3 + 3,
3735 .vtotal = 800 + 3 + 3 + 3,
3736 };
3737
3738 static const struct panel_desc ortustech_com43h4m85ulc = {
3739 .modes = &ortustech_com43h4m85ulc_mode,
3740 .num_modes = 1,
3741 .bpc = 6,
3742 .size = {
3743 .width = 56,
3744 .height = 93,
3745 },
3746 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3747 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3748 .connector_type = DRM_MODE_CONNECTOR_DPI,
3749 };
3750
3751 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3752 .clock = 33000,
3753 .hdisplay = 800,
3754 .hsync_start = 800 + 210,
3755 .hsync_end = 800 + 210 + 30,
3756 .htotal = 800 + 210 + 30 + 16,
3757 .vdisplay = 480,
3758 .vsync_start = 480 + 22,
3759 .vsync_end = 480 + 22 + 13,
3760 .vtotal = 480 + 22 + 13 + 10,
3761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3762 };
3763
3764 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3765 .modes = &osddisplays_osd070t1718_19ts_mode,
3766 .num_modes = 1,
3767 .bpc = 8,
3768 .size = {
3769 .width = 152,
3770 .height = 91,
3771 },
3772 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3773 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3774 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3775 .connector_type = DRM_MODE_CONNECTOR_DPI,
3776 };
3777
3778 static const struct drm_display_mode pda_91_00156_a0_mode = {
3779 .clock = 33300,
3780 .hdisplay = 800,
3781 .hsync_start = 800 + 1,
3782 .hsync_end = 800 + 1 + 64,
3783 .htotal = 800 + 1 + 64 + 64,
3784 .vdisplay = 480,
3785 .vsync_start = 480 + 1,
3786 .vsync_end = 480 + 1 + 23,
3787 .vtotal = 480 + 1 + 23 + 22,
3788 };
3789
3790 static const struct panel_desc pda_91_00156_a0 = {
3791 .modes = &pda_91_00156_a0_mode,
3792 .num_modes = 1,
3793 .size = {
3794 .width = 152,
3795 .height = 91,
3796 },
3797 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3798 };
3799
3800 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = {
3801 .clock = 66500,
3802 .hdisplay = 1280,
3803 .hsync_start = 1280 + 12,
3804 .hsync_end = 1280 + 12 + 20,
3805 .htotal = 1280 + 12 + 20 + 56,
3806 .vdisplay = 800,
3807 .vsync_start = 800 + 1,
3808 .vsync_end = 800 + 1 + 3,
3809 .vtotal = 800 + 1 + 3 + 20,
3810 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3811 };
3812
3813 static const struct panel_desc powertip_ph128800t006_zhc01 = {
3814 .modes = &powertip_ph128800t006_zhc01_mode,
3815 .num_modes = 1,
3816 .bpc = 8,
3817 .size = {
3818 .width = 216,
3819 .height = 135,
3820 },
3821 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3822 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3823 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3824 };
3825
3826 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3827 .clock = 24750,
3828 .hdisplay = 800,
3829 .hsync_start = 800 + 54,
3830 .hsync_end = 800 + 54 + 2,
3831 .htotal = 800 + 54 + 2 + 44,
3832 .vdisplay = 480,
3833 .vsync_start = 480 + 49,
3834 .vsync_end = 480 + 49 + 2,
3835 .vtotal = 480 + 49 + 2 + 22,
3836 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3837 };
3838
3839 static const struct panel_desc powertip_ph800480t013_idf02 = {
3840 .modes = &powertip_ph800480t013_idf02_mode,
3841 .num_modes = 1,
3842 .bpc = 8,
3843 .size = {
3844 .width = 152,
3845 .height = 91,
3846 },
3847 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3848 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3849 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3851 .connector_type = DRM_MODE_CONNECTOR_DPI,
3852 };
3853
3854 static const struct drm_display_mode primeview_pm070wl4_mode = {
3855 .clock = 32000,
3856 .hdisplay = 800,
3857 .hsync_start = 800 + 42,
3858 .hsync_end = 800 + 42 + 128,
3859 .htotal = 800 + 42 + 128 + 86,
3860 .vdisplay = 480,
3861 .vsync_start = 480 + 10,
3862 .vsync_end = 480 + 10 + 2,
3863 .vtotal = 480 + 10 + 2 + 33,
3864 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3865 };
3866
3867 static const struct panel_desc primeview_pm070wl4 = {
3868 .modes = &primeview_pm070wl4_mode,
3869 .num_modes = 1,
3870 .bpc = 6,
3871 .size = {
3872 .width = 152,
3873 .height = 91,
3874 },
3875 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3876 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3877 .connector_type = DRM_MODE_CONNECTOR_DPI,
3878 };
3879
3880 static const struct drm_display_mode qd43003c0_40_mode = {
3881 .clock = 9000,
3882 .hdisplay = 480,
3883 .hsync_start = 480 + 8,
3884 .hsync_end = 480 + 8 + 4,
3885 .htotal = 480 + 8 + 4 + 39,
3886 .vdisplay = 272,
3887 .vsync_start = 272 + 4,
3888 .vsync_end = 272 + 4 + 10,
3889 .vtotal = 272 + 4 + 10 + 2,
3890 };
3891
3892 static const struct panel_desc qd43003c0_40 = {
3893 .modes = &qd43003c0_40_mode,
3894 .num_modes = 1,
3895 .bpc = 8,
3896 .size = {
3897 .width = 95,
3898 .height = 53,
3899 },
3900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3901 };
3902
3903 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3904 { /* 60 Hz */
3905 .clock = 10800,
3906 .hdisplay = 480,
3907 .hsync_start = 480 + 77,
3908 .hsync_end = 480 + 77 + 41,
3909 .htotal = 480 + 77 + 41 + 2,
3910 .vdisplay = 272,
3911 .vsync_start = 272 + 16,
3912 .vsync_end = 272 + 16 + 10,
3913 .vtotal = 272 + 16 + 10 + 2,
3914 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3915 },
3916 { /* 50 Hz */
3917 .clock = 10800,
3918 .hdisplay = 480,
3919 .hsync_start = 480 + 17,
3920 .hsync_end = 480 + 17 + 41,
3921 .htotal = 480 + 17 + 41 + 2,
3922 .vdisplay = 272,
3923 .vsync_start = 272 + 116,
3924 .vsync_end = 272 + 116 + 10,
3925 .vtotal = 272 + 116 + 10 + 2,
3926 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3927 },
3928 };
3929
3930 static const struct panel_desc qishenglong_gopher2b_lcd = {
3931 .modes = qishenglong_gopher2b_lcd_modes,
3932 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3933 .bpc = 8,
3934 .size = {
3935 .width = 95,
3936 .height = 54,
3937 },
3938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3939 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3940 .connector_type = DRM_MODE_CONNECTOR_DPI,
3941 };
3942
3943 static const struct display_timing rocktech_rk043fn48h_timing = {
3944 .pixelclock = { 6000000, 9000000, 12000000 },
3945 .hactive = { 480, 480, 480 },
3946 .hback_porch = { 8, 43, 43 },
3947 .hfront_porch = { 2, 8, 10 },
3948 .hsync_len = { 1, 1, 1 },
3949 .vactive = { 272, 272, 272 },
3950 .vback_porch = { 2, 12, 26 },
3951 .vfront_porch = { 1, 4, 4 },
3952 .vsync_len = { 1, 10, 10 },
3953 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3954 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3955 DISPLAY_FLAGS_SYNC_POSEDGE,
3956 };
3957
3958 static const struct panel_desc rocktech_rk043fn48h = {
3959 .timings = &rocktech_rk043fn48h_timing,
3960 .num_timings = 1,
3961 .bpc = 8,
3962 .size = {
3963 .width = 95,
3964 .height = 54,
3965 },
3966 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3967 .connector_type = DRM_MODE_CONNECTOR_DPI,
3968 };
3969
3970 static const struct display_timing rocktech_rk070er9427_timing = {
3971 .pixelclock = { 26400000, 33300000, 46800000 },
3972 .hactive = { 800, 800, 800 },
3973 .hfront_porch = { 16, 210, 354 },
3974 .hback_porch = { 46, 46, 46 },
3975 .hsync_len = { 1, 1, 1 },
3976 .vactive = { 480, 480, 480 },
3977 .vfront_porch = { 7, 22, 147 },
3978 .vback_porch = { 23, 23, 23 },
3979 .vsync_len = { 1, 1, 1 },
3980 .flags = DISPLAY_FLAGS_DE_HIGH,
3981 };
3982
3983 static const struct panel_desc rocktech_rk070er9427 = {
3984 .timings = &rocktech_rk070er9427_timing,
3985 .num_timings = 1,
3986 .bpc = 6,
3987 .size = {
3988 .width = 154,
3989 .height = 86,
3990 },
3991 .delay = {
3992 .prepare = 41,
3993 .enable = 50,
3994 .unprepare = 41,
3995 .disable = 50,
3996 },
3997 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3998 };
3999
4000 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
4001 .clock = 71100,
4002 .hdisplay = 1280,
4003 .hsync_start = 1280 + 48,
4004 .hsync_end = 1280 + 48 + 32,
4005 .htotal = 1280 + 48 + 32 + 80,
4006 .vdisplay = 800,
4007 .vsync_start = 800 + 2,
4008 .vsync_end = 800 + 2 + 5,
4009 .vtotal = 800 + 2 + 5 + 16,
4010 };
4011
4012 static const struct panel_desc rocktech_rk101ii01d_ct = {
4013 .modes = &rocktech_rk101ii01d_ct_mode,
4014 .bpc = 8,
4015 .num_modes = 1,
4016 .size = {
4017 .width = 217,
4018 .height = 136,
4019 },
4020 .delay = {
4021 .prepare = 50,
4022 .disable = 50,
4023 },
4024 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4026 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4027 };
4028
4029 static const struct display_timing samsung_ltl101al01_timing = {
4030 .pixelclock = { 66663000, 66663000, 66663000 },
4031 .hactive = { 1280, 1280, 1280 },
4032 .hfront_porch = { 18, 18, 18 },
4033 .hback_porch = { 36, 36, 36 },
4034 .hsync_len = { 16, 16, 16 },
4035 .vactive = { 800, 800, 800 },
4036 .vfront_porch = { 4, 4, 4 },
4037 .vback_porch = { 16, 16, 16 },
4038 .vsync_len = { 3, 3, 3 },
4039 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4040 };
4041
4042 static const struct panel_desc samsung_ltl101al01 = {
4043 .timings = &samsung_ltl101al01_timing,
4044 .num_timings = 1,
4045 .bpc = 8,
4046 .size = {
4047 .width = 217,
4048 .height = 135,
4049 },
4050 .delay = {
4051 .prepare = 40,
4052 .enable = 300,
4053 .disable = 200,
4054 .unprepare = 600,
4055 },
4056 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4057 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4058 };
4059
4060 static const struct drm_display_mode samsung_ltn101nt05_mode = {
4061 .clock = 54030,
4062 .hdisplay = 1024,
4063 .hsync_start = 1024 + 24,
4064 .hsync_end = 1024 + 24 + 136,
4065 .htotal = 1024 + 24 + 136 + 160,
4066 .vdisplay = 600,
4067 .vsync_start = 600 + 3,
4068 .vsync_end = 600 + 3 + 6,
4069 .vtotal = 600 + 3 + 6 + 61,
4070 };
4071
4072 static const struct panel_desc samsung_ltn101nt05 = {
4073 .modes = &samsung_ltn101nt05_mode,
4074 .num_modes = 1,
4075 .bpc = 6,
4076 .size = {
4077 .width = 223,
4078 .height = 125,
4079 },
4080 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4081 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4082 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4083 };
4084
4085 static const struct display_timing satoz_sat050at40h12r2_timing = {
4086 .pixelclock = {33300000, 33300000, 50000000},
4087 .hactive = {800, 800, 800},
4088 .hfront_porch = {16, 210, 354},
4089 .hback_porch = {46, 46, 46},
4090 .hsync_len = {1, 1, 40},
4091 .vactive = {480, 480, 480},
4092 .vfront_porch = {7, 22, 147},
4093 .vback_porch = {23, 23, 23},
4094 .vsync_len = {1, 1, 20},
4095 };
4096
4097 static const struct panel_desc satoz_sat050at40h12r2 = {
4098 .timings = &satoz_sat050at40h12r2_timing,
4099 .num_timings = 1,
4100 .bpc = 8,
4101 .size = {
4102 .width = 108,
4103 .height = 65,
4104 },
4105 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4106 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4107 };
4108
4109 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
4110 .clock = 33260,
4111 .hdisplay = 800,
4112 .hsync_start = 800 + 64,
4113 .hsync_end = 800 + 64 + 128,
4114 .htotal = 800 + 64 + 128 + 64,
4115 .vdisplay = 480,
4116 .vsync_start = 480 + 8,
4117 .vsync_end = 480 + 8 + 2,
4118 .vtotal = 480 + 8 + 2 + 35,
4119 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4120 };
4121
4122 static const struct panel_desc sharp_lq070y3dg3b = {
4123 .modes = &sharp_lq070y3dg3b_mode,
4124 .num_modes = 1,
4125 .bpc = 8,
4126 .size = {
4127 .width = 152, /* 152.4mm */
4128 .height = 91, /* 91.4mm */
4129 },
4130 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4132 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
4133 };
4134
4135 static const struct drm_display_mode sharp_lq035q7db03_mode = {
4136 .clock = 5500,
4137 .hdisplay = 240,
4138 .hsync_start = 240 + 16,
4139 .hsync_end = 240 + 16 + 7,
4140 .htotal = 240 + 16 + 7 + 5,
4141 .vdisplay = 320,
4142 .vsync_start = 320 + 9,
4143 .vsync_end = 320 + 9 + 1,
4144 .vtotal = 320 + 9 + 1 + 7,
4145 };
4146
4147 static const struct panel_desc sharp_lq035q7db03 = {
4148 .modes = &sharp_lq035q7db03_mode,
4149 .num_modes = 1,
4150 .bpc = 6,
4151 .size = {
4152 .width = 54,
4153 .height = 72,
4154 },
4155 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4156 };
4157
4158 static const struct display_timing sharp_lq101k1ly04_timing = {
4159 .pixelclock = { 60000000, 65000000, 80000000 },
4160 .hactive = { 1280, 1280, 1280 },
4161 .hfront_porch = { 20, 20, 20 },
4162 .hback_porch = { 20, 20, 20 },
4163 .hsync_len = { 10, 10, 10 },
4164 .vactive = { 800, 800, 800 },
4165 .vfront_porch = { 4, 4, 4 },
4166 .vback_porch = { 4, 4, 4 },
4167 .vsync_len = { 4, 4, 4 },
4168 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4169 };
4170
4171 static const struct panel_desc sharp_lq101k1ly04 = {
4172 .timings = &sharp_lq101k1ly04_timing,
4173 .num_timings = 1,
4174 .bpc = 8,
4175 .size = {
4176 .width = 217,
4177 .height = 136,
4178 },
4179 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4180 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4181 };
4182
4183 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
4184 { /* 50 Hz */
4185 .clock = 3000,
4186 .hdisplay = 240,
4187 .hsync_start = 240 + 58,
4188 .hsync_end = 240 + 58 + 1,
4189 .htotal = 240 + 58 + 1 + 1,
4190 .vdisplay = 160,
4191 .vsync_start = 160 + 24,
4192 .vsync_end = 160 + 24 + 10,
4193 .vtotal = 160 + 24 + 10 + 6,
4194 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4195 },
4196 { /* 60 Hz */
4197 .clock = 3000,
4198 .hdisplay = 240,
4199 .hsync_start = 240 + 8,
4200 .hsync_end = 240 + 8 + 1,
4201 .htotal = 240 + 8 + 1 + 1,
4202 .vdisplay = 160,
4203 .vsync_start = 160 + 24,
4204 .vsync_end = 160 + 24 + 10,
4205 .vtotal = 160 + 24 + 10 + 6,
4206 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4207 },
4208 };
4209
4210 static const struct panel_desc sharp_ls020b1dd01d = {
4211 .modes = sharp_ls020b1dd01d_modes,
4212 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
4213 .bpc = 6,
4214 .size = {
4215 .width = 42,
4216 .height = 28,
4217 },
4218 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4219 .bus_flags = DRM_BUS_FLAG_DE_HIGH
4220 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
4221 | DRM_BUS_FLAG_SHARP_SIGNALS,
4222 };
4223
4224 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4225 .clock = 33300,
4226 .hdisplay = 800,
4227 .hsync_start = 800 + 1,
4228 .hsync_end = 800 + 1 + 64,
4229 .htotal = 800 + 1 + 64 + 64,
4230 .vdisplay = 480,
4231 .vsync_start = 480 + 1,
4232 .vsync_end = 480 + 1 + 23,
4233 .vtotal = 480 + 1 + 23 + 22,
4234 };
4235
4236 static const struct panel_desc shelly_sca07010_bfn_lnn = {
4237 .modes = &shelly_sca07010_bfn_lnn_mode,
4238 .num_modes = 1,
4239 .size = {
4240 .width = 152,
4241 .height = 91,
4242 },
4243 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4244 };
4245
4246 static const struct drm_display_mode starry_kr070pe2t_mode = {
4247 .clock = 33000,
4248 .hdisplay = 800,
4249 .hsync_start = 800 + 209,
4250 .hsync_end = 800 + 209 + 1,
4251 .htotal = 800 + 209 + 1 + 45,
4252 .vdisplay = 480,
4253 .vsync_start = 480 + 22,
4254 .vsync_end = 480 + 22 + 1,
4255 .vtotal = 480 + 22 + 1 + 22,
4256 };
4257
4258 static const struct panel_desc starry_kr070pe2t = {
4259 .modes = &starry_kr070pe2t_mode,
4260 .num_modes = 1,
4261 .bpc = 8,
4262 .size = {
4263 .width = 152,
4264 .height = 86,
4265 },
4266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4267 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
4268 .connector_type = DRM_MODE_CONNECTOR_DPI,
4269 };
4270
4271 static const struct display_timing startek_kd070wvfpa_mode = {
4272 .pixelclock = { 25200000, 27200000, 30500000 },
4273 .hactive = { 800, 800, 800 },
4274 .hfront_porch = { 19, 44, 115 },
4275 .hback_porch = { 5, 16, 101 },
4276 .hsync_len = { 1, 2, 100 },
4277 .vactive = { 480, 480, 480 },
4278 .vfront_porch = { 5, 43, 67 },
4279 .vback_porch = { 5, 5, 67 },
4280 .vsync_len = { 1, 2, 66 },
4281 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4282 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
4283 DISPLAY_FLAGS_SYNC_POSEDGE,
4284 };
4285
4286 static const struct panel_desc startek_kd070wvfpa = {
4287 .timings = &startek_kd070wvfpa_mode,
4288 .num_timings = 1,
4289 .bpc = 8,
4290 .size = {
4291 .width = 152,
4292 .height = 91,
4293 },
4294 .delay = {
4295 .prepare = 20,
4296 .enable = 200,
4297 .disable = 200,
4298 },
4299 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4300 .connector_type = DRM_MODE_CONNECTOR_DPI,
4301 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
4302 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4303 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
4304 };
4305
4306 static const struct display_timing tsd_tst043015cmhx_timing = {
4307 .pixelclock = { 5000000, 9000000, 12000000 },
4308 .hactive = { 480, 480, 480 },
4309 .hfront_porch = { 4, 5, 65 },
4310 .hback_porch = { 36, 40, 255 },
4311 .hsync_len = { 1, 1, 1 },
4312 .vactive = { 272, 272, 272 },
4313 .vfront_porch = { 2, 8, 97 },
4314 .vback_porch = { 3, 8, 31 },
4315 .vsync_len = { 1, 1, 1 },
4316
4317 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4318 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
4319 };
4320
4321 static const struct panel_desc tsd_tst043015cmhx = {
4322 .timings = &tsd_tst043015cmhx_timing,
4323 .num_timings = 1,
4324 .bpc = 8,
4325 .size = {
4326 .width = 105,
4327 .height = 67,
4328 },
4329 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4330 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4331 };
4332
4333 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4334 .clock = 30000,
4335 .hdisplay = 800,
4336 .hsync_start = 800 + 39,
4337 .hsync_end = 800 + 39 + 47,
4338 .htotal = 800 + 39 + 47 + 39,
4339 .vdisplay = 480,
4340 .vsync_start = 480 + 13,
4341 .vsync_end = 480 + 13 + 2,
4342 .vtotal = 480 + 13 + 2 + 29,
4343 };
4344
4345 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4346 .modes = &tfc_s9700rtwv43tr_01b_mode,
4347 .num_modes = 1,
4348 .bpc = 8,
4349 .size = {
4350 .width = 155,
4351 .height = 90,
4352 },
4353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4354 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4355 };
4356
4357 static const struct display_timing tianma_tm070jdhg30_timing = {
4358 .pixelclock = { 62600000, 68200000, 78100000 },
4359 .hactive = { 1280, 1280, 1280 },
4360 .hfront_porch = { 15, 64, 159 },
4361 .hback_porch = { 5, 5, 5 },
4362 .hsync_len = { 1, 1, 256 },
4363 .vactive = { 800, 800, 800 },
4364 .vfront_porch = { 3, 40, 99 },
4365 .vback_porch = { 2, 2, 2 },
4366 .vsync_len = { 1, 1, 128 },
4367 .flags = DISPLAY_FLAGS_DE_HIGH,
4368 };
4369
4370 static const struct panel_desc tianma_tm070jdhg30 = {
4371 .timings = &tianma_tm070jdhg30_timing,
4372 .num_timings = 1,
4373 .bpc = 8,
4374 .size = {
4375 .width = 151,
4376 .height = 95,
4377 },
4378 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4379 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4380 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4381 };
4382
4383 static const struct panel_desc tianma_tm070jvhg33 = {
4384 .timings = &tianma_tm070jdhg30_timing,
4385 .num_timings = 1,
4386 .bpc = 8,
4387 .size = {
4388 .width = 150,
4389 .height = 94,
4390 },
4391 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4392 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4393 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4394 };
4395
4396 /*
4397 * The datasheet computes total blanking as back porch + front porch, not
4398 * including sync pulse width. This is for both H and V. To make the total
4399 * blanking and period correct, subtract the pulse width from the front
4400 * porch.
4401 *
4402 * This works well for the Min and Typ values, but for Max values the sync
4403 * pulse width is higher than back porch + front porch, so work around that
4404 * by reducing the Max sync length value to 1 and then treating the Max
4405 * porches as in the Min and Typ cases.
4406 *
4407 * Exact datasheet values are added as a comment where they differ from the
4408 * ones implemented for the above reason.
4409 */
4410 static const struct display_timing tianma_tm070jdhg34_00_timing = {
4411 .pixelclock = { 68400000, 71900000, 78100000 },
4412 .hactive = { 1280, 1280, 1280 },
4413 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */
4414 .hback_porch = { 5, 5, 5 },
4415 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */
4416 .vactive = { 800, 800, 800 },
4417 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */
4418 .vback_porch = { 2, 2, 2 },
4419 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */
4420 .flags = DISPLAY_FLAGS_DE_HIGH,
4421 };
4422
4423 static const struct panel_desc tianma_tm070jdhg34_00 = {
4424 .timings = &tianma_tm070jdhg34_00_timing,
4425 .num_timings = 1,
4426 .bpc = 8,
4427 .size = {
4428 .width = 150, /* 149.76 */
4429 .height = 94, /* 93.60 */
4430 },
4431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4432 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4433 };
4434
4435 static const struct display_timing tianma_tm070rvhg71_timing = {
4436 .pixelclock = { 27700000, 29200000, 39600000 },
4437 .hactive = { 800, 800, 800 },
4438 .hfront_porch = { 12, 40, 212 },
4439 .hback_porch = { 88, 88, 88 },
4440 .hsync_len = { 1, 1, 40 },
4441 .vactive = { 480, 480, 480 },
4442 .vfront_porch = { 1, 13, 88 },
4443 .vback_porch = { 32, 32, 32 },
4444 .vsync_len = { 1, 1, 3 },
4445 .flags = DISPLAY_FLAGS_DE_HIGH,
4446 };
4447
4448 static const struct panel_desc tianma_tm070rvhg71 = {
4449 .timings = &tianma_tm070rvhg71_timing,
4450 .num_timings = 1,
4451 .bpc = 8,
4452 .size = {
4453 .width = 154,
4454 .height = 86,
4455 },
4456 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4457 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4458 };
4459
4460 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4461 {
4462 .clock = 10000,
4463 .hdisplay = 320,
4464 .hsync_start = 320 + 50,
4465 .hsync_end = 320 + 50 + 6,
4466 .htotal = 320 + 50 + 6 + 38,
4467 .vdisplay = 240,
4468 .vsync_start = 240 + 3,
4469 .vsync_end = 240 + 3 + 1,
4470 .vtotal = 240 + 3 + 1 + 17,
4471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4472 },
4473 };
4474
4475 static const struct panel_desc ti_nspire_cx_lcd_panel = {
4476 .modes = ti_nspire_cx_lcd_mode,
4477 .num_modes = 1,
4478 .bpc = 8,
4479 .size = {
4480 .width = 65,
4481 .height = 49,
4482 },
4483 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4484 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
4485 };
4486
4487 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4488 {
4489 .clock = 10000,
4490 .hdisplay = 320,
4491 .hsync_start = 320 + 6,
4492 .hsync_end = 320 + 6 + 6,
4493 .htotal = 320 + 6 + 6 + 6,
4494 .vdisplay = 240,
4495 .vsync_start = 240 + 0,
4496 .vsync_end = 240 + 0 + 1,
4497 .vtotal = 240 + 0 + 1 + 0,
4498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4499 },
4500 };
4501
4502 static const struct panel_desc ti_nspire_classic_lcd_panel = {
4503 .modes = ti_nspire_classic_lcd_mode,
4504 .num_modes = 1,
4505 /* The grayscale panel has 8 bit for the color .. Y (black) */
4506 .bpc = 8,
4507 .size = {
4508 .width = 71,
4509 .height = 53,
4510 },
4511 /* This is the grayscale bus format */
4512 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
4513 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4514 };
4515
4516 static const struct display_timing topland_tian_g07017_01_timing = {
4517 .pixelclock = { 44900000, 51200000, 63000000 },
4518 .hactive = { 1024, 1024, 1024 },
4519 .hfront_porch = { 16, 160, 216 },
4520 .hback_porch = { 160, 160, 160 },
4521 .hsync_len = { 1, 1, 140 },
4522 .vactive = { 600, 600, 600 },
4523 .vfront_porch = { 1, 12, 127 },
4524 .vback_porch = { 23, 23, 23 },
4525 .vsync_len = { 1, 1, 20 },
4526 };
4527
4528 static const struct panel_desc topland_tian_g07017_01 = {
4529 .timings = &topland_tian_g07017_01_timing,
4530 .num_timings = 1,
4531 .bpc = 8,
4532 .size = {
4533 .width = 154,
4534 .height = 86,
4535 },
4536 .delay = {
4537 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */
4538 .enable = 100, /* 6.4 - Power on: 6 VSyncs */
4539 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */
4540 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */
4541 },
4542 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4543 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4544 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4545 };
4546
4547 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4548 .clock = 79500,
4549 .hdisplay = 1280,
4550 .hsync_start = 1280 + 192,
4551 .hsync_end = 1280 + 192 + 128,
4552 .htotal = 1280 + 192 + 128 + 64,
4553 .vdisplay = 768,
4554 .vsync_start = 768 + 20,
4555 .vsync_end = 768 + 20 + 7,
4556 .vtotal = 768 + 20 + 7 + 3,
4557 };
4558
4559 static const struct panel_desc toshiba_lt089ac29000 = {
4560 .modes = &toshiba_lt089ac29000_mode,
4561 .num_modes = 1,
4562 .size = {
4563 .width = 194,
4564 .height = 116,
4565 },
4566 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4567 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4568 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4569 };
4570
4571 static const struct drm_display_mode tpk_f07a_0102_mode = {
4572 .clock = 33260,
4573 .hdisplay = 800,
4574 .hsync_start = 800 + 40,
4575 .hsync_end = 800 + 40 + 128,
4576 .htotal = 800 + 40 + 128 + 88,
4577 .vdisplay = 480,
4578 .vsync_start = 480 + 10,
4579 .vsync_end = 480 + 10 + 2,
4580 .vtotal = 480 + 10 + 2 + 33,
4581 };
4582
4583 static const struct panel_desc tpk_f07a_0102 = {
4584 .modes = &tpk_f07a_0102_mode,
4585 .num_modes = 1,
4586 .size = {
4587 .width = 152,
4588 .height = 91,
4589 },
4590 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
4591 };
4592
4593 static const struct drm_display_mode tpk_f10a_0102_mode = {
4594 .clock = 45000,
4595 .hdisplay = 1024,
4596 .hsync_start = 1024 + 176,
4597 .hsync_end = 1024 + 176 + 5,
4598 .htotal = 1024 + 176 + 5 + 88,
4599 .vdisplay = 600,
4600 .vsync_start = 600 + 20,
4601 .vsync_end = 600 + 20 + 5,
4602 .vtotal = 600 + 20 + 5 + 25,
4603 };
4604
4605 static const struct panel_desc tpk_f10a_0102 = {
4606 .modes = &tpk_f10a_0102_mode,
4607 .num_modes = 1,
4608 .size = {
4609 .width = 223,
4610 .height = 125,
4611 },
4612 };
4613
4614 static const struct display_timing urt_umsh_8596md_timing = {
4615 .pixelclock = { 33260000, 33260000, 33260000 },
4616 .hactive = { 800, 800, 800 },
4617 .hfront_porch = { 41, 41, 41 },
4618 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4619 .hsync_len = { 71, 128, 128 },
4620 .vactive = { 480, 480, 480 },
4621 .vfront_porch = { 10, 10, 10 },
4622 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4623 .vsync_len = { 2, 2, 2 },
4624 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4625 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4626 };
4627
4628 static const struct panel_desc urt_umsh_8596md_lvds = {
4629 .timings = &urt_umsh_8596md_timing,
4630 .num_timings = 1,
4631 .bpc = 6,
4632 .size = {
4633 .width = 152,
4634 .height = 91,
4635 },
4636 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4637 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4638 };
4639
4640 static const struct panel_desc urt_umsh_8596md_parallel = {
4641 .timings = &urt_umsh_8596md_timing,
4642 .num_timings = 1,
4643 .bpc = 6,
4644 .size = {
4645 .width = 152,
4646 .height = 91,
4647 },
4648 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4649 };
4650
4651 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4652 .clock = 60000,
4653 .hdisplay = 1024,
4654 .hsync_start = 1024 + 160,
4655 .hsync_end = 1024 + 160 + 100,
4656 .htotal = 1024 + 160 + 100 + 60,
4657 .vdisplay = 600,
4658 .vsync_start = 600 + 12,
4659 .vsync_end = 600 + 12 + 10,
4660 .vtotal = 600 + 12 + 10 + 13,
4661 };
4662
4663 static const struct panel_desc vivax_tpc9150_panel = {
4664 .modes = &vivax_tpc9150_panel_mode,
4665 .num_modes = 1,
4666 .bpc = 6,
4667 .size = {
4668 .width = 200,
4669 .height = 115,
4670 },
4671 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4672 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4673 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4674 };
4675
4676 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4677 .clock = 33333,
4678 .hdisplay = 800,
4679 .hsync_start = 800 + 210,
4680 .hsync_end = 800 + 210 + 20,
4681 .htotal = 800 + 210 + 20 + 46,
4682 .vdisplay = 480,
4683 .vsync_start = 480 + 22,
4684 .vsync_end = 480 + 22 + 10,
4685 .vtotal = 480 + 22 + 10 + 23,
4686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4687 };
4688
4689 static const struct panel_desc vl050_8048nt_c01 = {
4690 .modes = &vl050_8048nt_c01_mode,
4691 .num_modes = 1,
4692 .bpc = 8,
4693 .size = {
4694 .width = 120,
4695 .height = 76,
4696 },
4697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4699 };
4700
4701 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4702 .clock = 6410,
4703 .hdisplay = 320,
4704 .hsync_start = 320 + 20,
4705 .hsync_end = 320 + 20 + 30,
4706 .htotal = 320 + 20 + 30 + 38,
4707 .vdisplay = 240,
4708 .vsync_start = 240 + 4,
4709 .vsync_end = 240 + 4 + 3,
4710 .vtotal = 240 + 4 + 3 + 15,
4711 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4712 };
4713
4714 static const struct panel_desc winstar_wf35ltiacd = {
4715 .modes = &winstar_wf35ltiacd_mode,
4716 .num_modes = 1,
4717 .bpc = 8,
4718 .size = {
4719 .width = 70,
4720 .height = 53,
4721 },
4722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4723 };
4724
4725 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4726 .clock = 51200,
4727 .hdisplay = 1024,
4728 .hsync_start = 1024 + 100,
4729 .hsync_end = 1024 + 100 + 100,
4730 .htotal = 1024 + 100 + 100 + 120,
4731 .vdisplay = 600,
4732 .vsync_start = 600 + 10,
4733 .vsync_end = 600 + 10 + 10,
4734 .vtotal = 600 + 10 + 10 + 15,
4735 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4736 };
4737
4738 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4739 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4740 .num_modes = 1,
4741 .bpc = 8,
4742 .size = {
4743 .width = 154,
4744 .height = 90,
4745 },
4746 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4748 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4749 };
4750
4751 static const struct drm_display_mode mchp_ac69t88a_mode = {
4752 .clock = 25000,
4753 .hdisplay = 800,
4754 .hsync_start = 800 + 88,
4755 .hsync_end = 800 + 88 + 5,
4756 .htotal = 800 + 88 + 5 + 40,
4757 .vdisplay = 480,
4758 .vsync_start = 480 + 23,
4759 .vsync_end = 480 + 23 + 5,
4760 .vtotal = 480 + 23 + 5 + 1,
4761 };
4762
4763 static const struct panel_desc mchp_ac69t88a = {
4764 .modes = &mchp_ac69t88a_mode,
4765 .num_modes = 1,
4766 .bpc = 8,
4767 .size = {
4768 .width = 108,
4769 .height = 65,
4770 },
4771 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4772 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4773 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4774 };
4775
4776 static const struct drm_display_mode arm_rtsm_mode[] = {
4777 {
4778 .clock = 65000,
4779 .hdisplay = 1024,
4780 .hsync_start = 1024 + 24,
4781 .hsync_end = 1024 + 24 + 136,
4782 .htotal = 1024 + 24 + 136 + 160,
4783 .vdisplay = 768,
4784 .vsync_start = 768 + 3,
4785 .vsync_end = 768 + 3 + 6,
4786 .vtotal = 768 + 3 + 6 + 29,
4787 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4788 },
4789 };
4790
4791 static const struct panel_desc arm_rtsm = {
4792 .modes = arm_rtsm_mode,
4793 .num_modes = 1,
4794 .bpc = 8,
4795 .size = {
4796 .width = 400,
4797 .height = 300,
4798 },
4799 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4800 };
4801
4802 static const struct of_device_id platform_of_match[] = {
4803 {
4804 .compatible = "ampire,am-1280800n3tzqw-t00h",
4805 .data = &ire_am_1280800n3tzqw_t00h,
4806 }, {
4807 .compatible = "ampire,am-480272h3tmqw-t01h",
4808 .data = &ire_am_480272h3tmqw_t01h,
4809 }, {
4810 .compatible = "ampire,am-800480l1tmqw-t00h",
4811 .data = &ire_am_800480l1tmqw_t00h,
4812 }, {
4813 .compatible = "ampire,am800480r3tmqwa1h",
4814 .data = &ire_am800480r3tmqwa1h,
4815 }, {
4816 .compatible = "ampire,am800600p5tmqw-tb8h",
4817 .data = &ire_am800600p5tmqwtb8h,
4818 }, {
4819 .compatible = "arm,rtsm-display",
4820 .data = &arm_rtsm,
4821 }, {
4822 .compatible = "armadeus,st0700-adapt",
4823 .data = &armadeus_st0700_adapt,
4824 }, {
4825 .compatible = "auo,b101aw03",
4826 .data = &auo_b101aw03,
4827 }, {
4828 .compatible = "auo,b101xtn01",
4829 .data = &auo_b101xtn01,
4830 }, {
4831 .compatible = "auo,b116xw03",
4832 .data = &auo_b116xw03,
4833 }, {
4834 .compatible = "auo,g070vvn01",
4835 .data = &auo_g070vvn01,
4836 }, {
4837 .compatible = "auo,g101evn010",
4838 .data = &auo_g101evn010,
4839 }, {
4840 .compatible = "auo,g104sn02",
4841 .data = &auo_g104sn02,
4842 }, {
4843 .compatible = "auo,g104stn01",
4844 .data = &auo_g104stn01,
4845 }, {
4846 .compatible = "auo,g121ean01",
4847 .data = &auo_g121ean01,
4848 }, {
4849 .compatible = "auo,g133han01",
4850 .data = &auo_g133han01,
4851 }, {
4852 .compatible = "auo,g156han04",
4853 .data = &auo_g156han04,
4854 }, {
4855 .compatible = "auo,g156xtn01",
4856 .data = &auo_g156xtn01,
4857 }, {
4858 .compatible = "auo,g185han01",
4859 .data = &auo_g185han01,
4860 }, {
4861 .compatible = "auo,g190ean01",
4862 .data = &auo_g190ean01,
4863 }, {
4864 .compatible = "auo,p320hvn03",
4865 .data = &auo_p320hvn03,
4866 }, {
4867 .compatible = "auo,t215hvn01",
4868 .data = &auo_t215hvn01,
4869 }, {
4870 .compatible = "avic,tm070ddh03",
4871 .data = &avic_tm070ddh03,
4872 }, {
4873 .compatible = "bananapi,s070wv20-ct16",
4874 .data = &bananapi_s070wv20_ct16,
4875 }, {
4876 .compatible = "boe,av101hdt-a10",
4877 .data = &boe_av101hdt_a10,
4878 }, {
4879 .compatible = "boe,av123z7m-n17",
4880 .data = &boe_av123z7m_n17,
4881 }, {
4882 .compatible = "boe,bp082wx1-100",
4883 .data = &boe_bp082wx1_100,
4884 }, {
4885 .compatible = "boe,bp101wx1-100",
4886 .data = &boe_bp101wx1_100,
4887 }, {
4888 .compatible = "boe,ev121wxm-n10-1850",
4889 .data = &boe_ev121wxm_n10_1850,
4890 }, {
4891 .compatible = "boe,hv070wsa-100",
4892 .data = &boe_hv070wsa
4893 }, {
4894 .compatible = "cct,cmt430b19n00",
4895 .data = &cct_cmt430b19n00,
4896 }, {
4897 .compatible = "cdtech,s043wq26h-ct7",
4898 .data = &cdtech_s043wq26h_ct7,
4899 }, {
4900 .compatible = "cdtech,s070pws19hp-fc21",
4901 .data = &cdtech_s070pws19hp_fc21,
4902 }, {
4903 .compatible = "cdtech,s070swv29hg-dc44",
4904 .data = &cdtech_s070swv29hg_dc44,
4905 }, {
4906 .compatible = "cdtech,s070wv95-ct16",
4907 .data = &cdtech_s070wv95_ct16,
4908 }, {
4909 .compatible = "chefree,ch101olhlwh-002",
4910 .data = &chefree_ch101olhlwh_002,
4911 }, {
4912 .compatible = "chunghwa,claa070wp03xg",
4913 .data = &chunghwa_claa070wp03xg,
4914 }, {
4915 .compatible = "chunghwa,claa101wa01a",
4916 .data = &chunghwa_claa101wa01a
4917 }, {
4918 .compatible = "chunghwa,claa101wb01",
4919 .data = &chunghwa_claa101wb01
4920 }, {
4921 .compatible = "dataimage,fg040346dsswbg04",
4922 .data = &dataimage_fg040346dsswbg04,
4923 }, {
4924 .compatible = "dataimage,fg1001l0dsswmg01",
4925 .data = &dataimage_fg1001l0dsswmg01,
4926 }, {
4927 .compatible = "dataimage,scf0700c48ggu18",
4928 .data = &dataimage_scf0700c48ggu18,
4929 }, {
4930 .compatible = "dlc,dlc0700yzg-1",
4931 .data = &dlc_dlc0700yzg_1,
4932 }, {
4933 .compatible = "dlc,dlc1010gig",
4934 .data = &dlc_dlc1010gig,
4935 }, {
4936 .compatible = "edt,et035012dm6",
4937 .data = &edt_et035012dm6,
4938 }, {
4939 .compatible = "edt,etm0350g0dh6",
4940 .data = &edt_etm0350g0dh6,
4941 }, {
4942 .compatible = "edt,etm043080dh6gp",
4943 .data = &edt_etm043080dh6gp,
4944 }, {
4945 .compatible = "edt,etm0430g0dh6",
4946 .data = &edt_etm0430g0dh6,
4947 }, {
4948 .compatible = "edt,et057090dhu",
4949 .data = &edt_et057090dhu,
4950 }, {
4951 .compatible = "edt,et070080dh6",
4952 .data = &edt_etm0700g0dh6,
4953 }, {
4954 .compatible = "edt,etm0700g0dh6",
4955 .data = &edt_etm0700g0dh6,
4956 }, {
4957 .compatible = "edt,etm0700g0bdh6",
4958 .data = &edt_etm0700g0bdh6,
4959 }, {
4960 .compatible = "edt,etm0700g0edh6",
4961 .data = &edt_etm0700g0bdh6,
4962 }, {
4963 .compatible = "edt,etml0700y5dha",
4964 .data = &edt_etml0700y5dha,
4965 }, {
4966 .compatible = "edt,etml1010g3dra",
4967 .data = &edt_etml1010g3dra,
4968 }, {
4969 .compatible = "edt,etmv570g2dhu",
4970 .data = &edt_etmv570g2dhu,
4971 }, {
4972 .compatible = "eink,vb3300-kca",
4973 .data = &eink_vb3300_kca,
4974 }, {
4975 .compatible = "evervision,vgg644804",
4976 .data = &evervision_vgg644804,
4977 }, {
4978 .compatible = "evervision,vgg804821",
4979 .data = &evervision_vgg804821,
4980 }, {
4981 .compatible = "foxlink,fl500wvr00-a0t",
4982 .data = &foxlink_fl500wvr00_a0t,
4983 }, {
4984 .compatible = "frida,frd350h54004",
4985 .data = &frida_frd350h54004,
4986 }, {
4987 .compatible = "friendlyarm,hd702e",
4988 .data = &friendlyarm_hd702e,
4989 }, {
4990 .compatible = "giantplus,gpg482739qs5",
4991 .data = &giantplus_gpg482739qs5
4992 }, {
4993 .compatible = "giantplus,gpm940b0",
4994 .data = &giantplus_gpm940b0,
4995 }, {
4996 .compatible = "hannstar,hsd070pww1",
4997 .data = &hannstar_hsd070pww1,
4998 }, {
4999 .compatible = "hannstar,hsd100pxn1",
5000 .data = &hannstar_hsd100pxn1,
5001 }, {
5002 .compatible = "hannstar,hsd101pww2",
5003 .data = &hannstar_hsd101pww2,
5004 }, {
5005 .compatible = "hit,tx23d38vm0caa",
5006 .data = &hitachi_tx23d38vm0caa
5007 }, {
5008 .compatible = "innolux,at043tn24",
5009 .data = &innolux_at043tn24,
5010 }, {
5011 .compatible = "innolux,at070tn92",
5012 .data = &innolux_at070tn92,
5013 }, {
5014 .compatible = "innolux,g070ace-l01",
5015 .data = &innolux_g070ace_l01,
5016 }, {
5017 .compatible = "innolux,g070ace-lh3",
5018 .data = &innolux_g070ace_lh3,
5019 }, {
5020 .compatible = "innolux,g070y2-l01",
5021 .data = &innolux_g070y2_l01,
5022 }, {
5023 .compatible = "innolux,g070y2-t02",
5024 .data = &innolux_g070y2_t02,
5025 }, {
5026 .compatible = "innolux,g101ice-l01",
5027 .data = &innolux_g101ice_l01
5028 }, {
5029 .compatible = "innolux,g121i1-l01",
5030 .data = &innolux_g121i1_l01
5031 }, {
5032 .compatible = "innolux,g121x1-l03",
5033 .data = &innolux_g121x1_l03,
5034 }, {
5035 .compatible = "innolux,g121xce-l01",
5036 .data = &innolux_g121xce_l01,
5037 }, {
5038 .compatible = "innolux,g156hce-l01",
5039 .data = &innolux_g156hce_l01,
5040 }, {
5041 .compatible = "innolux,n156bge-l21",
5042 .data = &innolux_n156bge_l21,
5043 }, {
5044 .compatible = "innolux,zj070na-01p",
5045 .data = &innolux_zj070na_01p,
5046 }, {
5047 .compatible = "koe,tx14d24vm1bpa",
5048 .data = &koe_tx14d24vm1bpa,
5049 }, {
5050 .compatible = "koe,tx26d202vm0bwa",
5051 .data = &koe_tx26d202vm0bwa,
5052 }, {
5053 .compatible = "koe,tx31d200vm0baa",
5054 .data = &koe_tx31d200vm0baa,
5055 }, {
5056 .compatible = "kyo,tcg121xglp",
5057 .data = &kyo_tcg121xglp,
5058 }, {
5059 .compatible = "lemaker,bl035-rgb-002",
5060 .data = &lemaker_bl035_rgb_002,
5061 }, {
5062 .compatible = "lg,lb070wv8",
5063 .data = &lg_lb070wv8,
5064 }, {
5065 .compatible = "lincolntech,lcd185-101ct",
5066 .data = &lincolntech_lcd185_101ct,
5067 }, {
5068 .compatible = "logicpd,type28",
5069 .data = &logicpd_type_28,
5070 }, {
5071 .compatible = "logictechno,lt161010-2nhc",
5072 .data = &logictechno_lt161010_2nh,
5073 }, {
5074 .compatible = "logictechno,lt161010-2nhr",
5075 .data = &logictechno_lt161010_2nh,
5076 }, {
5077 .compatible = "logictechno,lt170410-2whc",
5078 .data = &logictechno_lt170410_2whc,
5079 }, {
5080 .compatible = "logictechno,lttd800480070-l2rt",
5081 .data = &logictechno_lttd800480070_l2rt,
5082 }, {
5083 .compatible = "logictechno,lttd800480070-l6wh-rt",
5084 .data = &logictechno_lttd800480070_l6wh_rt,
5085 }, {
5086 .compatible = "microtips,mf-101hiebcaf0",
5087 .data = µtips_mf_101hiebcaf0_c,
5088 }, {
5089 .compatible = "microtips,mf-103hieb0ga0",
5090 .data = µtips_mf_103hieb0ga0,
5091 }, {
5092 .compatible = "mitsubishi,aa070mc01-ca1",
5093 .data = &mitsubishi_aa070mc01,
5094 }, {
5095 .compatible = "mitsubishi,aa084xe01",
5096 .data = &mitsubishi_aa084xe01,
5097 }, {
5098 .compatible = "multi-inno,mi0700a2t-30",
5099 .data = &multi_inno_mi0700a2t_30,
5100 }, {
5101 .compatible = "multi-inno,mi0700s4t-6",
5102 .data = &multi_inno_mi0700s4t_6,
5103 }, {
5104 .compatible = "multi-inno,mi0800ft-9",
5105 .data = &multi_inno_mi0800ft_9,
5106 }, {
5107 .compatible = "multi-inno,mi1010ait-1cp",
5108 .data = &multi_inno_mi1010ait_1cp,
5109 }, {
5110 .compatible = "multi-inno,mi1010z1t-1cp11",
5111 .data = &multi_inno_mi1010z1t_1cp11,
5112 }, {
5113 .compatible = "nec,nl12880bc20-05",
5114 .data = &nec_nl12880bc20_05,
5115 }, {
5116 .compatible = "nec,nl4827hc19-05b",
5117 .data = &nec_nl4827hc19_05b,
5118 }, {
5119 .compatible = "netron-dy,e231732",
5120 .data = &netron_dy_e231732,
5121 }, {
5122 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
5123 .data = &newhaven_nhd_43_480272ef_atxl,
5124 }, {
5125 .compatible = "nlt,nl192108ac18-02d",
5126 .data = &nlt_nl192108ac18_02d,
5127 }, {
5128 .compatible = "nvd,9128",
5129 .data = &nvd_9128,
5130 }, {
5131 .compatible = "okaya,rs800480t-7x0gp",
5132 .data = &okaya_rs800480t_7x0gp,
5133 }, {
5134 .compatible = "olimex,lcd-olinuxino-43-ts",
5135 .data = &olimex_lcd_olinuxino_43ts,
5136 }, {
5137 .compatible = "ontat,kd50g21-40nt-a1",
5138 .data = &ontat_kd50g21_40nt_a1,
5139 }, {
5140 .compatible = "ontat,yx700wv03",
5141 .data = &ontat_yx700wv03,
5142 }, {
5143 .compatible = "ortustech,com37h3m05dtc",
5144 .data = &ortustech_com37h3m,
5145 }, {
5146 .compatible = "ortustech,com37h3m99dtc",
5147 .data = &ortustech_com37h3m,
5148 }, {
5149 .compatible = "ortustech,com43h4m85ulc",
5150 .data = &ortustech_com43h4m85ulc,
5151 }, {
5152 .compatible = "osddisplays,osd070t1718-19ts",
5153 .data = &osddisplays_osd070t1718_19ts,
5154 }, {
5155 .compatible = "pda,91-00156-a0",
5156 .data = &pda_91_00156_a0,
5157 }, {
5158 .compatible = "powertip,ph128800t006-zhc01",
5159 .data = &powertip_ph128800t006_zhc01,
5160 }, {
5161 .compatible = "powertip,ph800480t013-idf02",
5162 .data = &powertip_ph800480t013_idf02,
5163 }, {
5164 .compatible = "primeview,pm070wl4",
5165 .data = &primeview_pm070wl4,
5166 }, {
5167 .compatible = "qiaodian,qd43003c0-40",
5168 .data = &qd43003c0_40,
5169 }, {
5170 .compatible = "qishenglong,gopher2b-lcd",
5171 .data = &qishenglong_gopher2b_lcd,
5172 }, {
5173 .compatible = "rocktech,rk043fn48h",
5174 .data = &rocktech_rk043fn48h,
5175 }, {
5176 .compatible = "rocktech,rk070er9427",
5177 .data = &rocktech_rk070er9427,
5178 }, {
5179 .compatible = "rocktech,rk101ii01d-ct",
5180 .data = &rocktech_rk101ii01d_ct,
5181 }, {
5182 .compatible = "samsung,ltl101al01",
5183 .data = &samsung_ltl101al01,
5184 }, {
5185 .compatible = "samsung,ltn101nt05",
5186 .data = &samsung_ltn101nt05,
5187 }, {
5188 .compatible = "satoz,sat050at40h12r2",
5189 .data = &satoz_sat050at40h12r2,
5190 }, {
5191 .compatible = "sharp,lq035q7db03",
5192 .data = &sharp_lq035q7db03,
5193 }, {
5194 .compatible = "sharp,lq070y3dg3b",
5195 .data = &sharp_lq070y3dg3b,
5196 }, {
5197 .compatible = "sharp,lq101k1ly04",
5198 .data = &sharp_lq101k1ly04,
5199 }, {
5200 .compatible = "sharp,ls020b1dd01d",
5201 .data = &sharp_ls020b1dd01d,
5202 }, {
5203 .compatible = "shelly,sca07010-bfn-lnn",
5204 .data = &shelly_sca07010_bfn_lnn,
5205 }, {
5206 .compatible = "starry,kr070pe2t",
5207 .data = &starry_kr070pe2t,
5208 }, {
5209 .compatible = "startek,kd070wvfpa",
5210 .data = &startek_kd070wvfpa,
5211 }, {
5212 .compatible = "team-source-display,tst043015cmhx",
5213 .data = &tsd_tst043015cmhx,
5214 }, {
5215 .compatible = "tfc,s9700rtwv43tr-01b",
5216 .data = &tfc_s9700rtwv43tr_01b,
5217 }, {
5218 .compatible = "tianma,tm070jdhg30",
5219 .data = &tianma_tm070jdhg30,
5220 }, {
5221 .compatible = "tianma,tm070jdhg34-00",
5222 .data = &tianma_tm070jdhg34_00,
5223 }, {
5224 .compatible = "tianma,tm070jvhg33",
5225 .data = &tianma_tm070jvhg33,
5226 }, {
5227 .compatible = "tianma,tm070rvhg71",
5228 .data = &tianma_tm070rvhg71,
5229 }, {
5230 .compatible = "ti,nspire-cx-lcd-panel",
5231 .data = &ti_nspire_cx_lcd_panel,
5232 }, {
5233 .compatible = "ti,nspire-classic-lcd-panel",
5234 .data = &ti_nspire_classic_lcd_panel,
5235 }, {
5236 .compatible = "toshiba,lt089ac29000",
5237 .data = &toshiba_lt089ac29000,
5238 }, {
5239 .compatible = "topland,tian-g07017-01",
5240 .data = &topland_tian_g07017_01,
5241 }, {
5242 .compatible = "tpk,f07a-0102",
5243 .data = &tpk_f07a_0102,
5244 }, {
5245 .compatible = "tpk,f10a-0102",
5246 .data = &tpk_f10a_0102,
5247 }, {
5248 .compatible = "urt,umsh-8596md-t",
5249 .data = &urt_umsh_8596md_parallel,
5250 }, {
5251 .compatible = "urt,umsh-8596md-1t",
5252 .data = &urt_umsh_8596md_parallel,
5253 }, {
5254 .compatible = "urt,umsh-8596md-7t",
5255 .data = &urt_umsh_8596md_parallel,
5256 }, {
5257 .compatible = "urt,umsh-8596md-11t",
5258 .data = &urt_umsh_8596md_lvds,
5259 }, {
5260 .compatible = "urt,umsh-8596md-19t",
5261 .data = &urt_umsh_8596md_lvds,
5262 }, {
5263 .compatible = "urt,umsh-8596md-20t",
5264 .data = &urt_umsh_8596md_parallel,
5265 }, {
5266 .compatible = "vivax,tpc9150-panel",
5267 .data = &vivax_tpc9150_panel,
5268 }, {
5269 .compatible = "vxt,vl050-8048nt-c01",
5270 .data = &vl050_8048nt_c01,
5271 }, {
5272 .compatible = "winstar,wf35ltiacd",
5273 .data = &winstar_wf35ltiacd,
5274 }, {
5275 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
5276 .data = &yes_optoelectronics_ytc700tlag_05_201c,
5277 }, {
5278 .compatible = "microchip,ac69t88a",
5279 .data = &mchp_ac69t88a,
5280 }, {
5281 /* Must be the last entry */
5282 .compatible = "panel-dpi",
5283 .data = &panel_dpi,
5284 }, {
5285 /* sentinel */
5286 }
5287 };
5288 MODULE_DEVICE_TABLE(of, platform_of_match);
5289
panel_simple_platform_probe(struct platform_device * pdev)5290 static int panel_simple_platform_probe(struct platform_device *pdev)
5291 {
5292 const struct panel_desc *desc;
5293
5294 desc = of_device_get_match_data(&pdev->dev);
5295 if (!desc)
5296 return -ENODEV;
5297
5298 return panel_simple_probe(&pdev->dev, desc);
5299 }
5300
panel_simple_platform_remove(struct platform_device * pdev)5301 static void panel_simple_platform_remove(struct platform_device *pdev)
5302 {
5303 panel_simple_remove(&pdev->dev);
5304 }
5305
panel_simple_platform_shutdown(struct platform_device * pdev)5306 static void panel_simple_platform_shutdown(struct platform_device *pdev)
5307 {
5308 panel_simple_shutdown(&pdev->dev);
5309 }
5310
5311 static const struct dev_pm_ops panel_simple_pm_ops = {
5312 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
5313 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5314 pm_runtime_force_resume)
5315 };
5316
5317 static struct platform_driver panel_simple_platform_driver = {
5318 .driver = {
5319 .name = "panel-simple",
5320 .of_match_table = platform_of_match,
5321 .pm = &panel_simple_pm_ops,
5322 },
5323 .probe = panel_simple_platform_probe,
5324 .remove = panel_simple_platform_remove,
5325 .shutdown = panel_simple_platform_shutdown,
5326 };
5327
5328 struct panel_desc_dsi {
5329 struct panel_desc desc;
5330
5331 unsigned long flags;
5332 enum mipi_dsi_pixel_format format;
5333 unsigned int lanes;
5334 };
5335
5336 static const struct drm_display_mode auo_b080uan01_mode = {
5337 .clock = 154500,
5338 .hdisplay = 1200,
5339 .hsync_start = 1200 + 62,
5340 .hsync_end = 1200 + 62 + 4,
5341 .htotal = 1200 + 62 + 4 + 62,
5342 .vdisplay = 1920,
5343 .vsync_start = 1920 + 9,
5344 .vsync_end = 1920 + 9 + 2,
5345 .vtotal = 1920 + 9 + 2 + 8,
5346 };
5347
5348 static const struct panel_desc_dsi auo_b080uan01 = {
5349 .desc = {
5350 .modes = &auo_b080uan01_mode,
5351 .num_modes = 1,
5352 .bpc = 8,
5353 .size = {
5354 .width = 108,
5355 .height = 272,
5356 },
5357 .connector_type = DRM_MODE_CONNECTOR_DSI,
5358 },
5359 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5360 .format = MIPI_DSI_FMT_RGB888,
5361 .lanes = 4,
5362 };
5363
5364 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5365 .clock = 160000,
5366 .hdisplay = 1200,
5367 .hsync_start = 1200 + 120,
5368 .hsync_end = 1200 + 120 + 20,
5369 .htotal = 1200 + 120 + 20 + 21,
5370 .vdisplay = 1920,
5371 .vsync_start = 1920 + 21,
5372 .vsync_end = 1920 + 21 + 3,
5373 .vtotal = 1920 + 21 + 3 + 18,
5374 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5375 };
5376
5377 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5378 .desc = {
5379 .modes = &boe_tv080wum_nl0_mode,
5380 .num_modes = 1,
5381 .size = {
5382 .width = 107,
5383 .height = 172,
5384 },
5385 .connector_type = DRM_MODE_CONNECTOR_DSI,
5386 },
5387 .flags = MIPI_DSI_MODE_VIDEO |
5388 MIPI_DSI_MODE_VIDEO_BURST |
5389 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5390 .format = MIPI_DSI_FMT_RGB888,
5391 .lanes = 4,
5392 };
5393
5394 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5395 .clock = 71000,
5396 .hdisplay = 800,
5397 .hsync_start = 800 + 32,
5398 .hsync_end = 800 + 32 + 1,
5399 .htotal = 800 + 32 + 1 + 57,
5400 .vdisplay = 1280,
5401 .vsync_start = 1280 + 28,
5402 .vsync_end = 1280 + 28 + 1,
5403 .vtotal = 1280 + 28 + 1 + 14,
5404 };
5405
5406 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5407 .desc = {
5408 .modes = &lg_ld070wx3_sl01_mode,
5409 .num_modes = 1,
5410 .bpc = 8,
5411 .size = {
5412 .width = 94,
5413 .height = 151,
5414 },
5415 .connector_type = DRM_MODE_CONNECTOR_DSI,
5416 },
5417 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5418 .format = MIPI_DSI_FMT_RGB888,
5419 .lanes = 4,
5420 };
5421
5422 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5423 .clock = 67000,
5424 .hdisplay = 720,
5425 .hsync_start = 720 + 12,
5426 .hsync_end = 720 + 12 + 4,
5427 .htotal = 720 + 12 + 4 + 112,
5428 .vdisplay = 1280,
5429 .vsync_start = 1280 + 8,
5430 .vsync_end = 1280 + 8 + 4,
5431 .vtotal = 1280 + 8 + 4 + 12,
5432 };
5433
5434 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5435 .desc = {
5436 .modes = &lg_lh500wx1_sd03_mode,
5437 .num_modes = 1,
5438 .bpc = 8,
5439 .size = {
5440 .width = 62,
5441 .height = 110,
5442 },
5443 .connector_type = DRM_MODE_CONNECTOR_DSI,
5444 },
5445 .flags = MIPI_DSI_MODE_VIDEO,
5446 .format = MIPI_DSI_FMT_RGB888,
5447 .lanes = 4,
5448 };
5449
5450 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5451 .clock = 157200,
5452 .hdisplay = 1920,
5453 .hsync_start = 1920 + 154,
5454 .hsync_end = 1920 + 154 + 16,
5455 .htotal = 1920 + 154 + 16 + 32,
5456 .vdisplay = 1200,
5457 .vsync_start = 1200 + 17,
5458 .vsync_end = 1200 + 17 + 2,
5459 .vtotal = 1200 + 17 + 2 + 16,
5460 };
5461
5462 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5463 .desc = {
5464 .modes = &panasonic_vvx10f004b00_mode,
5465 .num_modes = 1,
5466 .bpc = 8,
5467 .size = {
5468 .width = 217,
5469 .height = 136,
5470 },
5471 .connector_type = DRM_MODE_CONNECTOR_DSI,
5472 },
5473 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5474 MIPI_DSI_CLOCK_NON_CONTINUOUS,
5475 .format = MIPI_DSI_FMT_RGB888,
5476 .lanes = 4,
5477 };
5478
5479 static const struct drm_display_mode lg_acx467akm_7_mode = {
5480 .clock = 150000,
5481 .hdisplay = 1080,
5482 .hsync_start = 1080 + 2,
5483 .hsync_end = 1080 + 2 + 2,
5484 .htotal = 1080 + 2 + 2 + 2,
5485 .vdisplay = 1920,
5486 .vsync_start = 1920 + 2,
5487 .vsync_end = 1920 + 2 + 2,
5488 .vtotal = 1920 + 2 + 2 + 2,
5489 };
5490
5491 static const struct panel_desc_dsi lg_acx467akm_7 = {
5492 .desc = {
5493 .modes = &lg_acx467akm_7_mode,
5494 .num_modes = 1,
5495 .bpc = 8,
5496 .size = {
5497 .width = 62,
5498 .height = 110,
5499 },
5500 .connector_type = DRM_MODE_CONNECTOR_DSI,
5501 },
5502 .flags = 0,
5503 .format = MIPI_DSI_FMT_RGB888,
5504 .lanes = 4,
5505 };
5506
5507 static const struct drm_display_mode osd101t2045_53ts_mode = {
5508 .clock = 154500,
5509 .hdisplay = 1920,
5510 .hsync_start = 1920 + 112,
5511 .hsync_end = 1920 + 112 + 16,
5512 .htotal = 1920 + 112 + 16 + 32,
5513 .vdisplay = 1200,
5514 .vsync_start = 1200 + 16,
5515 .vsync_end = 1200 + 16 + 2,
5516 .vtotal = 1200 + 16 + 2 + 16,
5517 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5518 };
5519
5520 static const struct panel_desc_dsi osd101t2045_53ts = {
5521 .desc = {
5522 .modes = &osd101t2045_53ts_mode,
5523 .num_modes = 1,
5524 .bpc = 8,
5525 .size = {
5526 .width = 217,
5527 .height = 136,
5528 },
5529 .connector_type = DRM_MODE_CONNECTOR_DSI,
5530 },
5531 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5532 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5533 MIPI_DSI_MODE_NO_EOT_PACKET,
5534 .format = MIPI_DSI_FMT_RGB888,
5535 .lanes = 4,
5536 };
5537
5538 static const struct of_device_id dsi_of_match[] = {
5539 {
5540 .compatible = "auo,b080uan01",
5541 .data = &auo_b080uan01
5542 }, {
5543 .compatible = "boe,tv080wum-nl0",
5544 .data = &boe_tv080wum_nl0
5545 }, {
5546 .compatible = "lg,ld070wx3-sl01",
5547 .data = &lg_ld070wx3_sl01
5548 }, {
5549 .compatible = "lg,lh500wx1-sd03",
5550 .data = &lg_lh500wx1_sd03
5551 }, {
5552 .compatible = "panasonic,vvx10f004b00",
5553 .data = &panasonic_vvx10f004b00
5554 }, {
5555 .compatible = "lg,acx467akm-7",
5556 .data = &lg_acx467akm_7
5557 }, {
5558 .compatible = "osddisplays,osd101t2045-53ts",
5559 .data = &osd101t2045_53ts
5560 }, {
5561 /* sentinel */
5562 }
5563 };
5564 MODULE_DEVICE_TABLE(of, dsi_of_match);
5565
panel_simple_dsi_probe(struct mipi_dsi_device * dsi)5566 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5567 {
5568 const struct panel_desc_dsi *desc;
5569 int err;
5570
5571 desc = of_device_get_match_data(&dsi->dev);
5572 if (!desc)
5573 return -ENODEV;
5574
5575 err = panel_simple_probe(&dsi->dev, &desc->desc);
5576 if (err < 0)
5577 return err;
5578
5579 dsi->mode_flags = desc->flags;
5580 dsi->format = desc->format;
5581 dsi->lanes = desc->lanes;
5582
5583 err = mipi_dsi_attach(dsi);
5584 if (err) {
5585 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
5586
5587 drm_panel_remove(&panel->base);
5588 }
5589
5590 return err;
5591 }
5592
panel_simple_dsi_remove(struct mipi_dsi_device * dsi)5593 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5594 {
5595 int err;
5596
5597 err = mipi_dsi_detach(dsi);
5598 if (err < 0)
5599 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5600
5601 panel_simple_remove(&dsi->dev);
5602 }
5603
panel_simple_dsi_shutdown(struct mipi_dsi_device * dsi)5604 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5605 {
5606 panel_simple_shutdown(&dsi->dev);
5607 }
5608
5609 static struct mipi_dsi_driver panel_simple_dsi_driver = {
5610 .driver = {
5611 .name = "panel-simple-dsi",
5612 .of_match_table = dsi_of_match,
5613 .pm = &panel_simple_pm_ops,
5614 },
5615 .probe = panel_simple_dsi_probe,
5616 .remove = panel_simple_dsi_remove,
5617 .shutdown = panel_simple_dsi_shutdown,
5618 };
5619
panel_simple_init(void)5620 static int __init panel_simple_init(void)
5621 {
5622 int err;
5623
5624 err = platform_driver_register(&panel_simple_platform_driver);
5625 if (err < 0)
5626 return err;
5627
5628 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5629 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
5630 if (err < 0)
5631 goto err_did_platform_register;
5632 }
5633
5634 return 0;
5635
5636 err_did_platform_register:
5637 platform_driver_unregister(&panel_simple_platform_driver);
5638
5639 return err;
5640 }
5641 module_init(panel_simple_init);
5642
panel_simple_exit(void)5643 static void __exit panel_simple_exit(void)
5644 {
5645 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5646 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5647
5648 platform_driver_unregister(&panel_simple_platform_driver);
5649 }
5650 module_exit(panel_simple_exit);
5651
5652 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5653 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5654 MODULE_LICENSE("GPL and additional rights");
5655